ezbrd.c 18 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf518/boards/ezbrd.c
  3. * Based on: arch/blackfin/mach-bf527/boards/ezbrd.c
  4. * Author: Bryan Wu <cooloney@kernel.org>
  5. *
  6. * Created:
  7. * Description:
  8. *
  9. * Modified:
  10. * Copyright 2005 National ICT Australia (NICTA)
  11. * Copyright 2004-2008 Analog Devices Inc.
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <linux/device.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/mtd/mtd.h>
  33. #include <linux/mtd/partitions.h>
  34. #include <linux/mtd/physmap.h>
  35. #include <linux/spi/spi.h>
  36. #include <linux/spi/flash.h>
  37. #include <linux/i2c.h>
  38. #include <linux/irq.h>
  39. #include <linux/interrupt.h>
  40. #include <asm/dma.h>
  41. #include <asm/bfin5xx_spi.h>
  42. #include <asm/reboot.h>
  43. #include <asm/portmux.h>
  44. #include <asm/dpmc.h>
  45. #include <asm/bfin_sdh.h>
  46. #include <linux/spi/ad7877.h>
  47. #include <net/dsa.h>
  48. /*
  49. * Name the Board for the /proc/cpuinfo
  50. */
  51. const char bfin_board_name[] = "ADI BF518F-EZBRD";
  52. /*
  53. * Driver needs to know address, irq and flag pin.
  54. */
  55. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  56. static struct mtd_partition ezbrd_partitions[] = {
  57. {
  58. .name = "bootloader(nor)",
  59. .size = 0x40000,
  60. .offset = 0,
  61. }, {
  62. .name = "linux kernel(nor)",
  63. .size = 0x1C0000,
  64. .offset = MTDPART_OFS_APPEND,
  65. }, {
  66. .name = "file system(nor)",
  67. .size = MTDPART_SIZ_FULL,
  68. .offset = MTDPART_OFS_APPEND,
  69. }
  70. };
  71. static struct physmap_flash_data ezbrd_flash_data = {
  72. .width = 2,
  73. .parts = ezbrd_partitions,
  74. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  75. };
  76. static struct resource ezbrd_flash_resource = {
  77. .start = 0x20000000,
  78. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  79. .end = 0x202fffff,
  80. #else
  81. .end = 0x203fffff,
  82. #endif
  83. .flags = IORESOURCE_MEM,
  84. };
  85. static struct platform_device ezbrd_flash_device = {
  86. .name = "physmap-flash",
  87. .id = 0,
  88. .dev = {
  89. .platform_data = &ezbrd_flash_data,
  90. },
  91. .num_resources = 1,
  92. .resource = &ezbrd_flash_resource,
  93. };
  94. #endif
  95. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  96. static struct platform_device rtc_device = {
  97. .name = "rtc-bfin",
  98. .id = -1,
  99. };
  100. #endif
  101. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  102. static struct platform_device bfin_mii_bus = {
  103. .name = "bfin_mii_bus",
  104. };
  105. static struct platform_device bfin_mac_device = {
  106. .name = "bfin_mac",
  107. .dev.platform_data = &bfin_mii_bus,
  108. };
  109. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  110. static struct dsa_platform_data ksz8893m_switch_data = {
  111. .mii_bus = &bfin_mii_bus.dev,
  112. .netdev = &bfin_mac_device.dev,
  113. .port_names[0] = NULL,
  114. .port_names[1] = "eth%d",
  115. .port_names[2] = "eth%d",
  116. .port_names[3] = "cpu",
  117. };
  118. static struct platform_device ksz8893m_switch_device = {
  119. .name = "dsa",
  120. .id = 0,
  121. .num_resources = 0,
  122. .dev.platform_data = &ksz8893m_switch_data,
  123. };
  124. #endif
  125. #endif
  126. #if defined(CONFIG_MTD_M25P80) \
  127. || defined(CONFIG_MTD_M25P80_MODULE)
  128. static struct mtd_partition bfin_spi_flash_partitions[] = {
  129. {
  130. .name = "bootloader(spi)",
  131. .size = 0x00040000,
  132. .offset = 0,
  133. .mask_flags = MTD_CAP_ROM
  134. }, {
  135. .name = "linux kernel(spi)",
  136. .size = MTDPART_SIZ_FULL,
  137. .offset = MTDPART_OFS_APPEND,
  138. }
  139. };
  140. static struct flash_platform_data bfin_spi_flash_data = {
  141. .name = "m25p80",
  142. .parts = bfin_spi_flash_partitions,
  143. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  144. .type = "m25p16",
  145. };
  146. /* SPI flash chip (m25p64) */
  147. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  148. .enable_dma = 0, /* use dma transfer with this chip*/
  149. .bits_per_word = 8,
  150. };
  151. #endif
  152. #if defined(CONFIG_SPI_ADC_BF533) \
  153. || defined(CONFIG_SPI_ADC_BF533_MODULE)
  154. /* SPI ADC chip */
  155. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  156. .enable_dma = 1, /* use dma transfer with this chip*/
  157. .bits_per_word = 16,
  158. };
  159. #endif
  160. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  161. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  162. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  163. /* SPI SWITCH CHIP */
  164. static struct bfin5xx_spi_chip spi_switch_info = {
  165. .enable_dma = 0,
  166. .bits_per_word = 8,
  167. };
  168. #endif
  169. #endif
  170. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  171. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  172. .enable_dma = 0,
  173. .bits_per_word = 8,
  174. };
  175. #endif
  176. #if defined(CONFIG_PBX)
  177. static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
  178. .ctl_reg = 0x4, /* send zero */
  179. .enable_dma = 0,
  180. .bits_per_word = 8,
  181. .cs_change_per_word = 1,
  182. };
  183. #endif
  184. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  185. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  186. .enable_dma = 0,
  187. .bits_per_word = 16,
  188. };
  189. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  190. .model = 7877,
  191. .vref_delay_usecs = 50, /* internal, no capacitor */
  192. .x_plate_ohms = 419,
  193. .y_plate_ohms = 486,
  194. .pressure_max = 1000,
  195. .pressure_min = 0,
  196. .stopacq_polarity = 1,
  197. .first_conversion_delay = 3,
  198. .acquisition_time = 1,
  199. .averaging = 1,
  200. .pen_down_acc_interval = 1,
  201. };
  202. #endif
  203. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  204. && defined(CONFIG_SND_SOC_WM8731_SPI)
  205. static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
  206. .enable_dma = 0,
  207. .bits_per_word = 16,
  208. };
  209. #endif
  210. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  211. static struct bfin5xx_spi_chip spidev_chip_info = {
  212. .enable_dma = 0,
  213. .bits_per_word = 8,
  214. };
  215. #endif
  216. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  217. #if defined(CONFIG_MTD_M25P80) \
  218. || defined(CONFIG_MTD_M25P80_MODULE)
  219. {
  220. /* the modalias must be the same as spi device driver name */
  221. .modalias = "m25p80", /* Name of spi_driver for this device */
  222. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  223. .bus_num = 0, /* Framework bus number */
  224. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  225. .platform_data = &bfin_spi_flash_data,
  226. .controller_data = &spi_flash_chip_info,
  227. .mode = SPI_MODE_3,
  228. },
  229. #endif
  230. #if defined(CONFIG_SPI_ADC_BF533) \
  231. || defined(CONFIG_SPI_ADC_BF533_MODULE)
  232. {
  233. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  234. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  235. .bus_num = 0, /* Framework bus number */
  236. .chip_select = 1, /* Framework chip select. */
  237. .platform_data = NULL, /* No spi_driver specific config */
  238. .controller_data = &spi_adc_chip_info,
  239. },
  240. #endif
  241. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  242. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  243. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  244. {
  245. .modalias = "ksz8893m",
  246. .max_speed_hz = 5000000,
  247. .bus_num = 0,
  248. .chip_select = 1,
  249. .platform_data = NULL,
  250. .controller_data = &spi_switch_info,
  251. .mode = SPI_MODE_3,
  252. },
  253. #endif
  254. #endif
  255. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  256. {
  257. .modalias = "mmc_spi",
  258. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  259. .bus_num = 0,
  260. .chip_select = 5,
  261. .controller_data = &mmc_spi_chip_info,
  262. .mode = SPI_MODE_3,
  263. },
  264. #endif
  265. #if defined(CONFIG_PBX)
  266. {
  267. .modalias = "fxs-spi",
  268. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  269. .bus_num = 0,
  270. .chip_select = 8 - CONFIG_J11_JUMPER,
  271. .controller_data = &spi_si3xxx_chip_info,
  272. .mode = SPI_MODE_3,
  273. },
  274. {
  275. .modalias = "fxo-spi",
  276. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  277. .bus_num = 0,
  278. .chip_select = 8 - CONFIG_J19_JUMPER,
  279. .controller_data = &spi_si3xxx_chip_info,
  280. .mode = SPI_MODE_3,
  281. },
  282. #endif
  283. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  284. {
  285. .modalias = "ad7877",
  286. .platform_data = &bfin_ad7877_ts_info,
  287. .irq = IRQ_PF8,
  288. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  289. .bus_num = 0,
  290. .chip_select = 2,
  291. .controller_data = &spi_ad7877_chip_info,
  292. },
  293. #endif
  294. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  295. && defined(CONFIG_SND_SOC_WM8731_SPI)
  296. {
  297. .modalias = "wm8731",
  298. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  299. .bus_num = 0,
  300. .chip_select = 5,
  301. .controller_data = &spi_wm8731_chip_info,
  302. .mode = SPI_MODE_0,
  303. },
  304. #endif
  305. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  306. {
  307. .modalias = "spidev",
  308. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  309. .bus_num = 0,
  310. .chip_select = 1,
  311. .controller_data = &spidev_chip_info,
  312. },
  313. #endif
  314. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  315. {
  316. .modalias = "bfin-lq035q1-spi",
  317. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  318. .bus_num = 0,
  319. .chip_select = 1,
  320. .controller_data = &lq035q1_spi_chip_info,
  321. .mode = SPI_CPHA | SPI_CPOL,
  322. },
  323. #endif
  324. };
  325. /* SPI controller data */
  326. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  327. /* SPI (0) */
  328. static struct bfin5xx_spi_master bfin_spi0_info = {
  329. .num_chipselect = 5,
  330. .enable_dma = 1, /* master has the ability to do dma transfer */
  331. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  332. };
  333. static struct resource bfin_spi0_resource[] = {
  334. [0] = {
  335. .start = SPI0_REGBASE,
  336. .end = SPI0_REGBASE + 0xFF,
  337. .flags = IORESOURCE_MEM,
  338. },
  339. [1] = {
  340. .start = CH_SPI0,
  341. .end = CH_SPI0,
  342. .flags = IORESOURCE_IRQ,
  343. },
  344. };
  345. static struct platform_device bfin_spi0_device = {
  346. .name = "bfin-spi",
  347. .id = 0, /* Bus number */
  348. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  349. .resource = bfin_spi0_resource,
  350. .dev = {
  351. .platform_data = &bfin_spi0_info, /* Passed to driver */
  352. },
  353. };
  354. /* SPI (1) */
  355. static struct bfin5xx_spi_master bfin_spi1_info = {
  356. .num_chipselect = 5,
  357. .enable_dma = 1, /* master has the ability to do dma transfer */
  358. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  359. };
  360. static struct resource bfin_spi1_resource[] = {
  361. [0] = {
  362. .start = SPI1_REGBASE,
  363. .end = SPI1_REGBASE + 0xFF,
  364. .flags = IORESOURCE_MEM,
  365. },
  366. [1] = {
  367. .start = CH_SPI1,
  368. .end = CH_SPI1,
  369. .flags = IORESOURCE_IRQ,
  370. },
  371. };
  372. static struct platform_device bfin_spi1_device = {
  373. .name = "bfin-spi",
  374. .id = 1, /* Bus number */
  375. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  376. .resource = bfin_spi1_resource,
  377. .dev = {
  378. .platform_data = &bfin_spi1_info, /* Passed to driver */
  379. },
  380. };
  381. #endif /* spi master and devices */
  382. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  383. static struct resource bfin_uart_resources[] = {
  384. #ifdef CONFIG_SERIAL_BFIN_UART0
  385. {
  386. .start = 0xFFC00400,
  387. .end = 0xFFC004FF,
  388. .flags = IORESOURCE_MEM,
  389. },
  390. #endif
  391. #ifdef CONFIG_SERIAL_BFIN_UART1
  392. {
  393. .start = 0xFFC02000,
  394. .end = 0xFFC020FF,
  395. .flags = IORESOURCE_MEM,
  396. },
  397. #endif
  398. };
  399. static struct platform_device bfin_uart_device = {
  400. .name = "bfin-uart",
  401. .id = 1,
  402. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  403. .resource = bfin_uart_resources,
  404. };
  405. #endif
  406. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  407. #ifdef CONFIG_BFIN_SIR0
  408. static struct resource bfin_sir0_resources[] = {
  409. {
  410. .start = 0xFFC00400,
  411. .end = 0xFFC004FF,
  412. .flags = IORESOURCE_MEM,
  413. },
  414. {
  415. .start = IRQ_UART0_RX,
  416. .end = IRQ_UART0_RX+1,
  417. .flags = IORESOURCE_IRQ,
  418. },
  419. {
  420. .start = CH_UART0_RX,
  421. .end = CH_UART0_RX+1,
  422. .flags = IORESOURCE_DMA,
  423. },
  424. };
  425. static struct platform_device bfin_sir0_device = {
  426. .name = "bfin_sir",
  427. .id = 0,
  428. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  429. .resource = bfin_sir0_resources,
  430. };
  431. #endif
  432. #ifdef CONFIG_BFIN_SIR1
  433. static struct resource bfin_sir1_resources[] = {
  434. {
  435. .start = 0xFFC02000,
  436. .end = 0xFFC020FF,
  437. .flags = IORESOURCE_MEM,
  438. },
  439. {
  440. .start = IRQ_UART1_RX,
  441. .end = IRQ_UART1_RX+1,
  442. .flags = IORESOURCE_IRQ,
  443. },
  444. {
  445. .start = CH_UART1_RX,
  446. .end = CH_UART1_RX+1,
  447. .flags = IORESOURCE_DMA,
  448. },
  449. };
  450. static struct platform_device bfin_sir1_device = {
  451. .name = "bfin_sir",
  452. .id = 1,
  453. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  454. .resource = bfin_sir1_resources,
  455. };
  456. #endif
  457. #endif
  458. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  459. static struct resource bfin_twi0_resource[] = {
  460. [0] = {
  461. .start = TWI0_REGBASE,
  462. .end = TWI0_REGBASE,
  463. .flags = IORESOURCE_MEM,
  464. },
  465. [1] = {
  466. .start = IRQ_TWI,
  467. .end = IRQ_TWI,
  468. .flags = IORESOURCE_IRQ,
  469. },
  470. };
  471. static struct platform_device i2c_bfin_twi_device = {
  472. .name = "i2c-bfin-twi",
  473. .id = 0,
  474. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  475. .resource = bfin_twi0_resource,
  476. };
  477. #endif
  478. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  479. #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
  480. {
  481. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  482. },
  483. #endif
  484. #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
  485. {
  486. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  487. .irq = IRQ_PF8,
  488. },
  489. #endif
  490. };
  491. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  492. static struct platform_device bfin_sport0_uart_device = {
  493. .name = "bfin-sport-uart",
  494. .id = 0,
  495. };
  496. static struct platform_device bfin_sport1_uart_device = {
  497. .name = "bfin-sport-uart",
  498. .id = 1,
  499. };
  500. #endif
  501. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  502. #include <linux/input.h>
  503. #include <linux/gpio_keys.h>
  504. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  505. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  506. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  507. };
  508. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  509. .buttons = bfin_gpio_keys_table,
  510. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  511. };
  512. static struct platform_device bfin_device_gpiokeys = {
  513. .name = "gpio-keys",
  514. .dev = {
  515. .platform_data = &bfin_gpio_keys_data,
  516. },
  517. };
  518. #endif
  519. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  520. static struct bfin_sd_host bfin_sdh_data = {
  521. .dma_chan = CH_RSI,
  522. .irq_int0 = IRQ_RSI_INT0,
  523. .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
  524. };
  525. static struct platform_device bf51x_sdh_device = {
  526. .name = "bfin-sdh",
  527. .id = 0,
  528. .dev = {
  529. .platform_data = &bfin_sdh_data,
  530. },
  531. };
  532. #endif
  533. static struct resource bfin_gpios_resources = {
  534. .start = 0,
  535. .end = MAX_BLACKFIN_GPIOS - 1,
  536. .flags = IORESOURCE_IRQ,
  537. };
  538. static struct platform_device bfin_gpios_device = {
  539. .name = "simple-gpio",
  540. .id = -1,
  541. .num_resources = 1,
  542. .resource = &bfin_gpios_resources,
  543. };
  544. static const unsigned int cclk_vlev_datasheet[] =
  545. {
  546. VRPAIR(VLEV_100, 400000000),
  547. VRPAIR(VLEV_105, 426000000),
  548. VRPAIR(VLEV_110, 500000000),
  549. VRPAIR(VLEV_115, 533000000),
  550. VRPAIR(VLEV_120, 600000000),
  551. };
  552. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  553. .tuple_tab = cclk_vlev_datasheet,
  554. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  555. .vr_settling_time = 25 /* us */,
  556. };
  557. static struct platform_device bfin_dpmc = {
  558. .name = "bfin dpmc",
  559. .dev = {
  560. .platform_data = &bfin_dmpc_vreg_data,
  561. },
  562. };
  563. static struct platform_device *stamp_devices[] __initdata = {
  564. &bfin_dpmc,
  565. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  566. &rtc_device,
  567. #endif
  568. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  569. &bfin_mii_bus,
  570. &bfin_mac_device,
  571. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  572. &ksz8893m_switch_device,
  573. #endif
  574. #endif
  575. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  576. &bfin_spi0_device,
  577. &bfin_spi1_device,
  578. #endif
  579. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  580. &bfin_uart_device,
  581. #endif
  582. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  583. #ifdef CONFIG_BFIN_SIR0
  584. &bfin_sir0_device,
  585. #endif
  586. #ifdef CONFIG_BFIN_SIR1
  587. &bfin_sir1_device,
  588. #endif
  589. #endif
  590. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  591. &i2c_bfin_twi_device,
  592. #endif
  593. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  594. &bfin_sport0_uart_device,
  595. &bfin_sport1_uart_device,
  596. #endif
  597. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  598. &bfin_device_gpiokeys,
  599. #endif
  600. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  601. &bf51x_sdh_device,
  602. #endif
  603. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  604. &ezbrd_flash_device,
  605. #endif
  606. &bfin_gpios_device,
  607. };
  608. static int __init ezbrd_init(void)
  609. {
  610. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  611. i2c_register_board_info(0, bfin_i2c_board_info,
  612. ARRAY_SIZE(bfin_i2c_board_info));
  613. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  614. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  615. /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
  616. peripheral_request(P_AMS2, "ParaFlash");
  617. #if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
  618. peripheral_request(P_AMS3, "ParaFlash");
  619. #endif
  620. return 0;
  621. }
  622. arch_initcall(ezbrd_init);
  623. void native_machine_restart(char *cmd)
  624. {
  625. /* workaround reboot hang when booting from SPI */
  626. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  627. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  628. }
  629. void bfin_get_ether_addr(char *addr)
  630. {
  631. /* the MAC is stored in OTP memory page 0xDF */
  632. u32 ret;
  633. u64 otp_mac;
  634. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  635. ret = otp_read(0xDF, 0x00, &otp_mac);
  636. if (!(ret & 0x1)) {
  637. char *otp_mac_p = (char *)&otp_mac;
  638. for (ret = 0; ret < 6; ++ret)
  639. addr[ret] = otp_mac_p[5 - ret];
  640. }
  641. }
  642. EXPORT_SYMBOL(bfin_get_ether_addr);