intel_crt.c 21 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "drm_crtc.h"
  32. #include "drm_crtc_helper.h"
  33. #include "drm_edid.h"
  34. #include "intel_drv.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  39. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  40. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  41. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  42. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  43. ADPA_CRT_HOTPLUG_ENABLE)
  44. struct intel_crt {
  45. struct intel_encoder base;
  46. bool force_hotplug_required;
  47. u32 adpa_reg;
  48. };
  49. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  50. {
  51. return container_of(intel_attached_encoder(connector),
  52. struct intel_crt, base);
  53. }
  54. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  55. {
  56. return container_of(encoder, struct intel_crt, base);
  57. }
  58. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  59. enum pipe *pipe)
  60. {
  61. struct drm_device *dev = encoder->base.dev;
  62. struct drm_i915_private *dev_priv = dev->dev_private;
  63. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  64. u32 tmp;
  65. tmp = I915_READ(crt->adpa_reg);
  66. if (!(tmp & ADPA_DAC_ENABLE))
  67. return false;
  68. if (HAS_PCH_CPT(dev))
  69. *pipe = PORT_TO_PIPE_CPT(tmp);
  70. else
  71. *pipe = PORT_TO_PIPE(tmp);
  72. return true;
  73. }
  74. static void intel_disable_crt(struct intel_encoder *encoder)
  75. {
  76. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  77. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  78. u32 temp;
  79. temp = I915_READ(crt->adpa_reg);
  80. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  81. temp &= ~ADPA_DAC_ENABLE;
  82. I915_WRITE(crt->adpa_reg, temp);
  83. }
  84. static void intel_enable_crt(struct intel_encoder *encoder)
  85. {
  86. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  87. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  88. u32 temp;
  89. temp = I915_READ(crt->adpa_reg);
  90. temp |= ADPA_DAC_ENABLE;
  91. I915_WRITE(crt->adpa_reg, temp);
  92. }
  93. /* Note: The caller is required to filter out dpms modes not supported by the
  94. * platform. */
  95. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  96. {
  97. struct drm_device *dev = encoder->base.dev;
  98. struct drm_i915_private *dev_priv = dev->dev_private;
  99. struct intel_crt *crt = intel_encoder_to_crt(encoder);
  100. u32 temp;
  101. temp = I915_READ(crt->adpa_reg);
  102. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  103. temp &= ~ADPA_DAC_ENABLE;
  104. switch (mode) {
  105. case DRM_MODE_DPMS_ON:
  106. temp |= ADPA_DAC_ENABLE;
  107. break;
  108. case DRM_MODE_DPMS_STANDBY:
  109. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  110. break;
  111. case DRM_MODE_DPMS_SUSPEND:
  112. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  113. break;
  114. case DRM_MODE_DPMS_OFF:
  115. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  116. break;
  117. }
  118. I915_WRITE(crt->adpa_reg, temp);
  119. }
  120. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  121. {
  122. struct drm_device *dev = connector->dev;
  123. struct intel_encoder *encoder = intel_attached_encoder(connector);
  124. struct drm_crtc *crtc;
  125. int old_dpms;
  126. /* PCH platforms and VLV only support on/off. */
  127. if (INTEL_INFO(dev)->gen < 5 && mode != DRM_MODE_DPMS_ON)
  128. mode = DRM_MODE_DPMS_OFF;
  129. if (mode == connector->dpms)
  130. return;
  131. old_dpms = connector->dpms;
  132. connector->dpms = mode;
  133. /* Only need to change hw state when actually enabled */
  134. crtc = encoder->base.crtc;
  135. if (!crtc) {
  136. encoder->connectors_active = false;
  137. return;
  138. }
  139. /* We need the pipe to run for anything but OFF. */
  140. if (mode == DRM_MODE_DPMS_OFF)
  141. encoder->connectors_active = false;
  142. else
  143. encoder->connectors_active = true;
  144. if (mode < old_dpms) {
  145. /* From off to on, enable the pipe first. */
  146. intel_crtc_update_dpms(crtc);
  147. intel_crt_set_dpms(encoder, mode);
  148. } else {
  149. intel_crt_set_dpms(encoder, mode);
  150. intel_crtc_update_dpms(crtc);
  151. }
  152. intel_modeset_check_state(connector->dev);
  153. }
  154. static int intel_crt_mode_valid(struct drm_connector *connector,
  155. struct drm_display_mode *mode)
  156. {
  157. struct drm_device *dev = connector->dev;
  158. int max_clock = 0;
  159. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  160. return MODE_NO_DBLESCAN;
  161. if (mode->clock < 25000)
  162. return MODE_CLOCK_LOW;
  163. if (IS_GEN2(dev))
  164. max_clock = 350000;
  165. else
  166. max_clock = 400000;
  167. if (mode->clock > max_clock)
  168. return MODE_CLOCK_HIGH;
  169. return MODE_OK;
  170. }
  171. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  172. const struct drm_display_mode *mode,
  173. struct drm_display_mode *adjusted_mode)
  174. {
  175. return true;
  176. }
  177. static void intel_crt_mode_set(struct drm_encoder *encoder,
  178. struct drm_display_mode *mode,
  179. struct drm_display_mode *adjusted_mode)
  180. {
  181. struct drm_device *dev = encoder->dev;
  182. struct drm_crtc *crtc = encoder->crtc;
  183. struct intel_crt *crt =
  184. intel_encoder_to_crt(to_intel_encoder(encoder));
  185. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  186. struct drm_i915_private *dev_priv = dev->dev_private;
  187. int dpll_md_reg;
  188. u32 adpa, dpll_md;
  189. dpll_md_reg = DPLL_MD(intel_crtc->pipe);
  190. /*
  191. * Disable separate mode multiplier used when cloning SDVO to CRT
  192. * XXX this needs to be adjusted when we really are cloning
  193. */
  194. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  195. dpll_md = I915_READ(dpll_md_reg);
  196. I915_WRITE(dpll_md_reg,
  197. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  198. }
  199. adpa = ADPA_HOTPLUG_BITS;
  200. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  201. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  202. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  203. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  204. /* For CPT allow 3 pipe config, for others just use A or B */
  205. if (HAS_PCH_CPT(dev))
  206. adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  207. else if (intel_crtc->pipe == 0)
  208. adpa |= ADPA_PIPE_A_SELECT;
  209. else
  210. adpa |= ADPA_PIPE_B_SELECT;
  211. if (!HAS_PCH_SPLIT(dev))
  212. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  213. I915_WRITE(crt->adpa_reg, adpa);
  214. }
  215. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  216. {
  217. struct drm_device *dev = connector->dev;
  218. struct intel_crt *crt = intel_attached_crt(connector);
  219. struct drm_i915_private *dev_priv = dev->dev_private;
  220. u32 adpa;
  221. bool ret;
  222. /* The first time through, trigger an explicit detection cycle */
  223. if (crt->force_hotplug_required) {
  224. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  225. u32 save_adpa;
  226. crt->force_hotplug_required = 0;
  227. save_adpa = adpa = I915_READ(PCH_ADPA);
  228. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  229. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  230. if (turn_off_dac)
  231. adpa &= ~ADPA_DAC_ENABLE;
  232. I915_WRITE(PCH_ADPA, adpa);
  233. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  234. 1000))
  235. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  236. if (turn_off_dac) {
  237. I915_WRITE(PCH_ADPA, save_adpa);
  238. POSTING_READ(PCH_ADPA);
  239. }
  240. }
  241. /* Check the status to see if both blue and green are on now */
  242. adpa = I915_READ(PCH_ADPA);
  243. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  244. ret = true;
  245. else
  246. ret = false;
  247. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  248. return ret;
  249. }
  250. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  251. {
  252. struct drm_device *dev = connector->dev;
  253. struct drm_i915_private *dev_priv = dev->dev_private;
  254. u32 adpa;
  255. bool ret;
  256. u32 save_adpa;
  257. save_adpa = adpa = I915_READ(ADPA);
  258. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  259. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  260. I915_WRITE(ADPA, adpa);
  261. if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  262. 1000)) {
  263. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  264. I915_WRITE(ADPA, save_adpa);
  265. }
  266. /* Check the status to see if both blue and green are on now */
  267. adpa = I915_READ(ADPA);
  268. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  269. ret = true;
  270. else
  271. ret = false;
  272. DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  273. /* FIXME: debug force function and remove */
  274. ret = true;
  275. return ret;
  276. }
  277. /**
  278. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  279. *
  280. * Not for i915G/i915GM
  281. *
  282. * \return true if CRT is connected.
  283. * \return false if CRT is disconnected.
  284. */
  285. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  286. {
  287. struct drm_device *dev = connector->dev;
  288. struct drm_i915_private *dev_priv = dev->dev_private;
  289. u32 hotplug_en, orig, stat;
  290. bool ret = false;
  291. int i, tries = 0;
  292. if (HAS_PCH_SPLIT(dev))
  293. return intel_ironlake_crt_detect_hotplug(connector);
  294. if (IS_VALLEYVIEW(dev))
  295. return valleyview_crt_detect_hotplug(connector);
  296. /*
  297. * On 4 series desktop, CRT detect sequence need to be done twice
  298. * to get a reliable result.
  299. */
  300. if (IS_G4X(dev) && !IS_GM45(dev))
  301. tries = 2;
  302. else
  303. tries = 1;
  304. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  305. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  306. for (i = 0; i < tries ; i++) {
  307. /* turn on the FORCE_DETECT */
  308. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  309. /* wait for FORCE_DETECT to go off */
  310. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  311. CRT_HOTPLUG_FORCE_DETECT) == 0,
  312. 1000))
  313. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  314. }
  315. stat = I915_READ(PORT_HOTPLUG_STAT);
  316. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  317. ret = true;
  318. /* clear the interrupt we just generated, if any */
  319. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  320. /* and put the bits back */
  321. I915_WRITE(PORT_HOTPLUG_EN, orig);
  322. return ret;
  323. }
  324. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  325. struct i2c_adapter *i2c)
  326. {
  327. struct edid *edid;
  328. edid = drm_get_edid(connector, i2c);
  329. if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  330. DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  331. intel_gmbus_force_bit(i2c, true);
  332. edid = drm_get_edid(connector, i2c);
  333. intel_gmbus_force_bit(i2c, false);
  334. }
  335. return edid;
  336. }
  337. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  338. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  339. struct i2c_adapter *adapter)
  340. {
  341. struct edid *edid;
  342. edid = intel_crt_get_edid(connector, adapter);
  343. if (!edid)
  344. return 0;
  345. return intel_connector_update_modes(connector, edid);
  346. }
  347. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  348. {
  349. struct intel_crt *crt = intel_attached_crt(connector);
  350. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  351. struct edid *edid;
  352. struct i2c_adapter *i2c;
  353. BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  354. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  355. edid = intel_crt_get_edid(connector, i2c);
  356. if (edid) {
  357. bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  358. /*
  359. * This may be a DVI-I connector with a shared DDC
  360. * link between analog and digital outputs, so we
  361. * have to check the EDID input spec of the attached device.
  362. */
  363. if (!is_digital) {
  364. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  365. return true;
  366. }
  367. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  368. } else {
  369. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  370. }
  371. kfree(edid);
  372. return false;
  373. }
  374. static enum drm_connector_status
  375. intel_crt_load_detect(struct intel_crt *crt)
  376. {
  377. struct drm_device *dev = crt->base.base.dev;
  378. struct drm_i915_private *dev_priv = dev->dev_private;
  379. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  380. uint32_t save_bclrpat;
  381. uint32_t save_vtotal;
  382. uint32_t vtotal, vactive;
  383. uint32_t vsample;
  384. uint32_t vblank, vblank_start, vblank_end;
  385. uint32_t dsl;
  386. uint32_t bclrpat_reg;
  387. uint32_t vtotal_reg;
  388. uint32_t vblank_reg;
  389. uint32_t vsync_reg;
  390. uint32_t pipeconf_reg;
  391. uint32_t pipe_dsl_reg;
  392. uint8_t st00;
  393. enum drm_connector_status status;
  394. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  395. bclrpat_reg = BCLRPAT(pipe);
  396. vtotal_reg = VTOTAL(pipe);
  397. vblank_reg = VBLANK(pipe);
  398. vsync_reg = VSYNC(pipe);
  399. pipeconf_reg = PIPECONF(pipe);
  400. pipe_dsl_reg = PIPEDSL(pipe);
  401. save_bclrpat = I915_READ(bclrpat_reg);
  402. save_vtotal = I915_READ(vtotal_reg);
  403. vblank = I915_READ(vblank_reg);
  404. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  405. vactive = (save_vtotal & 0x7ff) + 1;
  406. vblank_start = (vblank & 0xfff) + 1;
  407. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  408. /* Set the border color to purple. */
  409. I915_WRITE(bclrpat_reg, 0x500050);
  410. if (!IS_GEN2(dev)) {
  411. uint32_t pipeconf = I915_READ(pipeconf_reg);
  412. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  413. POSTING_READ(pipeconf_reg);
  414. /* Wait for next Vblank to substitue
  415. * border color for Color info */
  416. intel_wait_for_vblank(dev, pipe);
  417. st00 = I915_READ8(VGA_MSR_WRITE);
  418. status = ((st00 & (1 << 4)) != 0) ?
  419. connector_status_connected :
  420. connector_status_disconnected;
  421. I915_WRITE(pipeconf_reg, pipeconf);
  422. } else {
  423. bool restore_vblank = false;
  424. int count, detect;
  425. /*
  426. * If there isn't any border, add some.
  427. * Yes, this will flicker
  428. */
  429. if (vblank_start <= vactive && vblank_end >= vtotal) {
  430. uint32_t vsync = I915_READ(vsync_reg);
  431. uint32_t vsync_start = (vsync & 0xffff) + 1;
  432. vblank_start = vsync_start;
  433. I915_WRITE(vblank_reg,
  434. (vblank_start - 1) |
  435. ((vblank_end - 1) << 16));
  436. restore_vblank = true;
  437. }
  438. /* sample in the vertical border, selecting the larger one */
  439. if (vblank_start - vactive >= vtotal - vblank_end)
  440. vsample = (vblank_start + vactive) >> 1;
  441. else
  442. vsample = (vtotal + vblank_end) >> 1;
  443. /*
  444. * Wait for the border to be displayed
  445. */
  446. while (I915_READ(pipe_dsl_reg) >= vactive)
  447. ;
  448. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  449. ;
  450. /*
  451. * Watch ST00 for an entire scanline
  452. */
  453. detect = 0;
  454. count = 0;
  455. do {
  456. count++;
  457. /* Read the ST00 VGA status register */
  458. st00 = I915_READ8(VGA_MSR_WRITE);
  459. if (st00 & (1 << 4))
  460. detect++;
  461. } while ((I915_READ(pipe_dsl_reg) == dsl));
  462. /* restore vblank if necessary */
  463. if (restore_vblank)
  464. I915_WRITE(vblank_reg, vblank);
  465. /*
  466. * If more than 3/4 of the scanline detected a monitor,
  467. * then it is assumed to be present. This works even on i830,
  468. * where there isn't any way to force the border color across
  469. * the screen
  470. */
  471. status = detect * 4 > count * 3 ?
  472. connector_status_connected :
  473. connector_status_disconnected;
  474. }
  475. /* Restore previous settings */
  476. I915_WRITE(bclrpat_reg, save_bclrpat);
  477. return status;
  478. }
  479. static enum drm_connector_status
  480. intel_crt_detect(struct drm_connector *connector, bool force)
  481. {
  482. struct drm_device *dev = connector->dev;
  483. struct intel_crt *crt = intel_attached_crt(connector);
  484. enum drm_connector_status status;
  485. struct intel_load_detect_pipe tmp;
  486. if (I915_HAS_HOTPLUG(dev)) {
  487. /* We can not rely on the HPD pin always being correctly wired
  488. * up, for example many KVM do not pass it through, and so
  489. * only trust an assertion that the monitor is connected.
  490. */
  491. if (intel_crt_detect_hotplug(connector)) {
  492. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  493. return connector_status_connected;
  494. } else
  495. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  496. }
  497. if (intel_crt_detect_ddc(connector))
  498. return connector_status_connected;
  499. /* Load detection is broken on HPD capable machines. Whoever wants a
  500. * broken monitor (without edid) to work behind a broken kvm (that fails
  501. * to have the right resistors for HP detection) needs to fix this up.
  502. * For now just bail out. */
  503. if (I915_HAS_HOTPLUG(dev))
  504. return connector_status_disconnected;
  505. if (!force)
  506. return connector->status;
  507. /* for pre-945g platforms use load detect */
  508. if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  509. if (intel_crt_detect_ddc(connector))
  510. status = connector_status_connected;
  511. else
  512. status = intel_crt_load_detect(crt);
  513. intel_release_load_detect_pipe(connector, &tmp);
  514. } else
  515. status = connector_status_unknown;
  516. return status;
  517. }
  518. static void intel_crt_destroy(struct drm_connector *connector)
  519. {
  520. drm_sysfs_connector_remove(connector);
  521. drm_connector_cleanup(connector);
  522. kfree(connector);
  523. }
  524. static int intel_crt_get_modes(struct drm_connector *connector)
  525. {
  526. struct drm_device *dev = connector->dev;
  527. struct drm_i915_private *dev_priv = dev->dev_private;
  528. int ret;
  529. struct i2c_adapter *i2c;
  530. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  531. ret = intel_crt_ddc_get_modes(connector, i2c);
  532. if (ret || !IS_G4X(dev))
  533. return ret;
  534. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  535. i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  536. return intel_crt_ddc_get_modes(connector, i2c);
  537. }
  538. static int intel_crt_set_property(struct drm_connector *connector,
  539. struct drm_property *property,
  540. uint64_t value)
  541. {
  542. return 0;
  543. }
  544. static void intel_crt_reset(struct drm_connector *connector)
  545. {
  546. struct drm_device *dev = connector->dev;
  547. struct intel_crt *crt = intel_attached_crt(connector);
  548. if (HAS_PCH_SPLIT(dev))
  549. crt->force_hotplug_required = 1;
  550. }
  551. /*
  552. * Routines for controlling stuff on the analog port
  553. */
  554. static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
  555. .mode_fixup = intel_crt_mode_fixup,
  556. .mode_set = intel_crt_mode_set,
  557. .disable = intel_encoder_noop,
  558. };
  559. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  560. .reset = intel_crt_reset,
  561. .dpms = intel_crt_dpms,
  562. .detect = intel_crt_detect,
  563. .fill_modes = drm_helper_probe_single_connector_modes,
  564. .destroy = intel_crt_destroy,
  565. .set_property = intel_crt_set_property,
  566. };
  567. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  568. .mode_valid = intel_crt_mode_valid,
  569. .get_modes = intel_crt_get_modes,
  570. .best_encoder = intel_best_encoder,
  571. };
  572. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  573. .destroy = intel_encoder_destroy,
  574. };
  575. static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  576. {
  577. DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  578. return 1;
  579. }
  580. static const struct dmi_system_id intel_no_crt[] = {
  581. {
  582. .callback = intel_no_crt_dmi_callback,
  583. .ident = "ACER ZGB",
  584. .matches = {
  585. DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  586. DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  587. },
  588. },
  589. { }
  590. };
  591. void intel_crt_init(struct drm_device *dev)
  592. {
  593. struct drm_connector *connector;
  594. struct intel_crt *crt;
  595. struct intel_connector *intel_connector;
  596. struct drm_i915_private *dev_priv = dev->dev_private;
  597. /* Skip machines without VGA that falsely report hotplug events */
  598. if (dmi_check_system(intel_no_crt))
  599. return;
  600. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  601. if (!crt)
  602. return;
  603. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  604. if (!intel_connector) {
  605. kfree(crt);
  606. return;
  607. }
  608. connector = &intel_connector->base;
  609. drm_connector_init(dev, &intel_connector->base,
  610. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  611. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  612. DRM_MODE_ENCODER_DAC);
  613. intel_connector_attach_encoder(intel_connector, &crt->base);
  614. crt->base.type = INTEL_OUTPUT_ANALOG;
  615. crt->base.cloneable = true;
  616. if (IS_HASWELL(dev))
  617. crt->base.crtc_mask = (1 << 0);
  618. else
  619. crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  620. if (IS_GEN2(dev))
  621. connector->interlace_allowed = 0;
  622. else
  623. connector->interlace_allowed = 1;
  624. connector->doublescan_allowed = 0;
  625. if (HAS_PCH_SPLIT(dev))
  626. crt->adpa_reg = PCH_ADPA;
  627. else if (IS_VALLEYVIEW(dev))
  628. crt->adpa_reg = VLV_ADPA;
  629. else
  630. crt->adpa_reg = ADPA;
  631. crt->base.disable = intel_disable_crt;
  632. crt->base.enable = intel_enable_crt;
  633. crt->base.get_hw_state = intel_crt_get_hw_state;
  634. intel_connector->get_hw_state = intel_connector_get_hw_state;
  635. drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
  636. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  637. drm_sysfs_connector_add(connector);
  638. if (I915_HAS_HOTPLUG(dev))
  639. connector->polled = DRM_CONNECTOR_POLL_HPD;
  640. else
  641. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  642. /*
  643. * Configure the automatic hotplug detection stuff
  644. */
  645. crt->force_hotplug_required = 0;
  646. if (HAS_PCH_SPLIT(dev)) {
  647. u32 adpa;
  648. adpa = I915_READ(PCH_ADPA);
  649. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  650. adpa |= ADPA_HOTPLUG_BITS;
  651. I915_WRITE(PCH_ADPA, adpa);
  652. POSTING_READ(PCH_ADPA);
  653. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  654. crt->force_hotplug_required = 1;
  655. }
  656. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  657. }