i915_irq.c 76 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/sysrq.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. #include "i915_trace.h"
  36. #include "intel_drv.h"
  37. /* For display hotplug interrupt */
  38. static void
  39. ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  40. {
  41. if ((dev_priv->irq_mask & mask) != 0) {
  42. dev_priv->irq_mask &= ~mask;
  43. I915_WRITE(DEIMR, dev_priv->irq_mask);
  44. POSTING_READ(DEIMR);
  45. }
  46. }
  47. static inline void
  48. ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  49. {
  50. if ((dev_priv->irq_mask & mask) != mask) {
  51. dev_priv->irq_mask |= mask;
  52. I915_WRITE(DEIMR, dev_priv->irq_mask);
  53. POSTING_READ(DEIMR);
  54. }
  55. }
  56. void
  57. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  58. {
  59. if ((dev_priv->pipestat[pipe] & mask) != mask) {
  60. u32 reg = PIPESTAT(pipe);
  61. dev_priv->pipestat[pipe] |= mask;
  62. /* Enable the interrupt, clear any pending status */
  63. I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  64. POSTING_READ(reg);
  65. }
  66. }
  67. void
  68. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  69. {
  70. if ((dev_priv->pipestat[pipe] & mask) != 0) {
  71. u32 reg = PIPESTAT(pipe);
  72. dev_priv->pipestat[pipe] &= ~mask;
  73. I915_WRITE(reg, dev_priv->pipestat[pipe]);
  74. POSTING_READ(reg);
  75. }
  76. }
  77. /**
  78. * intel_enable_asle - enable ASLE interrupt for OpRegion
  79. */
  80. void intel_enable_asle(struct drm_device *dev)
  81. {
  82. drm_i915_private_t *dev_priv = dev->dev_private;
  83. unsigned long irqflags;
  84. /* FIXME: opregion/asle for VLV */
  85. if (IS_VALLEYVIEW(dev))
  86. return;
  87. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  88. if (HAS_PCH_SPLIT(dev))
  89. ironlake_enable_display_irq(dev_priv, DE_GSE);
  90. else {
  91. i915_enable_pipestat(dev_priv, 1,
  92. PIPE_LEGACY_BLC_EVENT_ENABLE);
  93. if (INTEL_INFO(dev)->gen >= 4)
  94. i915_enable_pipestat(dev_priv, 0,
  95. PIPE_LEGACY_BLC_EVENT_ENABLE);
  96. }
  97. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  98. }
  99. /**
  100. * i915_pipe_enabled - check if a pipe is enabled
  101. * @dev: DRM device
  102. * @pipe: pipe to check
  103. *
  104. * Reading certain registers when the pipe is disabled can hang the chip.
  105. * Use this routine to make sure the PLL is running and the pipe is active
  106. * before reading such registers if unsure.
  107. */
  108. static int
  109. i915_pipe_enabled(struct drm_device *dev, int pipe)
  110. {
  111. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  112. return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
  113. }
  114. /* Called from drm generic code, passed a 'crtc', which
  115. * we use as a pipe index
  116. */
  117. static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  118. {
  119. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  120. unsigned long high_frame;
  121. unsigned long low_frame;
  122. u32 high1, high2, low;
  123. if (!i915_pipe_enabled(dev, pipe)) {
  124. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  125. "pipe %c\n", pipe_name(pipe));
  126. return 0;
  127. }
  128. high_frame = PIPEFRAME(pipe);
  129. low_frame = PIPEFRAMEPIXEL(pipe);
  130. /*
  131. * High & low register fields aren't synchronized, so make sure
  132. * we get a low value that's stable across two reads of the high
  133. * register.
  134. */
  135. do {
  136. high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  137. low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
  138. high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  139. } while (high1 != high2);
  140. high1 >>= PIPE_FRAME_HIGH_SHIFT;
  141. low >>= PIPE_FRAME_LOW_SHIFT;
  142. return (high1 << 8) | low;
  143. }
  144. static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  145. {
  146. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  147. int reg = PIPE_FRMCOUNT_GM45(pipe);
  148. if (!i915_pipe_enabled(dev, pipe)) {
  149. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  150. "pipe %c\n", pipe_name(pipe));
  151. return 0;
  152. }
  153. return I915_READ(reg);
  154. }
  155. static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
  156. int *vpos, int *hpos)
  157. {
  158. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  159. u32 vbl = 0, position = 0;
  160. int vbl_start, vbl_end, htotal, vtotal;
  161. bool in_vbl = true;
  162. int ret = 0;
  163. if (!i915_pipe_enabled(dev, pipe)) {
  164. DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
  165. "pipe %c\n", pipe_name(pipe));
  166. return 0;
  167. }
  168. /* Get vtotal. */
  169. vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
  170. if (INTEL_INFO(dev)->gen >= 4) {
  171. /* No obvious pixelcount register. Only query vertical
  172. * scanout position from Display scan line register.
  173. */
  174. position = I915_READ(PIPEDSL(pipe));
  175. /* Decode into vertical scanout position. Don't have
  176. * horizontal scanout position.
  177. */
  178. *vpos = position & 0x1fff;
  179. *hpos = 0;
  180. } else {
  181. /* Have access to pixelcount since start of frame.
  182. * We can split this into vertical and horizontal
  183. * scanout position.
  184. */
  185. position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
  186. htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
  187. *vpos = position / htotal;
  188. *hpos = position - (*vpos * htotal);
  189. }
  190. /* Query vblank area. */
  191. vbl = I915_READ(VBLANK(pipe));
  192. /* Test position against vblank region. */
  193. vbl_start = vbl & 0x1fff;
  194. vbl_end = (vbl >> 16) & 0x1fff;
  195. if ((*vpos < vbl_start) || (*vpos > vbl_end))
  196. in_vbl = false;
  197. /* Inside "upper part" of vblank area? Apply corrective offset: */
  198. if (in_vbl && (*vpos >= vbl_start))
  199. *vpos = *vpos - vtotal;
  200. /* Readouts valid? */
  201. if (vbl > 0)
  202. ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
  203. /* In vblank? */
  204. if (in_vbl)
  205. ret |= DRM_SCANOUTPOS_INVBL;
  206. return ret;
  207. }
  208. static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
  209. int *max_error,
  210. struct timeval *vblank_time,
  211. unsigned flags)
  212. {
  213. struct drm_i915_private *dev_priv = dev->dev_private;
  214. struct drm_crtc *crtc;
  215. if (pipe < 0 || pipe >= dev_priv->num_pipe) {
  216. DRM_ERROR("Invalid crtc %d\n", pipe);
  217. return -EINVAL;
  218. }
  219. /* Get drm_crtc to timestamp: */
  220. crtc = intel_get_crtc_for_pipe(dev, pipe);
  221. if (crtc == NULL) {
  222. DRM_ERROR("Invalid crtc %d\n", pipe);
  223. return -EINVAL;
  224. }
  225. if (!crtc->enabled) {
  226. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  227. return -EBUSY;
  228. }
  229. /* Helper routine in DRM core does all the work: */
  230. return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
  231. vblank_time, flags,
  232. crtc);
  233. }
  234. /*
  235. * Handle hotplug events outside the interrupt handler proper.
  236. */
  237. static void i915_hotplug_work_func(struct work_struct *work)
  238. {
  239. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  240. hotplug_work);
  241. struct drm_device *dev = dev_priv->dev;
  242. struct drm_mode_config *mode_config = &dev->mode_config;
  243. struct intel_encoder *encoder;
  244. mutex_lock(&mode_config->mutex);
  245. DRM_DEBUG_KMS("running encoder hotplug functions\n");
  246. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  247. if (encoder->hot_plug)
  248. encoder->hot_plug(encoder);
  249. mutex_unlock(&mode_config->mutex);
  250. /* Just fire off a uevent and let userspace tell us what to do */
  251. drm_helper_hpd_irq_event(dev);
  252. }
  253. /* defined intel_pm.c */
  254. extern spinlock_t mchdev_lock;
  255. static void ironlake_handle_rps_change(struct drm_device *dev)
  256. {
  257. drm_i915_private_t *dev_priv = dev->dev_private;
  258. u32 busy_up, busy_down, max_avg, min_avg;
  259. u8 new_delay;
  260. unsigned long flags;
  261. spin_lock_irqsave(&mchdev_lock, flags);
  262. I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  263. new_delay = dev_priv->ips.cur_delay;
  264. I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
  265. busy_up = I915_READ(RCPREVBSYTUPAVG);
  266. busy_down = I915_READ(RCPREVBSYTDNAVG);
  267. max_avg = I915_READ(RCBMAXAVG);
  268. min_avg = I915_READ(RCBMINAVG);
  269. /* Handle RCS change request from hw */
  270. if (busy_up > max_avg) {
  271. if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
  272. new_delay = dev_priv->ips.cur_delay - 1;
  273. if (new_delay < dev_priv->ips.max_delay)
  274. new_delay = dev_priv->ips.max_delay;
  275. } else if (busy_down < min_avg) {
  276. if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
  277. new_delay = dev_priv->ips.cur_delay + 1;
  278. if (new_delay > dev_priv->ips.min_delay)
  279. new_delay = dev_priv->ips.min_delay;
  280. }
  281. if (ironlake_set_drps(dev, new_delay))
  282. dev_priv->ips.cur_delay = new_delay;
  283. spin_unlock_irqrestore(&mchdev_lock, flags);
  284. return;
  285. }
  286. static void notify_ring(struct drm_device *dev,
  287. struct intel_ring_buffer *ring)
  288. {
  289. struct drm_i915_private *dev_priv = dev->dev_private;
  290. if (ring->obj == NULL)
  291. return;
  292. trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
  293. wake_up_all(&ring->irq_queue);
  294. if (i915_enable_hangcheck) {
  295. dev_priv->hangcheck_count = 0;
  296. mod_timer(&dev_priv->hangcheck_timer,
  297. jiffies +
  298. msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
  299. }
  300. }
  301. static void gen6_pm_rps_work(struct work_struct *work)
  302. {
  303. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  304. rps.work);
  305. u32 pm_iir, pm_imr;
  306. u8 new_delay;
  307. spin_lock_irq(&dev_priv->rps.lock);
  308. pm_iir = dev_priv->rps.pm_iir;
  309. dev_priv->rps.pm_iir = 0;
  310. pm_imr = I915_READ(GEN6_PMIMR);
  311. I915_WRITE(GEN6_PMIMR, 0);
  312. spin_unlock_irq(&dev_priv->rps.lock);
  313. if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
  314. return;
  315. mutex_lock(&dev_priv->dev->struct_mutex);
  316. if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
  317. new_delay = dev_priv->rps.cur_delay + 1;
  318. else
  319. new_delay = dev_priv->rps.cur_delay - 1;
  320. /* sysfs frequency interfaces may have snuck in while servicing the
  321. * interrupt
  322. */
  323. if (!(new_delay > dev_priv->rps.max_delay ||
  324. new_delay < dev_priv->rps.min_delay)) {
  325. gen6_set_rps(dev_priv->dev, new_delay);
  326. }
  327. mutex_unlock(&dev_priv->dev->struct_mutex);
  328. }
  329. /**
  330. * ivybridge_parity_work - Workqueue called when a parity error interrupt
  331. * occurred.
  332. * @work: workqueue struct
  333. *
  334. * Doesn't actually do anything except notify userspace. As a consequence of
  335. * this event, userspace should try to remap the bad rows since statistically
  336. * it is likely the same row is more likely to go bad again.
  337. */
  338. static void ivybridge_parity_work(struct work_struct *work)
  339. {
  340. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  341. parity_error_work);
  342. u32 error_status, row, bank, subbank;
  343. char *parity_event[5];
  344. uint32_t misccpctl;
  345. unsigned long flags;
  346. /* We must turn off DOP level clock gating to access the L3 registers.
  347. * In order to prevent a get/put style interface, acquire struct mutex
  348. * any time we access those registers.
  349. */
  350. mutex_lock(&dev_priv->dev->struct_mutex);
  351. misccpctl = I915_READ(GEN7_MISCCPCTL);
  352. I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  353. POSTING_READ(GEN7_MISCCPCTL);
  354. error_status = I915_READ(GEN7_L3CDERRST1);
  355. row = GEN7_PARITY_ERROR_ROW(error_status);
  356. bank = GEN7_PARITY_ERROR_BANK(error_status);
  357. subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
  358. I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
  359. GEN7_L3CDERRST1_ENABLE);
  360. POSTING_READ(GEN7_L3CDERRST1);
  361. I915_WRITE(GEN7_MISCCPCTL, misccpctl);
  362. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  363. dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  364. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  365. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  366. mutex_unlock(&dev_priv->dev->struct_mutex);
  367. parity_event[0] = "L3_PARITY_ERROR=1";
  368. parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
  369. parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
  370. parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
  371. parity_event[4] = NULL;
  372. kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
  373. KOBJ_CHANGE, parity_event);
  374. DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
  375. row, bank, subbank);
  376. kfree(parity_event[3]);
  377. kfree(parity_event[2]);
  378. kfree(parity_event[1]);
  379. }
  380. static void ivybridge_handle_parity_error(struct drm_device *dev)
  381. {
  382. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  383. unsigned long flags;
  384. if (!HAS_L3_GPU_CACHE(dev))
  385. return;
  386. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  387. dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  388. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  389. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  390. queue_work(dev_priv->wq, &dev_priv->parity_error_work);
  391. }
  392. static void snb_gt_irq_handler(struct drm_device *dev,
  393. struct drm_i915_private *dev_priv,
  394. u32 gt_iir)
  395. {
  396. if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
  397. GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
  398. notify_ring(dev, &dev_priv->ring[RCS]);
  399. if (gt_iir & GEN6_BSD_USER_INTERRUPT)
  400. notify_ring(dev, &dev_priv->ring[VCS]);
  401. if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
  402. notify_ring(dev, &dev_priv->ring[BCS]);
  403. if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
  404. GT_GEN6_BSD_CS_ERROR_INTERRUPT |
  405. GT_RENDER_CS_ERROR_INTERRUPT)) {
  406. DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
  407. i915_handle_error(dev, false);
  408. }
  409. if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
  410. ivybridge_handle_parity_error(dev);
  411. }
  412. static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
  413. u32 pm_iir)
  414. {
  415. unsigned long flags;
  416. /*
  417. * IIR bits should never already be set because IMR should
  418. * prevent an interrupt from being shown in IIR. The warning
  419. * displays a case where we've unsafely cleared
  420. * dev_priv->rps.pm_iir. Although missing an interrupt of the same
  421. * type is not a problem, it displays a problem in the logic.
  422. *
  423. * The mask bit in IMR is cleared by dev_priv->rps.work.
  424. */
  425. spin_lock_irqsave(&dev_priv->rps.lock, flags);
  426. dev_priv->rps.pm_iir |= pm_iir;
  427. I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
  428. POSTING_READ(GEN6_PMIMR);
  429. spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
  430. queue_work(dev_priv->wq, &dev_priv->rps.work);
  431. }
  432. static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
  433. {
  434. struct drm_device *dev = (struct drm_device *) arg;
  435. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  436. u32 iir, gt_iir, pm_iir;
  437. irqreturn_t ret = IRQ_NONE;
  438. unsigned long irqflags;
  439. int pipe;
  440. u32 pipe_stats[I915_MAX_PIPES];
  441. bool blc_event;
  442. atomic_inc(&dev_priv->irq_received);
  443. while (true) {
  444. iir = I915_READ(VLV_IIR);
  445. gt_iir = I915_READ(GTIIR);
  446. pm_iir = I915_READ(GEN6_PMIIR);
  447. if (gt_iir == 0 && pm_iir == 0 && iir == 0)
  448. goto out;
  449. ret = IRQ_HANDLED;
  450. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  451. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  452. for_each_pipe(pipe) {
  453. int reg = PIPESTAT(pipe);
  454. pipe_stats[pipe] = I915_READ(reg);
  455. /*
  456. * Clear the PIPE*STAT regs before the IIR
  457. */
  458. if (pipe_stats[pipe] & 0x8000ffff) {
  459. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  460. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  461. pipe_name(pipe));
  462. I915_WRITE(reg, pipe_stats[pipe]);
  463. }
  464. }
  465. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  466. for_each_pipe(pipe) {
  467. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
  468. drm_handle_vblank(dev, pipe);
  469. if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
  470. intel_prepare_page_flip(dev, pipe);
  471. intel_finish_page_flip(dev, pipe);
  472. }
  473. }
  474. /* Consume port. Then clear IIR or we'll miss events */
  475. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  476. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  477. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  478. hotplug_status);
  479. if (hotplug_status & dev_priv->hotplug_supported_mask)
  480. queue_work(dev_priv->wq,
  481. &dev_priv->hotplug_work);
  482. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  483. I915_READ(PORT_HOTPLUG_STAT);
  484. }
  485. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  486. blc_event = true;
  487. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  488. gen6_queue_rps_work(dev_priv, pm_iir);
  489. I915_WRITE(GTIIR, gt_iir);
  490. I915_WRITE(GEN6_PMIIR, pm_iir);
  491. I915_WRITE(VLV_IIR, iir);
  492. }
  493. out:
  494. return ret;
  495. }
  496. static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
  497. {
  498. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  499. int pipe;
  500. if (pch_iir & SDE_AUDIO_POWER_MASK)
  501. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  502. (pch_iir & SDE_AUDIO_POWER_MASK) >>
  503. SDE_AUDIO_POWER_SHIFT);
  504. if (pch_iir & SDE_GMBUS)
  505. DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
  506. if (pch_iir & SDE_AUDIO_HDCP_MASK)
  507. DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
  508. if (pch_iir & SDE_AUDIO_TRANS_MASK)
  509. DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
  510. if (pch_iir & SDE_POISON)
  511. DRM_ERROR("PCH poison interrupt\n");
  512. if (pch_iir & SDE_FDI_MASK)
  513. for_each_pipe(pipe)
  514. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  515. pipe_name(pipe),
  516. I915_READ(FDI_RX_IIR(pipe)));
  517. if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
  518. DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
  519. if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
  520. DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
  521. if (pch_iir & SDE_TRANSB_FIFO_UNDER)
  522. DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
  523. if (pch_iir & SDE_TRANSA_FIFO_UNDER)
  524. DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
  525. }
  526. static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
  527. {
  528. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  529. int pipe;
  530. if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
  531. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  532. (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
  533. SDE_AUDIO_POWER_SHIFT_CPT);
  534. if (pch_iir & SDE_AUX_MASK_CPT)
  535. DRM_DEBUG_DRIVER("AUX channel interrupt\n");
  536. if (pch_iir & SDE_GMBUS_CPT)
  537. DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
  538. if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
  539. DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
  540. if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
  541. DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
  542. if (pch_iir & SDE_FDI_MASK_CPT)
  543. for_each_pipe(pipe)
  544. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  545. pipe_name(pipe),
  546. I915_READ(FDI_RX_IIR(pipe)));
  547. }
  548. static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
  549. {
  550. struct drm_device *dev = (struct drm_device *) arg;
  551. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  552. u32 de_iir, gt_iir, de_ier, pm_iir;
  553. irqreturn_t ret = IRQ_NONE;
  554. int i;
  555. atomic_inc(&dev_priv->irq_received);
  556. /* disable master interrupt before clearing iir */
  557. de_ier = I915_READ(DEIER);
  558. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  559. gt_iir = I915_READ(GTIIR);
  560. if (gt_iir) {
  561. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  562. I915_WRITE(GTIIR, gt_iir);
  563. ret = IRQ_HANDLED;
  564. }
  565. de_iir = I915_READ(DEIIR);
  566. if (de_iir) {
  567. if (de_iir & DE_GSE_IVB)
  568. intel_opregion_gse_intr(dev);
  569. for (i = 0; i < 3; i++) {
  570. if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
  571. drm_handle_vblank(dev, i);
  572. if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
  573. intel_prepare_page_flip(dev, i);
  574. intel_finish_page_flip_plane(dev, i);
  575. }
  576. }
  577. /* check event from PCH */
  578. if (de_iir & DE_PCH_EVENT_IVB) {
  579. u32 pch_iir = I915_READ(SDEIIR);
  580. if (pch_iir & SDE_HOTPLUG_MASK_CPT)
  581. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  582. cpt_irq_handler(dev, pch_iir);
  583. /* clear PCH hotplug event before clear CPU irq */
  584. I915_WRITE(SDEIIR, pch_iir);
  585. }
  586. I915_WRITE(DEIIR, de_iir);
  587. ret = IRQ_HANDLED;
  588. }
  589. pm_iir = I915_READ(GEN6_PMIIR);
  590. if (pm_iir) {
  591. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  592. gen6_queue_rps_work(dev_priv, pm_iir);
  593. I915_WRITE(GEN6_PMIIR, pm_iir);
  594. ret = IRQ_HANDLED;
  595. }
  596. I915_WRITE(DEIER, de_ier);
  597. POSTING_READ(DEIER);
  598. return ret;
  599. }
  600. static void ilk_gt_irq_handler(struct drm_device *dev,
  601. struct drm_i915_private *dev_priv,
  602. u32 gt_iir)
  603. {
  604. if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
  605. notify_ring(dev, &dev_priv->ring[RCS]);
  606. if (gt_iir & GT_BSD_USER_INTERRUPT)
  607. notify_ring(dev, &dev_priv->ring[VCS]);
  608. }
  609. static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
  610. {
  611. struct drm_device *dev = (struct drm_device *) arg;
  612. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  613. int ret = IRQ_NONE;
  614. u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
  615. u32 hotplug_mask;
  616. atomic_inc(&dev_priv->irq_received);
  617. /* disable master interrupt before clearing iir */
  618. de_ier = I915_READ(DEIER);
  619. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  620. POSTING_READ(DEIER);
  621. de_iir = I915_READ(DEIIR);
  622. gt_iir = I915_READ(GTIIR);
  623. pch_iir = I915_READ(SDEIIR);
  624. pm_iir = I915_READ(GEN6_PMIIR);
  625. if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
  626. (!IS_GEN6(dev) || pm_iir == 0))
  627. goto done;
  628. if (HAS_PCH_CPT(dev))
  629. hotplug_mask = SDE_HOTPLUG_MASK_CPT;
  630. else
  631. hotplug_mask = SDE_HOTPLUG_MASK;
  632. ret = IRQ_HANDLED;
  633. if (IS_GEN5(dev))
  634. ilk_gt_irq_handler(dev, dev_priv, gt_iir);
  635. else
  636. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  637. if (de_iir & DE_GSE)
  638. intel_opregion_gse_intr(dev);
  639. if (de_iir & DE_PIPEA_VBLANK)
  640. drm_handle_vblank(dev, 0);
  641. if (de_iir & DE_PIPEB_VBLANK)
  642. drm_handle_vblank(dev, 1);
  643. if (de_iir & DE_PLANEA_FLIP_DONE) {
  644. intel_prepare_page_flip(dev, 0);
  645. intel_finish_page_flip_plane(dev, 0);
  646. }
  647. if (de_iir & DE_PLANEB_FLIP_DONE) {
  648. intel_prepare_page_flip(dev, 1);
  649. intel_finish_page_flip_plane(dev, 1);
  650. }
  651. /* check event from PCH */
  652. if (de_iir & DE_PCH_EVENT) {
  653. if (pch_iir & hotplug_mask)
  654. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  655. if (HAS_PCH_CPT(dev))
  656. cpt_irq_handler(dev, pch_iir);
  657. else
  658. ibx_irq_handler(dev, pch_iir);
  659. }
  660. if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
  661. ironlake_handle_rps_change(dev);
  662. if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
  663. gen6_queue_rps_work(dev_priv, pm_iir);
  664. /* should clear PCH hotplug event before clear CPU irq */
  665. I915_WRITE(SDEIIR, pch_iir);
  666. I915_WRITE(GTIIR, gt_iir);
  667. I915_WRITE(DEIIR, de_iir);
  668. I915_WRITE(GEN6_PMIIR, pm_iir);
  669. done:
  670. I915_WRITE(DEIER, de_ier);
  671. POSTING_READ(DEIER);
  672. return ret;
  673. }
  674. /**
  675. * i915_error_work_func - do process context error handling work
  676. * @work: work struct
  677. *
  678. * Fire an error uevent so userspace can see that a hang or error
  679. * was detected.
  680. */
  681. static void i915_error_work_func(struct work_struct *work)
  682. {
  683. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  684. error_work);
  685. struct drm_device *dev = dev_priv->dev;
  686. char *error_event[] = { "ERROR=1", NULL };
  687. char *reset_event[] = { "RESET=1", NULL };
  688. char *reset_done_event[] = { "ERROR=0", NULL };
  689. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  690. if (atomic_read(&dev_priv->mm.wedged)) {
  691. DRM_DEBUG_DRIVER("resetting chip\n");
  692. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
  693. if (!i915_reset(dev)) {
  694. atomic_set(&dev_priv->mm.wedged, 0);
  695. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
  696. }
  697. complete_all(&dev_priv->error_completion);
  698. }
  699. }
  700. /* NB: please notice the memset */
  701. static void i915_get_extra_instdone(struct drm_device *dev,
  702. uint32_t *instdone)
  703. {
  704. struct drm_i915_private *dev_priv = dev->dev_private;
  705. memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
  706. switch(INTEL_INFO(dev)->gen) {
  707. case 2:
  708. case 3:
  709. instdone[0] = I915_READ(INSTDONE);
  710. break;
  711. case 4:
  712. case 5:
  713. case 6:
  714. instdone[0] = I915_READ(INSTDONE_I965);
  715. instdone[1] = I915_READ(INSTDONE1);
  716. break;
  717. default:
  718. WARN_ONCE(1, "Unsupported platform\n");
  719. case 7:
  720. instdone[0] = I915_READ(GEN7_INSTDONE_1);
  721. instdone[1] = I915_READ(GEN7_SC_INSTDONE);
  722. instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
  723. instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
  724. break;
  725. }
  726. }
  727. #ifdef CONFIG_DEBUG_FS
  728. static struct drm_i915_error_object *
  729. i915_error_object_create(struct drm_i915_private *dev_priv,
  730. struct drm_i915_gem_object *src)
  731. {
  732. struct drm_i915_error_object *dst;
  733. int i, count;
  734. u32 reloc_offset;
  735. if (src == NULL || src->pages == NULL)
  736. return NULL;
  737. count = src->base.size / PAGE_SIZE;
  738. dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
  739. if (dst == NULL)
  740. return NULL;
  741. reloc_offset = src->gtt_offset;
  742. for (i = 0; i < count; i++) {
  743. unsigned long flags;
  744. void *d;
  745. d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
  746. if (d == NULL)
  747. goto unwind;
  748. local_irq_save(flags);
  749. if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
  750. src->has_global_gtt_mapping) {
  751. void __iomem *s;
  752. /* Simply ignore tiling or any overlapping fence.
  753. * It's part of the error state, and this hopefully
  754. * captures what the GPU read.
  755. */
  756. s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
  757. reloc_offset);
  758. memcpy_fromio(d, s, PAGE_SIZE);
  759. io_mapping_unmap_atomic(s);
  760. } else {
  761. struct page *page;
  762. void *s;
  763. page = i915_gem_object_get_page(src, i);
  764. drm_clflush_pages(&page, 1);
  765. s = kmap_atomic(page);
  766. memcpy(d, s, PAGE_SIZE);
  767. kunmap_atomic(s);
  768. drm_clflush_pages(&page, 1);
  769. }
  770. local_irq_restore(flags);
  771. dst->pages[i] = d;
  772. reloc_offset += PAGE_SIZE;
  773. }
  774. dst->page_count = count;
  775. dst->gtt_offset = src->gtt_offset;
  776. return dst;
  777. unwind:
  778. while (i--)
  779. kfree(dst->pages[i]);
  780. kfree(dst);
  781. return NULL;
  782. }
  783. static void
  784. i915_error_object_free(struct drm_i915_error_object *obj)
  785. {
  786. int page;
  787. if (obj == NULL)
  788. return;
  789. for (page = 0; page < obj->page_count; page++)
  790. kfree(obj->pages[page]);
  791. kfree(obj);
  792. }
  793. void
  794. i915_error_state_free(struct kref *error_ref)
  795. {
  796. struct drm_i915_error_state *error = container_of(error_ref,
  797. typeof(*error), ref);
  798. int i;
  799. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  800. i915_error_object_free(error->ring[i].batchbuffer);
  801. i915_error_object_free(error->ring[i].ringbuffer);
  802. kfree(error->ring[i].requests);
  803. }
  804. kfree(error->active_bo);
  805. kfree(error->overlay);
  806. kfree(error);
  807. }
  808. static void capture_bo(struct drm_i915_error_buffer *err,
  809. struct drm_i915_gem_object *obj)
  810. {
  811. err->size = obj->base.size;
  812. err->name = obj->base.name;
  813. err->rseqno = obj->last_read_seqno;
  814. err->wseqno = obj->last_write_seqno;
  815. err->gtt_offset = obj->gtt_offset;
  816. err->read_domains = obj->base.read_domains;
  817. err->write_domain = obj->base.write_domain;
  818. err->fence_reg = obj->fence_reg;
  819. err->pinned = 0;
  820. if (obj->pin_count > 0)
  821. err->pinned = 1;
  822. if (obj->user_pin_count > 0)
  823. err->pinned = -1;
  824. err->tiling = obj->tiling_mode;
  825. err->dirty = obj->dirty;
  826. err->purgeable = obj->madv != I915_MADV_WILLNEED;
  827. err->ring = obj->ring ? obj->ring->id : -1;
  828. err->cache_level = obj->cache_level;
  829. }
  830. static u32 capture_active_bo(struct drm_i915_error_buffer *err,
  831. int count, struct list_head *head)
  832. {
  833. struct drm_i915_gem_object *obj;
  834. int i = 0;
  835. list_for_each_entry(obj, head, mm_list) {
  836. capture_bo(err++, obj);
  837. if (++i == count)
  838. break;
  839. }
  840. return i;
  841. }
  842. static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
  843. int count, struct list_head *head)
  844. {
  845. struct drm_i915_gem_object *obj;
  846. int i = 0;
  847. list_for_each_entry(obj, head, gtt_list) {
  848. if (obj->pin_count == 0)
  849. continue;
  850. capture_bo(err++, obj);
  851. if (++i == count)
  852. break;
  853. }
  854. return i;
  855. }
  856. static void i915_gem_record_fences(struct drm_device *dev,
  857. struct drm_i915_error_state *error)
  858. {
  859. struct drm_i915_private *dev_priv = dev->dev_private;
  860. int i;
  861. /* Fences */
  862. switch (INTEL_INFO(dev)->gen) {
  863. case 7:
  864. case 6:
  865. for (i = 0; i < 16; i++)
  866. error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
  867. break;
  868. case 5:
  869. case 4:
  870. for (i = 0; i < 16; i++)
  871. error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
  872. break;
  873. case 3:
  874. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  875. for (i = 0; i < 8; i++)
  876. error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
  877. case 2:
  878. for (i = 0; i < 8; i++)
  879. error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
  880. break;
  881. }
  882. }
  883. static struct drm_i915_error_object *
  884. i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
  885. struct intel_ring_buffer *ring)
  886. {
  887. struct drm_i915_gem_object *obj;
  888. u32 seqno;
  889. if (!ring->get_seqno)
  890. return NULL;
  891. seqno = ring->get_seqno(ring, false);
  892. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  893. if (obj->ring != ring)
  894. continue;
  895. if (i915_seqno_passed(seqno, obj->last_read_seqno))
  896. continue;
  897. if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
  898. continue;
  899. /* We need to copy these to an anonymous buffer as the simplest
  900. * method to avoid being overwritten by userspace.
  901. */
  902. return i915_error_object_create(dev_priv, obj);
  903. }
  904. return NULL;
  905. }
  906. static void i915_record_ring_state(struct drm_device *dev,
  907. struct drm_i915_error_state *error,
  908. struct intel_ring_buffer *ring)
  909. {
  910. struct drm_i915_private *dev_priv = dev->dev_private;
  911. if (INTEL_INFO(dev)->gen >= 6) {
  912. error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
  913. error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
  914. error->semaphore_mboxes[ring->id][0]
  915. = I915_READ(RING_SYNC_0(ring->mmio_base));
  916. error->semaphore_mboxes[ring->id][1]
  917. = I915_READ(RING_SYNC_1(ring->mmio_base));
  918. }
  919. if (INTEL_INFO(dev)->gen >= 4) {
  920. error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
  921. error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
  922. error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
  923. error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
  924. error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
  925. if (ring->id == RCS)
  926. error->bbaddr = I915_READ64(BB_ADDR);
  927. } else {
  928. error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
  929. error->ipeir[ring->id] = I915_READ(IPEIR);
  930. error->ipehr[ring->id] = I915_READ(IPEHR);
  931. error->instdone[ring->id] = I915_READ(INSTDONE);
  932. }
  933. error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
  934. error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
  935. error->seqno[ring->id] = ring->get_seqno(ring, false);
  936. error->acthd[ring->id] = intel_ring_get_active_head(ring);
  937. error->head[ring->id] = I915_READ_HEAD(ring);
  938. error->tail[ring->id] = I915_READ_TAIL(ring);
  939. error->cpu_ring_head[ring->id] = ring->head;
  940. error->cpu_ring_tail[ring->id] = ring->tail;
  941. }
  942. static void i915_gem_record_rings(struct drm_device *dev,
  943. struct drm_i915_error_state *error)
  944. {
  945. struct drm_i915_private *dev_priv = dev->dev_private;
  946. struct intel_ring_buffer *ring;
  947. struct drm_i915_gem_request *request;
  948. int i, count;
  949. for_each_ring(ring, dev_priv, i) {
  950. i915_record_ring_state(dev, error, ring);
  951. error->ring[i].batchbuffer =
  952. i915_error_first_batchbuffer(dev_priv, ring);
  953. error->ring[i].ringbuffer =
  954. i915_error_object_create(dev_priv, ring->obj);
  955. count = 0;
  956. list_for_each_entry(request, &ring->request_list, list)
  957. count++;
  958. error->ring[i].num_requests = count;
  959. error->ring[i].requests =
  960. kmalloc(count*sizeof(struct drm_i915_error_request),
  961. GFP_ATOMIC);
  962. if (error->ring[i].requests == NULL) {
  963. error->ring[i].num_requests = 0;
  964. continue;
  965. }
  966. count = 0;
  967. list_for_each_entry(request, &ring->request_list, list) {
  968. struct drm_i915_error_request *erq;
  969. erq = &error->ring[i].requests[count++];
  970. erq->seqno = request->seqno;
  971. erq->jiffies = request->emitted_jiffies;
  972. erq->tail = request->tail;
  973. }
  974. }
  975. }
  976. /**
  977. * i915_capture_error_state - capture an error record for later analysis
  978. * @dev: drm device
  979. *
  980. * Should be called when an error is detected (either a hang or an error
  981. * interrupt) to capture error state from the time of the error. Fills
  982. * out a structure which becomes available in debugfs for user level tools
  983. * to pick up.
  984. */
  985. static void i915_capture_error_state(struct drm_device *dev)
  986. {
  987. struct drm_i915_private *dev_priv = dev->dev_private;
  988. struct drm_i915_gem_object *obj;
  989. struct drm_i915_error_state *error;
  990. unsigned long flags;
  991. int i, pipe;
  992. spin_lock_irqsave(&dev_priv->error_lock, flags);
  993. error = dev_priv->first_error;
  994. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  995. if (error)
  996. return;
  997. /* Account for pipe specific data like PIPE*STAT */
  998. error = kzalloc(sizeof(*error), GFP_ATOMIC);
  999. if (!error) {
  1000. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  1001. return;
  1002. }
  1003. DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
  1004. dev->primary->index);
  1005. kref_init(&error->ref);
  1006. error->eir = I915_READ(EIR);
  1007. error->pgtbl_er = I915_READ(PGTBL_ER);
  1008. error->ccid = I915_READ(CCID);
  1009. if (HAS_PCH_SPLIT(dev))
  1010. error->ier = I915_READ(DEIER) | I915_READ(GTIER);
  1011. else if (IS_VALLEYVIEW(dev))
  1012. error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
  1013. else if (IS_GEN2(dev))
  1014. error->ier = I915_READ16(IER);
  1015. else
  1016. error->ier = I915_READ(IER);
  1017. for_each_pipe(pipe)
  1018. error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
  1019. if (INTEL_INFO(dev)->gen >= 6) {
  1020. error->error = I915_READ(ERROR_GEN6);
  1021. error->done_reg = I915_READ(DONE_REG);
  1022. }
  1023. if (INTEL_INFO(dev)->gen == 7)
  1024. error->err_int = I915_READ(GEN7_ERR_INT);
  1025. i915_get_extra_instdone(dev, error->extra_instdone);
  1026. i915_gem_record_fences(dev, error);
  1027. i915_gem_record_rings(dev, error);
  1028. /* Record buffers on the active and pinned lists. */
  1029. error->active_bo = NULL;
  1030. error->pinned_bo = NULL;
  1031. i = 0;
  1032. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
  1033. i++;
  1034. error->active_bo_count = i;
  1035. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
  1036. if (obj->pin_count)
  1037. i++;
  1038. error->pinned_bo_count = i - error->active_bo_count;
  1039. error->active_bo = NULL;
  1040. error->pinned_bo = NULL;
  1041. if (i) {
  1042. error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
  1043. GFP_ATOMIC);
  1044. if (error->active_bo)
  1045. error->pinned_bo =
  1046. error->active_bo + error->active_bo_count;
  1047. }
  1048. if (error->active_bo)
  1049. error->active_bo_count =
  1050. capture_active_bo(error->active_bo,
  1051. error->active_bo_count,
  1052. &dev_priv->mm.active_list);
  1053. if (error->pinned_bo)
  1054. error->pinned_bo_count =
  1055. capture_pinned_bo(error->pinned_bo,
  1056. error->pinned_bo_count,
  1057. &dev_priv->mm.bound_list);
  1058. do_gettimeofday(&error->time);
  1059. error->overlay = intel_overlay_capture_error_state(dev);
  1060. error->display = intel_display_capture_error_state(dev);
  1061. spin_lock_irqsave(&dev_priv->error_lock, flags);
  1062. if (dev_priv->first_error == NULL) {
  1063. dev_priv->first_error = error;
  1064. error = NULL;
  1065. }
  1066. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  1067. if (error)
  1068. i915_error_state_free(&error->ref);
  1069. }
  1070. void i915_destroy_error_state(struct drm_device *dev)
  1071. {
  1072. struct drm_i915_private *dev_priv = dev->dev_private;
  1073. struct drm_i915_error_state *error;
  1074. unsigned long flags;
  1075. spin_lock_irqsave(&dev_priv->error_lock, flags);
  1076. error = dev_priv->first_error;
  1077. dev_priv->first_error = NULL;
  1078. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  1079. if (error)
  1080. kref_put(&error->ref, i915_error_state_free);
  1081. }
  1082. #else
  1083. #define i915_capture_error_state(x)
  1084. #endif
  1085. static void i915_report_and_clear_eir(struct drm_device *dev)
  1086. {
  1087. struct drm_i915_private *dev_priv = dev->dev_private;
  1088. uint32_t instdone[I915_NUM_INSTDONE_REG];
  1089. u32 eir = I915_READ(EIR);
  1090. int pipe, i;
  1091. if (!eir)
  1092. return;
  1093. pr_err("render error detected, EIR: 0x%08x\n", eir);
  1094. i915_get_extra_instdone(dev, instdone);
  1095. if (IS_G4X(dev)) {
  1096. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  1097. u32 ipeir = I915_READ(IPEIR_I965);
  1098. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1099. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1100. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1101. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1102. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1103. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1104. I915_WRITE(IPEIR_I965, ipeir);
  1105. POSTING_READ(IPEIR_I965);
  1106. }
  1107. if (eir & GM45_ERROR_PAGE_TABLE) {
  1108. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1109. pr_err("page table error\n");
  1110. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1111. I915_WRITE(PGTBL_ER, pgtbl_err);
  1112. POSTING_READ(PGTBL_ER);
  1113. }
  1114. }
  1115. if (!IS_GEN2(dev)) {
  1116. if (eir & I915_ERROR_PAGE_TABLE) {
  1117. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1118. pr_err("page table error\n");
  1119. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1120. I915_WRITE(PGTBL_ER, pgtbl_err);
  1121. POSTING_READ(PGTBL_ER);
  1122. }
  1123. }
  1124. if (eir & I915_ERROR_MEMORY_REFRESH) {
  1125. pr_err("memory refresh error:\n");
  1126. for_each_pipe(pipe)
  1127. pr_err("pipe %c stat: 0x%08x\n",
  1128. pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
  1129. /* pipestat has already been acked */
  1130. }
  1131. if (eir & I915_ERROR_INSTRUCTION) {
  1132. pr_err("instruction error\n");
  1133. pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
  1134. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1135. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1136. if (INTEL_INFO(dev)->gen < 4) {
  1137. u32 ipeir = I915_READ(IPEIR);
  1138. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
  1139. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
  1140. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
  1141. I915_WRITE(IPEIR, ipeir);
  1142. POSTING_READ(IPEIR);
  1143. } else {
  1144. u32 ipeir = I915_READ(IPEIR_I965);
  1145. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1146. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1147. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1148. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1149. I915_WRITE(IPEIR_I965, ipeir);
  1150. POSTING_READ(IPEIR_I965);
  1151. }
  1152. }
  1153. I915_WRITE(EIR, eir);
  1154. POSTING_READ(EIR);
  1155. eir = I915_READ(EIR);
  1156. if (eir) {
  1157. /*
  1158. * some errors might have become stuck,
  1159. * mask them.
  1160. */
  1161. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  1162. I915_WRITE(EMR, I915_READ(EMR) | eir);
  1163. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1164. }
  1165. }
  1166. /**
  1167. * i915_handle_error - handle an error interrupt
  1168. * @dev: drm device
  1169. *
  1170. * Do some basic checking of regsiter state at error interrupt time and
  1171. * dump it to the syslog. Also call i915_capture_error_state() to make
  1172. * sure we get a record and make it available in debugfs. Fire a uevent
  1173. * so userspace knows something bad happened (should trigger collection
  1174. * of a ring dump etc.).
  1175. */
  1176. void i915_handle_error(struct drm_device *dev, bool wedged)
  1177. {
  1178. struct drm_i915_private *dev_priv = dev->dev_private;
  1179. struct intel_ring_buffer *ring;
  1180. int i;
  1181. i915_capture_error_state(dev);
  1182. i915_report_and_clear_eir(dev);
  1183. if (wedged) {
  1184. INIT_COMPLETION(dev_priv->error_completion);
  1185. atomic_set(&dev_priv->mm.wedged, 1);
  1186. /*
  1187. * Wakeup waiting processes so they don't hang
  1188. */
  1189. for_each_ring(ring, dev_priv, i)
  1190. wake_up_all(&ring->irq_queue);
  1191. }
  1192. queue_work(dev_priv->wq, &dev_priv->error_work);
  1193. }
  1194. static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
  1195. {
  1196. drm_i915_private_t *dev_priv = dev->dev_private;
  1197. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1198. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1199. struct drm_i915_gem_object *obj;
  1200. struct intel_unpin_work *work;
  1201. unsigned long flags;
  1202. bool stall_detected;
  1203. /* Ignore early vblank irqs */
  1204. if (intel_crtc == NULL)
  1205. return;
  1206. spin_lock_irqsave(&dev->event_lock, flags);
  1207. work = intel_crtc->unpin_work;
  1208. if (work == NULL || work->pending || !work->enable_stall_check) {
  1209. /* Either the pending flip IRQ arrived, or we're too early. Don't check */
  1210. spin_unlock_irqrestore(&dev->event_lock, flags);
  1211. return;
  1212. }
  1213. /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
  1214. obj = work->pending_flip_obj;
  1215. if (INTEL_INFO(dev)->gen >= 4) {
  1216. int dspsurf = DSPSURF(intel_crtc->plane);
  1217. stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
  1218. obj->gtt_offset;
  1219. } else {
  1220. int dspaddr = DSPADDR(intel_crtc->plane);
  1221. stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
  1222. crtc->y * crtc->fb->pitches[0] +
  1223. crtc->x * crtc->fb->bits_per_pixel/8);
  1224. }
  1225. spin_unlock_irqrestore(&dev->event_lock, flags);
  1226. if (stall_detected) {
  1227. DRM_DEBUG_DRIVER("Pageflip stall detected\n");
  1228. intel_prepare_page_flip(dev, intel_crtc->plane);
  1229. }
  1230. }
  1231. /* Called from drm generic code, passed 'crtc' which
  1232. * we use as a pipe index
  1233. */
  1234. static int i915_enable_vblank(struct drm_device *dev, int pipe)
  1235. {
  1236. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1237. unsigned long irqflags;
  1238. if (!i915_pipe_enabled(dev, pipe))
  1239. return -EINVAL;
  1240. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1241. if (INTEL_INFO(dev)->gen >= 4)
  1242. i915_enable_pipestat(dev_priv, pipe,
  1243. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1244. else
  1245. i915_enable_pipestat(dev_priv, pipe,
  1246. PIPE_VBLANK_INTERRUPT_ENABLE);
  1247. /* maintain vblank delivery even in deep C-states */
  1248. if (dev_priv->info->gen == 3)
  1249. I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
  1250. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1251. return 0;
  1252. }
  1253. static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
  1254. {
  1255. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1256. unsigned long irqflags;
  1257. if (!i915_pipe_enabled(dev, pipe))
  1258. return -EINVAL;
  1259. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1260. ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
  1261. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1262. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1263. return 0;
  1264. }
  1265. static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
  1266. {
  1267. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1268. unsigned long irqflags;
  1269. if (!i915_pipe_enabled(dev, pipe))
  1270. return -EINVAL;
  1271. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1272. ironlake_enable_display_irq(dev_priv,
  1273. DE_PIPEA_VBLANK_IVB << (5 * pipe));
  1274. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1275. return 0;
  1276. }
  1277. static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
  1278. {
  1279. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1280. unsigned long irqflags;
  1281. u32 imr;
  1282. if (!i915_pipe_enabled(dev, pipe))
  1283. return -EINVAL;
  1284. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1285. imr = I915_READ(VLV_IMR);
  1286. if (pipe == 0)
  1287. imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1288. else
  1289. imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1290. I915_WRITE(VLV_IMR, imr);
  1291. i915_enable_pipestat(dev_priv, pipe,
  1292. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1293. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1294. return 0;
  1295. }
  1296. /* Called from drm generic code, passed 'crtc' which
  1297. * we use as a pipe index
  1298. */
  1299. static void i915_disable_vblank(struct drm_device *dev, int pipe)
  1300. {
  1301. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1302. unsigned long irqflags;
  1303. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1304. if (dev_priv->info->gen == 3)
  1305. I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
  1306. i915_disable_pipestat(dev_priv, pipe,
  1307. PIPE_VBLANK_INTERRUPT_ENABLE |
  1308. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1309. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1310. }
  1311. static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
  1312. {
  1313. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1314. unsigned long irqflags;
  1315. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1316. ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
  1317. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1318. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1319. }
  1320. static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
  1321. {
  1322. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1323. unsigned long irqflags;
  1324. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1325. ironlake_disable_display_irq(dev_priv,
  1326. DE_PIPEA_VBLANK_IVB << (pipe * 5));
  1327. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1328. }
  1329. static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
  1330. {
  1331. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1332. unsigned long irqflags;
  1333. u32 imr;
  1334. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1335. i915_disable_pipestat(dev_priv, pipe,
  1336. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1337. imr = I915_READ(VLV_IMR);
  1338. if (pipe == 0)
  1339. imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1340. else
  1341. imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1342. I915_WRITE(VLV_IMR, imr);
  1343. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1344. }
  1345. static u32
  1346. ring_last_seqno(struct intel_ring_buffer *ring)
  1347. {
  1348. return list_entry(ring->request_list.prev,
  1349. struct drm_i915_gem_request, list)->seqno;
  1350. }
  1351. static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
  1352. {
  1353. if (list_empty(&ring->request_list) ||
  1354. i915_seqno_passed(ring->get_seqno(ring, false),
  1355. ring_last_seqno(ring))) {
  1356. /* Issue a wake-up to catch stuck h/w. */
  1357. if (waitqueue_active(&ring->irq_queue)) {
  1358. DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
  1359. ring->name);
  1360. wake_up_all(&ring->irq_queue);
  1361. *err = true;
  1362. }
  1363. return true;
  1364. }
  1365. return false;
  1366. }
  1367. static bool kick_ring(struct intel_ring_buffer *ring)
  1368. {
  1369. struct drm_device *dev = ring->dev;
  1370. struct drm_i915_private *dev_priv = dev->dev_private;
  1371. u32 tmp = I915_READ_CTL(ring);
  1372. if (tmp & RING_WAIT) {
  1373. DRM_ERROR("Kicking stuck wait on %s\n",
  1374. ring->name);
  1375. I915_WRITE_CTL(ring, tmp);
  1376. return true;
  1377. }
  1378. return false;
  1379. }
  1380. static bool i915_hangcheck_hung(struct drm_device *dev)
  1381. {
  1382. drm_i915_private_t *dev_priv = dev->dev_private;
  1383. if (dev_priv->hangcheck_count++ > 1) {
  1384. bool hung = true;
  1385. DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
  1386. i915_handle_error(dev, true);
  1387. if (!IS_GEN2(dev)) {
  1388. struct intel_ring_buffer *ring;
  1389. int i;
  1390. /* Is the chip hanging on a WAIT_FOR_EVENT?
  1391. * If so we can simply poke the RB_WAIT bit
  1392. * and break the hang. This should work on
  1393. * all but the second generation chipsets.
  1394. */
  1395. for_each_ring(ring, dev_priv, i)
  1396. hung &= !kick_ring(ring);
  1397. }
  1398. return hung;
  1399. }
  1400. return false;
  1401. }
  1402. /**
  1403. * This is called when the chip hasn't reported back with completed
  1404. * batchbuffers in a long time. The first time this is called we simply record
  1405. * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
  1406. * again, we assume the chip is wedged and try to fix it.
  1407. */
  1408. void i915_hangcheck_elapsed(unsigned long data)
  1409. {
  1410. struct drm_device *dev = (struct drm_device *)data;
  1411. drm_i915_private_t *dev_priv = dev->dev_private;
  1412. uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
  1413. struct intel_ring_buffer *ring;
  1414. bool err = false, idle;
  1415. int i;
  1416. if (!i915_enable_hangcheck)
  1417. return;
  1418. memset(acthd, 0, sizeof(acthd));
  1419. idle = true;
  1420. for_each_ring(ring, dev_priv, i) {
  1421. idle &= i915_hangcheck_ring_idle(ring, &err);
  1422. acthd[i] = intel_ring_get_active_head(ring);
  1423. }
  1424. /* If all work is done then ACTHD clearly hasn't advanced. */
  1425. if (idle) {
  1426. if (err) {
  1427. if (i915_hangcheck_hung(dev))
  1428. return;
  1429. goto repeat;
  1430. }
  1431. dev_priv->hangcheck_count = 0;
  1432. return;
  1433. }
  1434. i915_get_extra_instdone(dev, instdone);
  1435. if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
  1436. memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
  1437. if (i915_hangcheck_hung(dev))
  1438. return;
  1439. } else {
  1440. dev_priv->hangcheck_count = 0;
  1441. memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
  1442. memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
  1443. }
  1444. repeat:
  1445. /* Reset timer case chip hangs without another request being added */
  1446. mod_timer(&dev_priv->hangcheck_timer,
  1447. jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
  1448. }
  1449. /* drm_dma.h hooks
  1450. */
  1451. static void ironlake_irq_preinstall(struct drm_device *dev)
  1452. {
  1453. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1454. atomic_set(&dev_priv->irq_received, 0);
  1455. I915_WRITE(HWSTAM, 0xeffe);
  1456. /* XXX hotplug from PCH */
  1457. I915_WRITE(DEIMR, 0xffffffff);
  1458. I915_WRITE(DEIER, 0x0);
  1459. POSTING_READ(DEIER);
  1460. /* and GT */
  1461. I915_WRITE(GTIMR, 0xffffffff);
  1462. I915_WRITE(GTIER, 0x0);
  1463. POSTING_READ(GTIER);
  1464. /* south display irq */
  1465. I915_WRITE(SDEIMR, 0xffffffff);
  1466. I915_WRITE(SDEIER, 0x0);
  1467. POSTING_READ(SDEIER);
  1468. }
  1469. static void valleyview_irq_preinstall(struct drm_device *dev)
  1470. {
  1471. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1472. int pipe;
  1473. atomic_set(&dev_priv->irq_received, 0);
  1474. /* VLV magic */
  1475. I915_WRITE(VLV_IMR, 0);
  1476. I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
  1477. I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
  1478. I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
  1479. /* and GT */
  1480. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1481. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1482. I915_WRITE(GTIMR, 0xffffffff);
  1483. I915_WRITE(GTIER, 0x0);
  1484. POSTING_READ(GTIER);
  1485. I915_WRITE(DPINVGTT, 0xff);
  1486. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1487. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1488. for_each_pipe(pipe)
  1489. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1490. I915_WRITE(VLV_IIR, 0xffffffff);
  1491. I915_WRITE(VLV_IMR, 0xffffffff);
  1492. I915_WRITE(VLV_IER, 0x0);
  1493. POSTING_READ(VLV_IER);
  1494. }
  1495. /*
  1496. * Enable digital hotplug on the PCH, and configure the DP short pulse
  1497. * duration to 2ms (which is the minimum in the Display Port spec)
  1498. *
  1499. * This register is the same on all known PCH chips.
  1500. */
  1501. static void ironlake_enable_pch_hotplug(struct drm_device *dev)
  1502. {
  1503. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1504. u32 hotplug;
  1505. hotplug = I915_READ(PCH_PORT_HOTPLUG);
  1506. hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
  1507. hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
  1508. hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
  1509. hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
  1510. I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
  1511. }
  1512. static int ironlake_irq_postinstall(struct drm_device *dev)
  1513. {
  1514. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1515. /* enable kind of interrupts always enabled */
  1516. u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
  1517. DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
  1518. u32 render_irqs;
  1519. u32 hotplug_mask;
  1520. dev_priv->irq_mask = ~display_mask;
  1521. /* should always can generate irq */
  1522. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1523. I915_WRITE(DEIMR, dev_priv->irq_mask);
  1524. I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
  1525. POSTING_READ(DEIER);
  1526. dev_priv->gt_irq_mask = ~0;
  1527. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1528. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1529. if (IS_GEN6(dev))
  1530. render_irqs =
  1531. GT_USER_INTERRUPT |
  1532. GEN6_BSD_USER_INTERRUPT |
  1533. GEN6_BLITTER_USER_INTERRUPT;
  1534. else
  1535. render_irqs =
  1536. GT_USER_INTERRUPT |
  1537. GT_PIPE_NOTIFY |
  1538. GT_BSD_USER_INTERRUPT;
  1539. I915_WRITE(GTIER, render_irqs);
  1540. POSTING_READ(GTIER);
  1541. if (HAS_PCH_CPT(dev)) {
  1542. hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
  1543. SDE_PORTB_HOTPLUG_CPT |
  1544. SDE_PORTC_HOTPLUG_CPT |
  1545. SDE_PORTD_HOTPLUG_CPT);
  1546. } else {
  1547. hotplug_mask = (SDE_CRT_HOTPLUG |
  1548. SDE_PORTB_HOTPLUG |
  1549. SDE_PORTC_HOTPLUG |
  1550. SDE_PORTD_HOTPLUG |
  1551. SDE_AUX_MASK);
  1552. }
  1553. dev_priv->pch_irq_mask = ~hotplug_mask;
  1554. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1555. I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
  1556. I915_WRITE(SDEIER, hotplug_mask);
  1557. POSTING_READ(SDEIER);
  1558. ironlake_enable_pch_hotplug(dev);
  1559. if (IS_IRONLAKE_M(dev)) {
  1560. /* Clear & enable PCU event interrupts */
  1561. I915_WRITE(DEIIR, DE_PCU_EVENT);
  1562. I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
  1563. ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
  1564. }
  1565. return 0;
  1566. }
  1567. static int ivybridge_irq_postinstall(struct drm_device *dev)
  1568. {
  1569. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1570. /* enable kind of interrupts always enabled */
  1571. u32 display_mask =
  1572. DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
  1573. DE_PLANEC_FLIP_DONE_IVB |
  1574. DE_PLANEB_FLIP_DONE_IVB |
  1575. DE_PLANEA_FLIP_DONE_IVB;
  1576. u32 render_irqs;
  1577. u32 hotplug_mask;
  1578. dev_priv->irq_mask = ~display_mask;
  1579. /* should always can generate irq */
  1580. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1581. I915_WRITE(DEIMR, dev_priv->irq_mask);
  1582. I915_WRITE(DEIER,
  1583. display_mask |
  1584. DE_PIPEC_VBLANK_IVB |
  1585. DE_PIPEB_VBLANK_IVB |
  1586. DE_PIPEA_VBLANK_IVB);
  1587. POSTING_READ(DEIER);
  1588. dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  1589. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1590. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1591. render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
  1592. GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  1593. I915_WRITE(GTIER, render_irqs);
  1594. POSTING_READ(GTIER);
  1595. hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
  1596. SDE_PORTB_HOTPLUG_CPT |
  1597. SDE_PORTC_HOTPLUG_CPT |
  1598. SDE_PORTD_HOTPLUG_CPT);
  1599. dev_priv->pch_irq_mask = ~hotplug_mask;
  1600. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1601. I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
  1602. I915_WRITE(SDEIER, hotplug_mask);
  1603. POSTING_READ(SDEIER);
  1604. ironlake_enable_pch_hotplug(dev);
  1605. return 0;
  1606. }
  1607. static int valleyview_irq_postinstall(struct drm_device *dev)
  1608. {
  1609. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1610. u32 enable_mask;
  1611. u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  1612. u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
  1613. u16 msid;
  1614. enable_mask = I915_DISPLAY_PORT_INTERRUPT;
  1615. enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1616. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  1617. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1618. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1619. /*
  1620. *Leave vblank interrupts masked initially. enable/disable will
  1621. * toggle them based on usage.
  1622. */
  1623. dev_priv->irq_mask = (~enable_mask) |
  1624. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  1625. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1626. dev_priv->pipestat[0] = 0;
  1627. dev_priv->pipestat[1] = 0;
  1628. /* Hack for broken MSIs on VLV */
  1629. pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
  1630. pci_read_config_word(dev->pdev, 0x98, &msid);
  1631. msid &= 0xff; /* mask out delivery bits */
  1632. msid |= (1<<14);
  1633. pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
  1634. I915_WRITE(VLV_IMR, dev_priv->irq_mask);
  1635. I915_WRITE(VLV_IER, enable_mask);
  1636. I915_WRITE(VLV_IIR, 0xffffffff);
  1637. I915_WRITE(PIPESTAT(0), 0xffff);
  1638. I915_WRITE(PIPESTAT(1), 0xffff);
  1639. POSTING_READ(VLV_IER);
  1640. i915_enable_pipestat(dev_priv, 0, pipestat_enable);
  1641. i915_enable_pipestat(dev_priv, 1, pipestat_enable);
  1642. I915_WRITE(VLV_IIR, 0xffffffff);
  1643. I915_WRITE(VLV_IIR, 0xffffffff);
  1644. dev_priv->gt_irq_mask = ~0;
  1645. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1646. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1647. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1648. I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
  1649. GT_GEN6_BLT_CS_ERROR_INTERRUPT |
  1650. GT_GEN6_BLT_USER_INTERRUPT |
  1651. GT_GEN6_BSD_USER_INTERRUPT |
  1652. GT_GEN6_BSD_CS_ERROR_INTERRUPT |
  1653. GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
  1654. GT_PIPE_NOTIFY |
  1655. GT_RENDER_CS_ERROR_INTERRUPT |
  1656. GT_SYNC_STATUS |
  1657. GT_USER_INTERRUPT);
  1658. POSTING_READ(GTIER);
  1659. /* ack & enable invalid PTE error interrupts */
  1660. #if 0 /* FIXME: add support to irq handler for checking these bits */
  1661. I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
  1662. I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
  1663. #endif
  1664. I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
  1665. #if 0 /* FIXME: check register definitions; some have moved */
  1666. /* Note HDMI and DP share bits */
  1667. if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
  1668. hotplug_en |= HDMIB_HOTPLUG_INT_EN;
  1669. if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
  1670. hotplug_en |= HDMIC_HOTPLUG_INT_EN;
  1671. if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
  1672. hotplug_en |= HDMID_HOTPLUG_INT_EN;
  1673. if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
  1674. hotplug_en |= SDVOC_HOTPLUG_INT_EN;
  1675. if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
  1676. hotplug_en |= SDVOB_HOTPLUG_INT_EN;
  1677. if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
  1678. hotplug_en |= CRT_HOTPLUG_INT_EN;
  1679. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  1680. }
  1681. #endif
  1682. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  1683. return 0;
  1684. }
  1685. static void valleyview_irq_uninstall(struct drm_device *dev)
  1686. {
  1687. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1688. int pipe;
  1689. if (!dev_priv)
  1690. return;
  1691. for_each_pipe(pipe)
  1692. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1693. I915_WRITE(HWSTAM, 0xffffffff);
  1694. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1695. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1696. for_each_pipe(pipe)
  1697. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1698. I915_WRITE(VLV_IIR, 0xffffffff);
  1699. I915_WRITE(VLV_IMR, 0xffffffff);
  1700. I915_WRITE(VLV_IER, 0x0);
  1701. POSTING_READ(VLV_IER);
  1702. }
  1703. static void ironlake_irq_uninstall(struct drm_device *dev)
  1704. {
  1705. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1706. if (!dev_priv)
  1707. return;
  1708. I915_WRITE(HWSTAM, 0xffffffff);
  1709. I915_WRITE(DEIMR, 0xffffffff);
  1710. I915_WRITE(DEIER, 0x0);
  1711. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1712. I915_WRITE(GTIMR, 0xffffffff);
  1713. I915_WRITE(GTIER, 0x0);
  1714. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1715. I915_WRITE(SDEIMR, 0xffffffff);
  1716. I915_WRITE(SDEIER, 0x0);
  1717. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1718. }
  1719. static void i8xx_irq_preinstall(struct drm_device * dev)
  1720. {
  1721. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1722. int pipe;
  1723. atomic_set(&dev_priv->irq_received, 0);
  1724. for_each_pipe(pipe)
  1725. I915_WRITE(PIPESTAT(pipe), 0);
  1726. I915_WRITE16(IMR, 0xffff);
  1727. I915_WRITE16(IER, 0x0);
  1728. POSTING_READ16(IER);
  1729. }
  1730. static int i8xx_irq_postinstall(struct drm_device *dev)
  1731. {
  1732. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1733. dev_priv->pipestat[0] = 0;
  1734. dev_priv->pipestat[1] = 0;
  1735. I915_WRITE16(EMR,
  1736. ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  1737. /* Unmask the interrupts that we always want on. */
  1738. dev_priv->irq_mask =
  1739. ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1740. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1741. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  1742. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  1743. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1744. I915_WRITE16(IMR, dev_priv->irq_mask);
  1745. I915_WRITE16(IER,
  1746. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1747. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1748. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  1749. I915_USER_INTERRUPT);
  1750. POSTING_READ16(IER);
  1751. return 0;
  1752. }
  1753. static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
  1754. {
  1755. struct drm_device *dev = (struct drm_device *) arg;
  1756. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1757. u16 iir, new_iir;
  1758. u32 pipe_stats[2];
  1759. unsigned long irqflags;
  1760. int irq_received;
  1761. int pipe;
  1762. u16 flip_mask =
  1763. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  1764. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  1765. atomic_inc(&dev_priv->irq_received);
  1766. iir = I915_READ16(IIR);
  1767. if (iir == 0)
  1768. return IRQ_NONE;
  1769. while (iir & ~flip_mask) {
  1770. /* Can't rely on pipestat interrupt bit in iir as it might
  1771. * have been cleared after the pipestat interrupt was received.
  1772. * It doesn't set the bit in iir again, but it still produces
  1773. * interrupts (for non-MSI).
  1774. */
  1775. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1776. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  1777. i915_handle_error(dev, false);
  1778. for_each_pipe(pipe) {
  1779. int reg = PIPESTAT(pipe);
  1780. pipe_stats[pipe] = I915_READ(reg);
  1781. /*
  1782. * Clear the PIPE*STAT regs before the IIR
  1783. */
  1784. if (pipe_stats[pipe] & 0x8000ffff) {
  1785. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  1786. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  1787. pipe_name(pipe));
  1788. I915_WRITE(reg, pipe_stats[pipe]);
  1789. irq_received = 1;
  1790. }
  1791. }
  1792. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1793. I915_WRITE16(IIR, iir & ~flip_mask);
  1794. new_iir = I915_READ16(IIR); /* Flush posted writes */
  1795. i915_update_dri1_breadcrumb(dev);
  1796. if (iir & I915_USER_INTERRUPT)
  1797. notify_ring(dev, &dev_priv->ring[RCS]);
  1798. if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
  1799. drm_handle_vblank(dev, 0)) {
  1800. if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
  1801. intel_prepare_page_flip(dev, 0);
  1802. intel_finish_page_flip(dev, 0);
  1803. flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
  1804. }
  1805. }
  1806. if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
  1807. drm_handle_vblank(dev, 1)) {
  1808. if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
  1809. intel_prepare_page_flip(dev, 1);
  1810. intel_finish_page_flip(dev, 1);
  1811. flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  1812. }
  1813. }
  1814. iir = new_iir;
  1815. }
  1816. return IRQ_HANDLED;
  1817. }
  1818. static void i8xx_irq_uninstall(struct drm_device * dev)
  1819. {
  1820. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1821. int pipe;
  1822. for_each_pipe(pipe) {
  1823. /* Clear enable bits; then clear status bits */
  1824. I915_WRITE(PIPESTAT(pipe), 0);
  1825. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  1826. }
  1827. I915_WRITE16(IMR, 0xffff);
  1828. I915_WRITE16(IER, 0x0);
  1829. I915_WRITE16(IIR, I915_READ16(IIR));
  1830. }
  1831. static void i915_irq_preinstall(struct drm_device * dev)
  1832. {
  1833. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1834. int pipe;
  1835. atomic_set(&dev_priv->irq_received, 0);
  1836. if (I915_HAS_HOTPLUG(dev)) {
  1837. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1838. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1839. }
  1840. I915_WRITE16(HWSTAM, 0xeffe);
  1841. for_each_pipe(pipe)
  1842. I915_WRITE(PIPESTAT(pipe), 0);
  1843. I915_WRITE(IMR, 0xffffffff);
  1844. I915_WRITE(IER, 0x0);
  1845. POSTING_READ(IER);
  1846. }
  1847. static int i915_irq_postinstall(struct drm_device *dev)
  1848. {
  1849. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1850. u32 enable_mask;
  1851. dev_priv->pipestat[0] = 0;
  1852. dev_priv->pipestat[1] = 0;
  1853. I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  1854. /* Unmask the interrupts that we always want on. */
  1855. dev_priv->irq_mask =
  1856. ~(I915_ASLE_INTERRUPT |
  1857. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1858. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1859. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  1860. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  1861. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1862. enable_mask =
  1863. I915_ASLE_INTERRUPT |
  1864. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1865. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1866. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  1867. I915_USER_INTERRUPT;
  1868. if (I915_HAS_HOTPLUG(dev)) {
  1869. /* Enable in IER... */
  1870. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  1871. /* and unmask in IMR */
  1872. dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
  1873. }
  1874. I915_WRITE(IMR, dev_priv->irq_mask);
  1875. I915_WRITE(IER, enable_mask);
  1876. POSTING_READ(IER);
  1877. if (I915_HAS_HOTPLUG(dev)) {
  1878. u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  1879. if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
  1880. hotplug_en |= HDMIB_HOTPLUG_INT_EN;
  1881. if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
  1882. hotplug_en |= HDMIC_HOTPLUG_INT_EN;
  1883. if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
  1884. hotplug_en |= HDMID_HOTPLUG_INT_EN;
  1885. if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
  1886. hotplug_en |= SDVOC_HOTPLUG_INT_EN;
  1887. if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
  1888. hotplug_en |= SDVOB_HOTPLUG_INT_EN;
  1889. if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
  1890. hotplug_en |= CRT_HOTPLUG_INT_EN;
  1891. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  1892. }
  1893. /* Ignore TV since it's buggy */
  1894. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  1895. }
  1896. intel_opregion_enable_asle(dev);
  1897. return 0;
  1898. }
  1899. static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
  1900. {
  1901. struct drm_device *dev = (struct drm_device *) arg;
  1902. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1903. u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
  1904. unsigned long irqflags;
  1905. u32 flip_mask =
  1906. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  1907. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  1908. u32 flip[2] = {
  1909. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
  1910. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
  1911. };
  1912. int pipe, ret = IRQ_NONE;
  1913. atomic_inc(&dev_priv->irq_received);
  1914. iir = I915_READ(IIR);
  1915. do {
  1916. bool irq_received = (iir & ~flip_mask) != 0;
  1917. bool blc_event = false;
  1918. /* Can't rely on pipestat interrupt bit in iir as it might
  1919. * have been cleared after the pipestat interrupt was received.
  1920. * It doesn't set the bit in iir again, but it still produces
  1921. * interrupts (for non-MSI).
  1922. */
  1923. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1924. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  1925. i915_handle_error(dev, false);
  1926. for_each_pipe(pipe) {
  1927. int reg = PIPESTAT(pipe);
  1928. pipe_stats[pipe] = I915_READ(reg);
  1929. /* Clear the PIPE*STAT regs before the IIR */
  1930. if (pipe_stats[pipe] & 0x8000ffff) {
  1931. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  1932. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  1933. pipe_name(pipe));
  1934. I915_WRITE(reg, pipe_stats[pipe]);
  1935. irq_received = true;
  1936. }
  1937. }
  1938. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1939. if (!irq_received)
  1940. break;
  1941. /* Consume port. Then clear IIR or we'll miss events */
  1942. if ((I915_HAS_HOTPLUG(dev)) &&
  1943. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  1944. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  1945. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  1946. hotplug_status);
  1947. if (hotplug_status & dev_priv->hotplug_supported_mask)
  1948. queue_work(dev_priv->wq,
  1949. &dev_priv->hotplug_work);
  1950. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  1951. POSTING_READ(PORT_HOTPLUG_STAT);
  1952. }
  1953. I915_WRITE(IIR, iir & ~flip_mask);
  1954. new_iir = I915_READ(IIR); /* Flush posted writes */
  1955. if (iir & I915_USER_INTERRUPT)
  1956. notify_ring(dev, &dev_priv->ring[RCS]);
  1957. for_each_pipe(pipe) {
  1958. int plane = pipe;
  1959. if (IS_MOBILE(dev))
  1960. plane = !plane;
  1961. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
  1962. drm_handle_vblank(dev, pipe)) {
  1963. if (iir & flip[plane]) {
  1964. intel_prepare_page_flip(dev, plane);
  1965. intel_finish_page_flip(dev, pipe);
  1966. flip_mask &= ~flip[plane];
  1967. }
  1968. }
  1969. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  1970. blc_event = true;
  1971. }
  1972. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  1973. intel_opregion_asle_intr(dev);
  1974. /* With MSI, interrupts are only generated when iir
  1975. * transitions from zero to nonzero. If another bit got
  1976. * set while we were handling the existing iir bits, then
  1977. * we would never get another interrupt.
  1978. *
  1979. * This is fine on non-MSI as well, as if we hit this path
  1980. * we avoid exiting the interrupt handler only to generate
  1981. * another one.
  1982. *
  1983. * Note that for MSI this could cause a stray interrupt report
  1984. * if an interrupt landed in the time between writing IIR and
  1985. * the posting read. This should be rare enough to never
  1986. * trigger the 99% of 100,000 interrupts test for disabling
  1987. * stray interrupts.
  1988. */
  1989. ret = IRQ_HANDLED;
  1990. iir = new_iir;
  1991. } while (iir & ~flip_mask);
  1992. i915_update_dri1_breadcrumb(dev);
  1993. return ret;
  1994. }
  1995. static void i915_irq_uninstall(struct drm_device * dev)
  1996. {
  1997. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1998. int pipe;
  1999. if (I915_HAS_HOTPLUG(dev)) {
  2000. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2001. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2002. }
  2003. I915_WRITE16(HWSTAM, 0xffff);
  2004. for_each_pipe(pipe) {
  2005. /* Clear enable bits; then clear status bits */
  2006. I915_WRITE(PIPESTAT(pipe), 0);
  2007. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2008. }
  2009. I915_WRITE(IMR, 0xffffffff);
  2010. I915_WRITE(IER, 0x0);
  2011. I915_WRITE(IIR, I915_READ(IIR));
  2012. }
  2013. static void i965_irq_preinstall(struct drm_device * dev)
  2014. {
  2015. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2016. int pipe;
  2017. atomic_set(&dev_priv->irq_received, 0);
  2018. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2019. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2020. I915_WRITE(HWSTAM, 0xeffe);
  2021. for_each_pipe(pipe)
  2022. I915_WRITE(PIPESTAT(pipe), 0);
  2023. I915_WRITE(IMR, 0xffffffff);
  2024. I915_WRITE(IER, 0x0);
  2025. POSTING_READ(IER);
  2026. }
  2027. static int i965_irq_postinstall(struct drm_device *dev)
  2028. {
  2029. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2030. u32 hotplug_en;
  2031. u32 enable_mask;
  2032. u32 error_mask;
  2033. /* Unmask the interrupts that we always want on. */
  2034. dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
  2035. I915_DISPLAY_PORT_INTERRUPT |
  2036. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2037. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2038. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2039. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2040. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2041. enable_mask = ~dev_priv->irq_mask;
  2042. enable_mask |= I915_USER_INTERRUPT;
  2043. if (IS_G4X(dev))
  2044. enable_mask |= I915_BSD_USER_INTERRUPT;
  2045. dev_priv->pipestat[0] = 0;
  2046. dev_priv->pipestat[1] = 0;
  2047. /*
  2048. * Enable some error detection, note the instruction error mask
  2049. * bit is reserved, so we leave it masked.
  2050. */
  2051. if (IS_G4X(dev)) {
  2052. error_mask = ~(GM45_ERROR_PAGE_TABLE |
  2053. GM45_ERROR_MEM_PRIV |
  2054. GM45_ERROR_CP_PRIV |
  2055. I915_ERROR_MEMORY_REFRESH);
  2056. } else {
  2057. error_mask = ~(I915_ERROR_PAGE_TABLE |
  2058. I915_ERROR_MEMORY_REFRESH);
  2059. }
  2060. I915_WRITE(EMR, error_mask);
  2061. I915_WRITE(IMR, dev_priv->irq_mask);
  2062. I915_WRITE(IER, enable_mask);
  2063. POSTING_READ(IER);
  2064. /* Note HDMI and DP share hotplug bits */
  2065. hotplug_en = 0;
  2066. if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
  2067. hotplug_en |= HDMIB_HOTPLUG_INT_EN;
  2068. if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
  2069. hotplug_en |= HDMIC_HOTPLUG_INT_EN;
  2070. if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
  2071. hotplug_en |= HDMID_HOTPLUG_INT_EN;
  2072. if (IS_G4X(dev)) {
  2073. if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
  2074. hotplug_en |= SDVOC_HOTPLUG_INT_EN;
  2075. if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
  2076. hotplug_en |= SDVOB_HOTPLUG_INT_EN;
  2077. } else {
  2078. if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
  2079. hotplug_en |= SDVOC_HOTPLUG_INT_EN;
  2080. if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
  2081. hotplug_en |= SDVOB_HOTPLUG_INT_EN;
  2082. }
  2083. if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
  2084. hotplug_en |= CRT_HOTPLUG_INT_EN;
  2085. /* Programming the CRT detection parameters tends
  2086. to generate a spurious hotplug event about three
  2087. seconds later. So just do it once.
  2088. */
  2089. if (IS_G4X(dev))
  2090. hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
  2091. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  2092. }
  2093. /* Ignore TV since it's buggy */
  2094. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  2095. intel_opregion_enable_asle(dev);
  2096. return 0;
  2097. }
  2098. static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
  2099. {
  2100. struct drm_device *dev = (struct drm_device *) arg;
  2101. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2102. u32 iir, new_iir;
  2103. u32 pipe_stats[I915_MAX_PIPES];
  2104. unsigned long irqflags;
  2105. int irq_received;
  2106. int ret = IRQ_NONE, pipe;
  2107. atomic_inc(&dev_priv->irq_received);
  2108. iir = I915_READ(IIR);
  2109. for (;;) {
  2110. bool blc_event = false;
  2111. irq_received = iir != 0;
  2112. /* Can't rely on pipestat interrupt bit in iir as it might
  2113. * have been cleared after the pipestat interrupt was received.
  2114. * It doesn't set the bit in iir again, but it still produces
  2115. * interrupts (for non-MSI).
  2116. */
  2117. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2118. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2119. i915_handle_error(dev, false);
  2120. for_each_pipe(pipe) {
  2121. int reg = PIPESTAT(pipe);
  2122. pipe_stats[pipe] = I915_READ(reg);
  2123. /*
  2124. * Clear the PIPE*STAT regs before the IIR
  2125. */
  2126. if (pipe_stats[pipe] & 0x8000ffff) {
  2127. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2128. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2129. pipe_name(pipe));
  2130. I915_WRITE(reg, pipe_stats[pipe]);
  2131. irq_received = 1;
  2132. }
  2133. }
  2134. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2135. if (!irq_received)
  2136. break;
  2137. ret = IRQ_HANDLED;
  2138. /* Consume port. Then clear IIR or we'll miss events */
  2139. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  2140. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2141. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2142. hotplug_status);
  2143. if (hotplug_status & dev_priv->hotplug_supported_mask)
  2144. queue_work(dev_priv->wq,
  2145. &dev_priv->hotplug_work);
  2146. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2147. I915_READ(PORT_HOTPLUG_STAT);
  2148. }
  2149. I915_WRITE(IIR, iir);
  2150. new_iir = I915_READ(IIR); /* Flush posted writes */
  2151. if (iir & I915_USER_INTERRUPT)
  2152. notify_ring(dev, &dev_priv->ring[RCS]);
  2153. if (iir & I915_BSD_USER_INTERRUPT)
  2154. notify_ring(dev, &dev_priv->ring[VCS]);
  2155. if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
  2156. intel_prepare_page_flip(dev, 0);
  2157. if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
  2158. intel_prepare_page_flip(dev, 1);
  2159. for_each_pipe(pipe) {
  2160. if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
  2161. drm_handle_vblank(dev, pipe)) {
  2162. i915_pageflip_stall_check(dev, pipe);
  2163. intel_finish_page_flip(dev, pipe);
  2164. }
  2165. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2166. blc_event = true;
  2167. }
  2168. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2169. intel_opregion_asle_intr(dev);
  2170. /* With MSI, interrupts are only generated when iir
  2171. * transitions from zero to nonzero. If another bit got
  2172. * set while we were handling the existing iir bits, then
  2173. * we would never get another interrupt.
  2174. *
  2175. * This is fine on non-MSI as well, as if we hit this path
  2176. * we avoid exiting the interrupt handler only to generate
  2177. * another one.
  2178. *
  2179. * Note that for MSI this could cause a stray interrupt report
  2180. * if an interrupt landed in the time between writing IIR and
  2181. * the posting read. This should be rare enough to never
  2182. * trigger the 99% of 100,000 interrupts test for disabling
  2183. * stray interrupts.
  2184. */
  2185. iir = new_iir;
  2186. }
  2187. i915_update_dri1_breadcrumb(dev);
  2188. return ret;
  2189. }
  2190. static void i965_irq_uninstall(struct drm_device * dev)
  2191. {
  2192. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2193. int pipe;
  2194. if (!dev_priv)
  2195. return;
  2196. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2197. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2198. I915_WRITE(HWSTAM, 0xffffffff);
  2199. for_each_pipe(pipe)
  2200. I915_WRITE(PIPESTAT(pipe), 0);
  2201. I915_WRITE(IMR, 0xffffffff);
  2202. I915_WRITE(IER, 0x0);
  2203. for_each_pipe(pipe)
  2204. I915_WRITE(PIPESTAT(pipe),
  2205. I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
  2206. I915_WRITE(IIR, I915_READ(IIR));
  2207. }
  2208. void intel_irq_init(struct drm_device *dev)
  2209. {
  2210. struct drm_i915_private *dev_priv = dev->dev_private;
  2211. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  2212. INIT_WORK(&dev_priv->error_work, i915_error_work_func);
  2213. INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
  2214. INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
  2215. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  2216. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  2217. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  2218. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  2219. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  2220. }
  2221. if (drm_core_check_feature(dev, DRIVER_MODESET))
  2222. dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
  2223. else
  2224. dev->driver->get_vblank_timestamp = NULL;
  2225. dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
  2226. if (IS_VALLEYVIEW(dev)) {
  2227. dev->driver->irq_handler = valleyview_irq_handler;
  2228. dev->driver->irq_preinstall = valleyview_irq_preinstall;
  2229. dev->driver->irq_postinstall = valleyview_irq_postinstall;
  2230. dev->driver->irq_uninstall = valleyview_irq_uninstall;
  2231. dev->driver->enable_vblank = valleyview_enable_vblank;
  2232. dev->driver->disable_vblank = valleyview_disable_vblank;
  2233. } else if (IS_IVYBRIDGE(dev)) {
  2234. /* Share pre & uninstall handlers with ILK/SNB */
  2235. dev->driver->irq_handler = ivybridge_irq_handler;
  2236. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2237. dev->driver->irq_postinstall = ivybridge_irq_postinstall;
  2238. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2239. dev->driver->enable_vblank = ivybridge_enable_vblank;
  2240. dev->driver->disable_vblank = ivybridge_disable_vblank;
  2241. } else if (IS_HASWELL(dev)) {
  2242. /* Share interrupts handling with IVB */
  2243. dev->driver->irq_handler = ivybridge_irq_handler;
  2244. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2245. dev->driver->irq_postinstall = ivybridge_irq_postinstall;
  2246. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2247. dev->driver->enable_vblank = ivybridge_enable_vblank;
  2248. dev->driver->disable_vblank = ivybridge_disable_vblank;
  2249. } else if (HAS_PCH_SPLIT(dev)) {
  2250. dev->driver->irq_handler = ironlake_irq_handler;
  2251. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2252. dev->driver->irq_postinstall = ironlake_irq_postinstall;
  2253. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2254. dev->driver->enable_vblank = ironlake_enable_vblank;
  2255. dev->driver->disable_vblank = ironlake_disable_vblank;
  2256. } else {
  2257. if (INTEL_INFO(dev)->gen == 2) {
  2258. dev->driver->irq_preinstall = i8xx_irq_preinstall;
  2259. dev->driver->irq_postinstall = i8xx_irq_postinstall;
  2260. dev->driver->irq_handler = i8xx_irq_handler;
  2261. dev->driver->irq_uninstall = i8xx_irq_uninstall;
  2262. } else if (INTEL_INFO(dev)->gen == 3) {
  2263. dev->driver->irq_preinstall = i915_irq_preinstall;
  2264. dev->driver->irq_postinstall = i915_irq_postinstall;
  2265. dev->driver->irq_uninstall = i915_irq_uninstall;
  2266. dev->driver->irq_handler = i915_irq_handler;
  2267. } else {
  2268. dev->driver->irq_preinstall = i965_irq_preinstall;
  2269. dev->driver->irq_postinstall = i965_irq_postinstall;
  2270. dev->driver->irq_uninstall = i965_irq_uninstall;
  2271. dev->driver->irq_handler = i965_irq_handler;
  2272. }
  2273. dev->driver->enable_vblank = i915_enable_vblank;
  2274. dev->driver->disable_vblank = i915_disable_vblank;
  2275. }
  2276. }