ab8500.c 39 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License v2
  5. *
  6. * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
  7. * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
  8. *
  9. * AB8500 peripheral regulators
  10. *
  11. * AB8500 supports the following regulators:
  12. * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
  13. */
  14. #include <linux/init.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/err.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/mfd/abx500.h>
  20. #include <linux/mfd/abx500/ab8500.h>
  21. #include <linux/of.h>
  22. #include <linux/regulator/of_regulator.h>
  23. #include <linux/regulator/driver.h>
  24. #include <linux/regulator/machine.h>
  25. #include <linux/regulator/ab8500.h>
  26. #include <linux/slab.h>
  27. /**
  28. * struct ab8500_regulator_info - ab8500 regulator information
  29. * @dev: device pointer
  30. * @desc: regulator description
  31. * @regulator_dev: regulator device
  32. * @is_enabled: status of regulator (on/off)
  33. * @load_lp_uA: maximum load in idle (low power) mode
  34. * @update_bank: bank to control on/off
  35. * @update_reg: register to control on/off
  36. * @update_mask: mask to enable/disable and set mode of regulator
  37. * @update_val: bits holding the regulator current mode
  38. * @update_val_idle: bits to enable the regulator in idle (low power) mode
  39. * @update_val_normal: bits to enable the regulator in normal (high power) mode
  40. * @voltage_bank: bank to control regulator voltage
  41. * @voltage_reg: register to control regulator voltage
  42. * @voltage_mask: mask to control regulator voltage
  43. * @voltage_shift: shift to control regulator voltage
  44. */
  45. struct ab8500_regulator_info {
  46. struct device *dev;
  47. struct regulator_desc desc;
  48. struct regulator_dev *regulator;
  49. bool is_enabled;
  50. int load_lp_uA;
  51. u8 update_bank;
  52. u8 update_reg;
  53. u8 update_mask;
  54. u8 update_val;
  55. u8 update_val_idle;
  56. u8 update_val_normal;
  57. u8 voltage_bank;
  58. u8 voltage_reg;
  59. u8 voltage_mask;
  60. u8 voltage_shift;
  61. };
  62. /* voltage tables for the vauxn/vintcore supplies */
  63. static const unsigned int ldo_vauxn_voltages[] = {
  64. 1100000,
  65. 1200000,
  66. 1300000,
  67. 1400000,
  68. 1500000,
  69. 1800000,
  70. 1850000,
  71. 1900000,
  72. 2500000,
  73. 2650000,
  74. 2700000,
  75. 2750000,
  76. 2800000,
  77. 2900000,
  78. 3000000,
  79. 3300000,
  80. };
  81. static const unsigned int ldo_vaux3_voltages[] = {
  82. 1200000,
  83. 1500000,
  84. 1800000,
  85. 2100000,
  86. 2500000,
  87. 2750000,
  88. 2790000,
  89. 2910000,
  90. };
  91. static const unsigned int ldo_vintcore_voltages[] = {
  92. 1200000,
  93. 1225000,
  94. 1250000,
  95. 1275000,
  96. 1300000,
  97. 1325000,
  98. 1350000,
  99. };
  100. static int ab8500_regulator_enable(struct regulator_dev *rdev)
  101. {
  102. int ret;
  103. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  104. if (info == NULL) {
  105. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  106. return -EINVAL;
  107. }
  108. ret = abx500_mask_and_set_register_interruptible(info->dev,
  109. info->update_bank, info->update_reg,
  110. info->update_mask, info->update_val);
  111. if (ret < 0) {
  112. dev_err(rdev_get_dev(rdev),
  113. "couldn't set enable bits for regulator\n");
  114. return ret;
  115. }
  116. info->is_enabled = true;
  117. dev_vdbg(rdev_get_dev(rdev),
  118. "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
  119. info->desc.name, info->update_bank, info->update_reg,
  120. info->update_mask, info->update_val);
  121. return ret;
  122. }
  123. static int ab8500_regulator_disable(struct regulator_dev *rdev)
  124. {
  125. int ret;
  126. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  127. if (info == NULL) {
  128. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  129. return -EINVAL;
  130. }
  131. ret = abx500_mask_and_set_register_interruptible(info->dev,
  132. info->update_bank, info->update_reg,
  133. info->update_mask, 0x0);
  134. if (ret < 0) {
  135. dev_err(rdev_get_dev(rdev),
  136. "couldn't set disable bits for regulator\n");
  137. return ret;
  138. }
  139. info->is_enabled = false;
  140. dev_vdbg(rdev_get_dev(rdev),
  141. "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
  142. info->desc.name, info->update_bank, info->update_reg,
  143. info->update_mask, 0x0);
  144. return ret;
  145. }
  146. static unsigned int ab8500_regulator_get_optimum_mode(
  147. struct regulator_dev *rdev, int input_uV,
  148. int output_uV, int load_uA)
  149. {
  150. unsigned int mode;
  151. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  152. if (info == NULL) {
  153. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  154. return -EINVAL;
  155. }
  156. if (load_uA <= info->load_lp_uA)
  157. mode = REGULATOR_MODE_IDLE;
  158. else
  159. mode = REGULATOR_MODE_NORMAL;
  160. return mode;
  161. }
  162. static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
  163. unsigned int mode)
  164. {
  165. int ret;
  166. u8 update_val;
  167. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  168. if (info == NULL) {
  169. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  170. return -EINVAL;
  171. }
  172. switch (mode) {
  173. case REGULATOR_MODE_NORMAL:
  174. update_val = info->update_val_normal;
  175. break;
  176. case REGULATOR_MODE_IDLE:
  177. update_val = info->update_val_idle;
  178. break;
  179. default:
  180. return -EINVAL;
  181. }
  182. /* ab8500 regulators share mode and enable in the same register bits.
  183. off = 0b00
  184. low power mode= 0b11
  185. full powermode = 0b01
  186. (HW control mode = 0b10)
  187. Thus we don't write to the register when regulator is disabled.
  188. */
  189. if (info->is_enabled) {
  190. ret = abx500_mask_and_set_register_interruptible(info->dev,
  191. info->update_bank, info->update_reg,
  192. info->update_mask, update_val);
  193. if (ret < 0) {
  194. dev_err(rdev_get_dev(rdev),
  195. "couldn't set regulator mode\n");
  196. return ret;
  197. }
  198. dev_vdbg(rdev_get_dev(rdev),
  199. "%s-set_mode (bank, reg, mask, value): "
  200. "0x%x, 0x%x, 0x%x, 0x%x\n",
  201. info->desc.name, info->update_bank, info->update_reg,
  202. info->update_mask, update_val);
  203. }
  204. info->update_val = update_val;
  205. return 0;
  206. }
  207. static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
  208. {
  209. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  210. int ret;
  211. if (info == NULL) {
  212. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  213. return -EINVAL;
  214. }
  215. if (info->update_val == info->update_val_normal)
  216. ret = REGULATOR_MODE_NORMAL;
  217. else if (info->update_val == info->update_val_idle)
  218. ret = REGULATOR_MODE_IDLE;
  219. else
  220. ret = -EINVAL;
  221. return ret;
  222. }
  223. static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
  224. {
  225. int ret;
  226. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  227. u8 regval;
  228. if (info == NULL) {
  229. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  230. return -EINVAL;
  231. }
  232. ret = abx500_get_register_interruptible(info->dev,
  233. info->update_bank, info->update_reg, &regval);
  234. if (ret < 0) {
  235. dev_err(rdev_get_dev(rdev),
  236. "couldn't read 0x%x register\n", info->update_reg);
  237. return ret;
  238. }
  239. dev_vdbg(rdev_get_dev(rdev),
  240. "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
  241. " 0x%x\n",
  242. info->desc.name, info->update_bank, info->update_reg,
  243. info->update_mask, regval);
  244. if (regval & info->update_mask)
  245. info->is_enabled = true;
  246. else
  247. info->is_enabled = false;
  248. return info->is_enabled;
  249. }
  250. static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
  251. {
  252. int ret, val;
  253. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  254. u8 regval;
  255. if (info == NULL) {
  256. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  257. return -EINVAL;
  258. }
  259. ret = abx500_get_register_interruptible(info->dev,
  260. info->voltage_bank, info->voltage_reg, &regval);
  261. if (ret < 0) {
  262. dev_err(rdev_get_dev(rdev),
  263. "couldn't read voltage reg for regulator\n");
  264. return ret;
  265. }
  266. dev_vdbg(rdev_get_dev(rdev),
  267. "%s-get_voltage (bank, reg, mask, shift, value): "
  268. "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
  269. info->desc.name, info->voltage_bank,
  270. info->voltage_reg, info->voltage_mask,
  271. info->voltage_shift, regval);
  272. val = regval & info->voltage_mask;
  273. return val >> info->voltage_shift;
  274. }
  275. static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
  276. unsigned selector)
  277. {
  278. int ret;
  279. struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
  280. u8 regval;
  281. if (info == NULL) {
  282. dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
  283. return -EINVAL;
  284. }
  285. /* set the registers for the request */
  286. regval = (u8)selector << info->voltage_shift;
  287. ret = abx500_mask_and_set_register_interruptible(info->dev,
  288. info->voltage_bank, info->voltage_reg,
  289. info->voltage_mask, regval);
  290. if (ret < 0)
  291. dev_err(rdev_get_dev(rdev),
  292. "couldn't set voltage reg for regulator\n");
  293. dev_vdbg(rdev_get_dev(rdev),
  294. "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
  295. " 0x%x\n",
  296. info->desc.name, info->voltage_bank, info->voltage_reg,
  297. info->voltage_mask, regval);
  298. return ret;
  299. }
  300. static struct regulator_ops ab8500_regulator_volt_mode_ops = {
  301. .enable = ab8500_regulator_enable,
  302. .disable = ab8500_regulator_disable,
  303. .is_enabled = ab8500_regulator_is_enabled,
  304. .get_optimum_mode = ab8500_regulator_get_optimum_mode,
  305. .set_mode = ab8500_regulator_set_mode,
  306. .get_mode = ab8500_regulator_get_mode,
  307. .get_voltage_sel = ab8500_regulator_get_voltage_sel,
  308. .set_voltage_sel = ab8500_regulator_set_voltage_sel,
  309. .list_voltage = regulator_list_voltage_table,
  310. };
  311. static struct regulator_ops ab8500_regulator_mode_ops = {
  312. .enable = ab8500_regulator_enable,
  313. .disable = ab8500_regulator_disable,
  314. .is_enabled = ab8500_regulator_is_enabled,
  315. .get_optimum_mode = ab8500_regulator_get_optimum_mode,
  316. .set_mode = ab8500_regulator_set_mode,
  317. .get_mode = ab8500_regulator_get_mode,
  318. .get_voltage_sel = ab8500_regulator_get_voltage_sel,
  319. .list_voltage = regulator_list_voltage_linear,
  320. };
  321. static struct regulator_ops ab8500_regulator_ops = {
  322. .enable = ab8500_regulator_enable,
  323. .disable = ab8500_regulator_disable,
  324. .is_enabled = ab8500_regulator_is_enabled,
  325. .get_voltage_sel = ab8500_regulator_get_voltage_sel,
  326. .list_voltage = regulator_list_voltage_linear,
  327. };
  328. /* AB8500 regulator information */
  329. static struct ab8500_regulator_info
  330. ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
  331. /*
  332. * Variable Voltage Regulators
  333. * name, min mV, max mV,
  334. * update bank, reg, mask, enable val
  335. * volt bank, reg, mask
  336. */
  337. [AB8500_LDO_AUX1] = {
  338. .desc = {
  339. .name = "LDO-AUX1",
  340. .ops = &ab8500_regulator_volt_mode_ops,
  341. .type = REGULATOR_VOLTAGE,
  342. .id = AB8500_LDO_AUX1,
  343. .owner = THIS_MODULE,
  344. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  345. .volt_table = ldo_vauxn_voltages,
  346. .enable_time = 200,
  347. },
  348. .load_lp_uA = 5000,
  349. .update_bank = 0x04,
  350. .update_reg = 0x09,
  351. .update_mask = 0x03,
  352. .update_val = 0x01,
  353. .update_val_idle = 0x03,
  354. .update_val_normal = 0x01,
  355. .voltage_bank = 0x04,
  356. .voltage_reg = 0x1f,
  357. .voltage_mask = 0x0f,
  358. },
  359. [AB8500_LDO_AUX2] = {
  360. .desc = {
  361. .name = "LDO-AUX2",
  362. .ops = &ab8500_regulator_volt_mode_ops,
  363. .type = REGULATOR_VOLTAGE,
  364. .id = AB8500_LDO_AUX2,
  365. .owner = THIS_MODULE,
  366. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  367. .volt_table = ldo_vauxn_voltages,
  368. .enable_time = 200,
  369. },
  370. .load_lp_uA = 5000,
  371. .update_bank = 0x04,
  372. .update_reg = 0x09,
  373. .update_mask = 0x0c,
  374. .update_val = 0x04,
  375. .update_val_idle = 0x0c,
  376. .update_val_normal = 0x04,
  377. .voltage_bank = 0x04,
  378. .voltage_reg = 0x20,
  379. .voltage_mask = 0x0f,
  380. },
  381. [AB8500_LDO_AUX3] = {
  382. .desc = {
  383. .name = "LDO-AUX3",
  384. .ops = &ab8500_regulator_volt_mode_ops,
  385. .type = REGULATOR_VOLTAGE,
  386. .id = AB8500_LDO_AUX3,
  387. .owner = THIS_MODULE,
  388. .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
  389. .volt_table = ldo_vaux3_voltages,
  390. .enable_time = 450,
  391. },
  392. .load_lp_uA = 5000,
  393. .update_bank = 0x04,
  394. .update_reg = 0x0a,
  395. .update_mask = 0x03,
  396. .update_val = 0x01,
  397. .update_val_idle = 0x03,
  398. .update_val_normal = 0x01,
  399. .voltage_bank = 0x04,
  400. .voltage_reg = 0x21,
  401. .voltage_mask = 0x07,
  402. },
  403. [AB8500_LDO_INTCORE] = {
  404. .desc = {
  405. .name = "LDO-INTCORE",
  406. .ops = &ab8500_regulator_volt_mode_ops,
  407. .type = REGULATOR_VOLTAGE,
  408. .id = AB8500_LDO_INTCORE,
  409. .owner = THIS_MODULE,
  410. .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
  411. .volt_table = ldo_vintcore_voltages,
  412. .enable_time = 750,
  413. },
  414. .load_lp_uA = 5000,
  415. .update_bank = 0x03,
  416. .update_reg = 0x80,
  417. .update_mask = 0x44,
  418. .update_val = 0x44,
  419. .update_val_idle = 0x44,
  420. .update_val_normal = 0x04,
  421. .voltage_bank = 0x03,
  422. .voltage_reg = 0x80,
  423. .voltage_mask = 0x38,
  424. .voltage_shift = 3,
  425. },
  426. /*
  427. * Fixed Voltage Regulators
  428. * name, fixed mV,
  429. * update bank, reg, mask, enable val
  430. */
  431. [AB8500_LDO_TVOUT] = {
  432. .desc = {
  433. .name = "LDO-TVOUT",
  434. .ops = &ab8500_regulator_mode_ops,
  435. .type = REGULATOR_VOLTAGE,
  436. .id = AB8500_LDO_TVOUT,
  437. .owner = THIS_MODULE,
  438. .n_voltages = 1,
  439. .min_uV = 2000000,
  440. .enable_time = 500,
  441. },
  442. .load_lp_uA = 1000,
  443. .update_bank = 0x03,
  444. .update_reg = 0x80,
  445. .update_mask = 0x82,
  446. .update_val = 0x02,
  447. .update_val_idle = 0x82,
  448. .update_val_normal = 0x02,
  449. },
  450. [AB8500_LDO_AUDIO] = {
  451. .desc = {
  452. .name = "LDO-AUDIO",
  453. .ops = &ab8500_regulator_ops,
  454. .type = REGULATOR_VOLTAGE,
  455. .id = AB8500_LDO_AUDIO,
  456. .owner = THIS_MODULE,
  457. .n_voltages = 1,
  458. .min_uV = 2000000,
  459. .enable_time = 140,
  460. },
  461. .update_bank = 0x03,
  462. .update_reg = 0x83,
  463. .update_mask = 0x02,
  464. .update_val = 0x02,
  465. },
  466. [AB8500_LDO_ANAMIC1] = {
  467. .desc = {
  468. .name = "LDO-ANAMIC1",
  469. .ops = &ab8500_regulator_ops,
  470. .type = REGULATOR_VOLTAGE,
  471. .id = AB8500_LDO_ANAMIC1,
  472. .owner = THIS_MODULE,
  473. .n_voltages = 1,
  474. .min_uV = 2050000,
  475. .enable_time = 500,
  476. },
  477. .update_bank = 0x03,
  478. .update_reg = 0x83,
  479. .update_mask = 0x08,
  480. .update_val = 0x08,
  481. },
  482. [AB8500_LDO_ANAMIC2] = {
  483. .desc = {
  484. .name = "LDO-ANAMIC2",
  485. .ops = &ab8500_regulator_ops,
  486. .type = REGULATOR_VOLTAGE,
  487. .id = AB8500_LDO_ANAMIC2,
  488. .owner = THIS_MODULE,
  489. .n_voltages = 1,
  490. .min_uV = 2050000,
  491. .enable_time = 500,
  492. },
  493. .update_bank = 0x03,
  494. .update_reg = 0x83,
  495. .update_mask = 0x10,
  496. .update_val = 0x10,
  497. },
  498. [AB8500_LDO_DMIC] = {
  499. .desc = {
  500. .name = "LDO-DMIC",
  501. .ops = &ab8500_regulator_ops,
  502. .type = REGULATOR_VOLTAGE,
  503. .id = AB8500_LDO_DMIC,
  504. .owner = THIS_MODULE,
  505. .n_voltages = 1,
  506. .min_uV = 1800000,
  507. .enable_time = 420,
  508. },
  509. .update_bank = 0x03,
  510. .update_reg = 0x83,
  511. .update_mask = 0x04,
  512. .update_val = 0x04,
  513. },
  514. /*
  515. * Regulators with fixed voltage and normal/idle modes
  516. */
  517. [AB8500_LDO_ANA] = {
  518. .desc = {
  519. .name = "LDO-ANA",
  520. .ops = &ab8500_regulator_mode_ops,
  521. .type = REGULATOR_VOLTAGE,
  522. .id = AB8500_LDO_ANA,
  523. .owner = THIS_MODULE,
  524. .n_voltages = 1,
  525. .min_uV = 1200000,
  526. .enable_time = 140,
  527. },
  528. .load_lp_uA = 1000,
  529. .update_bank = 0x04,
  530. .update_reg = 0x06,
  531. .update_mask = 0x0c,
  532. .update_val = 0x04,
  533. .update_val_idle = 0x0c,
  534. .update_val_normal = 0x04,
  535. },
  536. };
  537. /* AB9540 regulator information */
  538. static struct ab8500_regulator_info
  539. ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
  540. /*
  541. * Variable Voltage Regulators
  542. * name, min mV, max mV,
  543. * update bank, reg, mask, enable val
  544. * volt bank, reg, mask, table, table length
  545. */
  546. [AB9540_LDO_AUX1] = {
  547. .desc = {
  548. .name = "LDO-AUX1",
  549. .ops = &ab8500_regulator_volt_mode_ops,
  550. .type = REGULATOR_VOLTAGE,
  551. .id = AB8500_LDO_AUX1,
  552. .owner = THIS_MODULE,
  553. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  554. },
  555. .min_uV = 1100000,
  556. .max_uV = 3300000,
  557. .load_lp_uA = 5000,
  558. .update_bank = 0x04,
  559. .update_reg = 0x09,
  560. .update_mask = 0x03,
  561. .update_val = 0x01,
  562. .update_val_idle = 0x03,
  563. .update_val_normal = 0x01,
  564. .voltage_bank = 0x04,
  565. .voltage_reg = 0x1f,
  566. .voltage_mask = 0x0f,
  567. .voltages = ldo_vauxn_voltages,
  568. .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
  569. },
  570. [AB9540_LDO_AUX2] = {
  571. .desc = {
  572. .name = "LDO-AUX2",
  573. .ops = &ab8500_regulator_volt_mode_ops,
  574. .type = REGULATOR_VOLTAGE,
  575. .id = AB8500_LDO_AUX2,
  576. .owner = THIS_MODULE,
  577. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  578. },
  579. .min_uV = 1100000,
  580. .max_uV = 3300000,
  581. .load_lp_uA = 5000,
  582. .update_bank = 0x04,
  583. .update_reg = 0x09,
  584. .update_mask = 0x0c,
  585. .update_val = 0x04,
  586. .update_val_idle = 0x0c,
  587. .update_val_normal = 0x04,
  588. .voltage_bank = 0x04,
  589. .voltage_reg = 0x20,
  590. .voltage_mask = 0x0f,
  591. .voltages = ldo_vauxn_voltages,
  592. .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
  593. },
  594. [AB9540_LDO_AUX3] = {
  595. .desc = {
  596. .name = "LDO-AUX3",
  597. .ops = &ab8500_regulator_volt_mode_ops,
  598. .type = REGULATOR_VOLTAGE,
  599. .id = AB8500_LDO_AUX3,
  600. .owner = THIS_MODULE,
  601. .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
  602. },
  603. .min_uV = 1100000,
  604. .max_uV = 3300000,
  605. .load_lp_uA = 5000,
  606. .update_bank = 0x04,
  607. .update_reg = 0x0a,
  608. .update_mask = 0x03,
  609. .update_val = 0x01,
  610. .update_val_idle = 0x03,
  611. .update_val_normal = 0x01,
  612. .voltage_bank = 0x04,
  613. .voltage_reg = 0x21,
  614. .voltage_mask = 0x07,
  615. .voltages = ldo_vaux3_voltages,
  616. .voltages_len = ARRAY_SIZE(ldo_vaux3_voltages),
  617. },
  618. [AB9540_LDO_AUX4] = {
  619. .desc = {
  620. .name = "LDO-AUX4",
  621. .ops = &ab8500_regulator_volt_mode_ops,
  622. .type = REGULATOR_VOLTAGE,
  623. .id = AB9540_LDO_AUX4,
  624. .owner = THIS_MODULE,
  625. .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
  626. },
  627. .min_uV = 1100000,
  628. .max_uV = 3300000,
  629. .load_lp_uA = 5000,
  630. /* values for Vaux4Regu register */
  631. .update_bank = 0x04,
  632. .update_reg = 0x2e,
  633. .update_mask = 0x03,
  634. .update_val = 0x01,
  635. .update_val_idle = 0x03,
  636. .update_val_normal = 0x01,
  637. /* values for Vaux4SEL register */
  638. .voltage_bank = 0x04,
  639. .voltage_reg = 0x2f,
  640. .voltage_mask = 0x0f,
  641. .voltages = ldo_vauxn_voltages,
  642. .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
  643. },
  644. [AB9540_LDO_INTCORE] = {
  645. .desc = {
  646. .name = "LDO-INTCORE",
  647. .ops = &ab8500_regulator_volt_mode_ops,
  648. .type = REGULATOR_VOLTAGE,
  649. .id = AB8500_LDO_INTCORE,
  650. .owner = THIS_MODULE,
  651. .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
  652. },
  653. .min_uV = 1100000,
  654. .max_uV = 3300000,
  655. .load_lp_uA = 5000,
  656. .update_bank = 0x03,
  657. .update_reg = 0x80,
  658. .update_mask = 0x44,
  659. .update_val = 0x44,
  660. .update_val_idle = 0x44,
  661. .update_val_normal = 0x04,
  662. .voltage_bank = 0x03,
  663. .voltage_reg = 0x80,
  664. .voltage_mask = 0x38,
  665. .voltages = ldo_vintcore_voltages,
  666. .voltages_len = ARRAY_SIZE(ldo_vintcore_voltages),
  667. .voltage_shift = 3,
  668. },
  669. /*
  670. * Fixed Voltage Regulators
  671. * name, fixed mV,
  672. * update bank, reg, mask, enable val
  673. */
  674. [AB9540_LDO_TVOUT] = {
  675. .desc = {
  676. .name = "LDO-TVOUT",
  677. .ops = &ab8500_regulator_mode_ops,
  678. .type = REGULATOR_VOLTAGE,
  679. .id = AB8500_LDO_TVOUT,
  680. .owner = THIS_MODULE,
  681. .n_voltages = 1,
  682. },
  683. .delay = 10000,
  684. .fixed_uV = 2000000,
  685. .load_lp_uA = 1000,
  686. .update_bank = 0x03,
  687. .update_reg = 0x80,
  688. .update_mask = 0x82,
  689. .update_val = 0x02,
  690. .update_val_idle = 0x82,
  691. .update_val_normal = 0x02,
  692. },
  693. [AB9540_LDO_USB] = {
  694. .desc = {
  695. .name = "LDO-USB",
  696. .ops = &ab8500_regulator_ops,
  697. .type = REGULATOR_VOLTAGE,
  698. .id = AB9540_LDO_USB,
  699. .owner = THIS_MODULE,
  700. .n_voltages = 1,
  701. },
  702. .fixed_uV = 3300000,
  703. .update_bank = 0x03,
  704. .update_reg = 0x82,
  705. .update_mask = 0x03,
  706. .update_val = 0x01,
  707. .update_val_idle = 0x03,
  708. .update_val_normal = 0x01,
  709. },
  710. [AB9540_LDO_AUDIO] = {
  711. .desc = {
  712. .name = "LDO-AUDIO",
  713. .ops = &ab8500_regulator_ops,
  714. .type = REGULATOR_VOLTAGE,
  715. .id = AB8500_LDO_AUDIO,
  716. .owner = THIS_MODULE,
  717. .n_voltages = 1,
  718. },
  719. .fixed_uV = 2000000,
  720. .update_bank = 0x03,
  721. .update_reg = 0x83,
  722. .update_mask = 0x02,
  723. .update_val = 0x02,
  724. },
  725. [AB9540_LDO_ANAMIC1] = {
  726. .desc = {
  727. .name = "LDO-ANAMIC1",
  728. .ops = &ab8500_regulator_ops,
  729. .type = REGULATOR_VOLTAGE,
  730. .id = AB8500_LDO_ANAMIC1,
  731. .owner = THIS_MODULE,
  732. .n_voltages = 1,
  733. },
  734. .fixed_uV = 2050000,
  735. .update_bank = 0x03,
  736. .update_reg = 0x83,
  737. .update_mask = 0x08,
  738. .update_val = 0x08,
  739. },
  740. [AB9540_LDO_ANAMIC2] = {
  741. .desc = {
  742. .name = "LDO-ANAMIC2",
  743. .ops = &ab8500_regulator_ops,
  744. .type = REGULATOR_VOLTAGE,
  745. .id = AB8500_LDO_ANAMIC2,
  746. .owner = THIS_MODULE,
  747. .n_voltages = 1,
  748. },
  749. .fixed_uV = 2050000,
  750. .update_bank = 0x03,
  751. .update_reg = 0x83,
  752. .update_mask = 0x10,
  753. .update_val = 0x10,
  754. },
  755. [AB9540_LDO_DMIC] = {
  756. .desc = {
  757. .name = "LDO-DMIC",
  758. .ops = &ab8500_regulator_ops,
  759. .type = REGULATOR_VOLTAGE,
  760. .id = AB8500_LDO_DMIC,
  761. .owner = THIS_MODULE,
  762. .n_voltages = 1,
  763. },
  764. .fixed_uV = 1800000,
  765. .update_bank = 0x03,
  766. .update_reg = 0x83,
  767. .update_mask = 0x04,
  768. .update_val = 0x04,
  769. },
  770. /*
  771. * Regulators with fixed voltage and normal/idle modes
  772. */
  773. [AB9540_LDO_ANA] = {
  774. .desc = {
  775. .name = "LDO-ANA",
  776. .ops = &ab8500_regulator_mode_ops,
  777. .type = REGULATOR_VOLTAGE,
  778. .id = AB8500_LDO_ANA,
  779. .owner = THIS_MODULE,
  780. .n_voltages = 1,
  781. },
  782. .fixed_uV = 1200000,
  783. .load_lp_uA = 1000,
  784. .update_bank = 0x04,
  785. .update_reg = 0x06,
  786. .update_mask = 0x0c,
  787. .update_val = 0x08,
  788. .update_val_idle = 0x0c,
  789. .update_val_normal = 0x08,
  790. },
  791. };
  792. struct ab8500_reg_init {
  793. u8 bank;
  794. u8 addr;
  795. u8 mask;
  796. };
  797. #define REG_INIT(_id, _bank, _addr, _mask) \
  798. [_id] = { \
  799. .bank = _bank, \
  800. .addr = _addr, \
  801. .mask = _mask, \
  802. }
  803. /* AB8500 register init */
  804. static struct ab8500_reg_init ab8500_reg_init[] = {
  805. /*
  806. * 0x30, VanaRequestCtrl
  807. * 0xc0, VextSupply1RequestCtrl
  808. */
  809. REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
  810. /*
  811. * 0x03, VextSupply2RequestCtrl
  812. * 0x0c, VextSupply3RequestCtrl
  813. * 0x30, Vaux1RequestCtrl
  814. * 0xc0, Vaux2RequestCtrl
  815. */
  816. REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
  817. /*
  818. * 0x03, Vaux3RequestCtrl
  819. * 0x04, SwHPReq
  820. */
  821. REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
  822. /*
  823. * 0x08, VanaSysClkReq1HPValid
  824. * 0x20, Vaux1SysClkReq1HPValid
  825. * 0x40, Vaux2SysClkReq1HPValid
  826. * 0x80, Vaux3SysClkReq1HPValid
  827. */
  828. REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
  829. /*
  830. * 0x10, VextSupply1SysClkReq1HPValid
  831. * 0x20, VextSupply2SysClkReq1HPValid
  832. * 0x40, VextSupply3SysClkReq1HPValid
  833. */
  834. REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
  835. /*
  836. * 0x08, VanaHwHPReq1Valid
  837. * 0x20, Vaux1HwHPReq1Valid
  838. * 0x40, Vaux2HwHPReq1Valid
  839. * 0x80, Vaux3HwHPReq1Valid
  840. */
  841. REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
  842. /*
  843. * 0x01, VextSupply1HwHPReq1Valid
  844. * 0x02, VextSupply2HwHPReq1Valid
  845. * 0x04, VextSupply3HwHPReq1Valid
  846. */
  847. REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
  848. /*
  849. * 0x08, VanaHwHPReq2Valid
  850. * 0x20, Vaux1HwHPReq2Valid
  851. * 0x40, Vaux2HwHPReq2Valid
  852. * 0x80, Vaux3HwHPReq2Valid
  853. */
  854. REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
  855. /*
  856. * 0x01, VextSupply1HwHPReq2Valid
  857. * 0x02, VextSupply2HwHPReq2Valid
  858. * 0x04, VextSupply3HwHPReq2Valid
  859. */
  860. REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
  861. /*
  862. * 0x20, VanaSwHPReqValid
  863. * 0x80, Vaux1SwHPReqValid
  864. */
  865. REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
  866. /*
  867. * 0x01, Vaux2SwHPReqValid
  868. * 0x02, Vaux3SwHPReqValid
  869. * 0x04, VextSupply1SwHPReqValid
  870. * 0x08, VextSupply2SwHPReqValid
  871. * 0x10, VextSupply3SwHPReqValid
  872. */
  873. REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
  874. /*
  875. * 0x02, SysClkReq2Valid1
  876. * 0x04, SysClkReq3Valid1
  877. * 0x08, SysClkReq4Valid1
  878. * 0x10, SysClkReq5Valid1
  879. * 0x20, SysClkReq6Valid1
  880. * 0x40, SysClkReq7Valid1
  881. * 0x80, SysClkReq8Valid1
  882. */
  883. REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
  884. /*
  885. * 0x02, SysClkReq2Valid2
  886. * 0x04, SysClkReq3Valid2
  887. * 0x08, SysClkReq4Valid2
  888. * 0x10, SysClkReq5Valid2
  889. * 0x20, SysClkReq6Valid2
  890. * 0x40, SysClkReq7Valid2
  891. * 0x80, SysClkReq8Valid2
  892. */
  893. REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
  894. /*
  895. * 0x02, VTVoutEna
  896. * 0x04, Vintcore12Ena
  897. * 0x38, Vintcore12Sel
  898. * 0x40, Vintcore12LP
  899. * 0x80, VTVoutLP
  900. */
  901. REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
  902. /*
  903. * 0x02, VaudioEna
  904. * 0x04, VdmicEna
  905. * 0x08, Vamic1Ena
  906. * 0x10, Vamic2Ena
  907. */
  908. REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
  909. /*
  910. * 0x01, Vamic1_dzout
  911. * 0x02, Vamic2_dzout
  912. */
  913. REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
  914. /*
  915. * 0x03, VpllRegu (NOTE! PRCMU register bits)
  916. * 0x0c, VanaRegu
  917. */
  918. REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
  919. /*
  920. * 0x01, VrefDDREna
  921. * 0x02, VrefDDRSleepMode
  922. */
  923. REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
  924. /*
  925. * 0x03, VextSupply1Regu
  926. * 0x0c, VextSupply2Regu
  927. * 0x30, VextSupply3Regu
  928. * 0x40, ExtSupply2Bypass
  929. * 0x80, ExtSupply3Bypass
  930. */
  931. REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
  932. /*
  933. * 0x03, Vaux1Regu
  934. * 0x0c, Vaux2Regu
  935. */
  936. REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
  937. /*
  938. * 0x03, Vaux3Regu
  939. */
  940. REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
  941. /*
  942. * 0x0f, Vaux1Sel
  943. */
  944. REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
  945. /*
  946. * 0x0f, Vaux2Sel
  947. */
  948. REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
  949. /*
  950. * 0x07, Vaux3Sel
  951. */
  952. REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
  953. /*
  954. * 0x01, VextSupply12LP
  955. */
  956. REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
  957. /*
  958. * 0x04, Vaux1Disch
  959. * 0x08, Vaux2Disch
  960. * 0x10, Vaux3Disch
  961. * 0x20, Vintcore12Disch
  962. * 0x40, VTVoutDisch
  963. * 0x80, VaudioDisch
  964. */
  965. REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
  966. /*
  967. * 0x02, VanaDisch
  968. * 0x04, VdmicPullDownEna
  969. * 0x10, VdmicDisch
  970. */
  971. REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
  972. };
  973. /* AB9540 register init */
  974. static struct ab8500_reg_init ab9540_reg_init[] = {
  975. /*
  976. * 0x03, VarmRequestCtrl
  977. * 0x0c, VapeRequestCtrl
  978. * 0x30, Vsmps1RequestCtrl
  979. * 0xc0, Vsmps2RequestCtrl
  980. */
  981. REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
  982. /*
  983. * 0x03, Vsmps3RequestCtrl
  984. * 0x0c, VpllRequestCtrl
  985. * 0x30, VanaRequestCtrl
  986. * 0xc0, VextSupply1RequestCtrl
  987. */
  988. REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
  989. /*
  990. * 0x03, VextSupply2RequestCtrl
  991. * 0x0c, VextSupply3RequestCtrl
  992. * 0x30, Vaux1RequestCtrl
  993. * 0xc0, Vaux2RequestCtrl
  994. */
  995. REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
  996. /*
  997. * 0x03, Vaux3RequestCtrl
  998. * 0x04, SwHPReq
  999. */
  1000. REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
  1001. /*
  1002. * 0x01, Vsmps1SysClkReq1HPValid
  1003. * 0x02, Vsmps2SysClkReq1HPValid
  1004. * 0x04, Vsmps3SysClkReq1HPValid
  1005. * 0x08, VanaSysClkReq1HPValid
  1006. * 0x10, VpllSysClkReq1HPValid
  1007. * 0x20, Vaux1SysClkReq1HPValid
  1008. * 0x40, Vaux2SysClkReq1HPValid
  1009. * 0x80, Vaux3SysClkReq1HPValid
  1010. */
  1011. REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
  1012. /*
  1013. * 0x01, VapeSysClkReq1HPValid
  1014. * 0x02, VarmSysClkReq1HPValid
  1015. * 0x04, VbbSysClkReq1HPValid
  1016. * 0x08, VmodSysClkReq1HPValid
  1017. * 0x10, VextSupply1SysClkReq1HPValid
  1018. * 0x20, VextSupply2SysClkReq1HPValid
  1019. * 0x40, VextSupply3SysClkReq1HPValid
  1020. */
  1021. REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
  1022. /*
  1023. * 0x01, Vsmps1HwHPReq1Valid
  1024. * 0x02, Vsmps2HwHPReq1Valid
  1025. * 0x04, Vsmps3HwHPReq1Valid
  1026. * 0x08, VanaHwHPReq1Valid
  1027. * 0x10, VpllHwHPReq1Valid
  1028. * 0x20, Vaux1HwHPReq1Valid
  1029. * 0x40, Vaux2HwHPReq1Valid
  1030. * 0x80, Vaux3HwHPReq1Valid
  1031. */
  1032. REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
  1033. /*
  1034. * 0x01, VextSupply1HwHPReq1Valid
  1035. * 0x02, VextSupply2HwHPReq1Valid
  1036. * 0x04, VextSupply3HwHPReq1Valid
  1037. * 0x08, VmodHwHPReq1Valid
  1038. */
  1039. REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
  1040. /*
  1041. * 0x01, Vsmps1HwHPReq2Valid
  1042. * 0x02, Vsmps2HwHPReq2Valid
  1043. * 0x03, Vsmps3HwHPReq2Valid
  1044. * 0x08, VanaHwHPReq2Valid
  1045. * 0x10, VpllHwHPReq2Valid
  1046. * 0x20, Vaux1HwHPReq2Valid
  1047. * 0x40, Vaux2HwHPReq2Valid
  1048. * 0x80, Vaux3HwHPReq2Valid
  1049. */
  1050. REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
  1051. /*
  1052. * 0x01, VextSupply1HwHPReq2Valid
  1053. * 0x02, VextSupply2HwHPReq2Valid
  1054. * 0x04, VextSupply3HwHPReq2Valid
  1055. * 0x08, VmodHwHPReq2Valid
  1056. */
  1057. REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
  1058. /*
  1059. * 0x01, VapeSwHPReqValid
  1060. * 0x02, VarmSwHPReqValid
  1061. * 0x04, Vsmps1SwHPReqValid
  1062. * 0x08, Vsmps2SwHPReqValid
  1063. * 0x10, Vsmps3SwHPReqValid
  1064. * 0x20, VanaSwHPReqValid
  1065. * 0x40, VpllSwHPReqValid
  1066. * 0x80, Vaux1SwHPReqValid
  1067. */
  1068. REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
  1069. /*
  1070. * 0x01, Vaux2SwHPReqValid
  1071. * 0x02, Vaux3SwHPReqValid
  1072. * 0x04, VextSupply1SwHPReqValid
  1073. * 0x08, VextSupply2SwHPReqValid
  1074. * 0x10, VextSupply3SwHPReqValid
  1075. * 0x20, VmodSwHPReqValid
  1076. */
  1077. REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
  1078. /*
  1079. * 0x02, SysClkReq2Valid1
  1080. * ...
  1081. * 0x80, SysClkReq8Valid1
  1082. */
  1083. REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
  1084. /*
  1085. * 0x02, SysClkReq2Valid2
  1086. * ...
  1087. * 0x80, SysClkReq8Valid2
  1088. */
  1089. REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
  1090. /*
  1091. * 0x01, Vaux4SwHPReqValid
  1092. * 0x02, Vaux4HwHPReq2Valid
  1093. * 0x04, Vaux4HwHPReq1Valid
  1094. * 0x08, Vaux4SysClkReq1HPValid
  1095. */
  1096. REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
  1097. /*
  1098. * 0x02, VTVoutEna
  1099. * 0x04, Vintcore12Ena
  1100. * 0x38, Vintcore12Sel
  1101. * 0x40, Vintcore12LP
  1102. * 0x80, VTVoutLP
  1103. */
  1104. REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
  1105. /*
  1106. * 0x02, VaudioEna
  1107. * 0x04, VdmicEna
  1108. * 0x08, Vamic1Ena
  1109. * 0x10, Vamic2Ena
  1110. */
  1111. REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
  1112. /*
  1113. * 0x01, Vamic1_dzout
  1114. * 0x02, Vamic2_dzout
  1115. */
  1116. REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
  1117. /*
  1118. * 0x03, Vsmps1Regu
  1119. * 0x0c, Vsmps1SelCtrl
  1120. * 0x10, Vsmps1AutoMode
  1121. * 0x20, Vsmps1PWMMode
  1122. */
  1123. REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
  1124. /*
  1125. * 0x03, Vsmps2Regu
  1126. * 0x0c, Vsmps2SelCtrl
  1127. * 0x10, Vsmps2AutoMode
  1128. * 0x20, Vsmps2PWMMode
  1129. */
  1130. REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
  1131. /*
  1132. * 0x03, Vsmps3Regu
  1133. * 0x0c, Vsmps3SelCtrl
  1134. * NOTE! PRCMU register
  1135. */
  1136. REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
  1137. /*
  1138. * 0x03, VpllRegu
  1139. * 0x0c, VanaRegu
  1140. */
  1141. REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
  1142. /*
  1143. * 0x03, VextSupply1Regu
  1144. * 0x0c, VextSupply2Regu
  1145. * 0x30, VextSupply3Regu
  1146. * 0x40, ExtSupply2Bypass
  1147. * 0x80, ExtSupply3Bypass
  1148. */
  1149. REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
  1150. /*
  1151. * 0x03, Vaux1Regu
  1152. * 0x0c, Vaux2Regu
  1153. */
  1154. REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
  1155. /*
  1156. * 0x0c, Vrf1Regu
  1157. * 0x03, Vaux3Regu
  1158. */
  1159. REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
  1160. /*
  1161. * 0x3f, Vsmps1Sel1
  1162. */
  1163. REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
  1164. /*
  1165. * 0x3f, Vsmps1Sel2
  1166. */
  1167. REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
  1168. /*
  1169. * 0x3f, Vsmps1Sel3
  1170. */
  1171. REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
  1172. /*
  1173. * 0x3f, Vsmps2Sel1
  1174. */
  1175. REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
  1176. /*
  1177. * 0x3f, Vsmps2Sel2
  1178. */
  1179. REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
  1180. /*
  1181. * 0x3f, Vsmps2Sel3
  1182. */
  1183. REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
  1184. /*
  1185. * 0x7f, Vsmps3Sel1
  1186. * NOTE! PRCMU register
  1187. */
  1188. REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
  1189. /*
  1190. * 0x7f, Vsmps3Sel2
  1191. * NOTE! PRCMU register
  1192. */
  1193. REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
  1194. /*
  1195. * 0x0f, Vaux1Sel
  1196. */
  1197. REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
  1198. /*
  1199. * 0x0f, Vaux2Sel
  1200. */
  1201. REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
  1202. /*
  1203. * 0x07, Vaux3Sel
  1204. * 0x30, Vrf1Sel
  1205. */
  1206. REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
  1207. /*
  1208. * 0x01, VextSupply12LP
  1209. */
  1210. REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
  1211. /*
  1212. * 0x03, Vaux4RequestCtrl
  1213. */
  1214. REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
  1215. /*
  1216. * 0x03, Vaux4Regu
  1217. */
  1218. REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
  1219. /*
  1220. * 0x08, Vaux4Sel
  1221. */
  1222. REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
  1223. /*
  1224. * 0x01, VpllDisch
  1225. * 0x02, Vrf1Disch
  1226. * 0x04, Vaux1Disch
  1227. * 0x08, Vaux2Disch
  1228. * 0x10, Vaux3Disch
  1229. * 0x20, Vintcore12Disch
  1230. * 0x40, VTVoutDisch
  1231. * 0x80, VaudioDisch
  1232. */
  1233. REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
  1234. /*
  1235. * 0x01, VsimDisch
  1236. * 0x02, VanaDisch
  1237. * 0x04, VdmicPullDownEna
  1238. * 0x08, VpllPullDownEna
  1239. * 0x10, VdmicDisch
  1240. */
  1241. REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
  1242. /*
  1243. * 0x01, Vaux4Disch
  1244. */
  1245. REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
  1246. };
  1247. static int ab8500_regulator_init_registers(struct platform_device *pdev,
  1248. struct ab8500_reg_init *reg_init,
  1249. int id, int mask, int value)
  1250. {
  1251. int err;
  1252. BUG_ON(value & ~mask);
  1253. BUG_ON(mask & ~reg_init[id].mask);
  1254. /* initialize register */
  1255. err = abx500_mask_and_set_register_interruptible(
  1256. &pdev->dev,
  1257. reg_init[id].bank,
  1258. reg_init[id].addr,
  1259. mask, value);
  1260. if (err < 0) {
  1261. dev_err(&pdev->dev,
  1262. "Failed to initialize 0x%02x, 0x%02x.\n",
  1263. reg_init[id].bank,
  1264. reg_init[id].addr);
  1265. return err;
  1266. }
  1267. dev_vdbg(&pdev->dev,
  1268. " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
  1269. reg_init[id].bank,
  1270. reg_init[id].addr,
  1271. mask, value);
  1272. return 0;
  1273. }
  1274. static int ab8500_regulator_register(struct platform_device *pdev,
  1275. struct regulator_init_data *init_data,
  1276. struct ab8500_regulator_info *regulator_info,
  1277. int id, struct device_node *np)
  1278. {
  1279. struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
  1280. struct ab8500_regulator_info *info = NULL;
  1281. struct regulator_config config = { };
  1282. int err;
  1283. /* assign per-regulator data */
  1284. info = &regulator_info[id];
  1285. info->dev = &pdev->dev;
  1286. config.dev = &pdev->dev;
  1287. config.init_data = init_data;
  1288. config.driver_data = info;
  1289. config.of_node = np;
  1290. /* fix for hardware before ab8500v2.0 */
  1291. if (is_ab8500_1p1_or_earlier(ab8500)) {
  1292. if (info->desc.id == AB8500_LDO_AUX3) {
  1293. info->desc.n_voltages =
  1294. ARRAY_SIZE(ldo_vauxn_voltages);
  1295. info->desc.volt_table = ldo_vauxn_voltages;
  1296. info->voltage_mask = 0xf;
  1297. }
  1298. }
  1299. /* register regulator with framework */
  1300. info->regulator = regulator_register(&info->desc, &config);
  1301. if (IS_ERR(info->regulator)) {
  1302. err = PTR_ERR(info->regulator);
  1303. dev_err(&pdev->dev, "failed to register regulator %s\n",
  1304. info->desc.name);
  1305. /* when we fail, un-register all earlier regulators */
  1306. while (--id >= 0) {
  1307. info = &regulator_info[id];
  1308. regulator_unregister(info->regulator);
  1309. }
  1310. return err;
  1311. }
  1312. return 0;
  1313. }
  1314. static struct of_regulator_match ab8500_regulator_match[] = {
  1315. { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
  1316. { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
  1317. { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
  1318. { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
  1319. { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
  1320. { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
  1321. { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
  1322. { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
  1323. { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
  1324. { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
  1325. };
  1326. static struct of_regulator_match ab9540_regulator_match[] = {
  1327. { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
  1328. { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
  1329. { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
  1330. { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
  1331. { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
  1332. { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
  1333. { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
  1334. { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
  1335. { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
  1336. { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
  1337. { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
  1338. };
  1339. static int
  1340. ab8500_regulator_of_probe(struct platform_device *pdev,
  1341. struct ab8500_regulator_info *regulator_info,
  1342. int regulator_info_size,
  1343. struct of_regulator_match *match,
  1344. struct device_node *np)
  1345. {
  1346. int err, i;
  1347. for (i = 0; i < regulator_info_size; i++) {
  1348. err = ab8500_regulator_register(
  1349. pdev, match[i].init_data, regulator_info,
  1350. i, match[i].of_node);
  1351. if (err)
  1352. return err;
  1353. }
  1354. return 0;
  1355. }
  1356. static int ab8500_regulator_probe(struct platform_device *pdev)
  1357. {
  1358. struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
  1359. struct device_node *np = pdev->dev.of_node;
  1360. struct of_regulator_match *match;
  1361. struct ab8500_platform_data *ppdata;
  1362. struct ab8500_regulator_platform_data *pdata;
  1363. int i, err;
  1364. struct ab8500_regulator_info *regulator_info;
  1365. int regulator_info_size;
  1366. struct ab8500_reg_init *reg_init;
  1367. int reg_init_size;
  1368. if (is_ab9540(ab8500)) {
  1369. regulator_info = ab9540_regulator_info;
  1370. regulator_info_size = ARRAY_SIZE(ab9540_regulator_info);
  1371. reg_init = ab9540_reg_init;
  1372. reg_init_size = AB9540_NUM_REGULATOR_REGISTERS;
  1373. match = ab9540_regulator_match;
  1374. match_size = ARRAY_SIZE(ab9540_regulator_match)
  1375. } else {
  1376. regulator_info = ab8500_regulator_info;
  1377. regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
  1378. reg_init = ab8500_reg_init;
  1379. reg_init_size = AB8500_NUM_REGULATOR_REGISTERS;
  1380. match = ab8500_regulator_match;
  1381. match_size = ARRAY_SIZE(ab8500_regulator_match)
  1382. }
  1383. if (np) {
  1384. err = of_regulator_match(&pdev->dev, np, match, match_size);
  1385. if (err < 0) {
  1386. dev_err(&pdev->dev,
  1387. "Error parsing regulator init data: %d\n", err);
  1388. return err;
  1389. }
  1390. err = ab8500_regulator_of_probe(pdev, regulator_info,
  1391. regulator_info_size, match, np);
  1392. return err;
  1393. }
  1394. if (!ab8500) {
  1395. dev_err(&pdev->dev, "null mfd parent\n");
  1396. return -EINVAL;
  1397. }
  1398. ppdata = dev_get_platdata(ab8500->dev);
  1399. if (!ppdata) {
  1400. dev_err(&pdev->dev, "null parent pdata\n");
  1401. return -EINVAL;
  1402. }
  1403. pdata = ppdata->regulator;
  1404. if (!pdata) {
  1405. dev_err(&pdev->dev, "null pdata\n");
  1406. return -EINVAL;
  1407. }
  1408. /* make sure the platform data has the correct size */
  1409. if (pdata->num_regulator != regulator_info_size) {
  1410. dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
  1411. return -EINVAL;
  1412. }
  1413. /* initialize debug (initial state is recorded with this call) */
  1414. err = ab8500_regulator_debug_init(pdev);
  1415. if (err)
  1416. return err;
  1417. /* initialize registers */
  1418. for (i = 0; i < pdata->num_reg_init; i++) {
  1419. int id, mask, value;
  1420. id = pdata->reg_init[i].id;
  1421. mask = pdata->reg_init[i].mask;
  1422. value = pdata->reg_init[i].value;
  1423. /* check for configuration errors */
  1424. BUG_ON(id >= AB8500_NUM_REGULATOR_REGISTERS);
  1425. err = ab8500_regulator_init_registers(pdev, reg_init, id, mask, value);
  1426. if (err < 0)
  1427. return err;
  1428. }
  1429. /* register external regulators (before Vaux1, 2 and 3) */
  1430. err = ab8500_ext_regulator_init(pdev);
  1431. if (err)
  1432. return err;
  1433. /* register all regulators */
  1434. for (i = 0; i < regulator_info_size; i++) {
  1435. err = ab8500_regulator_register(pdev, &pdata->regulator[i],
  1436. regulator_info, i, NULL);
  1437. if (err < 0)
  1438. return err;
  1439. }
  1440. return 0;
  1441. }
  1442. static int ab8500_regulator_remove(struct platform_device *pdev)
  1443. {
  1444. int i, err;
  1445. struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
  1446. struct ab8500_regulator_info *regulator_info;
  1447. int regulator_info_size;
  1448. if (is_ab9540(ab8500)) {
  1449. regulator_info = ab9540_regulator_info;
  1450. regulator_info_size = ARRAY_SIZE(ab9540_regulator_info);
  1451. } else {
  1452. regulator_info = ab8500_regulator_info;
  1453. regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
  1454. }
  1455. for (i = 0; i < regulator_info_size; i++) {
  1456. struct ab8500_regulator_info *info = NULL;
  1457. info = &regulator_info[i];
  1458. dev_vdbg(rdev_get_dev(info->regulator),
  1459. "%s-remove\n", info->desc.name);
  1460. regulator_unregister(info->regulator);
  1461. }
  1462. /* remove external regulators (after Vaux1, 2 and 3) */
  1463. err = ab8500_ext_regulator_exit(pdev);
  1464. if (err)
  1465. return err;
  1466. /* remove regulator debug */
  1467. err = ab8500_regulator_debug_exit(pdev);
  1468. if (err)
  1469. return err;
  1470. return 0;
  1471. }
  1472. static struct platform_driver ab8500_regulator_driver = {
  1473. .probe = ab8500_regulator_probe,
  1474. .remove = ab8500_regulator_remove,
  1475. .driver = {
  1476. .name = "ab8500-regulator",
  1477. .owner = THIS_MODULE,
  1478. },
  1479. };
  1480. static int __init ab8500_regulator_init(void)
  1481. {
  1482. int ret;
  1483. ret = platform_driver_register(&ab8500_regulator_driver);
  1484. if (ret != 0)
  1485. pr_err("Failed to register ab8500 regulator: %d\n", ret);
  1486. return ret;
  1487. }
  1488. subsys_initcall(ab8500_regulator_init);
  1489. static void __exit ab8500_regulator_exit(void)
  1490. {
  1491. platform_driver_unregister(&ab8500_regulator_driver);
  1492. }
  1493. module_exit(ab8500_regulator_exit);
  1494. MODULE_LICENSE("GPL v2");
  1495. MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
  1496. MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
  1497. MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
  1498. MODULE_ALIAS("platform:ab8500-regulator");