s3c2410.c 28 KB

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  1. /* linux/drivers/mtd/nand/s3c2410.c
  2. *
  3. * Copyright © 2004-2008 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * Samsung S3C2410/S3C2440/S3C2412 NAND driver
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  24. #define DEBUG
  25. #endif
  26. #include <linux/module.h>
  27. #include <linux/types.h>
  28. #include <linux/init.h>
  29. #include <linux/kernel.h>
  30. #include <linux/string.h>
  31. #include <linux/ioport.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/delay.h>
  34. #include <linux/err.h>
  35. #include <linux/slab.h>
  36. #include <linux/clk.h>
  37. #include <linux/cpufreq.h>
  38. #include <linux/mtd/mtd.h>
  39. #include <linux/mtd/nand.h>
  40. #include <linux/mtd/nand_ecc.h>
  41. #include <linux/mtd/partitions.h>
  42. #include <asm/io.h>
  43. #include <plat/regs-nand.h>
  44. #include <plat/nand.h>
  45. #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
  46. static int hardware_ecc = 1;
  47. #else
  48. static int hardware_ecc = 0;
  49. #endif
  50. #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
  51. static int clock_stop = 1;
  52. #else
  53. static const int clock_stop = 0;
  54. #endif
  55. /* new oob placement block for use with hardware ecc generation
  56. */
  57. static struct nand_ecclayout nand_hw_eccoob = {
  58. .eccbytes = 3,
  59. .eccpos = {0, 1, 2},
  60. .oobfree = {{8, 8}}
  61. };
  62. /* controller and mtd information */
  63. struct s3c2410_nand_info;
  64. /**
  65. * struct s3c2410_nand_mtd - driver MTD structure
  66. * @mtd: The MTD instance to pass to the MTD layer.
  67. * @chip: The NAND chip information.
  68. * @set: The platform information supplied for this set of NAND chips.
  69. * @info: Link back to the hardware information.
  70. * @scan_res: The result from calling nand_scan_ident().
  71. */
  72. struct s3c2410_nand_mtd {
  73. struct mtd_info mtd;
  74. struct nand_chip chip;
  75. struct s3c2410_nand_set *set;
  76. struct s3c2410_nand_info *info;
  77. int scan_res;
  78. };
  79. enum s3c_cpu_type {
  80. TYPE_S3C2410,
  81. TYPE_S3C2412,
  82. TYPE_S3C2440,
  83. };
  84. /* overview of the s3c2410 nand state */
  85. /**
  86. * struct s3c2410_nand_info - NAND controller state.
  87. * @mtds: An array of MTD instances on this controoler.
  88. * @platform: The platform data for this board.
  89. * @device: The platform device we bound to.
  90. * @area: The IO area resource that came from request_mem_region().
  91. * @clk: The clock resource for this controller.
  92. * @regs: The area mapped for the hardware registers described by @area.
  93. * @sel_reg: Pointer to the register controlling the NAND selection.
  94. * @sel_bit: The bit in @sel_reg to select the NAND chip.
  95. * @mtd_count: The number of MTDs created from this controller.
  96. * @save_sel: The contents of @sel_reg to be saved over suspend.
  97. * @clk_rate: The clock rate from @clk.
  98. * @cpu_type: The exact type of this controller.
  99. */
  100. struct s3c2410_nand_info {
  101. /* mtd info */
  102. struct nand_hw_control controller;
  103. struct s3c2410_nand_mtd *mtds;
  104. struct s3c2410_platform_nand *platform;
  105. /* device info */
  106. struct device *device;
  107. struct resource *area;
  108. struct clk *clk;
  109. void __iomem *regs;
  110. void __iomem *sel_reg;
  111. int sel_bit;
  112. int mtd_count;
  113. unsigned long save_sel;
  114. unsigned long clk_rate;
  115. enum s3c_cpu_type cpu_type;
  116. #ifdef CONFIG_CPU_FREQ
  117. struct notifier_block freq_transition;
  118. #endif
  119. };
  120. /* conversion functions */
  121. static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
  122. {
  123. return container_of(mtd, struct s3c2410_nand_mtd, mtd);
  124. }
  125. static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
  126. {
  127. return s3c2410_nand_mtd_toours(mtd)->info;
  128. }
  129. static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
  130. {
  131. return platform_get_drvdata(dev);
  132. }
  133. static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
  134. {
  135. return dev->dev.platform_data;
  136. }
  137. static inline int allow_clk_stop(struct s3c2410_nand_info *info)
  138. {
  139. return clock_stop;
  140. }
  141. /* timing calculations */
  142. #define NS_IN_KHZ 1000000
  143. /**
  144. * s3c_nand_calc_rate - calculate timing data.
  145. * @wanted: The cycle time in nanoseconds.
  146. * @clk: The clock rate in kHz.
  147. * @max: The maximum divider value.
  148. *
  149. * Calculate the timing value from the given parameters.
  150. */
  151. static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
  152. {
  153. int result;
  154. result = (wanted * clk) / NS_IN_KHZ;
  155. result++;
  156. pr_debug("result %d from %ld, %d\n", result, clk, wanted);
  157. if (result > max) {
  158. printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
  159. return -1;
  160. }
  161. if (result < 1)
  162. result = 1;
  163. return result;
  164. }
  165. #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
  166. /* controller setup */
  167. /**
  168. * s3c2410_nand_setrate - setup controller timing information.
  169. * @info: The controller instance.
  170. *
  171. * Given the information supplied by the platform, calculate and set
  172. * the necessary timing registers in the hardware to generate the
  173. * necessary timing cycles to the hardware.
  174. */
  175. static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
  176. {
  177. struct s3c2410_platform_nand *plat = info->platform;
  178. int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
  179. int tacls, twrph0, twrph1;
  180. unsigned long clkrate = clk_get_rate(info->clk);
  181. unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
  182. unsigned long flags;
  183. /* calculate the timing information for the controller */
  184. info->clk_rate = clkrate;
  185. clkrate /= 1000; /* turn clock into kHz for ease of use */
  186. if (plat != NULL) {
  187. tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
  188. twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
  189. twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
  190. } else {
  191. /* default timings */
  192. tacls = tacls_max;
  193. twrph0 = 8;
  194. twrph1 = 8;
  195. }
  196. if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
  197. dev_err(info->device, "cannot get suitable timings\n");
  198. return -EINVAL;
  199. }
  200. dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
  201. tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
  202. switch (info->cpu_type) {
  203. case TYPE_S3C2410:
  204. mask = (S3C2410_NFCONF_TACLS(3) |
  205. S3C2410_NFCONF_TWRPH0(7) |
  206. S3C2410_NFCONF_TWRPH1(7));
  207. set = S3C2410_NFCONF_EN;
  208. set |= S3C2410_NFCONF_TACLS(tacls - 1);
  209. set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
  210. set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
  211. break;
  212. case TYPE_S3C2440:
  213. case TYPE_S3C2412:
  214. mask = (S3C2410_NFCONF_TACLS(tacls_max - 1) |
  215. S3C2410_NFCONF_TWRPH0(7) |
  216. S3C2410_NFCONF_TWRPH1(7));
  217. set = S3C2440_NFCONF_TACLS(tacls - 1);
  218. set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
  219. set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
  220. break;
  221. default:
  222. BUG();
  223. }
  224. local_irq_save(flags);
  225. cfg = readl(info->regs + S3C2410_NFCONF);
  226. cfg &= ~mask;
  227. cfg |= set;
  228. writel(cfg, info->regs + S3C2410_NFCONF);
  229. local_irq_restore(flags);
  230. dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
  231. return 0;
  232. }
  233. /**
  234. * s3c2410_nand_inithw - basic hardware initialisation
  235. * @info: The hardware state.
  236. *
  237. * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
  238. * to setup the hardware access speeds and set the controller to be enabled.
  239. */
  240. static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
  241. {
  242. int ret;
  243. ret = s3c2410_nand_setrate(info);
  244. if (ret < 0)
  245. return ret;
  246. switch (info->cpu_type) {
  247. case TYPE_S3C2410:
  248. default:
  249. break;
  250. case TYPE_S3C2440:
  251. case TYPE_S3C2412:
  252. /* enable the controller and de-assert nFCE */
  253. writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
  254. }
  255. return 0;
  256. }
  257. /**
  258. * s3c2410_nand_select_chip - select the given nand chip
  259. * @mtd: The MTD instance for this chip.
  260. * @chip: The chip number.
  261. *
  262. * This is called by the MTD layer to either select a given chip for the
  263. * @mtd instance, or to indicate that the access has finished and the
  264. * chip can be de-selected.
  265. *
  266. * The routine ensures that the nFCE line is correctly setup, and any
  267. * platform specific selection code is called to route nFCE to the specific
  268. * chip.
  269. */
  270. static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
  271. {
  272. struct s3c2410_nand_info *info;
  273. struct s3c2410_nand_mtd *nmtd;
  274. struct nand_chip *this = mtd->priv;
  275. unsigned long cur;
  276. nmtd = this->priv;
  277. info = nmtd->info;
  278. if (chip != -1 && allow_clk_stop(info))
  279. clk_enable(info->clk);
  280. cur = readl(info->sel_reg);
  281. if (chip == -1) {
  282. cur |= info->sel_bit;
  283. } else {
  284. if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
  285. dev_err(info->device, "invalid chip %d\n", chip);
  286. return;
  287. }
  288. if (info->platform != NULL) {
  289. if (info->platform->select_chip != NULL)
  290. (info->platform->select_chip) (nmtd->set, chip);
  291. }
  292. cur &= ~info->sel_bit;
  293. }
  294. writel(cur, info->sel_reg);
  295. if (chip == -1 && allow_clk_stop(info))
  296. clk_disable(info->clk);
  297. }
  298. /* s3c2410_nand_hwcontrol
  299. *
  300. * Issue command and address cycles to the chip
  301. */
  302. static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
  303. unsigned int ctrl)
  304. {
  305. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  306. if (cmd == NAND_CMD_NONE)
  307. return;
  308. if (ctrl & NAND_CLE)
  309. writeb(cmd, info->regs + S3C2410_NFCMD);
  310. else
  311. writeb(cmd, info->regs + S3C2410_NFADDR);
  312. }
  313. /* command and control functions */
  314. static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
  315. unsigned int ctrl)
  316. {
  317. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  318. if (cmd == NAND_CMD_NONE)
  319. return;
  320. if (ctrl & NAND_CLE)
  321. writeb(cmd, info->regs + S3C2440_NFCMD);
  322. else
  323. writeb(cmd, info->regs + S3C2440_NFADDR);
  324. }
  325. /* s3c2410_nand_devready()
  326. *
  327. * returns 0 if the nand is busy, 1 if it is ready
  328. */
  329. static int s3c2410_nand_devready(struct mtd_info *mtd)
  330. {
  331. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  332. return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
  333. }
  334. static int s3c2440_nand_devready(struct mtd_info *mtd)
  335. {
  336. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  337. return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
  338. }
  339. static int s3c2412_nand_devready(struct mtd_info *mtd)
  340. {
  341. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  342. return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
  343. }
  344. /* ECC handling functions */
  345. static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
  346. u_char *read_ecc, u_char *calc_ecc)
  347. {
  348. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  349. unsigned int diff0, diff1, diff2;
  350. unsigned int bit, byte;
  351. pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
  352. diff0 = read_ecc[0] ^ calc_ecc[0];
  353. diff1 = read_ecc[1] ^ calc_ecc[1];
  354. diff2 = read_ecc[2] ^ calc_ecc[2];
  355. pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
  356. __func__,
  357. read_ecc[0], read_ecc[1], read_ecc[2],
  358. calc_ecc[0], calc_ecc[1], calc_ecc[2],
  359. diff0, diff1, diff2);
  360. if (diff0 == 0 && diff1 == 0 && diff2 == 0)
  361. return 0; /* ECC is ok */
  362. /* sometimes people do not think about using the ECC, so check
  363. * to see if we have an 0xff,0xff,0xff read ECC and then ignore
  364. * the error, on the assumption that this is an un-eccd page.
  365. */
  366. if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
  367. && info->platform->ignore_unset_ecc)
  368. return 0;
  369. /* Can we correct this ECC (ie, one row and column change).
  370. * Note, this is similar to the 256 error code on smartmedia */
  371. if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
  372. ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
  373. ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
  374. /* calculate the bit position of the error */
  375. bit = ((diff2 >> 3) & 1) |
  376. ((diff2 >> 4) & 2) |
  377. ((diff2 >> 5) & 4);
  378. /* calculate the byte position of the error */
  379. byte = ((diff2 << 7) & 0x100) |
  380. ((diff1 << 0) & 0x80) |
  381. ((diff1 << 1) & 0x40) |
  382. ((diff1 << 2) & 0x20) |
  383. ((diff1 << 3) & 0x10) |
  384. ((diff0 >> 4) & 0x08) |
  385. ((diff0 >> 3) & 0x04) |
  386. ((diff0 >> 2) & 0x02) |
  387. ((diff0 >> 1) & 0x01);
  388. dev_dbg(info->device, "correcting error bit %d, byte %d\n",
  389. bit, byte);
  390. dat[byte] ^= (1 << bit);
  391. return 1;
  392. }
  393. /* if there is only one bit difference in the ECC, then
  394. * one of only a row or column parity has changed, which
  395. * means the error is most probably in the ECC itself */
  396. diff0 |= (diff1 << 8);
  397. diff0 |= (diff2 << 16);
  398. if ((diff0 & ~(1<<fls(diff0))) == 0)
  399. return 1;
  400. return -1;
  401. }
  402. /* ECC functions
  403. *
  404. * These allow the s3c2410 and s3c2440 to use the controller's ECC
  405. * generator block to ECC the data as it passes through]
  406. */
  407. static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  408. {
  409. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  410. unsigned long ctrl;
  411. ctrl = readl(info->regs + S3C2410_NFCONF);
  412. ctrl |= S3C2410_NFCONF_INITECC;
  413. writel(ctrl, info->regs + S3C2410_NFCONF);
  414. }
  415. static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  416. {
  417. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  418. unsigned long ctrl;
  419. ctrl = readl(info->regs + S3C2440_NFCONT);
  420. writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT);
  421. }
  422. static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  423. {
  424. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  425. unsigned long ctrl;
  426. ctrl = readl(info->regs + S3C2440_NFCONT);
  427. writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
  428. }
  429. static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
  430. {
  431. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  432. ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
  433. ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
  434. ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
  435. pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
  436. ecc_code[0], ecc_code[1], ecc_code[2]);
  437. return 0;
  438. }
  439. static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
  440. {
  441. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  442. unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
  443. ecc_code[0] = ecc;
  444. ecc_code[1] = ecc >> 8;
  445. ecc_code[2] = ecc >> 16;
  446. pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
  447. return 0;
  448. }
  449. static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
  450. {
  451. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  452. unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
  453. ecc_code[0] = ecc;
  454. ecc_code[1] = ecc >> 8;
  455. ecc_code[2] = ecc >> 16;
  456. pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
  457. return 0;
  458. }
  459. /* over-ride the standard functions for a little more speed. We can
  460. * use read/write block to move the data buffers to/from the controller
  461. */
  462. static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  463. {
  464. struct nand_chip *this = mtd->priv;
  465. readsb(this->IO_ADDR_R, buf, len);
  466. }
  467. static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  468. {
  469. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  470. readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
  471. }
  472. static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  473. {
  474. struct nand_chip *this = mtd->priv;
  475. writesb(this->IO_ADDR_W, buf, len);
  476. }
  477. static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  478. {
  479. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  480. writesl(info->regs + S3C2440_NFDATA, buf, len / 4);
  481. }
  482. /* cpufreq driver support */
  483. #ifdef CONFIG_CPU_FREQ
  484. static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
  485. unsigned long val, void *data)
  486. {
  487. struct s3c2410_nand_info *info;
  488. unsigned long newclk;
  489. info = container_of(nb, struct s3c2410_nand_info, freq_transition);
  490. newclk = clk_get_rate(info->clk);
  491. if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
  492. (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
  493. s3c2410_nand_setrate(info);
  494. }
  495. return 0;
  496. }
  497. static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
  498. {
  499. info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
  500. return cpufreq_register_notifier(&info->freq_transition,
  501. CPUFREQ_TRANSITION_NOTIFIER);
  502. }
  503. static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
  504. {
  505. cpufreq_unregister_notifier(&info->freq_transition,
  506. CPUFREQ_TRANSITION_NOTIFIER);
  507. }
  508. #else
  509. static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
  510. {
  511. return 0;
  512. }
  513. static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
  514. {
  515. }
  516. #endif
  517. /* device management functions */
  518. static int s3c24xx_nand_remove(struct platform_device *pdev)
  519. {
  520. struct s3c2410_nand_info *info = to_nand_info(pdev);
  521. platform_set_drvdata(pdev, NULL);
  522. if (info == NULL)
  523. return 0;
  524. s3c2410_nand_cpufreq_deregister(info);
  525. /* Release all our mtds and their partitions, then go through
  526. * freeing the resources used
  527. */
  528. if (info->mtds != NULL) {
  529. struct s3c2410_nand_mtd *ptr = info->mtds;
  530. int mtdno;
  531. for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
  532. pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
  533. nand_release(&ptr->mtd);
  534. }
  535. kfree(info->mtds);
  536. }
  537. /* free the common resources */
  538. if (info->clk != NULL && !IS_ERR(info->clk)) {
  539. if (!allow_clk_stop(info))
  540. clk_disable(info->clk);
  541. clk_put(info->clk);
  542. }
  543. if (info->regs != NULL) {
  544. iounmap(info->regs);
  545. info->regs = NULL;
  546. }
  547. if (info->area != NULL) {
  548. release_resource(info->area);
  549. kfree(info->area);
  550. info->area = NULL;
  551. }
  552. kfree(info);
  553. return 0;
  554. }
  555. #ifdef CONFIG_MTD_PARTITIONS
  556. const char *part_probes[] = { "cmdlinepart", NULL };
  557. static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
  558. struct s3c2410_nand_mtd *mtd,
  559. struct s3c2410_nand_set *set)
  560. {
  561. struct mtd_partition *part_info;
  562. int nr_part = 0;
  563. if (set == NULL)
  564. return add_mtd_device(&mtd->mtd);
  565. if (set->nr_partitions == 0) {
  566. mtd->mtd.name = set->name;
  567. nr_part = parse_mtd_partitions(&mtd->mtd, part_probes,
  568. &part_info, 0);
  569. } else {
  570. if (set->nr_partitions > 0 && set->partitions != NULL) {
  571. nr_part = set->nr_partitions;
  572. part_info = set->partitions;
  573. }
  574. }
  575. if (nr_part > 0 && part_info)
  576. return add_mtd_partitions(&mtd->mtd, part_info, nr_part);
  577. return add_mtd_device(&mtd->mtd);
  578. }
  579. #else
  580. static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
  581. struct s3c2410_nand_mtd *mtd,
  582. struct s3c2410_nand_set *set)
  583. {
  584. return add_mtd_device(&mtd->mtd);
  585. }
  586. #endif
  587. /**
  588. * s3c2410_nand_init_chip - initialise a single instance of an chip
  589. * @info: The base NAND controller the chip is on.
  590. * @nmtd: The new controller MTD instance to fill in.
  591. * @set: The information passed from the board specific platform data.
  592. *
  593. * Initialise the given @nmtd from the information in @info and @set. This
  594. * readies the structure for use with the MTD layer functions by ensuring
  595. * all pointers are setup and the necessary control routines selected.
  596. */
  597. static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
  598. struct s3c2410_nand_mtd *nmtd,
  599. struct s3c2410_nand_set *set)
  600. {
  601. struct nand_chip *chip = &nmtd->chip;
  602. void __iomem *regs = info->regs;
  603. chip->write_buf = s3c2410_nand_write_buf;
  604. chip->read_buf = s3c2410_nand_read_buf;
  605. chip->select_chip = s3c2410_nand_select_chip;
  606. chip->chip_delay = 50;
  607. chip->priv = nmtd;
  608. chip->options = 0;
  609. chip->controller = &info->controller;
  610. switch (info->cpu_type) {
  611. case TYPE_S3C2410:
  612. chip->IO_ADDR_W = regs + S3C2410_NFDATA;
  613. info->sel_reg = regs + S3C2410_NFCONF;
  614. info->sel_bit = S3C2410_NFCONF_nFCE;
  615. chip->cmd_ctrl = s3c2410_nand_hwcontrol;
  616. chip->dev_ready = s3c2410_nand_devready;
  617. break;
  618. case TYPE_S3C2440:
  619. chip->IO_ADDR_W = regs + S3C2440_NFDATA;
  620. info->sel_reg = regs + S3C2440_NFCONT;
  621. info->sel_bit = S3C2440_NFCONT_nFCE;
  622. chip->cmd_ctrl = s3c2440_nand_hwcontrol;
  623. chip->dev_ready = s3c2440_nand_devready;
  624. chip->read_buf = s3c2440_nand_read_buf;
  625. chip->write_buf = s3c2440_nand_write_buf;
  626. break;
  627. case TYPE_S3C2412:
  628. chip->IO_ADDR_W = regs + S3C2440_NFDATA;
  629. info->sel_reg = regs + S3C2440_NFCONT;
  630. info->sel_bit = S3C2412_NFCONT_nFCE0;
  631. chip->cmd_ctrl = s3c2440_nand_hwcontrol;
  632. chip->dev_ready = s3c2412_nand_devready;
  633. if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
  634. dev_info(info->device, "System booted from NAND\n");
  635. break;
  636. }
  637. chip->IO_ADDR_R = chip->IO_ADDR_W;
  638. nmtd->info = info;
  639. nmtd->mtd.priv = chip;
  640. nmtd->mtd.owner = THIS_MODULE;
  641. nmtd->set = set;
  642. if (hardware_ecc) {
  643. chip->ecc.calculate = s3c2410_nand_calculate_ecc;
  644. chip->ecc.correct = s3c2410_nand_correct_data;
  645. chip->ecc.mode = NAND_ECC_HW;
  646. switch (info->cpu_type) {
  647. case TYPE_S3C2410:
  648. chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
  649. chip->ecc.calculate = s3c2410_nand_calculate_ecc;
  650. break;
  651. case TYPE_S3C2412:
  652. chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
  653. chip->ecc.calculate = s3c2412_nand_calculate_ecc;
  654. break;
  655. case TYPE_S3C2440:
  656. chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
  657. chip->ecc.calculate = s3c2440_nand_calculate_ecc;
  658. break;
  659. }
  660. } else {
  661. chip->ecc.mode = NAND_ECC_SOFT;
  662. }
  663. if (set->ecc_layout != NULL)
  664. chip->ecc.layout = set->ecc_layout;
  665. if (set->disable_ecc)
  666. chip->ecc.mode = NAND_ECC_NONE;
  667. switch (chip->ecc.mode) {
  668. case NAND_ECC_NONE:
  669. dev_info(info->device, "NAND ECC disabled\n");
  670. break;
  671. case NAND_ECC_SOFT:
  672. dev_info(info->device, "NAND soft ECC\n");
  673. break;
  674. case NAND_ECC_HW:
  675. dev_info(info->device, "NAND hardware ECC\n");
  676. break;
  677. default:
  678. dev_info(info->device, "NAND ECC UNKNOWN\n");
  679. break;
  680. }
  681. }
  682. /**
  683. * s3c2410_nand_update_chip - post probe update
  684. * @info: The controller instance.
  685. * @nmtd: The driver version of the MTD instance.
  686. *
  687. * This routine is called after the chip probe has succesfully completed
  688. * and the relevant per-chip information updated. This call ensure that
  689. * we update the internal state accordingly.
  690. *
  691. * The internal state is currently limited to the ECC state information.
  692. */
  693. static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
  694. struct s3c2410_nand_mtd *nmtd)
  695. {
  696. struct nand_chip *chip = &nmtd->chip;
  697. dev_dbg(info->device, "chip %p => page shift %d\n",
  698. chip, chip->page_shift);
  699. if (chip->ecc.mode != NAND_ECC_HW)
  700. return;
  701. /* change the behaviour depending on wether we are using
  702. * the large or small page nand device */
  703. if (chip->page_shift > 10) {
  704. chip->ecc.size = 256;
  705. chip->ecc.bytes = 3;
  706. } else {
  707. chip->ecc.size = 512;
  708. chip->ecc.bytes = 3;
  709. chip->ecc.layout = &nand_hw_eccoob;
  710. }
  711. }
  712. /* s3c24xx_nand_probe
  713. *
  714. * called by device layer when it finds a device matching
  715. * one our driver can handled. This code checks to see if
  716. * it can allocate all necessary resources then calls the
  717. * nand layer to look for devices
  718. */
  719. static int s3c24xx_nand_probe(struct platform_device *pdev)
  720. {
  721. struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
  722. enum s3c_cpu_type cpu_type;
  723. struct s3c2410_nand_info *info;
  724. struct s3c2410_nand_mtd *nmtd;
  725. struct s3c2410_nand_set *sets;
  726. struct resource *res;
  727. int err = 0;
  728. int size;
  729. int nr_sets;
  730. int setno;
  731. cpu_type = platform_get_device_id(pdev)->driver_data;
  732. pr_debug("s3c2410_nand_probe(%p)\n", pdev);
  733. info = kmalloc(sizeof(*info), GFP_KERNEL);
  734. if (info == NULL) {
  735. dev_err(&pdev->dev, "no memory for flash info\n");
  736. err = -ENOMEM;
  737. goto exit_error;
  738. }
  739. memset(info, 0, sizeof(*info));
  740. platform_set_drvdata(pdev, info);
  741. spin_lock_init(&info->controller.lock);
  742. init_waitqueue_head(&info->controller.wq);
  743. /* get the clock source and enable it */
  744. info->clk = clk_get(&pdev->dev, "nand");
  745. if (IS_ERR(info->clk)) {
  746. dev_err(&pdev->dev, "failed to get clock\n");
  747. err = -ENOENT;
  748. goto exit_error;
  749. }
  750. clk_enable(info->clk);
  751. /* allocate and map the resource */
  752. /* currently we assume we have the one resource */
  753. res = pdev->resource;
  754. size = res->end - res->start + 1;
  755. info->area = request_mem_region(res->start, size, pdev->name);
  756. if (info->area == NULL) {
  757. dev_err(&pdev->dev, "cannot reserve register region\n");
  758. err = -ENOENT;
  759. goto exit_error;
  760. }
  761. info->device = &pdev->dev;
  762. info->platform = plat;
  763. info->regs = ioremap(res->start, size);
  764. info->cpu_type = cpu_type;
  765. if (info->regs == NULL) {
  766. dev_err(&pdev->dev, "cannot reserve register region\n");
  767. err = -EIO;
  768. goto exit_error;
  769. }
  770. dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
  771. /* initialise the hardware */
  772. err = s3c2410_nand_inithw(info);
  773. if (err != 0)
  774. goto exit_error;
  775. sets = (plat != NULL) ? plat->sets : NULL;
  776. nr_sets = (plat != NULL) ? plat->nr_sets : 1;
  777. info->mtd_count = nr_sets;
  778. /* allocate our information */
  779. size = nr_sets * sizeof(*info->mtds);
  780. info->mtds = kmalloc(size, GFP_KERNEL);
  781. if (info->mtds == NULL) {
  782. dev_err(&pdev->dev, "failed to allocate mtd storage\n");
  783. err = -ENOMEM;
  784. goto exit_error;
  785. }
  786. memset(info->mtds, 0, size);
  787. /* initialise all possible chips */
  788. nmtd = info->mtds;
  789. for (setno = 0; setno < nr_sets; setno++, nmtd++) {
  790. pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
  791. s3c2410_nand_init_chip(info, nmtd, sets);
  792. nmtd->scan_res = nand_scan_ident(&nmtd->mtd,
  793. (sets) ? sets->nr_chips : 1);
  794. if (nmtd->scan_res == 0) {
  795. s3c2410_nand_update_chip(info, nmtd);
  796. nand_scan_tail(&nmtd->mtd);
  797. s3c2410_nand_add_partition(info, nmtd, sets);
  798. }
  799. if (sets != NULL)
  800. sets++;
  801. }
  802. err = s3c2410_nand_cpufreq_register(info);
  803. if (err < 0) {
  804. dev_err(&pdev->dev, "failed to init cpufreq support\n");
  805. goto exit_error;
  806. }
  807. if (allow_clk_stop(info)) {
  808. dev_info(&pdev->dev, "clock idle support enabled\n");
  809. clk_disable(info->clk);
  810. }
  811. pr_debug("initialised ok\n");
  812. return 0;
  813. exit_error:
  814. s3c24xx_nand_remove(pdev);
  815. if (err == 0)
  816. err = -EINVAL;
  817. return err;
  818. }
  819. /* PM Support */
  820. #ifdef CONFIG_PM
  821. static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
  822. {
  823. struct s3c2410_nand_info *info = platform_get_drvdata(dev);
  824. if (info) {
  825. info->save_sel = readl(info->sel_reg);
  826. /* For the moment, we must ensure nFCE is high during
  827. * the time we are suspended. This really should be
  828. * handled by suspending the MTDs we are using, but
  829. * that is currently not the case. */
  830. writel(info->save_sel | info->sel_bit, info->sel_reg);
  831. if (!allow_clk_stop(info))
  832. clk_disable(info->clk);
  833. }
  834. return 0;
  835. }
  836. static int s3c24xx_nand_resume(struct platform_device *dev)
  837. {
  838. struct s3c2410_nand_info *info = platform_get_drvdata(dev);
  839. unsigned long sel;
  840. if (info) {
  841. clk_enable(info->clk);
  842. s3c2410_nand_inithw(info);
  843. /* Restore the state of the nFCE line. */
  844. sel = readl(info->sel_reg);
  845. sel &= ~info->sel_bit;
  846. sel |= info->save_sel & info->sel_bit;
  847. writel(sel, info->sel_reg);
  848. if (allow_clk_stop(info))
  849. clk_disable(info->clk);
  850. }
  851. return 0;
  852. }
  853. #else
  854. #define s3c24xx_nand_suspend NULL
  855. #define s3c24xx_nand_resume NULL
  856. #endif
  857. /* driver device registration */
  858. static struct platform_device_id s3c24xx_driver_ids[] = {
  859. {
  860. .name = "s3c2410-nand",
  861. .driver_data = TYPE_S3C2410,
  862. }, {
  863. .name = "s3c2440-nand",
  864. .driver_data = TYPE_S3C2440,
  865. }, {
  866. .name = "s3c2412-nand",
  867. .driver_data = TYPE_S3C2412,
  868. },
  869. { }
  870. };
  871. MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
  872. static struct platform_driver s3c24xx_nand_driver = {
  873. .probe = s3c24xx_nand_probe,
  874. .remove = s3c24xx_nand_remove,
  875. .suspend = s3c24xx_nand_suspend,
  876. .resume = s3c24xx_nand_resume,
  877. .id_table = s3c24xx_driver_ids,
  878. .driver = {
  879. .name = "s3c24xx-nand",
  880. .owner = THIS_MODULE,
  881. },
  882. };
  883. static int __init s3c2410_nand_init(void)
  884. {
  885. printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
  886. return platform_driver_register(&s3c24xx_nand_driver);
  887. }
  888. static void __exit s3c2410_nand_exit(void)
  889. {
  890. platform_driver_unregister(&s3c24xx_nand_driver);
  891. }
  892. module_init(s3c2410_nand_init);
  893. module_exit(s3c2410_nand_exit);
  894. MODULE_LICENSE("GPL");
  895. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  896. MODULE_DESCRIPTION("S3C24XX MTD NAND driver");