radeon_test.c 14 KB

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  1. /*
  2. * Copyright 2009 VMware, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Michel Dänzer
  23. */
  24. #include <drm/drmP.h>
  25. #include <drm/radeon_drm.h>
  26. #include "radeon_reg.h"
  27. #include "radeon.h"
  28. #define RADEON_TEST_COPY_BLIT 1
  29. #define RADEON_TEST_COPY_DMA 0
  30. /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
  31. static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
  32. {
  33. struct radeon_bo *vram_obj = NULL;
  34. struct radeon_bo **gtt_obj = NULL;
  35. uint64_t gtt_addr, vram_addr;
  36. unsigned i, n, size;
  37. int r, ring;
  38. switch (flag) {
  39. case RADEON_TEST_COPY_DMA:
  40. ring = radeon_copy_dma_ring_index(rdev);
  41. break;
  42. case RADEON_TEST_COPY_BLIT:
  43. ring = radeon_copy_blit_ring_index(rdev);
  44. break;
  45. default:
  46. DRM_ERROR("Unknown copy method\n");
  47. return;
  48. }
  49. size = 1024 * 1024;
  50. /* Number of tests =
  51. * (Total GTT - IB pool - writeback page - ring buffers) / test size
  52. */
  53. n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024;
  54. for (i = 0; i < RADEON_NUM_RINGS; ++i)
  55. n -= rdev->ring[i].ring_size;
  56. if (rdev->wb.wb_obj)
  57. n -= RADEON_GPU_PAGE_SIZE;
  58. if (rdev->ih.ring_obj)
  59. n -= rdev->ih.ring_size;
  60. n /= size;
  61. gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
  62. if (!gtt_obj) {
  63. DRM_ERROR("Failed to allocate %d pointers\n", n);
  64. r = 1;
  65. goto out_cleanup;
  66. }
  67. r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  68. NULL, &vram_obj);
  69. if (r) {
  70. DRM_ERROR("Failed to create VRAM object\n");
  71. goto out_cleanup;
  72. }
  73. r = radeon_bo_reserve(vram_obj, false);
  74. if (unlikely(r != 0))
  75. goto out_unref;
  76. r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);
  77. if (r) {
  78. DRM_ERROR("Failed to pin VRAM object\n");
  79. goto out_unres;
  80. }
  81. for (i = 0; i < n; i++) {
  82. void *gtt_map, *vram_map;
  83. void **gtt_start, **gtt_end;
  84. void **vram_start, **vram_end;
  85. struct radeon_fence *fence = NULL;
  86. r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
  87. RADEON_GEM_DOMAIN_GTT, NULL, gtt_obj + i);
  88. if (r) {
  89. DRM_ERROR("Failed to create GTT object %d\n", i);
  90. goto out_lclean;
  91. }
  92. r = radeon_bo_reserve(gtt_obj[i], false);
  93. if (unlikely(r != 0))
  94. goto out_lclean_unref;
  95. r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, &gtt_addr);
  96. if (r) {
  97. DRM_ERROR("Failed to pin GTT object %d\n", i);
  98. goto out_lclean_unres;
  99. }
  100. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  101. if (r) {
  102. DRM_ERROR("Failed to map GTT object %d\n", i);
  103. goto out_lclean_unpin;
  104. }
  105. for (gtt_start = gtt_map, gtt_end = gtt_map + size;
  106. gtt_start < gtt_end;
  107. gtt_start++)
  108. *gtt_start = gtt_start;
  109. radeon_bo_kunmap(gtt_obj[i]);
  110. if (ring == R600_RING_TYPE_DMA_INDEX)
  111. r = radeon_copy_dma(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  112. else
  113. r = radeon_copy_blit(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  114. if (r) {
  115. DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
  116. goto out_lclean_unpin;
  117. }
  118. r = radeon_fence_wait(fence, false);
  119. if (r) {
  120. DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
  121. goto out_lclean_unpin;
  122. }
  123. radeon_fence_unref(&fence);
  124. r = radeon_bo_kmap(vram_obj, &vram_map);
  125. if (r) {
  126. DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
  127. goto out_lclean_unpin;
  128. }
  129. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  130. vram_start = vram_map, vram_end = vram_map + size;
  131. vram_start < vram_end;
  132. gtt_start++, vram_start++) {
  133. if (*vram_start != gtt_start) {
  134. DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
  135. "expected 0x%p (GTT/VRAM offset "
  136. "0x%16llx/0x%16llx)\n",
  137. i, *vram_start, gtt_start,
  138. (unsigned long long)
  139. (gtt_addr - rdev->mc.gtt_start +
  140. (void*)gtt_start - gtt_map),
  141. (unsigned long long)
  142. (vram_addr - rdev->mc.vram_start +
  143. (void*)gtt_start - gtt_map));
  144. radeon_bo_kunmap(vram_obj);
  145. goto out_lclean_unpin;
  146. }
  147. *vram_start = vram_start;
  148. }
  149. radeon_bo_kunmap(vram_obj);
  150. if (ring == R600_RING_TYPE_DMA_INDEX)
  151. r = radeon_copy_dma(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  152. else
  153. r = radeon_copy_blit(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  154. if (r) {
  155. DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
  156. goto out_lclean_unpin;
  157. }
  158. r = radeon_fence_wait(fence, false);
  159. if (r) {
  160. DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
  161. goto out_lclean_unpin;
  162. }
  163. radeon_fence_unref(&fence);
  164. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  165. if (r) {
  166. DRM_ERROR("Failed to map GTT object after copy %d\n", i);
  167. goto out_lclean_unpin;
  168. }
  169. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  170. vram_start = vram_map, vram_end = vram_map + size;
  171. gtt_start < gtt_end;
  172. gtt_start++, vram_start++) {
  173. if (*gtt_start != vram_start) {
  174. DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
  175. "expected 0x%p (VRAM/GTT offset "
  176. "0x%16llx/0x%16llx)\n",
  177. i, *gtt_start, vram_start,
  178. (unsigned long long)
  179. (vram_addr - rdev->mc.vram_start +
  180. (void*)vram_start - vram_map),
  181. (unsigned long long)
  182. (gtt_addr - rdev->mc.gtt_start +
  183. (void*)vram_start - vram_map));
  184. radeon_bo_kunmap(gtt_obj[i]);
  185. goto out_lclean_unpin;
  186. }
  187. }
  188. radeon_bo_kunmap(gtt_obj[i]);
  189. DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
  190. gtt_addr - rdev->mc.gtt_start);
  191. continue;
  192. out_lclean_unpin:
  193. radeon_bo_unpin(gtt_obj[i]);
  194. out_lclean_unres:
  195. radeon_bo_unreserve(gtt_obj[i]);
  196. out_lclean_unref:
  197. radeon_bo_unref(&gtt_obj[i]);
  198. out_lclean:
  199. for (--i; i >= 0; --i) {
  200. radeon_bo_unpin(gtt_obj[i]);
  201. radeon_bo_unreserve(gtt_obj[i]);
  202. radeon_bo_unref(&gtt_obj[i]);
  203. }
  204. if (fence)
  205. radeon_fence_unref(&fence);
  206. break;
  207. }
  208. radeon_bo_unpin(vram_obj);
  209. out_unres:
  210. radeon_bo_unreserve(vram_obj);
  211. out_unref:
  212. radeon_bo_unref(&vram_obj);
  213. out_cleanup:
  214. kfree(gtt_obj);
  215. if (r) {
  216. printk(KERN_WARNING "Error while testing BO move.\n");
  217. }
  218. }
  219. void radeon_test_moves(struct radeon_device *rdev)
  220. {
  221. if (rdev->asic->copy.dma)
  222. radeon_do_test_moves(rdev, RADEON_TEST_COPY_DMA);
  223. if (rdev->asic->copy.blit)
  224. radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT);
  225. }
  226. static int radeon_test_create_and_emit_fence(struct radeon_device *rdev,
  227. struct radeon_ring *ring,
  228. struct radeon_fence **fence)
  229. {
  230. int r;
  231. if (ring->idx == R600_RING_TYPE_UVD_INDEX) {
  232. r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
  233. if (r) {
  234. DRM_ERROR("Failed to get dummy create msg\n");
  235. return r;
  236. }
  237. r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, fence);
  238. if (r) {
  239. DRM_ERROR("Failed to get dummy destroy msg\n");
  240. return r;
  241. }
  242. } else {
  243. r = radeon_ring_lock(rdev, ring, 64);
  244. if (r) {
  245. DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
  246. return r;
  247. }
  248. radeon_fence_emit(rdev, fence, ring->idx);
  249. radeon_ring_unlock_commit(rdev, ring);
  250. }
  251. return 0;
  252. }
  253. void radeon_test_ring_sync(struct radeon_device *rdev,
  254. struct radeon_ring *ringA,
  255. struct radeon_ring *ringB)
  256. {
  257. struct radeon_fence *fence1 = NULL, *fence2 = NULL;
  258. struct radeon_semaphore *semaphore = NULL;
  259. int r;
  260. r = radeon_semaphore_create(rdev, &semaphore);
  261. if (r) {
  262. DRM_ERROR("Failed to create semaphore\n");
  263. goto out_cleanup;
  264. }
  265. r = radeon_ring_lock(rdev, ringA, 64);
  266. if (r) {
  267. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  268. goto out_cleanup;
  269. }
  270. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  271. radeon_ring_unlock_commit(rdev, ringA);
  272. r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1);
  273. if (r)
  274. goto out_cleanup;
  275. r = radeon_ring_lock(rdev, ringA, 64);
  276. if (r) {
  277. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  278. goto out_cleanup;
  279. }
  280. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  281. radeon_ring_unlock_commit(rdev, ringA);
  282. r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2);
  283. if (r)
  284. goto out_cleanup;
  285. mdelay(1000);
  286. if (radeon_fence_signaled(fence1)) {
  287. DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
  288. goto out_cleanup;
  289. }
  290. r = radeon_ring_lock(rdev, ringB, 64);
  291. if (r) {
  292. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  293. goto out_cleanup;
  294. }
  295. radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
  296. radeon_ring_unlock_commit(rdev, ringB);
  297. r = radeon_fence_wait(fence1, false);
  298. if (r) {
  299. DRM_ERROR("Failed to wait for sync fence 1\n");
  300. goto out_cleanup;
  301. }
  302. mdelay(1000);
  303. if (radeon_fence_signaled(fence2)) {
  304. DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
  305. goto out_cleanup;
  306. }
  307. r = radeon_ring_lock(rdev, ringB, 64);
  308. if (r) {
  309. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  310. goto out_cleanup;
  311. }
  312. radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
  313. radeon_ring_unlock_commit(rdev, ringB);
  314. r = radeon_fence_wait(fence2, false);
  315. if (r) {
  316. DRM_ERROR("Failed to wait for sync fence 1\n");
  317. goto out_cleanup;
  318. }
  319. out_cleanup:
  320. radeon_semaphore_free(rdev, &semaphore, NULL);
  321. if (fence1)
  322. radeon_fence_unref(&fence1);
  323. if (fence2)
  324. radeon_fence_unref(&fence2);
  325. if (r)
  326. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  327. }
  328. static void radeon_test_ring_sync2(struct radeon_device *rdev,
  329. struct radeon_ring *ringA,
  330. struct radeon_ring *ringB,
  331. struct radeon_ring *ringC)
  332. {
  333. struct radeon_fence *fenceA = NULL, *fenceB = NULL;
  334. struct radeon_semaphore *semaphore = NULL;
  335. bool sigA, sigB;
  336. int i, r;
  337. r = radeon_semaphore_create(rdev, &semaphore);
  338. if (r) {
  339. DRM_ERROR("Failed to create semaphore\n");
  340. goto out_cleanup;
  341. }
  342. r = radeon_ring_lock(rdev, ringA, 64);
  343. if (r) {
  344. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  345. goto out_cleanup;
  346. }
  347. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  348. radeon_ring_unlock_commit(rdev, ringA);
  349. r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA);
  350. if (r)
  351. goto out_cleanup;
  352. r = radeon_ring_lock(rdev, ringB, 64);
  353. if (r) {
  354. DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
  355. goto out_cleanup;
  356. }
  357. radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore);
  358. radeon_ring_unlock_commit(rdev, ringB);
  359. r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB);
  360. if (r)
  361. goto out_cleanup;
  362. mdelay(1000);
  363. if (radeon_fence_signaled(fenceA)) {
  364. DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
  365. goto out_cleanup;
  366. }
  367. if (radeon_fence_signaled(fenceB)) {
  368. DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
  369. goto out_cleanup;
  370. }
  371. r = radeon_ring_lock(rdev, ringC, 64);
  372. if (r) {
  373. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  374. goto out_cleanup;
  375. }
  376. radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
  377. radeon_ring_unlock_commit(rdev, ringC);
  378. for (i = 0; i < 30; ++i) {
  379. mdelay(100);
  380. sigA = radeon_fence_signaled(fenceA);
  381. sigB = radeon_fence_signaled(fenceB);
  382. if (sigA || sigB)
  383. break;
  384. }
  385. if (!sigA && !sigB) {
  386. DRM_ERROR("Neither fence A nor B has been signaled\n");
  387. goto out_cleanup;
  388. } else if (sigA && sigB) {
  389. DRM_ERROR("Both fence A and B has been signaled\n");
  390. goto out_cleanup;
  391. }
  392. DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
  393. r = radeon_ring_lock(rdev, ringC, 64);
  394. if (r) {
  395. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  396. goto out_cleanup;
  397. }
  398. radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
  399. radeon_ring_unlock_commit(rdev, ringC);
  400. mdelay(1000);
  401. r = radeon_fence_wait(fenceA, false);
  402. if (r) {
  403. DRM_ERROR("Failed to wait for sync fence A\n");
  404. goto out_cleanup;
  405. }
  406. r = radeon_fence_wait(fenceB, false);
  407. if (r) {
  408. DRM_ERROR("Failed to wait for sync fence B\n");
  409. goto out_cleanup;
  410. }
  411. out_cleanup:
  412. radeon_semaphore_free(rdev, &semaphore, NULL);
  413. if (fenceA)
  414. radeon_fence_unref(&fenceA);
  415. if (fenceB)
  416. radeon_fence_unref(&fenceB);
  417. if (r)
  418. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  419. }
  420. void radeon_test_syncing(struct radeon_device *rdev)
  421. {
  422. int i, j, k;
  423. for (i = 1; i < RADEON_NUM_RINGS; ++i) {
  424. struct radeon_ring *ringA = &rdev->ring[i];
  425. if (!ringA->ready)
  426. continue;
  427. for (j = 0; j < i; ++j) {
  428. struct radeon_ring *ringB = &rdev->ring[j];
  429. if (!ringB->ready)
  430. continue;
  431. DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
  432. radeon_test_ring_sync(rdev, ringA, ringB);
  433. DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
  434. radeon_test_ring_sync(rdev, ringB, ringA);
  435. for (k = 0; k < j; ++k) {
  436. struct radeon_ring *ringC = &rdev->ring[k];
  437. if (!ringC->ready)
  438. continue;
  439. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
  440. radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
  441. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
  442. radeon_test_ring_sync2(rdev, ringA, ringC, ringB);
  443. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
  444. radeon_test_ring_sync2(rdev, ringB, ringA, ringC);
  445. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
  446. radeon_test_ring_sync2(rdev, ringB, ringC, ringA);
  447. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
  448. radeon_test_ring_sync2(rdev, ringC, ringA, ringB);
  449. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
  450. radeon_test_ring_sync2(rdev, ringC, ringB, ringA);
  451. }
  452. }
  453. }
  454. }