i915_gem_debug.c 3.5 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Keith Packard <keithp@keithp.com>
  25. *
  26. */
  27. #include <drm/drmP.h>
  28. #include <drm/i915_drm.h>
  29. #include "i915_drv.h"
  30. #if WATCH_LISTS
  31. int
  32. i915_verify_lists(struct drm_device *dev)
  33. {
  34. static int warned;
  35. drm_i915_private_t *dev_priv = dev->dev_private;
  36. struct drm_i915_gem_object *obj;
  37. int err = 0;
  38. if (warned)
  39. return 0;
  40. list_for_each_entry(obj, &dev_priv->render_ring.active_list, list) {
  41. if (obj->base.dev != dev ||
  42. !atomic_read(&obj->base.refcount.refcount)) {
  43. DRM_ERROR("freed render active %p\n", obj);
  44. err++;
  45. break;
  46. } else if (!obj->active ||
  47. (obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) {
  48. DRM_ERROR("invalid render active %p (a %d r %x)\n",
  49. obj,
  50. obj->active,
  51. obj->base.read_domains);
  52. err++;
  53. } else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) {
  54. DRM_ERROR("invalid render active %p (w %x, gwl %d)\n",
  55. obj,
  56. obj->base.write_domain,
  57. !list_empty(&obj->gpu_write_list));
  58. err++;
  59. }
  60. }
  61. list_for_each_entry(obj, &dev_priv->mm.flushing_list, list) {
  62. if (obj->base.dev != dev ||
  63. !atomic_read(&obj->base.refcount.refcount)) {
  64. DRM_ERROR("freed flushing %p\n", obj);
  65. err++;
  66. break;
  67. } else if (!obj->active ||
  68. (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 ||
  69. list_empty(&obj->gpu_write_list)) {
  70. DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n",
  71. obj,
  72. obj->active,
  73. obj->base.write_domain,
  74. !list_empty(&obj->gpu_write_list));
  75. err++;
  76. }
  77. }
  78. list_for_each_entry(obj, &dev_priv->mm.gpu_write_list, gpu_write_list) {
  79. if (obj->base.dev != dev ||
  80. !atomic_read(&obj->base.refcount.refcount)) {
  81. DRM_ERROR("freed gpu write %p\n", obj);
  82. err++;
  83. break;
  84. } else if (!obj->active ||
  85. (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) {
  86. DRM_ERROR("invalid gpu write %p (a %d w %x)\n",
  87. obj,
  88. obj->active,
  89. obj->base.write_domain);
  90. err++;
  91. }
  92. }
  93. list_for_each_entry(obj, &i915_gtt_vm->inactive_list, list) {
  94. if (obj->base.dev != dev ||
  95. !atomic_read(&obj->base.refcount.refcount)) {
  96. DRM_ERROR("freed inactive %p\n", obj);
  97. err++;
  98. break;
  99. } else if (obj->pin_count || obj->active ||
  100. (obj->base.write_domain & I915_GEM_GPU_DOMAINS)) {
  101. DRM_ERROR("invalid inactive %p (p %d a %d w %x)\n",
  102. obj,
  103. obj->pin_count, obj->active,
  104. obj->base.write_domain);
  105. err++;
  106. }
  107. }
  108. return warned = err;
  109. }
  110. #endif /* WATCH_LIST */