i915_debugfs.c 57 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "intel_drv.h"
  35. #include "intel_ringbuffer.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #define DRM_I915_RING_DEBUG 1
  39. #if defined(CONFIG_DEBUG_FS)
  40. enum {
  41. ACTIVE_LIST,
  42. INACTIVE_LIST,
  43. PINNED_LIST,
  44. };
  45. static const char *yesno(int v)
  46. {
  47. return v ? "yes" : "no";
  48. }
  49. static int i915_capabilities(struct seq_file *m, void *data)
  50. {
  51. struct drm_info_node *node = (struct drm_info_node *) m->private;
  52. struct drm_device *dev = node->minor->dev;
  53. const struct intel_device_info *info = INTEL_INFO(dev);
  54. seq_printf(m, "gen: %d\n", info->gen);
  55. seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  56. #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  57. #define DEV_INFO_SEP ;
  58. DEV_INFO_FLAGS;
  59. #undef DEV_INFO_FLAG
  60. #undef DEV_INFO_SEP
  61. return 0;
  62. }
  63. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  64. {
  65. if (obj->user_pin_count > 0)
  66. return "P";
  67. else if (obj->pin_count > 0)
  68. return "p";
  69. else
  70. return " ";
  71. }
  72. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  73. {
  74. switch (obj->tiling_mode) {
  75. default:
  76. case I915_TILING_NONE: return " ";
  77. case I915_TILING_X: return "X";
  78. case I915_TILING_Y: return "Y";
  79. }
  80. }
  81. static const char *cache_level_str(int type)
  82. {
  83. switch (type) {
  84. case I915_CACHE_NONE: return " uncached";
  85. case I915_CACHE_LLC: return " snooped (LLC)";
  86. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  87. default: return "";
  88. }
  89. }
  90. static void
  91. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  92. {
  93. seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d %d%s%s%s",
  94. &obj->base,
  95. get_pin_flag(obj),
  96. get_tiling_flag(obj),
  97. obj->base.size / 1024,
  98. obj->base.read_domains,
  99. obj->base.write_domain,
  100. obj->last_read_seqno,
  101. obj->last_write_seqno,
  102. obj->last_fenced_seqno,
  103. cache_level_str(obj->cache_level),
  104. obj->dirty ? " dirty" : "",
  105. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  106. if (obj->base.name)
  107. seq_printf(m, " (name: %d)", obj->base.name);
  108. if (obj->pin_count)
  109. seq_printf(m, " (pinned x %d)", obj->pin_count);
  110. if (obj->fence_reg != I915_FENCE_REG_NONE)
  111. seq_printf(m, " (fence: %d)", obj->fence_reg);
  112. if (obj->gtt_space != NULL)
  113. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  114. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  115. if (obj->pin_mappable || obj->fault_mappable) {
  116. char s[3], *t = s;
  117. if (obj->pin_mappable)
  118. *t++ = 'p';
  119. if (obj->fault_mappable)
  120. *t++ = 'f';
  121. *t = '\0';
  122. seq_printf(m, " (%s mappable)", s);
  123. }
  124. if (obj->ring != NULL)
  125. seq_printf(m, " (%s)", obj->ring->name);
  126. }
  127. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  128. {
  129. struct drm_info_node *node = (struct drm_info_node *) m->private;
  130. uintptr_t list = (uintptr_t) node->info_ent->data;
  131. struct list_head *head;
  132. struct drm_device *dev = node->minor->dev;
  133. drm_i915_private_t *dev_priv = dev->dev_private;
  134. struct drm_i915_gem_object *obj;
  135. size_t total_obj_size, total_gtt_size;
  136. int count, ret;
  137. ret = mutex_lock_interruptible(&dev->struct_mutex);
  138. if (ret)
  139. return ret;
  140. switch (list) {
  141. case ACTIVE_LIST:
  142. seq_printf(m, "Active:\n");
  143. head = &dev_priv->mm.active_list;
  144. break;
  145. case INACTIVE_LIST:
  146. seq_printf(m, "Inactive:\n");
  147. head = &dev_priv->mm.inactive_list;
  148. break;
  149. default:
  150. mutex_unlock(&dev->struct_mutex);
  151. return -EINVAL;
  152. }
  153. total_obj_size = total_gtt_size = count = 0;
  154. list_for_each_entry(obj, head, mm_list) {
  155. seq_printf(m, " ");
  156. describe_obj(m, obj);
  157. seq_printf(m, "\n");
  158. total_obj_size += obj->base.size;
  159. total_gtt_size += obj->gtt_space->size;
  160. count++;
  161. }
  162. mutex_unlock(&dev->struct_mutex);
  163. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  164. count, total_obj_size, total_gtt_size);
  165. return 0;
  166. }
  167. #define count_objects(list, member) do { \
  168. list_for_each_entry(obj, list, member) { \
  169. size += obj->gtt_space->size; \
  170. ++count; \
  171. if (obj->map_and_fenceable) { \
  172. mappable_size += obj->gtt_space->size; \
  173. ++mappable_count; \
  174. } \
  175. } \
  176. } while (0)
  177. static int i915_gem_object_info(struct seq_file *m, void* data)
  178. {
  179. struct drm_info_node *node = (struct drm_info_node *) m->private;
  180. struct drm_device *dev = node->minor->dev;
  181. struct drm_i915_private *dev_priv = dev->dev_private;
  182. u32 count, mappable_count, purgeable_count;
  183. size_t size, mappable_size, purgeable_size;
  184. struct drm_i915_gem_object *obj;
  185. int ret;
  186. ret = mutex_lock_interruptible(&dev->struct_mutex);
  187. if (ret)
  188. return ret;
  189. seq_printf(m, "%u objects, %zu bytes\n",
  190. dev_priv->mm.object_count,
  191. dev_priv->mm.object_memory);
  192. size = count = mappable_size = mappable_count = 0;
  193. count_objects(&dev_priv->mm.bound_list, gtt_list);
  194. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  195. count, mappable_count, size, mappable_size);
  196. size = count = mappable_size = mappable_count = 0;
  197. count_objects(&dev_priv->mm.active_list, mm_list);
  198. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  199. count, mappable_count, size, mappable_size);
  200. size = count = mappable_size = mappable_count = 0;
  201. count_objects(&dev_priv->mm.inactive_list, mm_list);
  202. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  203. count, mappable_count, size, mappable_size);
  204. size = count = purgeable_size = purgeable_count = 0;
  205. list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
  206. size += obj->base.size, ++count;
  207. if (obj->madv == I915_MADV_DONTNEED)
  208. purgeable_size += obj->base.size, ++purgeable_count;
  209. }
  210. seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
  211. size = count = mappable_size = mappable_count = 0;
  212. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  213. if (obj->fault_mappable) {
  214. size += obj->gtt_space->size;
  215. ++count;
  216. }
  217. if (obj->pin_mappable) {
  218. mappable_size += obj->gtt_space->size;
  219. ++mappable_count;
  220. }
  221. if (obj->madv == I915_MADV_DONTNEED) {
  222. purgeable_size += obj->base.size;
  223. ++purgeable_count;
  224. }
  225. }
  226. seq_printf(m, "%u purgeable objects, %zu bytes\n",
  227. purgeable_count, purgeable_size);
  228. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  229. mappable_count, mappable_size);
  230. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  231. count, size);
  232. seq_printf(m, "%zu [%zu] gtt total\n",
  233. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  234. mutex_unlock(&dev->struct_mutex);
  235. return 0;
  236. }
  237. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  238. {
  239. struct drm_info_node *node = (struct drm_info_node *) m->private;
  240. struct drm_device *dev = node->minor->dev;
  241. uintptr_t list = (uintptr_t) node->info_ent->data;
  242. struct drm_i915_private *dev_priv = dev->dev_private;
  243. struct drm_i915_gem_object *obj;
  244. size_t total_obj_size, total_gtt_size;
  245. int count, ret;
  246. ret = mutex_lock_interruptible(&dev->struct_mutex);
  247. if (ret)
  248. return ret;
  249. total_obj_size = total_gtt_size = count = 0;
  250. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  251. if (list == PINNED_LIST && obj->pin_count == 0)
  252. continue;
  253. seq_printf(m, " ");
  254. describe_obj(m, obj);
  255. seq_printf(m, "\n");
  256. total_obj_size += obj->base.size;
  257. total_gtt_size += obj->gtt_space->size;
  258. count++;
  259. }
  260. mutex_unlock(&dev->struct_mutex);
  261. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  262. count, total_obj_size, total_gtt_size);
  263. return 0;
  264. }
  265. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  266. {
  267. struct drm_info_node *node = (struct drm_info_node *) m->private;
  268. struct drm_device *dev = node->minor->dev;
  269. unsigned long flags;
  270. struct intel_crtc *crtc;
  271. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  272. const char pipe = pipe_name(crtc->pipe);
  273. const char plane = plane_name(crtc->plane);
  274. struct intel_unpin_work *work;
  275. spin_lock_irqsave(&dev->event_lock, flags);
  276. work = crtc->unpin_work;
  277. if (work == NULL) {
  278. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  279. pipe, plane);
  280. } else {
  281. if (!work->pending) {
  282. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  283. pipe, plane);
  284. } else {
  285. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  286. pipe, plane);
  287. }
  288. if (work->enable_stall_check)
  289. seq_printf(m, "Stall check enabled, ");
  290. else
  291. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  292. seq_printf(m, "%d prepares\n", work->pending);
  293. if (work->old_fb_obj) {
  294. struct drm_i915_gem_object *obj = work->old_fb_obj;
  295. if (obj)
  296. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  297. }
  298. if (work->pending_flip_obj) {
  299. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  300. if (obj)
  301. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  302. }
  303. }
  304. spin_unlock_irqrestore(&dev->event_lock, flags);
  305. }
  306. return 0;
  307. }
  308. static int i915_gem_request_info(struct seq_file *m, void *data)
  309. {
  310. struct drm_info_node *node = (struct drm_info_node *) m->private;
  311. struct drm_device *dev = node->minor->dev;
  312. drm_i915_private_t *dev_priv = dev->dev_private;
  313. struct intel_ring_buffer *ring;
  314. struct drm_i915_gem_request *gem_request;
  315. int ret, count, i;
  316. ret = mutex_lock_interruptible(&dev->struct_mutex);
  317. if (ret)
  318. return ret;
  319. count = 0;
  320. for_each_ring(ring, dev_priv, i) {
  321. if (list_empty(&ring->request_list))
  322. continue;
  323. seq_printf(m, "%s requests:\n", ring->name);
  324. list_for_each_entry(gem_request,
  325. &ring->request_list,
  326. list) {
  327. seq_printf(m, " %d @ %d\n",
  328. gem_request->seqno,
  329. (int) (jiffies - gem_request->emitted_jiffies));
  330. }
  331. count++;
  332. }
  333. mutex_unlock(&dev->struct_mutex);
  334. if (count == 0)
  335. seq_printf(m, "No requests\n");
  336. return 0;
  337. }
  338. static void i915_ring_seqno_info(struct seq_file *m,
  339. struct intel_ring_buffer *ring)
  340. {
  341. if (ring->get_seqno) {
  342. seq_printf(m, "Current sequence (%s): %d\n",
  343. ring->name, ring->get_seqno(ring, false));
  344. }
  345. }
  346. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  347. {
  348. struct drm_info_node *node = (struct drm_info_node *) m->private;
  349. struct drm_device *dev = node->minor->dev;
  350. drm_i915_private_t *dev_priv = dev->dev_private;
  351. struct intel_ring_buffer *ring;
  352. int ret, i;
  353. ret = mutex_lock_interruptible(&dev->struct_mutex);
  354. if (ret)
  355. return ret;
  356. for_each_ring(ring, dev_priv, i)
  357. i915_ring_seqno_info(m, ring);
  358. mutex_unlock(&dev->struct_mutex);
  359. return 0;
  360. }
  361. static int i915_interrupt_info(struct seq_file *m, void *data)
  362. {
  363. struct drm_info_node *node = (struct drm_info_node *) m->private;
  364. struct drm_device *dev = node->minor->dev;
  365. drm_i915_private_t *dev_priv = dev->dev_private;
  366. struct intel_ring_buffer *ring;
  367. int ret, i, pipe;
  368. ret = mutex_lock_interruptible(&dev->struct_mutex);
  369. if (ret)
  370. return ret;
  371. if (IS_VALLEYVIEW(dev)) {
  372. seq_printf(m, "Display IER:\t%08x\n",
  373. I915_READ(VLV_IER));
  374. seq_printf(m, "Display IIR:\t%08x\n",
  375. I915_READ(VLV_IIR));
  376. seq_printf(m, "Display IIR_RW:\t%08x\n",
  377. I915_READ(VLV_IIR_RW));
  378. seq_printf(m, "Display IMR:\t%08x\n",
  379. I915_READ(VLV_IMR));
  380. for_each_pipe(pipe)
  381. seq_printf(m, "Pipe %c stat:\t%08x\n",
  382. pipe_name(pipe),
  383. I915_READ(PIPESTAT(pipe)));
  384. seq_printf(m, "Master IER:\t%08x\n",
  385. I915_READ(VLV_MASTER_IER));
  386. seq_printf(m, "Render IER:\t%08x\n",
  387. I915_READ(GTIER));
  388. seq_printf(m, "Render IIR:\t%08x\n",
  389. I915_READ(GTIIR));
  390. seq_printf(m, "Render IMR:\t%08x\n",
  391. I915_READ(GTIMR));
  392. seq_printf(m, "PM IER:\t\t%08x\n",
  393. I915_READ(GEN6_PMIER));
  394. seq_printf(m, "PM IIR:\t\t%08x\n",
  395. I915_READ(GEN6_PMIIR));
  396. seq_printf(m, "PM IMR:\t\t%08x\n",
  397. I915_READ(GEN6_PMIMR));
  398. seq_printf(m, "Port hotplug:\t%08x\n",
  399. I915_READ(PORT_HOTPLUG_EN));
  400. seq_printf(m, "DPFLIPSTAT:\t%08x\n",
  401. I915_READ(VLV_DPFLIPSTAT));
  402. seq_printf(m, "DPINVGTT:\t%08x\n",
  403. I915_READ(DPINVGTT));
  404. } else if (!HAS_PCH_SPLIT(dev)) {
  405. seq_printf(m, "Interrupt enable: %08x\n",
  406. I915_READ(IER));
  407. seq_printf(m, "Interrupt identity: %08x\n",
  408. I915_READ(IIR));
  409. seq_printf(m, "Interrupt mask: %08x\n",
  410. I915_READ(IMR));
  411. for_each_pipe(pipe)
  412. seq_printf(m, "Pipe %c stat: %08x\n",
  413. pipe_name(pipe),
  414. I915_READ(PIPESTAT(pipe)));
  415. } else {
  416. seq_printf(m, "North Display Interrupt enable: %08x\n",
  417. I915_READ(DEIER));
  418. seq_printf(m, "North Display Interrupt identity: %08x\n",
  419. I915_READ(DEIIR));
  420. seq_printf(m, "North Display Interrupt mask: %08x\n",
  421. I915_READ(DEIMR));
  422. seq_printf(m, "South Display Interrupt enable: %08x\n",
  423. I915_READ(SDEIER));
  424. seq_printf(m, "South Display Interrupt identity: %08x\n",
  425. I915_READ(SDEIIR));
  426. seq_printf(m, "South Display Interrupt mask: %08x\n",
  427. I915_READ(SDEIMR));
  428. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  429. I915_READ(GTIER));
  430. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  431. I915_READ(GTIIR));
  432. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  433. I915_READ(GTIMR));
  434. }
  435. seq_printf(m, "Interrupts received: %d\n",
  436. atomic_read(&dev_priv->irq_received));
  437. for_each_ring(ring, dev_priv, i) {
  438. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  439. seq_printf(m,
  440. "Graphics Interrupt mask (%s): %08x\n",
  441. ring->name, I915_READ_IMR(ring));
  442. }
  443. i915_ring_seqno_info(m, ring);
  444. }
  445. mutex_unlock(&dev->struct_mutex);
  446. return 0;
  447. }
  448. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  449. {
  450. struct drm_info_node *node = (struct drm_info_node *) m->private;
  451. struct drm_device *dev = node->minor->dev;
  452. drm_i915_private_t *dev_priv = dev->dev_private;
  453. int i, ret;
  454. ret = mutex_lock_interruptible(&dev->struct_mutex);
  455. if (ret)
  456. return ret;
  457. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  458. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  459. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  460. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  461. seq_printf(m, "Fence %d, pin count = %d, object = ",
  462. i, dev_priv->fence_regs[i].pin_count);
  463. if (obj == NULL)
  464. seq_printf(m, "unused");
  465. else
  466. describe_obj(m, obj);
  467. seq_printf(m, "\n");
  468. }
  469. mutex_unlock(&dev->struct_mutex);
  470. return 0;
  471. }
  472. static int i915_hws_info(struct seq_file *m, void *data)
  473. {
  474. struct drm_info_node *node = (struct drm_info_node *) m->private;
  475. struct drm_device *dev = node->minor->dev;
  476. drm_i915_private_t *dev_priv = dev->dev_private;
  477. struct intel_ring_buffer *ring;
  478. const volatile u32 __iomem *hws;
  479. int i;
  480. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  481. hws = (volatile u32 __iomem *)ring->status_page.page_addr;
  482. if (hws == NULL)
  483. return 0;
  484. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  485. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  486. i * 4,
  487. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  488. }
  489. return 0;
  490. }
  491. static const char *ring_str(int ring)
  492. {
  493. switch (ring) {
  494. case RCS: return "render";
  495. case VCS: return "bsd";
  496. case BCS: return "blt";
  497. default: return "";
  498. }
  499. }
  500. static const char *pin_flag(int pinned)
  501. {
  502. if (pinned > 0)
  503. return " P";
  504. else if (pinned < 0)
  505. return " p";
  506. else
  507. return "";
  508. }
  509. static const char *tiling_flag(int tiling)
  510. {
  511. switch (tiling) {
  512. default:
  513. case I915_TILING_NONE: return "";
  514. case I915_TILING_X: return " X";
  515. case I915_TILING_Y: return " Y";
  516. }
  517. }
  518. static const char *dirty_flag(int dirty)
  519. {
  520. return dirty ? " dirty" : "";
  521. }
  522. static const char *purgeable_flag(int purgeable)
  523. {
  524. return purgeable ? " purgeable" : "";
  525. }
  526. static void print_error_buffers(struct seq_file *m,
  527. const char *name,
  528. struct drm_i915_error_buffer *err,
  529. int count)
  530. {
  531. seq_printf(m, "%s [%d]:\n", name, count);
  532. while (count--) {
  533. seq_printf(m, " %08x %8u %04x %04x %x %x%s%s%s%s%s%s%s",
  534. err->gtt_offset,
  535. err->size,
  536. err->read_domains,
  537. err->write_domain,
  538. err->rseqno, err->wseqno,
  539. pin_flag(err->pinned),
  540. tiling_flag(err->tiling),
  541. dirty_flag(err->dirty),
  542. purgeable_flag(err->purgeable),
  543. err->ring != -1 ? " " : "",
  544. ring_str(err->ring),
  545. cache_level_str(err->cache_level));
  546. if (err->name)
  547. seq_printf(m, " (name: %d)", err->name);
  548. if (err->fence_reg != I915_FENCE_REG_NONE)
  549. seq_printf(m, " (fence: %d)", err->fence_reg);
  550. seq_printf(m, "\n");
  551. err++;
  552. }
  553. }
  554. static void i915_ring_error_state(struct seq_file *m,
  555. struct drm_device *dev,
  556. struct drm_i915_error_state *error,
  557. unsigned ring)
  558. {
  559. BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
  560. seq_printf(m, "%s command stream:\n", ring_str(ring));
  561. seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
  562. seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
  563. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
  564. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
  565. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
  566. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
  567. if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
  568. seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
  569. if (INTEL_INFO(dev)->gen >= 4)
  570. seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
  571. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
  572. seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
  573. if (INTEL_INFO(dev)->gen >= 6) {
  574. seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
  575. seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
  576. seq_printf(m, " SYNC_0: 0x%08x\n",
  577. error->semaphore_mboxes[ring][0]);
  578. seq_printf(m, " SYNC_1: 0x%08x\n",
  579. error->semaphore_mboxes[ring][1]);
  580. }
  581. seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
  582. seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
  583. seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
  584. seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
  585. }
  586. struct i915_error_state_file_priv {
  587. struct drm_device *dev;
  588. struct drm_i915_error_state *error;
  589. };
  590. static int i915_error_state(struct seq_file *m, void *unused)
  591. {
  592. struct i915_error_state_file_priv *error_priv = m->private;
  593. struct drm_device *dev = error_priv->dev;
  594. drm_i915_private_t *dev_priv = dev->dev_private;
  595. struct drm_i915_error_state *error = error_priv->error;
  596. struct intel_ring_buffer *ring;
  597. int i, j, page, offset, elt;
  598. if (!error) {
  599. seq_printf(m, "no error state collected\n");
  600. return 0;
  601. }
  602. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  603. error->time.tv_usec);
  604. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  605. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  606. seq_printf(m, "IER: 0x%08x\n", error->ier);
  607. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  608. seq_printf(m, "CCID: 0x%08x\n", error->ccid);
  609. for (i = 0; i < dev_priv->num_fence_regs; i++)
  610. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  611. for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
  612. seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]);
  613. if (INTEL_INFO(dev)->gen >= 6) {
  614. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  615. seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
  616. }
  617. if (INTEL_INFO(dev)->gen == 7)
  618. seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
  619. for_each_ring(ring, dev_priv, i)
  620. i915_ring_error_state(m, dev, error, i);
  621. if (error->active_bo)
  622. print_error_buffers(m, "Active",
  623. error->active_bo,
  624. error->active_bo_count);
  625. if (error->pinned_bo)
  626. print_error_buffers(m, "Pinned",
  627. error->pinned_bo,
  628. error->pinned_bo_count);
  629. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  630. struct drm_i915_error_object *obj;
  631. if ((obj = error->ring[i].batchbuffer)) {
  632. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  633. dev_priv->ring[i].name,
  634. obj->gtt_offset);
  635. offset = 0;
  636. for (page = 0; page < obj->page_count; page++) {
  637. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  638. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  639. offset += 4;
  640. }
  641. }
  642. }
  643. if (error->ring[i].num_requests) {
  644. seq_printf(m, "%s --- %d requests\n",
  645. dev_priv->ring[i].name,
  646. error->ring[i].num_requests);
  647. for (j = 0; j < error->ring[i].num_requests; j++) {
  648. seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
  649. error->ring[i].requests[j].seqno,
  650. error->ring[i].requests[j].jiffies,
  651. error->ring[i].requests[j].tail);
  652. }
  653. }
  654. if ((obj = error->ring[i].ringbuffer)) {
  655. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  656. dev_priv->ring[i].name,
  657. obj->gtt_offset);
  658. offset = 0;
  659. for (page = 0; page < obj->page_count; page++) {
  660. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  661. seq_printf(m, "%08x : %08x\n",
  662. offset,
  663. obj->pages[page][elt]);
  664. offset += 4;
  665. }
  666. }
  667. }
  668. }
  669. if (error->overlay)
  670. intel_overlay_print_error_state(m, error->overlay);
  671. if (error->display)
  672. intel_display_print_error_state(m, dev, error->display);
  673. return 0;
  674. }
  675. static ssize_t
  676. i915_error_state_write(struct file *filp,
  677. const char __user *ubuf,
  678. size_t cnt,
  679. loff_t *ppos)
  680. {
  681. struct seq_file *m = filp->private_data;
  682. struct i915_error_state_file_priv *error_priv = m->private;
  683. struct drm_device *dev = error_priv->dev;
  684. int ret;
  685. DRM_DEBUG_DRIVER("Resetting error state\n");
  686. ret = mutex_lock_interruptible(&dev->struct_mutex);
  687. if (ret)
  688. return ret;
  689. i915_destroy_error_state(dev);
  690. mutex_unlock(&dev->struct_mutex);
  691. return cnt;
  692. }
  693. static int i915_error_state_open(struct inode *inode, struct file *file)
  694. {
  695. struct drm_device *dev = inode->i_private;
  696. drm_i915_private_t *dev_priv = dev->dev_private;
  697. struct i915_error_state_file_priv *error_priv;
  698. unsigned long flags;
  699. error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
  700. if (!error_priv)
  701. return -ENOMEM;
  702. error_priv->dev = dev;
  703. spin_lock_irqsave(&dev_priv->error_lock, flags);
  704. error_priv->error = dev_priv->first_error;
  705. if (error_priv->error)
  706. kref_get(&error_priv->error->ref);
  707. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  708. return single_open(file, i915_error_state, error_priv);
  709. }
  710. static int i915_error_state_release(struct inode *inode, struct file *file)
  711. {
  712. struct seq_file *m = file->private_data;
  713. struct i915_error_state_file_priv *error_priv = m->private;
  714. if (error_priv->error)
  715. kref_put(&error_priv->error->ref, i915_error_state_free);
  716. kfree(error_priv);
  717. return single_release(inode, file);
  718. }
  719. static const struct file_operations i915_error_state_fops = {
  720. .owner = THIS_MODULE,
  721. .open = i915_error_state_open,
  722. .read = seq_read,
  723. .write = i915_error_state_write,
  724. .llseek = default_llseek,
  725. .release = i915_error_state_release,
  726. };
  727. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  728. {
  729. struct drm_info_node *node = (struct drm_info_node *) m->private;
  730. struct drm_device *dev = node->minor->dev;
  731. drm_i915_private_t *dev_priv = dev->dev_private;
  732. u16 crstanddelay;
  733. int ret;
  734. ret = mutex_lock_interruptible(&dev->struct_mutex);
  735. if (ret)
  736. return ret;
  737. crstanddelay = I915_READ16(CRSTANDVID);
  738. mutex_unlock(&dev->struct_mutex);
  739. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  740. return 0;
  741. }
  742. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  743. {
  744. struct drm_info_node *node = (struct drm_info_node *) m->private;
  745. struct drm_device *dev = node->minor->dev;
  746. drm_i915_private_t *dev_priv = dev->dev_private;
  747. int ret;
  748. if (IS_GEN5(dev)) {
  749. u16 rgvswctl = I915_READ16(MEMSWCTL);
  750. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  751. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  752. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  753. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  754. MEMSTAT_VID_SHIFT);
  755. seq_printf(m, "Current P-state: %d\n",
  756. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  757. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  758. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  759. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  760. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  761. u32 rpstat;
  762. u32 rpupei, rpcurup, rpprevup;
  763. u32 rpdownei, rpcurdown, rpprevdown;
  764. int max_freq;
  765. /* RPSTAT1 is in the GT power well */
  766. ret = mutex_lock_interruptible(&dev->struct_mutex);
  767. if (ret)
  768. return ret;
  769. gen6_gt_force_wake_get(dev_priv);
  770. rpstat = I915_READ(GEN6_RPSTAT1);
  771. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  772. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  773. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  774. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  775. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  776. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  777. gen6_gt_force_wake_put(dev_priv);
  778. mutex_unlock(&dev->struct_mutex);
  779. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  780. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  781. seq_printf(m, "Render p-state ratio: %d\n",
  782. (gt_perf_status & 0xff00) >> 8);
  783. seq_printf(m, "Render p-state VID: %d\n",
  784. gt_perf_status & 0xff);
  785. seq_printf(m, "Render p-state limit: %d\n",
  786. rp_state_limits & 0xff);
  787. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  788. GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER);
  789. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  790. GEN6_CURICONT_MASK);
  791. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  792. GEN6_CURBSYTAVG_MASK);
  793. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  794. GEN6_CURBSYTAVG_MASK);
  795. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  796. GEN6_CURIAVG_MASK);
  797. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  798. GEN6_CURBSYTAVG_MASK);
  799. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  800. GEN6_CURBSYTAVG_MASK);
  801. max_freq = (rp_state_cap & 0xff0000) >> 16;
  802. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  803. max_freq * GT_FREQUENCY_MULTIPLIER);
  804. max_freq = (rp_state_cap & 0xff00) >> 8;
  805. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  806. max_freq * GT_FREQUENCY_MULTIPLIER);
  807. max_freq = rp_state_cap & 0xff;
  808. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  809. max_freq * GT_FREQUENCY_MULTIPLIER);
  810. } else {
  811. seq_printf(m, "no P-state info available\n");
  812. }
  813. return 0;
  814. }
  815. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  816. {
  817. struct drm_info_node *node = (struct drm_info_node *) m->private;
  818. struct drm_device *dev = node->minor->dev;
  819. drm_i915_private_t *dev_priv = dev->dev_private;
  820. u32 delayfreq;
  821. int ret, i;
  822. ret = mutex_lock_interruptible(&dev->struct_mutex);
  823. if (ret)
  824. return ret;
  825. for (i = 0; i < 16; i++) {
  826. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  827. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  828. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  829. }
  830. mutex_unlock(&dev->struct_mutex);
  831. return 0;
  832. }
  833. static inline int MAP_TO_MV(int map)
  834. {
  835. return 1250 - (map * 25);
  836. }
  837. static int i915_inttoext_table(struct seq_file *m, void *unused)
  838. {
  839. struct drm_info_node *node = (struct drm_info_node *) m->private;
  840. struct drm_device *dev = node->minor->dev;
  841. drm_i915_private_t *dev_priv = dev->dev_private;
  842. u32 inttoext;
  843. int ret, i;
  844. ret = mutex_lock_interruptible(&dev->struct_mutex);
  845. if (ret)
  846. return ret;
  847. for (i = 1; i <= 32; i++) {
  848. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  849. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  850. }
  851. mutex_unlock(&dev->struct_mutex);
  852. return 0;
  853. }
  854. static int ironlake_drpc_info(struct seq_file *m)
  855. {
  856. struct drm_info_node *node = (struct drm_info_node *) m->private;
  857. struct drm_device *dev = node->minor->dev;
  858. drm_i915_private_t *dev_priv = dev->dev_private;
  859. u32 rgvmodectl, rstdbyctl;
  860. u16 crstandvid;
  861. int ret;
  862. ret = mutex_lock_interruptible(&dev->struct_mutex);
  863. if (ret)
  864. return ret;
  865. rgvmodectl = I915_READ(MEMMODECTL);
  866. rstdbyctl = I915_READ(RSTDBYCTL);
  867. crstandvid = I915_READ16(CRSTANDVID);
  868. mutex_unlock(&dev->struct_mutex);
  869. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  870. "yes" : "no");
  871. seq_printf(m, "Boost freq: %d\n",
  872. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  873. MEMMODE_BOOST_FREQ_SHIFT);
  874. seq_printf(m, "HW control enabled: %s\n",
  875. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  876. seq_printf(m, "SW control enabled: %s\n",
  877. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  878. seq_printf(m, "Gated voltage change: %s\n",
  879. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  880. seq_printf(m, "Starting frequency: P%d\n",
  881. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  882. seq_printf(m, "Max P-state: P%d\n",
  883. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  884. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  885. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  886. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  887. seq_printf(m, "Render standby enabled: %s\n",
  888. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  889. seq_printf(m, "Current RS state: ");
  890. switch (rstdbyctl & RSX_STATUS_MASK) {
  891. case RSX_STATUS_ON:
  892. seq_printf(m, "on\n");
  893. break;
  894. case RSX_STATUS_RC1:
  895. seq_printf(m, "RC1\n");
  896. break;
  897. case RSX_STATUS_RC1E:
  898. seq_printf(m, "RC1E\n");
  899. break;
  900. case RSX_STATUS_RS1:
  901. seq_printf(m, "RS1\n");
  902. break;
  903. case RSX_STATUS_RS2:
  904. seq_printf(m, "RS2 (RC6)\n");
  905. break;
  906. case RSX_STATUS_RS3:
  907. seq_printf(m, "RC3 (RC6+)\n");
  908. break;
  909. default:
  910. seq_printf(m, "unknown\n");
  911. break;
  912. }
  913. return 0;
  914. }
  915. static int gen6_drpc_info(struct seq_file *m)
  916. {
  917. struct drm_info_node *node = (struct drm_info_node *) m->private;
  918. struct drm_device *dev = node->minor->dev;
  919. struct drm_i915_private *dev_priv = dev->dev_private;
  920. u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
  921. unsigned forcewake_count;
  922. int count=0, ret;
  923. ret = mutex_lock_interruptible(&dev->struct_mutex);
  924. if (ret)
  925. return ret;
  926. spin_lock_irq(&dev_priv->gt_lock);
  927. forcewake_count = dev_priv->forcewake_count;
  928. spin_unlock_irq(&dev_priv->gt_lock);
  929. if (forcewake_count) {
  930. seq_printf(m, "RC information inaccurate because somebody "
  931. "holds a forcewake reference \n");
  932. } else {
  933. /* NB: we cannot use forcewake, else we read the wrong values */
  934. while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  935. udelay(10);
  936. seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
  937. }
  938. gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
  939. trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
  940. rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
  941. rcctl1 = I915_READ(GEN6_RC_CONTROL);
  942. sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
  943. mutex_unlock(&dev->struct_mutex);
  944. seq_printf(m, "Video Turbo Mode: %s\n",
  945. yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
  946. seq_printf(m, "HW control enabled: %s\n",
  947. yesno(rpmodectl1 & GEN6_RP_ENABLE));
  948. seq_printf(m, "SW control enabled: %s\n",
  949. yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
  950. GEN6_RP_MEDIA_SW_MODE));
  951. seq_printf(m, "RC1e Enabled: %s\n",
  952. yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
  953. seq_printf(m, "RC6 Enabled: %s\n",
  954. yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
  955. seq_printf(m, "Deep RC6 Enabled: %s\n",
  956. yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
  957. seq_printf(m, "Deepest RC6 Enabled: %s\n",
  958. yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
  959. seq_printf(m, "Current RC state: ");
  960. switch (gt_core_status & GEN6_RCn_MASK) {
  961. case GEN6_RC0:
  962. if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
  963. seq_printf(m, "Core Power Down\n");
  964. else
  965. seq_printf(m, "on\n");
  966. break;
  967. case GEN6_RC3:
  968. seq_printf(m, "RC3\n");
  969. break;
  970. case GEN6_RC6:
  971. seq_printf(m, "RC6\n");
  972. break;
  973. case GEN6_RC7:
  974. seq_printf(m, "RC7\n");
  975. break;
  976. default:
  977. seq_printf(m, "Unknown\n");
  978. break;
  979. }
  980. seq_printf(m, "Core Power Down: %s\n",
  981. yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
  982. /* Not exactly sure what this is */
  983. seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
  984. I915_READ(GEN6_GT_GFX_RC6_LOCKED));
  985. seq_printf(m, "RC6 residency since boot: %u\n",
  986. I915_READ(GEN6_GT_GFX_RC6));
  987. seq_printf(m, "RC6+ residency since boot: %u\n",
  988. I915_READ(GEN6_GT_GFX_RC6p));
  989. seq_printf(m, "RC6++ residency since boot: %u\n",
  990. I915_READ(GEN6_GT_GFX_RC6pp));
  991. seq_printf(m, "RC6 voltage: %dmV\n",
  992. GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
  993. seq_printf(m, "RC6+ voltage: %dmV\n",
  994. GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
  995. seq_printf(m, "RC6++ voltage: %dmV\n",
  996. GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
  997. return 0;
  998. }
  999. static int i915_drpc_info(struct seq_file *m, void *unused)
  1000. {
  1001. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1002. struct drm_device *dev = node->minor->dev;
  1003. if (IS_GEN6(dev) || IS_GEN7(dev))
  1004. return gen6_drpc_info(m);
  1005. else
  1006. return ironlake_drpc_info(m);
  1007. }
  1008. static int i915_fbc_status(struct seq_file *m, void *unused)
  1009. {
  1010. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1011. struct drm_device *dev = node->minor->dev;
  1012. drm_i915_private_t *dev_priv = dev->dev_private;
  1013. if (!I915_HAS_FBC(dev)) {
  1014. seq_printf(m, "FBC unsupported on this chipset\n");
  1015. return 0;
  1016. }
  1017. if (intel_fbc_enabled(dev)) {
  1018. seq_printf(m, "FBC enabled\n");
  1019. } else {
  1020. seq_printf(m, "FBC disabled: ");
  1021. switch (dev_priv->no_fbc_reason) {
  1022. case FBC_NO_OUTPUT:
  1023. seq_printf(m, "no outputs");
  1024. break;
  1025. case FBC_STOLEN_TOO_SMALL:
  1026. seq_printf(m, "not enough stolen memory");
  1027. break;
  1028. case FBC_UNSUPPORTED_MODE:
  1029. seq_printf(m, "mode not supported");
  1030. break;
  1031. case FBC_MODE_TOO_LARGE:
  1032. seq_printf(m, "mode too large");
  1033. break;
  1034. case FBC_BAD_PLANE:
  1035. seq_printf(m, "FBC unsupported on plane");
  1036. break;
  1037. case FBC_NOT_TILED:
  1038. seq_printf(m, "scanout buffer not tiled");
  1039. break;
  1040. case FBC_MULTIPLE_PIPES:
  1041. seq_printf(m, "multiple pipes are enabled");
  1042. break;
  1043. case FBC_MODULE_PARAM:
  1044. seq_printf(m, "disabled per module param (default off)");
  1045. break;
  1046. default:
  1047. seq_printf(m, "unknown reason");
  1048. }
  1049. seq_printf(m, "\n");
  1050. }
  1051. return 0;
  1052. }
  1053. static int i915_sr_status(struct seq_file *m, void *unused)
  1054. {
  1055. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1056. struct drm_device *dev = node->minor->dev;
  1057. drm_i915_private_t *dev_priv = dev->dev_private;
  1058. bool sr_enabled = false;
  1059. if (HAS_PCH_SPLIT(dev))
  1060. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  1061. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  1062. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  1063. else if (IS_I915GM(dev))
  1064. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  1065. else if (IS_PINEVIEW(dev))
  1066. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  1067. seq_printf(m, "self-refresh: %s\n",
  1068. sr_enabled ? "enabled" : "disabled");
  1069. return 0;
  1070. }
  1071. static int i915_emon_status(struct seq_file *m, void *unused)
  1072. {
  1073. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1074. struct drm_device *dev = node->minor->dev;
  1075. drm_i915_private_t *dev_priv = dev->dev_private;
  1076. unsigned long temp, chipset, gfx;
  1077. int ret;
  1078. if (!IS_GEN5(dev))
  1079. return -ENODEV;
  1080. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1081. if (ret)
  1082. return ret;
  1083. temp = i915_mch_val(dev_priv);
  1084. chipset = i915_chipset_val(dev_priv);
  1085. gfx = i915_gfx_val(dev_priv);
  1086. mutex_unlock(&dev->struct_mutex);
  1087. seq_printf(m, "GMCH temp: %ld\n", temp);
  1088. seq_printf(m, "Chipset power: %ld\n", chipset);
  1089. seq_printf(m, "GFX power: %ld\n", gfx);
  1090. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  1091. return 0;
  1092. }
  1093. static int i915_ring_freq_table(struct seq_file *m, void *unused)
  1094. {
  1095. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1096. struct drm_device *dev = node->minor->dev;
  1097. drm_i915_private_t *dev_priv = dev->dev_private;
  1098. int ret;
  1099. int gpu_freq, ia_freq;
  1100. if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
  1101. seq_printf(m, "unsupported on this chipset\n");
  1102. return 0;
  1103. }
  1104. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1105. if (ret)
  1106. return ret;
  1107. seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
  1108. for (gpu_freq = dev_priv->rps.min_delay;
  1109. gpu_freq <= dev_priv->rps.max_delay;
  1110. gpu_freq++) {
  1111. ia_freq = gpu_freq;
  1112. sandybridge_pcode_read(dev_priv,
  1113. GEN6_PCODE_READ_MIN_FREQ_TABLE,
  1114. &ia_freq);
  1115. seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
  1116. }
  1117. mutex_unlock(&dev->struct_mutex);
  1118. return 0;
  1119. }
  1120. static int i915_gfxec(struct seq_file *m, void *unused)
  1121. {
  1122. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1123. struct drm_device *dev = node->minor->dev;
  1124. drm_i915_private_t *dev_priv = dev->dev_private;
  1125. int ret;
  1126. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1127. if (ret)
  1128. return ret;
  1129. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  1130. mutex_unlock(&dev->struct_mutex);
  1131. return 0;
  1132. }
  1133. static int i915_opregion(struct seq_file *m, void *unused)
  1134. {
  1135. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1136. struct drm_device *dev = node->minor->dev;
  1137. drm_i915_private_t *dev_priv = dev->dev_private;
  1138. struct intel_opregion *opregion = &dev_priv->opregion;
  1139. void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
  1140. int ret;
  1141. if (data == NULL)
  1142. return -ENOMEM;
  1143. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1144. if (ret)
  1145. goto out;
  1146. if (opregion->header) {
  1147. memcpy_fromio(data, opregion->header, OPREGION_SIZE);
  1148. seq_write(m, data, OPREGION_SIZE);
  1149. }
  1150. mutex_unlock(&dev->struct_mutex);
  1151. out:
  1152. kfree(data);
  1153. return 0;
  1154. }
  1155. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1156. {
  1157. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1158. struct drm_device *dev = node->minor->dev;
  1159. drm_i915_private_t *dev_priv = dev->dev_private;
  1160. struct intel_fbdev *ifbdev;
  1161. struct intel_framebuffer *fb;
  1162. int ret;
  1163. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1164. if (ret)
  1165. return ret;
  1166. ifbdev = dev_priv->fbdev;
  1167. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1168. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1169. fb->base.width,
  1170. fb->base.height,
  1171. fb->base.depth,
  1172. fb->base.bits_per_pixel);
  1173. describe_obj(m, fb->obj);
  1174. seq_printf(m, "\n");
  1175. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1176. if (&fb->base == ifbdev->helper.fb)
  1177. continue;
  1178. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1179. fb->base.width,
  1180. fb->base.height,
  1181. fb->base.depth,
  1182. fb->base.bits_per_pixel);
  1183. describe_obj(m, fb->obj);
  1184. seq_printf(m, "\n");
  1185. }
  1186. mutex_unlock(&dev->mode_config.mutex);
  1187. return 0;
  1188. }
  1189. static int i915_context_status(struct seq_file *m, void *unused)
  1190. {
  1191. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1192. struct drm_device *dev = node->minor->dev;
  1193. drm_i915_private_t *dev_priv = dev->dev_private;
  1194. int ret;
  1195. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1196. if (ret)
  1197. return ret;
  1198. if (dev_priv->pwrctx) {
  1199. seq_printf(m, "power context ");
  1200. describe_obj(m, dev_priv->pwrctx);
  1201. seq_printf(m, "\n");
  1202. }
  1203. if (dev_priv->renderctx) {
  1204. seq_printf(m, "render context ");
  1205. describe_obj(m, dev_priv->renderctx);
  1206. seq_printf(m, "\n");
  1207. }
  1208. mutex_unlock(&dev->mode_config.mutex);
  1209. return 0;
  1210. }
  1211. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1212. {
  1213. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1214. struct drm_device *dev = node->minor->dev;
  1215. struct drm_i915_private *dev_priv = dev->dev_private;
  1216. unsigned forcewake_count;
  1217. spin_lock_irq(&dev_priv->gt_lock);
  1218. forcewake_count = dev_priv->forcewake_count;
  1219. spin_unlock_irq(&dev_priv->gt_lock);
  1220. seq_printf(m, "forcewake count = %u\n", forcewake_count);
  1221. return 0;
  1222. }
  1223. static const char *swizzle_string(unsigned swizzle)
  1224. {
  1225. switch(swizzle) {
  1226. case I915_BIT_6_SWIZZLE_NONE:
  1227. return "none";
  1228. case I915_BIT_6_SWIZZLE_9:
  1229. return "bit9";
  1230. case I915_BIT_6_SWIZZLE_9_10:
  1231. return "bit9/bit10";
  1232. case I915_BIT_6_SWIZZLE_9_11:
  1233. return "bit9/bit11";
  1234. case I915_BIT_6_SWIZZLE_9_10_11:
  1235. return "bit9/bit10/bit11";
  1236. case I915_BIT_6_SWIZZLE_9_17:
  1237. return "bit9/bit17";
  1238. case I915_BIT_6_SWIZZLE_9_10_17:
  1239. return "bit9/bit10/bit17";
  1240. case I915_BIT_6_SWIZZLE_UNKNOWN:
  1241. return "unkown";
  1242. }
  1243. return "bug";
  1244. }
  1245. static int i915_swizzle_info(struct seq_file *m, void *data)
  1246. {
  1247. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1248. struct drm_device *dev = node->minor->dev;
  1249. struct drm_i915_private *dev_priv = dev->dev_private;
  1250. int ret;
  1251. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1252. if (ret)
  1253. return ret;
  1254. seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
  1255. swizzle_string(dev_priv->mm.bit_6_swizzle_x));
  1256. seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
  1257. swizzle_string(dev_priv->mm.bit_6_swizzle_y));
  1258. if (IS_GEN3(dev) || IS_GEN4(dev)) {
  1259. seq_printf(m, "DDC = 0x%08x\n",
  1260. I915_READ(DCC));
  1261. seq_printf(m, "C0DRB3 = 0x%04x\n",
  1262. I915_READ16(C0DRB3));
  1263. seq_printf(m, "C1DRB3 = 0x%04x\n",
  1264. I915_READ16(C1DRB3));
  1265. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  1266. seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
  1267. I915_READ(MAD_DIMM_C0));
  1268. seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
  1269. I915_READ(MAD_DIMM_C1));
  1270. seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
  1271. I915_READ(MAD_DIMM_C2));
  1272. seq_printf(m, "TILECTL = 0x%08x\n",
  1273. I915_READ(TILECTL));
  1274. seq_printf(m, "ARB_MODE = 0x%08x\n",
  1275. I915_READ(ARB_MODE));
  1276. seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
  1277. I915_READ(DISP_ARB_CTL));
  1278. }
  1279. mutex_unlock(&dev->struct_mutex);
  1280. return 0;
  1281. }
  1282. static int i915_ppgtt_info(struct seq_file *m, void *data)
  1283. {
  1284. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1285. struct drm_device *dev = node->minor->dev;
  1286. struct drm_i915_private *dev_priv = dev->dev_private;
  1287. struct intel_ring_buffer *ring;
  1288. int i, ret;
  1289. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1290. if (ret)
  1291. return ret;
  1292. if (INTEL_INFO(dev)->gen == 6)
  1293. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
  1294. for_each_ring(ring, dev_priv, i) {
  1295. seq_printf(m, "%s\n", ring->name);
  1296. if (INTEL_INFO(dev)->gen == 7)
  1297. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
  1298. seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
  1299. seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
  1300. seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
  1301. }
  1302. if (dev_priv->mm.aliasing_ppgtt) {
  1303. struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  1304. seq_printf(m, "aliasing PPGTT:\n");
  1305. seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
  1306. }
  1307. seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
  1308. mutex_unlock(&dev->struct_mutex);
  1309. return 0;
  1310. }
  1311. static int i915_dpio_info(struct seq_file *m, void *data)
  1312. {
  1313. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1314. struct drm_device *dev = node->minor->dev;
  1315. struct drm_i915_private *dev_priv = dev->dev_private;
  1316. int ret;
  1317. if (!IS_VALLEYVIEW(dev)) {
  1318. seq_printf(m, "unsupported\n");
  1319. return 0;
  1320. }
  1321. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1322. if (ret)
  1323. return ret;
  1324. seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
  1325. seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
  1326. intel_dpio_read(dev_priv, _DPIO_DIV_A));
  1327. seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
  1328. intel_dpio_read(dev_priv, _DPIO_DIV_B));
  1329. seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
  1330. intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
  1331. seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
  1332. intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
  1333. seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
  1334. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
  1335. seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
  1336. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
  1337. seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
  1338. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
  1339. seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
  1340. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
  1341. seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
  1342. intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
  1343. mutex_unlock(&dev->mode_config.mutex);
  1344. return 0;
  1345. }
  1346. static ssize_t
  1347. i915_wedged_read(struct file *filp,
  1348. char __user *ubuf,
  1349. size_t max,
  1350. loff_t *ppos)
  1351. {
  1352. struct drm_device *dev = filp->private_data;
  1353. drm_i915_private_t *dev_priv = dev->dev_private;
  1354. char buf[80];
  1355. int len;
  1356. len = snprintf(buf, sizeof(buf),
  1357. "wedged : %d\n",
  1358. atomic_read(&dev_priv->mm.wedged));
  1359. if (len > sizeof(buf))
  1360. len = sizeof(buf);
  1361. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1362. }
  1363. static ssize_t
  1364. i915_wedged_write(struct file *filp,
  1365. const char __user *ubuf,
  1366. size_t cnt,
  1367. loff_t *ppos)
  1368. {
  1369. struct drm_device *dev = filp->private_data;
  1370. char buf[20];
  1371. int val = 1;
  1372. if (cnt > 0) {
  1373. if (cnt > sizeof(buf) - 1)
  1374. return -EINVAL;
  1375. if (copy_from_user(buf, ubuf, cnt))
  1376. return -EFAULT;
  1377. buf[cnt] = 0;
  1378. val = simple_strtoul(buf, NULL, 0);
  1379. }
  1380. DRM_INFO("Manually setting wedged to %d\n", val);
  1381. i915_handle_error(dev, val);
  1382. return cnt;
  1383. }
  1384. static const struct file_operations i915_wedged_fops = {
  1385. .owner = THIS_MODULE,
  1386. .open = simple_open,
  1387. .read = i915_wedged_read,
  1388. .write = i915_wedged_write,
  1389. .llseek = default_llseek,
  1390. };
  1391. static ssize_t
  1392. i915_ring_stop_read(struct file *filp,
  1393. char __user *ubuf,
  1394. size_t max,
  1395. loff_t *ppos)
  1396. {
  1397. struct drm_device *dev = filp->private_data;
  1398. drm_i915_private_t *dev_priv = dev->dev_private;
  1399. char buf[20];
  1400. int len;
  1401. len = snprintf(buf, sizeof(buf),
  1402. "0x%08x\n", dev_priv->stop_rings);
  1403. if (len > sizeof(buf))
  1404. len = sizeof(buf);
  1405. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1406. }
  1407. static ssize_t
  1408. i915_ring_stop_write(struct file *filp,
  1409. const char __user *ubuf,
  1410. size_t cnt,
  1411. loff_t *ppos)
  1412. {
  1413. struct drm_device *dev = filp->private_data;
  1414. struct drm_i915_private *dev_priv = dev->dev_private;
  1415. char buf[20];
  1416. int val = 0, ret;
  1417. if (cnt > 0) {
  1418. if (cnt > sizeof(buf) - 1)
  1419. return -EINVAL;
  1420. if (copy_from_user(buf, ubuf, cnt))
  1421. return -EFAULT;
  1422. buf[cnt] = 0;
  1423. val = simple_strtoul(buf, NULL, 0);
  1424. }
  1425. DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
  1426. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1427. if (ret)
  1428. return ret;
  1429. dev_priv->stop_rings = val;
  1430. mutex_unlock(&dev->struct_mutex);
  1431. return cnt;
  1432. }
  1433. static const struct file_operations i915_ring_stop_fops = {
  1434. .owner = THIS_MODULE,
  1435. .open = simple_open,
  1436. .read = i915_ring_stop_read,
  1437. .write = i915_ring_stop_write,
  1438. .llseek = default_llseek,
  1439. };
  1440. static ssize_t
  1441. i915_max_freq_read(struct file *filp,
  1442. char __user *ubuf,
  1443. size_t max,
  1444. loff_t *ppos)
  1445. {
  1446. struct drm_device *dev = filp->private_data;
  1447. drm_i915_private_t *dev_priv = dev->dev_private;
  1448. char buf[80];
  1449. int len, ret;
  1450. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1451. return -ENODEV;
  1452. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1453. if (ret)
  1454. return ret;
  1455. len = snprintf(buf, sizeof(buf),
  1456. "max freq: %d\n", dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER);
  1457. mutex_unlock(&dev->struct_mutex);
  1458. if (len > sizeof(buf))
  1459. len = sizeof(buf);
  1460. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1461. }
  1462. static ssize_t
  1463. i915_max_freq_write(struct file *filp,
  1464. const char __user *ubuf,
  1465. size_t cnt,
  1466. loff_t *ppos)
  1467. {
  1468. struct drm_device *dev = filp->private_data;
  1469. struct drm_i915_private *dev_priv = dev->dev_private;
  1470. char buf[20];
  1471. int val = 1, ret;
  1472. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1473. return -ENODEV;
  1474. if (cnt > 0) {
  1475. if (cnt > sizeof(buf) - 1)
  1476. return -EINVAL;
  1477. if (copy_from_user(buf, ubuf, cnt))
  1478. return -EFAULT;
  1479. buf[cnt] = 0;
  1480. val = simple_strtoul(buf, NULL, 0);
  1481. }
  1482. DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
  1483. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1484. if (ret)
  1485. return ret;
  1486. /*
  1487. * Turbo will still be enabled, but won't go above the set value.
  1488. */
  1489. dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER;
  1490. gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
  1491. mutex_unlock(&dev->struct_mutex);
  1492. return cnt;
  1493. }
  1494. static const struct file_operations i915_max_freq_fops = {
  1495. .owner = THIS_MODULE,
  1496. .open = simple_open,
  1497. .read = i915_max_freq_read,
  1498. .write = i915_max_freq_write,
  1499. .llseek = default_llseek,
  1500. };
  1501. static ssize_t
  1502. i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
  1503. loff_t *ppos)
  1504. {
  1505. struct drm_device *dev = filp->private_data;
  1506. drm_i915_private_t *dev_priv = dev->dev_private;
  1507. char buf[80];
  1508. int len, ret;
  1509. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1510. return -ENODEV;
  1511. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1512. if (ret)
  1513. return ret;
  1514. len = snprintf(buf, sizeof(buf),
  1515. "min freq: %d\n", dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER);
  1516. mutex_unlock(&dev->struct_mutex);
  1517. if (len > sizeof(buf))
  1518. len = sizeof(buf);
  1519. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1520. }
  1521. static ssize_t
  1522. i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
  1523. loff_t *ppos)
  1524. {
  1525. struct drm_device *dev = filp->private_data;
  1526. struct drm_i915_private *dev_priv = dev->dev_private;
  1527. char buf[20];
  1528. int val = 1, ret;
  1529. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1530. return -ENODEV;
  1531. if (cnt > 0) {
  1532. if (cnt > sizeof(buf) - 1)
  1533. return -EINVAL;
  1534. if (copy_from_user(buf, ubuf, cnt))
  1535. return -EFAULT;
  1536. buf[cnt] = 0;
  1537. val = simple_strtoul(buf, NULL, 0);
  1538. }
  1539. DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
  1540. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1541. if (ret)
  1542. return ret;
  1543. /*
  1544. * Turbo will still be enabled, but won't go below the set value.
  1545. */
  1546. dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER;
  1547. gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
  1548. mutex_unlock(&dev->struct_mutex);
  1549. return cnt;
  1550. }
  1551. static const struct file_operations i915_min_freq_fops = {
  1552. .owner = THIS_MODULE,
  1553. .open = simple_open,
  1554. .read = i915_min_freq_read,
  1555. .write = i915_min_freq_write,
  1556. .llseek = default_llseek,
  1557. };
  1558. static ssize_t
  1559. i915_cache_sharing_read(struct file *filp,
  1560. char __user *ubuf,
  1561. size_t max,
  1562. loff_t *ppos)
  1563. {
  1564. struct drm_device *dev = filp->private_data;
  1565. drm_i915_private_t *dev_priv = dev->dev_private;
  1566. char buf[80];
  1567. u32 snpcr;
  1568. int len, ret;
  1569. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1570. return -ENODEV;
  1571. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1572. if (ret)
  1573. return ret;
  1574. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1575. mutex_unlock(&dev_priv->dev->struct_mutex);
  1576. len = snprintf(buf, sizeof(buf),
  1577. "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
  1578. GEN6_MBC_SNPCR_SHIFT);
  1579. if (len > sizeof(buf))
  1580. len = sizeof(buf);
  1581. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1582. }
  1583. static ssize_t
  1584. i915_cache_sharing_write(struct file *filp,
  1585. const char __user *ubuf,
  1586. size_t cnt,
  1587. loff_t *ppos)
  1588. {
  1589. struct drm_device *dev = filp->private_data;
  1590. struct drm_i915_private *dev_priv = dev->dev_private;
  1591. char buf[20];
  1592. u32 snpcr;
  1593. int val = 1;
  1594. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1595. return -ENODEV;
  1596. if (cnt > 0) {
  1597. if (cnt > sizeof(buf) - 1)
  1598. return -EINVAL;
  1599. if (copy_from_user(buf, ubuf, cnt))
  1600. return -EFAULT;
  1601. buf[cnt] = 0;
  1602. val = simple_strtoul(buf, NULL, 0);
  1603. }
  1604. if (val < 0 || val > 3)
  1605. return -EINVAL;
  1606. DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
  1607. /* Update the cache sharing policy here as well */
  1608. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1609. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  1610. snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
  1611. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  1612. return cnt;
  1613. }
  1614. static const struct file_operations i915_cache_sharing_fops = {
  1615. .owner = THIS_MODULE,
  1616. .open = simple_open,
  1617. .read = i915_cache_sharing_read,
  1618. .write = i915_cache_sharing_write,
  1619. .llseek = default_llseek,
  1620. };
  1621. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1622. * allocated we need to hook into the minor for release. */
  1623. static int
  1624. drm_add_fake_info_node(struct drm_minor *minor,
  1625. struct dentry *ent,
  1626. const void *key)
  1627. {
  1628. struct drm_info_node *node;
  1629. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1630. if (node == NULL) {
  1631. debugfs_remove(ent);
  1632. return -ENOMEM;
  1633. }
  1634. node->minor = minor;
  1635. node->dent = ent;
  1636. node->info_ent = (void *) key;
  1637. mutex_lock(&minor->debugfs_lock);
  1638. list_add(&node->list, &minor->debugfs_list);
  1639. mutex_unlock(&minor->debugfs_lock);
  1640. return 0;
  1641. }
  1642. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1643. {
  1644. struct drm_device *dev = inode->i_private;
  1645. struct drm_i915_private *dev_priv = dev->dev_private;
  1646. if (INTEL_INFO(dev)->gen < 6)
  1647. return 0;
  1648. gen6_gt_force_wake_get(dev_priv);
  1649. return 0;
  1650. }
  1651. static int i915_forcewake_release(struct inode *inode, struct file *file)
  1652. {
  1653. struct drm_device *dev = inode->i_private;
  1654. struct drm_i915_private *dev_priv = dev->dev_private;
  1655. if (INTEL_INFO(dev)->gen < 6)
  1656. return 0;
  1657. gen6_gt_force_wake_put(dev_priv);
  1658. return 0;
  1659. }
  1660. static const struct file_operations i915_forcewake_fops = {
  1661. .owner = THIS_MODULE,
  1662. .open = i915_forcewake_open,
  1663. .release = i915_forcewake_release,
  1664. };
  1665. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1666. {
  1667. struct drm_device *dev = minor->dev;
  1668. struct dentry *ent;
  1669. ent = debugfs_create_file("i915_forcewake_user",
  1670. S_IRUSR,
  1671. root, dev,
  1672. &i915_forcewake_fops);
  1673. if (IS_ERR(ent))
  1674. return PTR_ERR(ent);
  1675. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1676. }
  1677. static int i915_debugfs_create(struct dentry *root,
  1678. struct drm_minor *minor,
  1679. const char *name,
  1680. const struct file_operations *fops)
  1681. {
  1682. struct drm_device *dev = minor->dev;
  1683. struct dentry *ent;
  1684. ent = debugfs_create_file(name,
  1685. S_IRUGO | S_IWUSR,
  1686. root, dev,
  1687. fops);
  1688. if (IS_ERR(ent))
  1689. return PTR_ERR(ent);
  1690. return drm_add_fake_info_node(minor, ent, fops);
  1691. }
  1692. static struct drm_info_list i915_debugfs_list[] = {
  1693. {"i915_capabilities", i915_capabilities, 0},
  1694. {"i915_gem_objects", i915_gem_object_info, 0},
  1695. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1696. {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
  1697. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1698. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1699. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1700. {"i915_gem_request", i915_gem_request_info, 0},
  1701. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1702. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1703. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1704. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1705. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1706. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1707. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1708. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1709. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1710. {"i915_inttoext_table", i915_inttoext_table, 0},
  1711. {"i915_drpc_info", i915_drpc_info, 0},
  1712. {"i915_emon_status", i915_emon_status, 0},
  1713. {"i915_ring_freq_table", i915_ring_freq_table, 0},
  1714. {"i915_gfxec", i915_gfxec, 0},
  1715. {"i915_fbc_status", i915_fbc_status, 0},
  1716. {"i915_sr_status", i915_sr_status, 0},
  1717. {"i915_opregion", i915_opregion, 0},
  1718. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1719. {"i915_context_status", i915_context_status, 0},
  1720. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1721. {"i915_swizzle_info", i915_swizzle_info, 0},
  1722. {"i915_ppgtt_info", i915_ppgtt_info, 0},
  1723. {"i915_dpio", i915_dpio_info, 0},
  1724. };
  1725. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1726. int i915_debugfs_init(struct drm_minor *minor)
  1727. {
  1728. int ret;
  1729. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1730. "i915_wedged",
  1731. &i915_wedged_fops);
  1732. if (ret)
  1733. return ret;
  1734. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1735. if (ret)
  1736. return ret;
  1737. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1738. "i915_max_freq",
  1739. &i915_max_freq_fops);
  1740. if (ret)
  1741. return ret;
  1742. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1743. "i915_min_freq",
  1744. &i915_min_freq_fops);
  1745. if (ret)
  1746. return ret;
  1747. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1748. "i915_cache_sharing",
  1749. &i915_cache_sharing_fops);
  1750. if (ret)
  1751. return ret;
  1752. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1753. "i915_ring_stop",
  1754. &i915_ring_stop_fops);
  1755. if (ret)
  1756. return ret;
  1757. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1758. "i915_error_state",
  1759. &i915_error_state_fops);
  1760. if (ret)
  1761. return ret;
  1762. return drm_debugfs_create_files(i915_debugfs_list,
  1763. I915_DEBUGFS_ENTRIES,
  1764. minor->debugfs_root, minor);
  1765. }
  1766. void i915_debugfs_cleanup(struct drm_minor *minor)
  1767. {
  1768. drm_debugfs_remove_files(i915_debugfs_list,
  1769. I915_DEBUGFS_ENTRIES, minor);
  1770. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1771. 1, minor);
  1772. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1773. 1, minor);
  1774. drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
  1775. 1, minor);
  1776. drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
  1777. 1, minor);
  1778. drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
  1779. 1, minor);
  1780. drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
  1781. 1, minor);
  1782. drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
  1783. 1, minor);
  1784. }
  1785. #endif /* CONFIG_DEBUG_FS */