tegra-seaboard.dts 9.0 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Seaboard";
  5. compatible = "nvidia,seaboard", "nvidia,tegra20";
  6. memory {
  7. device_type = "memory";
  8. reg = < 0x00000000 0x40000000 >;
  9. };
  10. pinmux@70000000 {
  11. pinctrl-names = "default";
  12. pinctrl-0 = <&state_default>;
  13. state_default: pinmux {
  14. ata {
  15. nvidia,pins = "ata";
  16. nvidia,function = "ide";
  17. };
  18. atb {
  19. nvidia,pins = "atb", "gma", "gme";
  20. nvidia,function = "sdio4";
  21. };
  22. atc {
  23. nvidia,pins = "atc";
  24. nvidia,function = "nand";
  25. };
  26. atd {
  27. nvidia,pins = "atd", "ate", "gmb", "spia",
  28. "spib", "spic";
  29. nvidia,function = "gmi";
  30. };
  31. cdev1 {
  32. nvidia,pins = "cdev1";
  33. nvidia,function = "plla_out";
  34. };
  35. cdev2 {
  36. nvidia,pins = "cdev2";
  37. nvidia,function = "pllp_out4";
  38. };
  39. crtp {
  40. nvidia,pins = "crtp", "lm1";
  41. nvidia,function = "crt";
  42. };
  43. csus {
  44. nvidia,pins = "csus";
  45. nvidia,function = "vi_sensor_clk";
  46. };
  47. dap1 {
  48. nvidia,pins = "dap1";
  49. nvidia,function = "dap1";
  50. };
  51. dap2 {
  52. nvidia,pins = "dap2";
  53. nvidia,function = "dap2";
  54. };
  55. dap3 {
  56. nvidia,pins = "dap3";
  57. nvidia,function = "dap3";
  58. };
  59. dap4 {
  60. nvidia,pins = "dap4";
  61. nvidia,function = "dap4";
  62. };
  63. ddc {
  64. nvidia,pins = "ddc", "owc", "spdi", "spdo",
  65. "uac";
  66. nvidia,function = "rsvd2";
  67. };
  68. dta {
  69. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  70. nvidia,function = "vi";
  71. };
  72. dtf {
  73. nvidia,pins = "dtf";
  74. nvidia,function = "i2c3";
  75. };
  76. gmc {
  77. nvidia,pins = "gmc";
  78. nvidia,function = "uartd";
  79. };
  80. gmd {
  81. nvidia,pins = "gmd";
  82. nvidia,function = "sflash";
  83. };
  84. gpu {
  85. nvidia,pins = "gpu";
  86. nvidia,function = "pwm";
  87. };
  88. gpu7 {
  89. nvidia,pins = "gpu7";
  90. nvidia,function = "rtck";
  91. };
  92. gpv {
  93. nvidia,pins = "gpv", "slxa", "slxk";
  94. nvidia,function = "pcie";
  95. };
  96. hdint {
  97. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  98. "lsck", "lsda", "pta";
  99. nvidia,function = "hdmi";
  100. };
  101. i2cp {
  102. nvidia,pins = "i2cp";
  103. nvidia,function = "i2cp";
  104. };
  105. irrx {
  106. nvidia,pins = "irrx", "irtx";
  107. nvidia,function = "uartb";
  108. };
  109. kbca {
  110. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  111. "kbce", "kbcf";
  112. nvidia,function = "kbc";
  113. };
  114. lcsn {
  115. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  116. "lsdi", "lvp0";
  117. nvidia,function = "rsvd4";
  118. };
  119. ld0 {
  120. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  121. "ld5", "ld6", "ld7", "ld8", "ld9",
  122. "ld10", "ld11", "ld12", "ld13", "ld14",
  123. "ld15", "ld16", "ld17", "ldi", "lhp0",
  124. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  125. "lspi", "lvp1", "lvs";
  126. nvidia,function = "displaya";
  127. };
  128. pmc {
  129. nvidia,pins = "pmc";
  130. nvidia,function = "pwr_on";
  131. };
  132. rm {
  133. nvidia,pins = "rm";
  134. nvidia,function = "i2c1";
  135. };
  136. sdb {
  137. nvidia,pins = "sdb", "sdc", "sdd";
  138. nvidia,function = "sdio3";
  139. };
  140. sdio1 {
  141. nvidia,pins = "sdio1";
  142. nvidia,function = "sdio1";
  143. };
  144. slxc {
  145. nvidia,pins = "slxc", "slxd";
  146. nvidia,function = "spdif";
  147. };
  148. spid {
  149. nvidia,pins = "spid", "spie", "spif";
  150. nvidia,function = "spi1";
  151. };
  152. spig {
  153. nvidia,pins = "spig", "spih";
  154. nvidia,function = "spi2_alt";
  155. };
  156. uaa {
  157. nvidia,pins = "uaa", "uab", "uda";
  158. nvidia,function = "ulpi";
  159. };
  160. uad {
  161. nvidia,pins = "uad";
  162. nvidia,function = "irda";
  163. };
  164. uca {
  165. nvidia,pins = "uca", "ucb";
  166. nvidia,function = "uartc";
  167. };
  168. conf_ata {
  169. nvidia,pins = "ata", "atb", "atc", "atd",
  170. "cdev1", "cdev2", "dap1", "dap2",
  171. "dap4", "dtf", "gma", "gmc", "gmd",
  172. "gme", "gpu", "gpu7", "i2cp", "irrx",
  173. "irtx", "pta", "rm", "sdc", "sdd",
  174. "slxd", "slxk", "spdi", "spdo", "uac",
  175. "uad", "uca", "ucb", "uda";
  176. nvidia,pull = <0>;
  177. nvidia,tristate = <0>;
  178. };
  179. conf_ate {
  180. nvidia,pins = "ate", "csus", "dap3", "ddc",
  181. "gpv", "owc", "slxc", "spib", "spid",
  182. "spie";
  183. nvidia,pull = <0>;
  184. nvidia,tristate = <1>;
  185. };
  186. conf_ck32 {
  187. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  188. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  189. nvidia,pull = <0>;
  190. };
  191. conf_crtp {
  192. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  193. "spig", "spih";
  194. nvidia,pull = <2>;
  195. nvidia,tristate = <1>;
  196. };
  197. conf_dta {
  198. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  199. nvidia,pull = <1>;
  200. nvidia,tristate = <0>;
  201. };
  202. conf_dte {
  203. nvidia,pins = "dte", "spif";
  204. nvidia,pull = <1>;
  205. nvidia,tristate = <1>;
  206. };
  207. conf_hdint {
  208. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  209. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  210. "lvp0";
  211. nvidia,tristate = <1>;
  212. };
  213. conf_kbca {
  214. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  215. "kbce", "kbcf", "sdio1", "spic", "uaa",
  216. "uab";
  217. nvidia,pull = <2>;
  218. nvidia,tristate = <0>;
  219. };
  220. conf_lc {
  221. nvidia,pins = "lc", "ls";
  222. nvidia,pull = <2>;
  223. };
  224. conf_ld0 {
  225. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  226. "ld5", "ld6", "ld7", "ld8", "ld9",
  227. "ld10", "ld11", "ld12", "ld13", "ld14",
  228. "ld15", "ld16", "ld17", "ldi", "lhp0",
  229. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  230. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  231. "lvs", "pmc", "sdb";
  232. nvidia,tristate = <0>;
  233. };
  234. conf_ld17_0 {
  235. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  236. "ld23_22";
  237. nvidia,pull = <1>;
  238. };
  239. drive_sdio1 {
  240. nvidia,pins = "drive_sdio1";
  241. nvidia,high-speed-mode = <0>;
  242. nvidia,schmitt = <0>;
  243. nvidia,low-power-mode = <3>;
  244. nvidia,pull-down-strength = <31>;
  245. nvidia,pull-up-strength = <31>;
  246. nvidia,slew-rate-rising = <3>;
  247. nvidia,slew-rate-falling = <3>;
  248. };
  249. };
  250. };
  251. i2c@7000c000 {
  252. clock-frequency = <400000>;
  253. wm8903: wm8903@1a {
  254. compatible = "wlf,wm8903";
  255. reg = <0x1a>;
  256. interrupt-parent = <&gpio>;
  257. interrupts = < 187 0x04 >;
  258. gpio-controller;
  259. #gpio-cells = <2>;
  260. micdet-cfg = <0>;
  261. micdet-delay = <100>;
  262. gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
  263. };
  264. };
  265. i2c@7000c400 {
  266. clock-frequency = <400000>;
  267. };
  268. i2c@7000c500 {
  269. clock-frequency = <400000>;
  270. };
  271. i2c@7000d000 {
  272. clock-frequency = <400000>;
  273. adt7461@4c {
  274. compatible = "adt7461";
  275. reg = <0x4c>;
  276. };
  277. };
  278. i2s@70002a00 {
  279. status = "disable";
  280. };
  281. sound {
  282. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  283. "nvidia,tegra-audio-wm8903";
  284. nvidia,model = "NVIDIA Tegra Seaboard";
  285. nvidia,audio-routing =
  286. "Headphone Jack", "HPOUTR",
  287. "Headphone Jack", "HPOUTL",
  288. "Int Spk", "ROP",
  289. "Int Spk", "RON",
  290. "Int Spk", "LOP",
  291. "Int Spk", "LON",
  292. "Mic Jack", "MICBIAS",
  293. "IN1R", "Mic Jack";
  294. nvidia,i2s-controller = <&tegra_i2s1>;
  295. nvidia,audio-codec = <&wm8903>;
  296. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  297. nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
  298. };
  299. serial@70006000 {
  300. status = "disable";
  301. };
  302. serial@70006040 {
  303. status = "disable";
  304. };
  305. serial@70006200 {
  306. status = "disable";
  307. };
  308. serial@70006300 {
  309. clock-frequency = < 216000000 >;
  310. };
  311. serial@70006400 {
  312. status = "disable";
  313. };
  314. sdhci@c8000000 {
  315. status = "disable";
  316. };
  317. sdhci@c8000200 {
  318. status = "disable";
  319. };
  320. sdhci@c8000400 {
  321. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  322. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  323. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  324. };
  325. sdhci@c8000600 {
  326. support-8bit;
  327. };
  328. usb@c5000000 {
  329. nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
  330. dr_mode = "otg";
  331. };
  332. gpio-keys {
  333. compatible = "gpio-keys";
  334. power {
  335. label = "Power";
  336. gpios = <&gpio 170 1>; /* gpio PV2, active low */
  337. linux,code = <116>; /* KEY_POWER */
  338. gpio-key,wakeup;
  339. };
  340. lid {
  341. label = "Lid";
  342. gpios = <&gpio 23 0>; /* gpio PC7 */
  343. linux,input-type = <5>; /* EV_SW */
  344. linux,code = <0>; /* SW_LID */
  345. debounce-interval = <1>;
  346. gpio-key,wakeup;
  347. };
  348. };
  349. emc@7000f400 {
  350. emc-table@190000 {
  351. reg = < 190000 >;
  352. compatible = "nvidia,tegra20-emc-table";
  353. clock-frequency = < 190000 >;
  354. nvidia,emc-registers = < 0x0000000c 0x00000026
  355. 0x00000009 0x00000003 0x00000004 0x00000004
  356. 0x00000002 0x0000000c 0x00000003 0x00000003
  357. 0x00000002 0x00000001 0x00000004 0x00000005
  358. 0x00000004 0x00000009 0x0000000d 0x0000059f
  359. 0x00000000 0x00000003 0x00000003 0x00000003
  360. 0x00000003 0x00000001 0x0000000b 0x000000c8
  361. 0x00000003 0x00000007 0x00000004 0x0000000f
  362. 0x00000002 0x00000000 0x00000000 0x00000002
  363. 0x00000000 0x00000000 0x00000083 0xa06204ae
  364. 0x007dc010 0x00000000 0x00000000 0x00000000
  365. 0x00000000 0x00000000 0x00000000 0x00000000 >;
  366. };
  367. emc-table@380000 {
  368. reg = < 380000 >;
  369. compatible = "nvidia,tegra20-emc-table";
  370. clock-frequency = < 380000 >;
  371. nvidia,emc-registers = < 0x00000017 0x0000004b
  372. 0x00000012 0x00000006 0x00000004 0x00000005
  373. 0x00000003 0x0000000c 0x00000006 0x00000006
  374. 0x00000003 0x00000001 0x00000004 0x00000005
  375. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  376. 0x00000000 0x00000003 0x00000003 0x00000006
  377. 0x00000006 0x00000001 0x00000011 0x000000c8
  378. 0x00000003 0x0000000e 0x00000007 0x0000000f
  379. 0x00000002 0x00000000 0x00000000 0x00000002
  380. 0x00000000 0x00000000 0x00000083 0xe044048b
  381. 0x007d8010 0x00000000 0x00000000 0x00000000
  382. 0x00000000 0x00000000 0x00000000 0x00000000 >;
  383. };
  384. };
  385. };