intel_idle.c 10 KB

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  1. /*
  2. * intel_idle.c - native hardware idle loop for modern Intel processors
  3. *
  4. * Copyright (c) 2010, Intel Corporation.
  5. * Len Brown <len.brown@intel.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19. */
  20. /*
  21. * intel_idle is a cpuidle driver that loads on specific Intel processors
  22. * in lieu of the legacy ACPI processor_idle driver. The intent is to
  23. * make Linux more efficient on these processors, as intel_idle knows
  24. * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  25. */
  26. /*
  27. * Design Assumptions
  28. *
  29. * All CPUs have same idle states as boot CPU
  30. *
  31. * Chipset BM_STS (bus master status) bit is a NOP
  32. * for preventing entry into deep C-stats
  33. */
  34. /*
  35. * Known limitations
  36. *
  37. * The driver currently initializes for_each_online_cpu() upon modprobe.
  38. * It it unaware of subsequent processors hot-added to the system.
  39. * This means that if you boot with maxcpus=n and later online
  40. * processors above n, those processors will use C1 only.
  41. *
  42. * ACPI has a .suspend hack to turn off deep c-statees during suspend
  43. * to avoid complications with the lapic timer workaround.
  44. * Have not seen issues with suspend, but may need same workaround here.
  45. *
  46. * There is currently no kernel-based automatic probing/loading mechanism
  47. * if the driver is built as a module.
  48. */
  49. /* un-comment DEBUG to enable pr_debug() statements */
  50. #define DEBUG
  51. #include <linux/kernel.h>
  52. #include <linux/cpuidle.h>
  53. #include <linux/clockchips.h>
  54. #include <linux/hrtimer.h> /* ktime_get_real() */
  55. #include <trace/events/power.h>
  56. #include <linux/sched.h>
  57. #define INTEL_IDLE_VERSION "0.4"
  58. #define PREFIX "intel_idle: "
  59. #define MWAIT_SUBSTATE_MASK (0xf)
  60. #define MWAIT_CSTATE_MASK (0xf)
  61. #define MWAIT_SUBSTATE_SIZE (4)
  62. #define MWAIT_MAX_NUM_CSTATES 8
  63. #define CPUID_MWAIT_LEAF (5)
  64. #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
  65. #define CPUID5_ECX_INTERRUPT_BREAK (0x2)
  66. static struct cpuidle_driver intel_idle_driver = {
  67. .name = "intel_idle",
  68. .owner = THIS_MODULE,
  69. };
  70. /* intel_idle.max_cstate=0 disables driver */
  71. static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
  72. static unsigned int mwait_substates;
  73. /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
  74. static unsigned int lapic_timer_reliable_states;
  75. static struct cpuidle_device *intel_idle_cpuidle_devices;
  76. static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
  77. static struct cpuidle_state *cpuidle_state_table;
  78. /*
  79. * States are indexed by the cstate number,
  80. * which is also the index into the MWAIT hint array.
  81. * Thus C0 is a dummy.
  82. */
  83. static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
  84. { /* MWAIT C0 */ },
  85. { /* MWAIT C1 */
  86. .name = "NHM-C1",
  87. .desc = "MWAIT 0x00",
  88. .driver_data = (void *) 0x00,
  89. .flags = CPUIDLE_FLAG_TIME_VALID,
  90. .exit_latency = 3,
  91. .power_usage = 1000,
  92. .target_residency = 6,
  93. .enter = &intel_idle },
  94. { /* MWAIT C2 */
  95. .name = "NHM-C3",
  96. .desc = "MWAIT 0x10",
  97. .driver_data = (void *) 0x10,
  98. .flags = CPUIDLE_FLAG_TIME_VALID,
  99. .exit_latency = 20,
  100. .power_usage = 500,
  101. .target_residency = 80,
  102. .enter = &intel_idle },
  103. { /* MWAIT C3 */
  104. .name = "NHM-C6",
  105. .desc = "MWAIT 0x20",
  106. .driver_data = (void *) 0x20,
  107. .flags = CPUIDLE_FLAG_TIME_VALID,
  108. .exit_latency = 200,
  109. .power_usage = 350,
  110. .target_residency = 800,
  111. .enter = &intel_idle },
  112. };
  113. static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
  114. { /* MWAIT C0 */ },
  115. { /* MWAIT C1 */
  116. .name = "ATM-C1",
  117. .desc = "MWAIT 0x00",
  118. .driver_data = (void *) 0x00,
  119. .flags = CPUIDLE_FLAG_TIME_VALID,
  120. .exit_latency = 1,
  121. .power_usage = 1000,
  122. .target_residency = 4,
  123. .enter = &intel_idle },
  124. { /* MWAIT C2 */
  125. .name = "ATM-C2",
  126. .desc = "MWAIT 0x10",
  127. .driver_data = (void *) 0x10,
  128. .flags = CPUIDLE_FLAG_TIME_VALID,
  129. .exit_latency = 20,
  130. .power_usage = 500,
  131. .target_residency = 80,
  132. .enter = &intel_idle },
  133. { /* MWAIT C3 */ },
  134. { /* MWAIT C4 */
  135. .name = "ATM-C4",
  136. .desc = "MWAIT 0x30",
  137. .driver_data = (void *) 0x30,
  138. .flags = CPUIDLE_FLAG_TIME_VALID,
  139. .exit_latency = 100,
  140. .power_usage = 250,
  141. .target_residency = 400,
  142. .enter = &intel_idle },
  143. { /* MWAIT C5 */ },
  144. { /* MWAIT C6 */
  145. .name = "ATM-C6",
  146. .desc = "MWAIT 0x40",
  147. .driver_data = (void *) 0x40,
  148. .flags = CPUIDLE_FLAG_TIME_VALID,
  149. .exit_latency = 200,
  150. .power_usage = 150,
  151. .target_residency = 800,
  152. .enter = NULL }, /* disabled */
  153. };
  154. /**
  155. * intel_idle
  156. * @dev: cpuidle_device
  157. * @state: cpuidle state
  158. *
  159. */
  160. static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
  161. {
  162. unsigned long ecx = 1; /* break on interrupt flag */
  163. unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
  164. unsigned int cstate;
  165. ktime_t kt_before, kt_after;
  166. s64 usec_delta;
  167. int cpu = smp_processor_id();
  168. cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
  169. local_irq_disable();
  170. if (!(lapic_timer_reliable_states & (1 << (cstate))))
  171. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
  172. kt_before = ktime_get_real();
  173. stop_critical_timings();
  174. #ifndef MODULE
  175. trace_power_start(POWER_CSTATE, (eax >> 4) + 1);
  176. #endif
  177. if (!need_resched()) {
  178. __monitor((void *)&current_thread_info()->flags, 0, 0);
  179. smp_mb();
  180. if (!need_resched())
  181. __mwait(eax, ecx);
  182. }
  183. start_critical_timings();
  184. kt_after = ktime_get_real();
  185. usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
  186. local_irq_enable();
  187. if (!(lapic_timer_reliable_states & (1 << (cstate))))
  188. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
  189. return usec_delta;
  190. }
  191. /*
  192. * intel_idle_probe()
  193. */
  194. static int intel_idle_probe(void)
  195. {
  196. unsigned int eax, ebx, ecx;
  197. if (max_cstate == 0) {
  198. pr_debug(PREFIX "disabled\n");
  199. return -EPERM;
  200. }
  201. if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
  202. return -ENODEV;
  203. if (!boot_cpu_has(X86_FEATURE_MWAIT))
  204. return -ENODEV;
  205. if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
  206. return -ENODEV;
  207. cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
  208. if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
  209. !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
  210. return -ENODEV;
  211. pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
  212. if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
  213. lapic_timer_reliable_states = 0xFFFFFFFF;
  214. if (boot_cpu_data.x86 != 6) /* family 6 */
  215. return -ENODEV;
  216. switch (boot_cpu_data.x86_model) {
  217. case 0x1A: /* Core i7, Xeon 5500 series */
  218. case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
  219. case 0x1F: /* Core i7 and i5 Processor - Nehalem */
  220. case 0x2E: /* Nehalem-EX Xeon */
  221. case 0x2F: /* Westmere-EX Xeon */
  222. lapic_timer_reliable_states = (1 << 1); /* C1 */
  223. case 0x25: /* Westmere */
  224. case 0x2C: /* Westmere */
  225. cpuidle_state_table = nehalem_cstates;
  226. break;
  227. case 0x1C: /* 28 - Atom Processor */
  228. lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
  229. cpuidle_state_table = atom_cstates;
  230. break;
  231. #ifdef FUTURE_USE
  232. case 0x17: /* 23 - Core 2 Duo */
  233. lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
  234. #endif
  235. default:
  236. pr_debug(PREFIX "does not run on family %d model %d\n",
  237. boot_cpu_data.x86, boot_cpu_data.x86_model);
  238. return -ENODEV;
  239. }
  240. pr_debug(PREFIX "v" INTEL_IDLE_VERSION
  241. " model 0x%X\n", boot_cpu_data.x86_model);
  242. pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
  243. lapic_timer_reliable_states);
  244. return 0;
  245. }
  246. /*
  247. * intel_idle_cpuidle_devices_uninit()
  248. * unregister, free cpuidle_devices
  249. */
  250. static void intel_idle_cpuidle_devices_uninit(void)
  251. {
  252. int i;
  253. struct cpuidle_device *dev;
  254. for_each_online_cpu(i) {
  255. dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
  256. cpuidle_unregister_device(dev);
  257. }
  258. free_percpu(intel_idle_cpuidle_devices);
  259. return;
  260. }
  261. /*
  262. * intel_idle_cpuidle_devices_init()
  263. * allocate, initialize, register cpuidle_devices
  264. */
  265. static int intel_idle_cpuidle_devices_init(void)
  266. {
  267. int i, cstate;
  268. struct cpuidle_device *dev;
  269. intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
  270. if (intel_idle_cpuidle_devices == NULL)
  271. return -ENOMEM;
  272. for_each_online_cpu(i) {
  273. dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
  274. dev->state_count = 1;
  275. for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
  276. int num_substates;
  277. if (cstate > max_cstate) {
  278. printk(PREFIX "max_cstate %d reached\n",
  279. max_cstate);
  280. break;
  281. }
  282. /* does the state exist in CPUID.MWAIT? */
  283. num_substates = (mwait_substates >> ((cstate) * 4))
  284. & MWAIT_SUBSTATE_MASK;
  285. if (num_substates == 0)
  286. continue;
  287. /* is the state not enabled? */
  288. if (cpuidle_state_table[cstate].enter == NULL) {
  289. /* does the driver not know about the state? */
  290. if (*cpuidle_state_table[cstate].name == '\0')
  291. pr_debug(PREFIX "unaware of model 0x%x"
  292. " MWAIT %d please"
  293. " contact lenb@kernel.org",
  294. boot_cpu_data.x86_model, cstate);
  295. continue;
  296. }
  297. if ((cstate > 2) &&
  298. !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
  299. mark_tsc_unstable("TSC halts in idle"
  300. " states deeper than C2");
  301. dev->states[dev->state_count] = /* structure copy */
  302. cpuidle_state_table[cstate];
  303. dev->state_count += 1;
  304. }
  305. dev->cpu = i;
  306. if (cpuidle_register_device(dev)) {
  307. pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
  308. i);
  309. intel_idle_cpuidle_devices_uninit();
  310. return -EIO;
  311. }
  312. }
  313. return 0;
  314. }
  315. static int __init intel_idle_init(void)
  316. {
  317. int retval;
  318. retval = intel_idle_probe();
  319. if (retval)
  320. return retval;
  321. retval = cpuidle_register_driver(&intel_idle_driver);
  322. if (retval) {
  323. printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
  324. cpuidle_get_driver()->name);
  325. return retval;
  326. }
  327. retval = intel_idle_cpuidle_devices_init();
  328. if (retval) {
  329. cpuidle_unregister_driver(&intel_idle_driver);
  330. return retval;
  331. }
  332. return 0;
  333. }
  334. static void __exit intel_idle_exit(void)
  335. {
  336. intel_idle_cpuidle_devices_uninit();
  337. cpuidle_unregister_driver(&intel_idle_driver);
  338. return;
  339. }
  340. module_init(intel_idle_init);
  341. module_exit(intel_idle_exit);
  342. module_param(max_cstate, int, 0444);
  343. MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
  344. MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
  345. MODULE_LICENSE("GPL");