at91sam9n12.dtsi 7.6 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. };
  29. cpus {
  30. cpu@0 {
  31. compatible = "arm,arm926ejs";
  32. };
  33. };
  34. memory {
  35. reg = <0x20000000 0x10000000>;
  36. };
  37. ahb {
  38. compatible = "simple-bus";
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. ranges;
  42. apb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. aic: interrupt-controller@fffff000 {
  48. #interrupt-cells = <3>;
  49. compatible = "atmel,at91rm9200-aic";
  50. interrupt-controller;
  51. reg = <0xfffff000 0x200>;
  52. };
  53. ramc0: ramc@ffffe800 {
  54. compatible = "atmel,at91sam9g45-ddramc";
  55. reg = <0xffffe800 0x200>;
  56. };
  57. pmc: pmc@fffffc00 {
  58. compatible = "atmel,at91rm9200-pmc";
  59. reg = <0xfffffc00 0x100>;
  60. };
  61. rstc@fffffe00 {
  62. compatible = "atmel,at91sam9g45-rstc";
  63. reg = <0xfffffe00 0x10>;
  64. };
  65. pit: timer@fffffe30 {
  66. compatible = "atmel,at91sam9260-pit";
  67. reg = <0xfffffe30 0xf>;
  68. interrupts = <1 4 7>;
  69. };
  70. shdwc@fffffe10 {
  71. compatible = "atmel,at91sam9x5-shdwc";
  72. reg = <0xfffffe10 0x10>;
  73. };
  74. tcb0: timer@f8008000 {
  75. compatible = "atmel,at91sam9x5-tcb";
  76. reg = <0xf8008000 0x100>;
  77. interrupts = <17 4 0>;
  78. };
  79. tcb1: timer@f800c000 {
  80. compatible = "atmel,at91sam9x5-tcb";
  81. reg = <0xf800c000 0x100>;
  82. interrupts = <17 4 0>;
  83. };
  84. dma: dma-controller@ffffec00 {
  85. compatible = "atmel,at91sam9g45-dma";
  86. reg = <0xffffec00 0x200>;
  87. interrupts = <20 4 0>;
  88. };
  89. pinctrl@fffff400 {
  90. #address-cells = <1>;
  91. #size-cells = <1>;
  92. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  93. ranges = <0xfffff400 0xfffff400 0x800>;
  94. atmel,mux-mask = <
  95. /* A B C */
  96. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  97. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  98. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  99. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  100. >;
  101. /* shared pinctrl settings */
  102. dbgu {
  103. pinctrl_dbgu: dbgu-0 {
  104. atmel,pins =
  105. <0 9 0x1 0x0 /* PA9 periph A */
  106. 0 10 0x1 0x1>; /* PA10 periph with pullup */
  107. };
  108. };
  109. uart0 {
  110. pinctrl_uart0: uart0-0 {
  111. atmel,pins =
  112. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  113. 0 0 0x1 0x0>; /* PA0 periph A */
  114. };
  115. pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  116. atmel,pins =
  117. <0 2 0x1 0x0 /* PA2 periph A */
  118. 0 3 0x1 0x0>; /* PA3 periph A */
  119. };
  120. };
  121. uart1 {
  122. pinctrl_uart1: uart1-0 {
  123. atmel,pins =
  124. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  125. 0 5 0x1 0x0>; /* PA5 periph A */
  126. };
  127. };
  128. uart2 {
  129. pinctrl_uart2: uart2-0 {
  130. atmel,pins =
  131. <0 8 0x1 0x1 /* PA8 periph A with pullup */
  132. 0 7 0x1 0x0>; /* PA7 periph A */
  133. };
  134. pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  135. atmel,pins =
  136. <1 0 0x2 0x0 /* PB0 periph B */
  137. 1 1 0x2 0x0>; /* PB1 periph B */
  138. };
  139. };
  140. uart3 {
  141. pinctrl_uart3: uart3-0 {
  142. atmel,pins =
  143. <2 23 0x2 0x1 /* PC23 periph B with pullup */
  144. 2 22 0x2 0x0>; /* PC22 periph B */
  145. };
  146. pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
  147. atmel,pins =
  148. <2 24 0x2 0x0 /* PC24 periph B */
  149. 2 25 0x2 0x0>; /* PC25 periph B */
  150. };
  151. };
  152. usart0 {
  153. pinctrl_usart0: usart0-0 {
  154. atmel,pins =
  155. <2 9 0x3 0x1 /* PC9 periph C with pullup */
  156. 2 8 0x3 0x0>; /* PC8 periph C */
  157. };
  158. };
  159. usart1 {
  160. pinctrl_usart1: usart1-0 {
  161. atmel,pins =
  162. <2 16 0x3 0x1 /* PC17 periph C with pullup */
  163. 2 17 0x3 0x0>; /* PC16 periph C */
  164. };
  165. };
  166. pioA: gpio@fffff400 {
  167. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  168. reg = <0xfffff400 0x200>;
  169. interrupts = <2 4 1>;
  170. #gpio-cells = <2>;
  171. gpio-controller;
  172. interrupt-controller;
  173. #interrupt-cells = <2>;
  174. };
  175. pioB: gpio@fffff600 {
  176. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  177. reg = <0xfffff600 0x200>;
  178. interrupts = <2 4 1>;
  179. #gpio-cells = <2>;
  180. gpio-controller;
  181. interrupt-controller;
  182. #interrupt-cells = <2>;
  183. };
  184. pioC: gpio@fffff800 {
  185. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  186. reg = <0xfffff800 0x200>;
  187. interrupts = <3 4 1>;
  188. #gpio-cells = <2>;
  189. gpio-controller;
  190. interrupt-controller;
  191. #interrupt-cells = <2>;
  192. };
  193. pioD: gpio@fffffa00 {
  194. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  195. reg = <0xfffffa00 0x200>;
  196. interrupts = <3 4 1>;
  197. #gpio-cells = <2>;
  198. gpio-controller;
  199. interrupt-controller;
  200. #interrupt-cells = <2>;
  201. };
  202. };
  203. dbgu: serial@fffff200 {
  204. compatible = "atmel,at91sam9260-usart";
  205. reg = <0xfffff200 0x200>;
  206. interrupts = <1 4 7>;
  207. pinctrl-names = "default";
  208. pinctrl-0 = <&pinctrl_dbgu>;
  209. status = "disabled";
  210. };
  211. usart0: serial@f801c000 {
  212. compatible = "atmel,at91sam9260-usart";
  213. reg = <0xf801c000 0x4000>;
  214. interrupts = <5 4 5>;
  215. atmel,use-dma-rx;
  216. atmel,use-dma-tx;
  217. pinctrl-names = "default";
  218. pinctrl-0 = <&pinctrl_uart0>;
  219. status = "disabled";
  220. };
  221. usart1: serial@f8020000 {
  222. compatible = "atmel,at91sam9260-usart";
  223. reg = <0xf8020000 0x4000>;
  224. interrupts = <6 4 5>;
  225. atmel,use-dma-rx;
  226. atmel,use-dma-tx;
  227. pinctrl-names = "default";
  228. pinctrl-0 = <&pinctrl_uart1>;
  229. status = "disabled";
  230. };
  231. usart2: serial@f8024000 {
  232. compatible = "atmel,at91sam9260-usart";
  233. reg = <0xf8024000 0x4000>;
  234. interrupts = <7 4 5>;
  235. atmel,use-dma-rx;
  236. atmel,use-dma-tx;
  237. pinctrl-names = "default";
  238. pinctrl-0 = <&pinctrl_uart2>;
  239. status = "disabled";
  240. };
  241. usart3: serial@f8028000 {
  242. compatible = "atmel,at91sam9260-usart";
  243. reg = <0xf8028000 0x4000>;
  244. interrupts = <8 4 5>;
  245. atmel,use-dma-rx;
  246. atmel,use-dma-tx;
  247. pinctrl-names = "default";
  248. pinctrl-0 = <&pinctrl_uart3>;
  249. status = "disabled";
  250. };
  251. i2c0: i2c@f8010000 {
  252. compatible = "atmel,at91sam9x5-i2c";
  253. reg = <0xf8010000 0x100>;
  254. interrupts = <9 4 6>;
  255. #address-cells = <1>;
  256. #size-cells = <0>;
  257. status = "disabled";
  258. };
  259. i2c1: i2c@f8014000 {
  260. compatible = "atmel,at91sam9x5-i2c";
  261. reg = <0xf8014000 0x100>;
  262. interrupts = <10 4 6>;
  263. #address-cells = <1>;
  264. #size-cells = <0>;
  265. status = "disabled";
  266. };
  267. };
  268. nand0: nand@40000000 {
  269. compatible = "atmel,at91rm9200-nand";
  270. #address-cells = <1>;
  271. #size-cells = <1>;
  272. reg = < 0x40000000 0x10000000
  273. 0xffffe000 0x00000600
  274. 0xffffe600 0x00000200
  275. 0x00100000 0x00100000
  276. >;
  277. atmel,nand-addr-offset = <21>;
  278. atmel,nand-cmd-offset = <22>;
  279. gpios = <&pioD 5 0
  280. &pioD 4 0
  281. 0
  282. >;
  283. status = "disabled";
  284. };
  285. usb0: ohci@00500000 {
  286. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  287. reg = <0x00500000 0x00100000>;
  288. interrupts = <22 4 2>;
  289. status = "disabled";
  290. };
  291. };
  292. i2c@0 {
  293. compatible = "i2c-gpio";
  294. gpios = <&pioA 30 0 /* sda */
  295. &pioA 31 0 /* scl */
  296. >;
  297. i2c-gpio,sda-open-drain;
  298. i2c-gpio,scl-open-drain;
  299. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  300. #address-cells = <1>;
  301. #size-cells = <0>;
  302. status = "disabled";
  303. };
  304. };