at91sam9g45.dtsi 8.9 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x70000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe400 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe400 0x200
  60. 0xffffe600 0x200>;
  61. };
  62. pmc: pmc@fffffc00 {
  63. compatible = "atmel,at91rm9200-pmc";
  64. reg = <0xfffffc00 0x100>;
  65. };
  66. rstc@fffffd00 {
  67. compatible = "atmel,at91sam9g45-rstc";
  68. reg = <0xfffffd00 0x10>;
  69. };
  70. pit: timer@fffffd30 {
  71. compatible = "atmel,at91sam9260-pit";
  72. reg = <0xfffffd30 0xf>;
  73. interrupts = <1 4 7>;
  74. };
  75. shdwc@fffffd10 {
  76. compatible = "atmel,at91sam9rl-shdwc";
  77. reg = <0xfffffd10 0x10>;
  78. };
  79. tcb0: timer@fff7c000 {
  80. compatible = "atmel,at91rm9200-tcb";
  81. reg = <0xfff7c000 0x100>;
  82. interrupts = <18 4 0>;
  83. };
  84. tcb1: timer@fffd4000 {
  85. compatible = "atmel,at91rm9200-tcb";
  86. reg = <0xfffd4000 0x100>;
  87. interrupts = <18 4 0>;
  88. };
  89. dma: dma-controller@ffffec00 {
  90. compatible = "atmel,at91sam9g45-dma";
  91. reg = <0xffffec00 0x200>;
  92. interrupts = <21 4 0>;
  93. };
  94. pinctrl@fffff200 {
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  98. ranges = <0xfffff200 0xfffff200 0xa00>;
  99. atmel,mux-mask = <
  100. /* A B */
  101. 0xffffffff 0xffc003ff /* pioA */
  102. 0xffffffff 0x800f8f00 /* pioB */
  103. 0xffffffff 0x00000e00 /* pioC */
  104. 0xffffffff 0xff0c1381 /* pioD */
  105. 0xffffffff 0x81ffff81 /* pioE */
  106. >;
  107. /* shared pinctrl settings */
  108. dbgu {
  109. pinctrl_dbgu: dbgu-0 {
  110. atmel,pins =
  111. <1 12 0x1 0x0 /* PB12 periph A */
  112. 1 13 0x1 0x0>; /* PB13 periph A */
  113. };
  114. };
  115. uart0 {
  116. pinctrl_uart0: uart0-0 {
  117. atmel,pins =
  118. <1 19 0x1 0x1 /* PB19 periph A with pullup */
  119. 1 18 0x1 0x0>; /* PB18 periph A */
  120. };
  121. pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  122. atmel,pins =
  123. <1 17 0x2 0x0 /* PB17 periph B */
  124. 1 15 0x2 0x0>; /* PB15 periph B */
  125. };
  126. };
  127. uart1 {
  128. pinctrl_uart1: uart1-0 {
  129. atmel,pins =
  130. <1 4 0x1 0x1 /* PB4 periph A with pullup */
  131. 1 5 0x1 0x0>; /* PB5 periph A */
  132. };
  133. pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
  134. atmel,pins =
  135. <3 16 0x1 0x0 /* PD16 periph A */
  136. 3 17 0x1 0x0>; /* PD17 periph A */
  137. };
  138. };
  139. uart2 {
  140. pinctrl_uart2: uart2-0 {
  141. atmel,pins =
  142. <1 6 0x1 0x1 /* PB6 periph A with pullup */
  143. 1 7 0x1 0x0>; /* PB7 periph A */
  144. };
  145. pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  146. atmel,pins =
  147. <2 9 0x2 0x0 /* PC9 periph B */
  148. 2 11 0x2 0x0>; /* PC11 periph B */
  149. };
  150. };
  151. uart3 {
  152. pinctrl_uart3: uart3-0 {
  153. atmel,pins =
  154. <1 8 0x1 0x1 /* PB9 periph A with pullup */
  155. 1 9 0x1 0x0>; /* PB8 periph A */
  156. };
  157. pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
  158. atmel,pins =
  159. <0 23 0x2 0x0 /* PA23 periph B */
  160. 0 24 0x2 0x0>; /* PA24 periph B */
  161. };
  162. };
  163. pioA: gpio@fffff200 {
  164. compatible = "atmel,at91rm9200-gpio";
  165. reg = <0xfffff200 0x200>;
  166. interrupts = <2 4 1>;
  167. #gpio-cells = <2>;
  168. gpio-controller;
  169. interrupt-controller;
  170. #interrupt-cells = <2>;
  171. };
  172. pioB: gpio@fffff400 {
  173. compatible = "atmel,at91rm9200-gpio";
  174. reg = <0xfffff400 0x200>;
  175. interrupts = <3 4 1>;
  176. #gpio-cells = <2>;
  177. gpio-controller;
  178. interrupt-controller;
  179. #interrupt-cells = <2>;
  180. };
  181. pioC: gpio@fffff600 {
  182. compatible = "atmel,at91rm9200-gpio";
  183. reg = <0xfffff600 0x200>;
  184. interrupts = <4 4 1>;
  185. #gpio-cells = <2>;
  186. gpio-controller;
  187. interrupt-controller;
  188. #interrupt-cells = <2>;
  189. };
  190. pioD: gpio@fffff800 {
  191. compatible = "atmel,at91rm9200-gpio";
  192. reg = <0xfffff800 0x200>;
  193. interrupts = <5 4 1>;
  194. #gpio-cells = <2>;
  195. gpio-controller;
  196. interrupt-controller;
  197. #interrupt-cells = <2>;
  198. };
  199. pioE: gpio@fffffa00 {
  200. compatible = "atmel,at91rm9200-gpio";
  201. reg = <0xfffffa00 0x200>;
  202. interrupts = <5 4 1>;
  203. #gpio-cells = <2>;
  204. gpio-controller;
  205. interrupt-controller;
  206. #interrupt-cells = <2>;
  207. };
  208. };
  209. dbgu: serial@ffffee00 {
  210. compatible = "atmel,at91sam9260-usart";
  211. reg = <0xffffee00 0x200>;
  212. interrupts = <1 4 7>;
  213. pinctrl-names = "default";
  214. pinctrl-0 = <&pinctrl_dbgu>;
  215. status = "disabled";
  216. };
  217. usart0: serial@fff8c000 {
  218. compatible = "atmel,at91sam9260-usart";
  219. reg = <0xfff8c000 0x200>;
  220. interrupts = <7 4 5>;
  221. atmel,use-dma-rx;
  222. atmel,use-dma-tx;
  223. pinctrl-names = "default";
  224. pinctrl-0 = <&pinctrl_uart0>;
  225. status = "disabled";
  226. };
  227. usart1: serial@fff90000 {
  228. compatible = "atmel,at91sam9260-usart";
  229. reg = <0xfff90000 0x200>;
  230. interrupts = <8 4 5>;
  231. atmel,use-dma-rx;
  232. atmel,use-dma-tx;
  233. pinctrl-names = "default";
  234. pinctrl-0 = <&pinctrl_uart1>;
  235. status = "disabled";
  236. };
  237. usart2: serial@fff94000 {
  238. compatible = "atmel,at91sam9260-usart";
  239. reg = <0xfff94000 0x200>;
  240. interrupts = <9 4 5>;
  241. atmel,use-dma-rx;
  242. atmel,use-dma-tx;
  243. pinctrl-names = "default";
  244. pinctrl-0 = <&pinctrl_uart2>;
  245. status = "disabled";
  246. };
  247. usart3: serial@fff98000 {
  248. compatible = "atmel,at91sam9260-usart";
  249. reg = <0xfff98000 0x200>;
  250. interrupts = <10 4 5>;
  251. atmel,use-dma-rx;
  252. atmel,use-dma-tx;
  253. pinctrl-names = "default";
  254. pinctrl-0 = <&pinctrl_uart3>;
  255. status = "disabled";
  256. };
  257. macb0: ethernet@fffbc000 {
  258. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  259. reg = <0xfffbc000 0x100>;
  260. interrupts = <25 4 3>;
  261. status = "disabled";
  262. };
  263. i2c0: i2c@fff84000 {
  264. compatible = "atmel,at91sam9g10-i2c";
  265. reg = <0xfff84000 0x100>;
  266. interrupts = <12 4 6>;
  267. #address-cells = <1>;
  268. #size-cells = <0>;
  269. status = "disabled";
  270. };
  271. i2c1: i2c@fff88000 {
  272. compatible = "atmel,at91sam9g10-i2c";
  273. reg = <0xfff88000 0x100>;
  274. interrupts = <13 4 6>;
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. status = "disabled";
  278. };
  279. adc0: adc@fffb0000 {
  280. compatible = "atmel,at91sam9260-adc";
  281. reg = <0xfffb0000 0x100>;
  282. interrupts = <20 4 0>;
  283. atmel,adc-use-external-triggers;
  284. atmel,adc-channels-used = <0xff>;
  285. atmel,adc-vref = <3300>;
  286. atmel,adc-num-channels = <8>;
  287. atmel,adc-startup-time = <40>;
  288. atmel,adc-channel-base = <0x30>;
  289. atmel,adc-drdy-mask = <0x10000>;
  290. atmel,adc-status-register = <0x1c>;
  291. atmel,adc-trigger-register = <0x08>;
  292. trigger@0 {
  293. trigger-name = "external-rising";
  294. trigger-value = <0x1>;
  295. trigger-external;
  296. };
  297. trigger@1 {
  298. trigger-name = "external-falling";
  299. trigger-value = <0x2>;
  300. trigger-external;
  301. };
  302. trigger@2 {
  303. trigger-name = "external-any";
  304. trigger-value = <0x3>;
  305. trigger-external;
  306. };
  307. trigger@3 {
  308. trigger-name = "continuous";
  309. trigger-value = <0x6>;
  310. };
  311. };
  312. };
  313. nand0: nand@40000000 {
  314. compatible = "atmel,at91rm9200-nand";
  315. #address-cells = <1>;
  316. #size-cells = <1>;
  317. reg = <0x40000000 0x10000000
  318. 0xffffe200 0x200
  319. >;
  320. atmel,nand-addr-offset = <21>;
  321. atmel,nand-cmd-offset = <22>;
  322. gpios = <&pioC 8 0
  323. &pioC 14 0
  324. 0
  325. >;
  326. status = "disabled";
  327. };
  328. usb0: ohci@00700000 {
  329. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  330. reg = <0x00700000 0x100000>;
  331. interrupts = <22 4 2>;
  332. status = "disabled";
  333. };
  334. usb1: ehci@00800000 {
  335. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  336. reg = <0x00800000 0x100000>;
  337. interrupts = <22 4 2>;
  338. status = "disabled";
  339. };
  340. };
  341. i2c@0 {
  342. compatible = "i2c-gpio";
  343. gpios = <&pioA 20 0 /* sda */
  344. &pioA 21 0 /* scl */
  345. >;
  346. i2c-gpio,sda-open-drain;
  347. i2c-gpio,scl-open-drain;
  348. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  349. #address-cells = <1>;
  350. #size-cells = <0>;
  351. status = "disabled";
  352. };
  353. };