at91sam9263.dtsi 6.8 KB

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  1. /*
  2. * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
  3. *
  4. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5. *
  6. * Licensed under GPLv2 only.
  7. */
  8. /include/ "skeleton.dtsi"
  9. / {
  10. model = "Atmel AT91SAM9263 family SoC";
  11. compatible = "atmel,at91sam9263";
  12. interrupt-parent = <&aic>;
  13. aliases {
  14. serial0 = &dbgu;
  15. serial1 = &usart0;
  16. serial2 = &usart1;
  17. serial3 = &usart2;
  18. gpio0 = &pioA;
  19. gpio1 = &pioB;
  20. gpio2 = &pioC;
  21. gpio3 = &pioD;
  22. gpio4 = &pioE;
  23. tcb0 = &tcb0;
  24. i2c0 = &i2c0;
  25. };
  26. cpus {
  27. cpu@0 {
  28. compatible = "arm,arm926ejs";
  29. };
  30. };
  31. memory {
  32. reg = <0x20000000 0x08000000>;
  33. };
  34. ahb {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. ranges;
  39. apb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. aic: interrupt-controller@fffff000 {
  45. #interrupt-cells = <3>;
  46. compatible = "atmel,at91rm9200-aic";
  47. interrupt-controller;
  48. reg = <0xfffff000 0x200>;
  49. atmel,external-irqs = <30 31>;
  50. };
  51. pmc: pmc@fffffc00 {
  52. compatible = "atmel,at91rm9200-pmc";
  53. reg = <0xfffffc00 0x100>;
  54. };
  55. ramc: ramc@ffffe200 {
  56. compatible = "atmel,at91sam9260-sdramc";
  57. reg = <0xffffe200 0x200
  58. 0xffffe800 0x200>;
  59. };
  60. pit: timer@fffffd30 {
  61. compatible = "atmel,at91sam9260-pit";
  62. reg = <0xfffffd30 0xf>;
  63. interrupts = <1 4 7>;
  64. };
  65. tcb0: timer@fff7c000 {
  66. compatible = "atmel,at91rm9200-tcb";
  67. reg = <0xfff7c000 0x100>;
  68. interrupts = <19 4 0>;
  69. };
  70. rstc@fffffd00 {
  71. compatible = "atmel,at91sam9260-rstc";
  72. reg = <0xfffffd00 0x10>;
  73. };
  74. shdwc@fffffd10 {
  75. compatible = "atmel,at91sam9260-shdwc";
  76. reg = <0xfffffd10 0x10>;
  77. };
  78. pinctrl@fffff200 {
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  82. ranges = <0xfffff200 0xfffff200 0xa00>;
  83. atmel,mux-mask = <
  84. /* A B */
  85. 0xfffffffb 0xffffe07f /* pioA */
  86. 0x0007ffff 0x39072fff /* pioB */
  87. 0xffffffff 0x3ffffff8 /* pioC */
  88. 0xfffffbff 0xffffffff /* pioD */
  89. 0xffe00fff 0xfbfcff00 /* pioE */
  90. >;
  91. /* shared pinctrl settings */
  92. dbgu {
  93. pinctrl_dbgu: dbgu-0 {
  94. atmel,pins =
  95. <2 30 0x1 0x0 /* PC30 periph A */
  96. 2 31 0x1 0x1>; /* PC31 periph with pullup */
  97. };
  98. };
  99. uart0 {
  100. pinctrl_uart0: uart0-0 {
  101. atmel,pins =
  102. <0 26 0x1 0x1 /* PA26 periph A with pullup */
  103. 0 27 0x1 0x0>; /* PA27 periph A */
  104. };
  105. pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  106. atmel,pins =
  107. <0 28 0x1 0x0 /* PA28 periph A */
  108. 0 29 0x1 0x0>; /* PA29 periph A */
  109. };
  110. };
  111. uart1 {
  112. pinctrl_uart1: uart1-0 {
  113. atmel,pins =
  114. <3 0 0x1 0x1 /* PD0 periph A with pullup */
  115. 3 1 0x1 0x0>; /* PD1 periph A */
  116. };
  117. pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
  118. atmel,pins =
  119. <3 7 0x2 0x0 /* PD7 periph B */
  120. 3 8 0x2 0x0>; /* PD8 periph B */
  121. };
  122. };
  123. uart2 {
  124. pinctrl_uart2: uart2-0 {
  125. atmel,pins =
  126. <3 2 0x1 0x1 /* PD2 periph A with pullup */
  127. 3 3 0x1 0x0>; /* PD3 periph A */
  128. };
  129. pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  130. atmel,pins =
  131. <3 5 0x2 0x0 /* PD5 periph B */
  132. 4 6 0x2 0x0>; /* PD6 periph B */
  133. };
  134. };
  135. pioA: gpio@fffff200 {
  136. compatible = "atmel,at91rm9200-gpio";
  137. reg = <0xfffff200 0x200>;
  138. interrupts = <2 4 1>;
  139. #gpio-cells = <2>;
  140. gpio-controller;
  141. interrupt-controller;
  142. #interrupt-cells = <2>;
  143. };
  144. pioB: gpio@fffff400 {
  145. compatible = "atmel,at91rm9200-gpio";
  146. reg = <0xfffff400 0x200>;
  147. interrupts = <3 4 1>;
  148. #gpio-cells = <2>;
  149. gpio-controller;
  150. interrupt-controller;
  151. #interrupt-cells = <2>;
  152. };
  153. pioC: gpio@fffff600 {
  154. compatible = "atmel,at91rm9200-gpio";
  155. reg = <0xfffff600 0x200>;
  156. interrupts = <4 4 1>;
  157. #gpio-cells = <2>;
  158. gpio-controller;
  159. interrupt-controller;
  160. #interrupt-cells = <2>;
  161. };
  162. pioD: gpio@fffff800 {
  163. compatible = "atmel,at91rm9200-gpio";
  164. reg = <0xfffff800 0x200>;
  165. interrupts = <4 4 1>;
  166. #gpio-cells = <2>;
  167. gpio-controller;
  168. interrupt-controller;
  169. #interrupt-cells = <2>;
  170. };
  171. pioE: gpio@fffffa00 {
  172. compatible = "atmel,at91rm9200-gpio";
  173. reg = <0xfffffa00 0x200>;
  174. interrupts = <4 4 1>;
  175. #gpio-cells = <2>;
  176. gpio-controller;
  177. interrupt-controller;
  178. #interrupt-cells = <2>;
  179. };
  180. };
  181. dbgu: serial@ffffee00 {
  182. compatible = "atmel,at91sam9260-usart";
  183. reg = <0xffffee00 0x200>;
  184. interrupts = <1 4 7>;
  185. pinctrl-names = "default";
  186. pinctrl-0 = <&pinctrl_dbgu>;
  187. status = "disabled";
  188. };
  189. usart0: serial@fff8c000 {
  190. compatible = "atmel,at91sam9260-usart";
  191. reg = <0xfff8c000 0x200>;
  192. interrupts = <7 4 5>;
  193. atmel,use-dma-rx;
  194. atmel,use-dma-tx;
  195. pinctrl-names = "default";
  196. pinctrl-0 = <&pinctrl_uart0>;
  197. status = "disabled";
  198. };
  199. usart1: serial@fff90000 {
  200. compatible = "atmel,at91sam9260-usart";
  201. reg = <0xfff90000 0x200>;
  202. interrupts = <8 4 5>;
  203. atmel,use-dma-rx;
  204. atmel,use-dma-tx;
  205. pinctrl-names = "default";
  206. pinctrl-0 = <&pinctrl_uart1>;
  207. status = "disabled";
  208. };
  209. usart2: serial@fff94000 {
  210. compatible = "atmel,at91sam9260-usart";
  211. reg = <0xfff94000 0x200>;
  212. interrupts = <9 4 5>;
  213. atmel,use-dma-rx;
  214. atmel,use-dma-tx;
  215. pinctrl-names = "default";
  216. pinctrl-0 = <&pinctrl_uart2>;
  217. status = "disabled";
  218. };
  219. macb0: ethernet@fffbc000 {
  220. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  221. reg = <0xfffbc000 0x100>;
  222. interrupts = <21 4 3>;
  223. status = "disabled";
  224. };
  225. usb1: gadget@fff78000 {
  226. compatible = "atmel,at91rm9200-udc";
  227. reg = <0xfff78000 0x4000>;
  228. interrupts = <24 4 2>;
  229. status = "disabled";
  230. };
  231. i2c0: i2c@fff88000 {
  232. compatible = "atmel,at91sam9263-i2c";
  233. reg = <0xfff88000 0x100>;
  234. interrupts = <13 4 6>;
  235. #address-cells = <1>;
  236. #size-cells = <0>;
  237. status = "disabled";
  238. };
  239. };
  240. nand0: nand@40000000 {
  241. compatible = "atmel,at91rm9200-nand";
  242. #address-cells = <1>;
  243. #size-cells = <1>;
  244. reg = <0x40000000 0x10000000
  245. 0xffffe000 0x200
  246. >;
  247. atmel,nand-addr-offset = <21>;
  248. atmel,nand-cmd-offset = <22>;
  249. gpios = <&pioA 22 0
  250. &pioD 15 0
  251. 0
  252. >;
  253. status = "disabled";
  254. };
  255. usb0: ohci@00a00000 {
  256. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  257. reg = <0x00a00000 0x100000>;
  258. interrupts = <29 4 2>;
  259. status = "disabled";
  260. };
  261. };
  262. i2c@0 {
  263. compatible = "i2c-gpio";
  264. gpios = <&pioB 4 0 /* sda */
  265. &pioB 5 0 /* scl */
  266. >;
  267. i2c-gpio,sda-open-drain;
  268. i2c-gpio,scl-open-drain;
  269. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. status = "disabled";
  273. };
  274. };