Kconfig 9.6 KB

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  1. #
  2. # Processor families
  3. #
  4. config CPU_SH2
  5. select SH_WRITETHROUGH if !CPU_SH2A
  6. bool
  7. config CPU_SH2A
  8. bool
  9. select CPU_SH2
  10. config CPU_SH3
  11. bool
  12. select CPU_HAS_INTEVT
  13. select CPU_HAS_SR_RB
  14. config CPU_SH4
  15. bool
  16. select CPU_HAS_INTEVT
  17. select CPU_HAS_SR_RB
  18. select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
  19. config CPU_SH4A
  20. bool
  21. select CPU_SH4
  22. config CPU_SH4AL_DSP
  23. bool
  24. select CPU_SH4A
  25. select CPU_HAS_DSP
  26. config CPU_SUBTYPE_ST40
  27. bool
  28. select CPU_SH4
  29. select CPU_HAS_INTC2_IRQ
  30. config CPU_SHX2
  31. bool
  32. config CPU_SHX3
  33. bool
  34. choice
  35. prompt "Processor sub-type selection"
  36. #
  37. # Processor subtypes
  38. #
  39. # SH-2 Processor Support
  40. config CPU_SUBTYPE_SH7619
  41. bool "Support SH7619 processor"
  42. select CPU_SH2
  43. select CPU_HAS_IPR_IRQ
  44. # SH-2A Processor Support
  45. config CPU_SUBTYPE_SH7206
  46. bool "Support SH7206 processor"
  47. select CPU_SH2A
  48. select CPU_HAS_IPR_IRQ
  49. # SH-3 Processor Support
  50. config CPU_SUBTYPE_SH7705
  51. bool "Support SH7705 processor"
  52. select CPU_SH3
  53. select CPU_HAS_INTC_IRQ
  54. config CPU_SUBTYPE_SH7706
  55. bool "Support SH7706 processor"
  56. select CPU_SH3
  57. select CPU_HAS_INTC_IRQ
  58. help
  59. Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
  60. config CPU_SUBTYPE_SH7707
  61. bool "Support SH7707 processor"
  62. select CPU_SH3
  63. select CPU_HAS_INTC_IRQ
  64. help
  65. Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
  66. config CPU_SUBTYPE_SH7708
  67. bool "Support SH7708 processor"
  68. select CPU_SH3
  69. select CPU_HAS_INTC_IRQ
  70. help
  71. Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
  72. if you have a 100 Mhz SH-3 HD6417708R CPU.
  73. config CPU_SUBTYPE_SH7709
  74. bool "Support SH7709 processor"
  75. select CPU_SH3
  76. select CPU_HAS_INTC_IRQ
  77. help
  78. Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
  79. config CPU_SUBTYPE_SH7710
  80. bool "Support SH7710 processor"
  81. select CPU_SH3
  82. select CPU_HAS_INTC_IRQ
  83. select CPU_HAS_DSP
  84. help
  85. Select SH7710 if you have a SH3-DSP SH7710 CPU.
  86. config CPU_SUBTYPE_SH7712
  87. bool "Support SH7712 processor"
  88. select CPU_SH3
  89. select CPU_HAS_INTC_IRQ
  90. select CPU_HAS_DSP
  91. help
  92. Select SH7712 if you have a SH3-DSP SH7712 CPU.
  93. # SH-4 Processor Support
  94. config CPU_SUBTYPE_SH7750
  95. bool "Support SH7750 processor"
  96. select CPU_SH4
  97. select CPU_HAS_INTC_IRQ
  98. help
  99. Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
  100. config CPU_SUBTYPE_SH7091
  101. bool "Support SH7091 processor"
  102. select CPU_SH4
  103. select CPU_HAS_INTC_IRQ
  104. help
  105. Select SH7091 if you have an SH-4 based Sega device (such as
  106. the Dreamcast, Naomi, and Naomi 2).
  107. config CPU_SUBTYPE_SH7750R
  108. bool "Support SH7750R processor"
  109. select CPU_SH4
  110. select CPU_HAS_INTC_IRQ
  111. config CPU_SUBTYPE_SH7750S
  112. bool "Support SH7750S processor"
  113. select CPU_SH4
  114. select CPU_HAS_INTC_IRQ
  115. config CPU_SUBTYPE_SH7751
  116. bool "Support SH7751 processor"
  117. select CPU_SH4
  118. select CPU_HAS_INTC_IRQ
  119. help
  120. Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
  121. or if you have a HD6417751R CPU.
  122. config CPU_SUBTYPE_SH7751R
  123. bool "Support SH7751R processor"
  124. select CPU_SH4
  125. select CPU_HAS_INTC_IRQ
  126. config CPU_SUBTYPE_SH7760
  127. bool "Support SH7760 processor"
  128. select CPU_SH4
  129. select CPU_HAS_INTC2_IRQ
  130. select CPU_HAS_IPR_IRQ
  131. config CPU_SUBTYPE_SH4_202
  132. bool "Support SH4-202 processor"
  133. select CPU_SH4
  134. # ST40 Processor Support
  135. config CPU_SUBTYPE_ST40STB1
  136. bool "Support ST40STB1/ST40RA processors"
  137. select CPU_SUBTYPE_ST40
  138. help
  139. Select ST40STB1 if you have a ST40RA CPU.
  140. This was previously called the ST40STB1, hence the option name.
  141. config CPU_SUBTYPE_ST40GX1
  142. bool "Support ST40GX1 processor"
  143. select CPU_SUBTYPE_ST40
  144. help
  145. Select ST40GX1 if you have a ST40GX1 CPU.
  146. # SH-4A Processor Support
  147. config CPU_SUBTYPE_SH7770
  148. bool "Support SH7770 processor"
  149. select CPU_SH4A
  150. config CPU_SUBTYPE_SH7780
  151. bool "Support SH7780 processor"
  152. select CPU_SH4A
  153. select CPU_HAS_INTC_IRQ
  154. config CPU_SUBTYPE_SH7785
  155. bool "Support SH7785 processor"
  156. select CPU_SH4A
  157. select CPU_SHX2
  158. select CPU_HAS_INTC2_IRQ
  159. config CPU_SUBTYPE_SHX3
  160. bool "Support SH-X3 processor"
  161. select CPU_SH4A
  162. select CPU_SHX3
  163. select CPU_HAS_INTC2_IRQ
  164. # SH4AL-DSP Processor Support
  165. config CPU_SUBTYPE_SH7343
  166. bool "Support SH7343 processor"
  167. select CPU_SH4AL_DSP
  168. config CPU_SUBTYPE_SH7722
  169. bool "Support SH7722 processor"
  170. select CPU_SH4AL_DSP
  171. select CPU_SHX2
  172. select CPU_HAS_INTC_IRQ
  173. select ARCH_SPARSEMEM_ENABLE
  174. select SYS_SUPPORTS_NUMA
  175. endchoice
  176. menu "Memory management options"
  177. config QUICKLIST
  178. def_bool y
  179. config MMU
  180. bool "Support for memory management hardware"
  181. depends on !CPU_SH2
  182. default y
  183. help
  184. Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
  185. boot on these systems, this option must not be set.
  186. On other systems (such as the SH-3 and 4) where an MMU exists,
  187. turning this off will boot the kernel on these machines with the
  188. MMU implicitly switched off.
  189. config PAGE_OFFSET
  190. hex
  191. default "0x80000000" if MMU
  192. default "0x00000000"
  193. config MEMORY_START
  194. hex "Physical memory start address"
  195. default "0x08000000"
  196. ---help---
  197. Computers built with Hitachi SuperH processors always
  198. map the ROM starting at address zero. But the processor
  199. does not specify the range that RAM takes.
  200. The physical memory (RAM) start address will be automatically
  201. set to 08000000. Other platforms, such as the Solution Engine
  202. boards typically map RAM at 0C000000.
  203. Tweak this only when porting to a new machine which does not
  204. already have a defconfig. Changing it from the known correct
  205. value on any of the known systems will only lead to disaster.
  206. config MEMORY_SIZE
  207. hex "Physical memory size"
  208. default "0x00400000"
  209. help
  210. This sets the default memory size assumed by your SH kernel. It can
  211. be overridden as normal by the 'mem=' argument on the kernel command
  212. line. If unsure, consult your board specifications or just leave it
  213. as 0x00400000 which was the default value before this became
  214. configurable.
  215. config 32BIT
  216. bool "Support 32-bit physical addressing through PMB"
  217. depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
  218. default y
  219. help
  220. If you say Y here, physical addressing will be extended to
  221. 32-bits through the SH-4A PMB. If this is not set, legacy
  222. 29-bit physical addressing will be used.
  223. config X2TLB
  224. bool "Enable extended TLB mode"
  225. depends on CPU_SHX2 && MMU && EXPERIMENTAL
  226. help
  227. Selecting this option will enable the extended mode of the SH-X2
  228. TLB. For legacy SH-X behaviour and interoperability, say N. For
  229. all of the fun new features and a willingless to submit bug reports,
  230. say Y.
  231. config VSYSCALL
  232. bool "Support vsyscall page"
  233. depends on MMU
  234. default y
  235. help
  236. This will enable support for the kernel mapping a vDSO page
  237. in process space, and subsequently handing down the entry point
  238. to the libc through the ELF auxiliary vector.
  239. From the kernel side this is used for the signal trampoline.
  240. For systems with an MMU that can afford to give up a page,
  241. (the default value) say Y.
  242. config NUMA
  243. bool "Non Uniform Memory Access (NUMA) Support"
  244. depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
  245. default n
  246. help
  247. Some SH systems have many various memories scattered around
  248. the address space, each with varying latencies. This enables
  249. support for these blocks by binding them to nodes and allowing
  250. memory policies to be used for prioritizing and controlling
  251. allocation behaviour.
  252. config NODES_SHIFT
  253. int
  254. default "1"
  255. depends on NEED_MULTIPLE_NODES
  256. config ARCH_FLATMEM_ENABLE
  257. def_bool y
  258. depends on !NUMA
  259. config ARCH_SPARSEMEM_ENABLE
  260. def_bool y
  261. select SPARSEMEM_STATIC
  262. config ARCH_SPARSEMEM_DEFAULT
  263. def_bool y
  264. config MAX_ACTIVE_REGIONS
  265. int
  266. default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
  267. default "1"
  268. config ARCH_POPULATES_NODE_MAP
  269. def_bool y
  270. config ARCH_SELECT_MEMORY_MODEL
  271. def_bool y
  272. config ARCH_ENABLE_MEMORY_HOTPLUG
  273. def_bool y
  274. depends on SPARSEMEM
  275. config ARCH_MEMORY_PROBE
  276. def_bool y
  277. depends on MEMORY_HOTPLUG
  278. choice
  279. prompt "Kernel page size"
  280. default PAGE_SIZE_4KB
  281. config PAGE_SIZE_4KB
  282. bool "4kB"
  283. help
  284. This is the default page size used by all SuperH CPUs.
  285. config PAGE_SIZE_8KB
  286. bool "8kB"
  287. depends on EXPERIMENTAL && X2TLB
  288. help
  289. This enables 8kB pages as supported by SH-X2 and later MMUs.
  290. config PAGE_SIZE_64KB
  291. bool "64kB"
  292. depends on EXPERIMENTAL && CPU_SH4
  293. help
  294. This enables support for 64kB pages, possible on all SH-4
  295. CPUs and later. Highly experimental, not recommended.
  296. endchoice
  297. choice
  298. prompt "HugeTLB page size"
  299. depends on HUGETLB_PAGE && CPU_SH4 && MMU
  300. default HUGETLB_PAGE_SIZE_64K
  301. config HUGETLB_PAGE_SIZE_64K
  302. bool "64kB"
  303. config HUGETLB_PAGE_SIZE_256K
  304. bool "256kB"
  305. depends on X2TLB
  306. config HUGETLB_PAGE_SIZE_1MB
  307. bool "1MB"
  308. config HUGETLB_PAGE_SIZE_4MB
  309. bool "4MB"
  310. depends on X2TLB
  311. config HUGETLB_PAGE_SIZE_64MB
  312. bool "64MB"
  313. depends on X2TLB
  314. endchoice
  315. source "mm/Kconfig"
  316. endmenu
  317. menu "Cache configuration"
  318. config SH7705_CACHE_32KB
  319. bool "Enable 32KB cache size for SH7705"
  320. depends on CPU_SUBTYPE_SH7705
  321. default y
  322. config SH_DIRECT_MAPPED
  323. bool "Use direct-mapped caching"
  324. default n
  325. help
  326. Selecting this option will configure the caches to be direct-mapped,
  327. even if the cache supports a 2 or 4-way mode. This is useful primarily
  328. for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
  329. SH4-202, SH4-501, etc.)
  330. Turn this option off for platforms that do not have a direct-mapped
  331. cache, and you have no need to run the caches in such a configuration.
  332. config SH_WRITETHROUGH
  333. bool "Use write-through caching"
  334. help
  335. Selecting this option will configure the caches in write-through
  336. mode, as opposed to the default write-back configuration.
  337. Since there's sill some aliasing issues on SH-4, this option will
  338. unfortunately still require the majority of flushing functions to
  339. be implemented to deal with aliasing.
  340. If unsure, say N.
  341. endmenu