r600_cs.c 63 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/kernel.h>
  29. #include "drmP.h"
  30. #include "radeon.h"
  31. #include "r600d.h"
  32. #include "r600_reg_safe.h"
  33. static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  34. struct radeon_cs_reloc **cs_reloc);
  35. static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  36. struct radeon_cs_reloc **cs_reloc);
  37. typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
  38. static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
  39. extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
  40. struct r600_cs_track {
  41. /* configuration we miror so that we use same code btw kms/ums */
  42. u32 group_size;
  43. u32 nbanks;
  44. u32 npipes;
  45. /* value we track */
  46. u32 sq_config;
  47. u32 nsamples;
  48. u32 cb_color_base_last[8];
  49. struct radeon_bo *cb_color_bo[8];
  50. u64 cb_color_bo_mc[8];
  51. u32 cb_color_bo_offset[8];
  52. struct radeon_bo *cb_color_frag_bo[8];
  53. struct radeon_bo *cb_color_tile_bo[8];
  54. u32 cb_color_info[8];
  55. u32 cb_color_view[8];
  56. u32 cb_color_size_idx[8];
  57. u32 cb_target_mask;
  58. u32 cb_shader_mask;
  59. u32 cb_color_size[8];
  60. u32 vgt_strmout_en;
  61. u32 vgt_strmout_buffer_en;
  62. struct radeon_bo *vgt_strmout_bo[4];
  63. u64 vgt_strmout_bo_mc[4];
  64. u32 vgt_strmout_bo_offset[4];
  65. u32 vgt_strmout_size[4];
  66. u32 db_depth_control;
  67. u32 db_depth_info;
  68. u32 db_depth_size_idx;
  69. u32 db_depth_view;
  70. u32 db_depth_size;
  71. u32 db_offset;
  72. struct radeon_bo *db_bo;
  73. u64 db_bo_mc;
  74. };
  75. #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
  76. #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
  77. #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
  78. #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
  79. #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
  80. #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
  81. #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
  82. #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
  83. struct gpu_formats {
  84. unsigned blockwidth;
  85. unsigned blockheight;
  86. unsigned blocksize;
  87. unsigned valid_color;
  88. enum radeon_family min_family;
  89. };
  90. static const struct gpu_formats color_formats_table[] = {
  91. /* 8 bit */
  92. FMT_8_BIT(V_038004_COLOR_8, 1),
  93. FMT_8_BIT(V_038004_COLOR_4_4, 1),
  94. FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
  95. FMT_8_BIT(V_038004_FMT_1, 0),
  96. /* 16-bit */
  97. FMT_16_BIT(V_038004_COLOR_16, 1),
  98. FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
  99. FMT_16_BIT(V_038004_COLOR_8_8, 1),
  100. FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
  101. FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
  102. FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
  103. FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
  104. FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
  105. /* 24-bit */
  106. FMT_24_BIT(V_038004_FMT_8_8_8),
  107. /* 32-bit */
  108. FMT_32_BIT(V_038004_COLOR_32, 1),
  109. FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
  110. FMT_32_BIT(V_038004_COLOR_16_16, 1),
  111. FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
  112. FMT_32_BIT(V_038004_COLOR_8_24, 1),
  113. FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
  114. FMT_32_BIT(V_038004_COLOR_24_8, 1),
  115. FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
  116. FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
  117. FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
  118. FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
  119. FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
  120. FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
  121. FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
  122. FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
  123. FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
  124. FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
  125. FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
  126. /* 48-bit */
  127. FMT_48_BIT(V_038004_FMT_16_16_16),
  128. FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
  129. /* 64-bit */
  130. FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
  131. FMT_64_BIT(V_038004_COLOR_32_32, 1),
  132. FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
  133. FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
  134. FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
  135. FMT_96_BIT(V_038004_FMT_32_32_32),
  136. FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
  137. /* 128-bit */
  138. FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
  139. FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
  140. [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
  141. [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
  142. /* block compressed formats */
  143. [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
  144. [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
  145. [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
  146. [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
  147. [V_038004_FMT_BC5] = { 4, 4, 16, 0},
  148. [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
  149. [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
  150. /* The other Evergreen formats */
  151. [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
  152. };
  153. bool r600_fmt_is_valid_color(u32 format)
  154. {
  155. if (format >= ARRAY_SIZE(color_formats_table))
  156. return false;
  157. if (color_formats_table[format].valid_color)
  158. return true;
  159. return false;
  160. }
  161. bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
  162. {
  163. if (format >= ARRAY_SIZE(color_formats_table))
  164. return false;
  165. if (family < color_formats_table[format].min_family)
  166. return false;
  167. if (color_formats_table[format].blockwidth > 0)
  168. return true;
  169. return false;
  170. }
  171. int r600_fmt_get_blocksize(u32 format)
  172. {
  173. if (format >= ARRAY_SIZE(color_formats_table))
  174. return 0;
  175. return color_formats_table[format].blocksize;
  176. }
  177. int r600_fmt_get_nblocksx(u32 format, u32 w)
  178. {
  179. unsigned bw;
  180. if (format >= ARRAY_SIZE(color_formats_table))
  181. return 0;
  182. bw = color_formats_table[format].blockwidth;
  183. if (bw == 0)
  184. return 0;
  185. return (w + bw - 1) / bw;
  186. }
  187. int r600_fmt_get_nblocksy(u32 format, u32 h)
  188. {
  189. unsigned bh;
  190. if (format >= ARRAY_SIZE(color_formats_table))
  191. return 0;
  192. bh = color_formats_table[format].blockheight;
  193. if (bh == 0)
  194. return 0;
  195. return (h + bh - 1) / bh;
  196. }
  197. struct array_mode_checker {
  198. int array_mode;
  199. u32 group_size;
  200. u32 nbanks;
  201. u32 npipes;
  202. u32 nsamples;
  203. u32 blocksize;
  204. };
  205. /* returns alignment in pixels for pitch/height/depth and bytes for base */
  206. static int r600_get_array_mode_alignment(struct array_mode_checker *values,
  207. u32 *pitch_align,
  208. u32 *height_align,
  209. u32 *depth_align,
  210. u64 *base_align)
  211. {
  212. u32 tile_width = 8;
  213. u32 tile_height = 8;
  214. u32 macro_tile_width = values->nbanks;
  215. u32 macro_tile_height = values->npipes;
  216. u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
  217. u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
  218. switch (values->array_mode) {
  219. case ARRAY_LINEAR_GENERAL:
  220. /* technically tile_width/_height for pitch/height */
  221. *pitch_align = 1; /* tile_width */
  222. *height_align = 1; /* tile_height */
  223. *depth_align = 1;
  224. *base_align = 1;
  225. break;
  226. case ARRAY_LINEAR_ALIGNED:
  227. *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
  228. *height_align = 1;
  229. *depth_align = 1;
  230. *base_align = values->group_size;
  231. break;
  232. case ARRAY_1D_TILED_THIN1:
  233. *pitch_align = max((u32)tile_width,
  234. (u32)(values->group_size /
  235. (tile_height * values->blocksize * values->nsamples)));
  236. *height_align = tile_height;
  237. *depth_align = 1;
  238. *base_align = values->group_size;
  239. break;
  240. case ARRAY_2D_TILED_THIN1:
  241. *pitch_align = max((u32)macro_tile_width * tile_width,
  242. (u32)((values->group_size * values->nbanks) /
  243. (values->blocksize * values->nsamples * tile_width)));
  244. *height_align = macro_tile_height * tile_height;
  245. *depth_align = 1;
  246. *base_align = max(macro_tile_bytes,
  247. (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
  248. break;
  249. default:
  250. return -EINVAL;
  251. }
  252. return 0;
  253. }
  254. static void r600_cs_track_init(struct r600_cs_track *track)
  255. {
  256. int i;
  257. /* assume DX9 mode */
  258. track->sq_config = DX9_CONSTS;
  259. for (i = 0; i < 8; i++) {
  260. track->cb_color_base_last[i] = 0;
  261. track->cb_color_size[i] = 0;
  262. track->cb_color_size_idx[i] = 0;
  263. track->cb_color_info[i] = 0;
  264. track->cb_color_view[i] = 0xFFFFFFFF;
  265. track->cb_color_bo[i] = NULL;
  266. track->cb_color_bo_offset[i] = 0xFFFFFFFF;
  267. track->cb_color_bo_mc[i] = 0xFFFFFFFF;
  268. }
  269. track->cb_target_mask = 0xFFFFFFFF;
  270. track->cb_shader_mask = 0xFFFFFFFF;
  271. track->db_bo = NULL;
  272. track->db_bo_mc = 0xFFFFFFFF;
  273. /* assume the biggest format and that htile is enabled */
  274. track->db_depth_info = 7 | (1 << 25);
  275. track->db_depth_view = 0xFFFFC000;
  276. track->db_depth_size = 0xFFFFFFFF;
  277. track->db_depth_size_idx = 0;
  278. track->db_depth_control = 0xFFFFFFFF;
  279. for (i = 0; i < 4; i++) {
  280. track->vgt_strmout_size[i] = 0;
  281. track->vgt_strmout_bo[i] = NULL;
  282. track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
  283. track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
  284. }
  285. }
  286. static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
  287. {
  288. struct r600_cs_track *track = p->track;
  289. u32 slice_tile_max, size, tmp;
  290. u32 height, height_align, pitch, pitch_align, depth_align;
  291. u64 base_offset, base_align;
  292. struct array_mode_checker array_check;
  293. volatile u32 *ib = p->ib->ptr;
  294. unsigned array_mode;
  295. u32 format;
  296. if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
  297. dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
  298. return -EINVAL;
  299. }
  300. size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
  301. format = G_0280A0_FORMAT(track->cb_color_info[i]);
  302. if (!r600_fmt_is_valid_color(format)) {
  303. dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
  304. __func__, __LINE__, format,
  305. i, track->cb_color_info[i]);
  306. return -EINVAL;
  307. }
  308. /* pitch in pixels */
  309. pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
  310. slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
  311. slice_tile_max *= 64;
  312. height = slice_tile_max / pitch;
  313. if (height > 8192)
  314. height = 8192;
  315. array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
  316. base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
  317. array_check.array_mode = array_mode;
  318. array_check.group_size = track->group_size;
  319. array_check.nbanks = track->nbanks;
  320. array_check.npipes = track->npipes;
  321. array_check.nsamples = track->nsamples;
  322. array_check.blocksize = r600_fmt_get_blocksize(format);
  323. if (r600_get_array_mode_alignment(&array_check,
  324. &pitch_align, &height_align, &depth_align, &base_align)) {
  325. dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
  326. G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
  327. track->cb_color_info[i]);
  328. return -EINVAL;
  329. }
  330. switch (array_mode) {
  331. case V_0280A0_ARRAY_LINEAR_GENERAL:
  332. break;
  333. case V_0280A0_ARRAY_LINEAR_ALIGNED:
  334. break;
  335. case V_0280A0_ARRAY_1D_TILED_THIN1:
  336. /* avoid breaking userspace */
  337. if (height > 7)
  338. height &= ~0x7;
  339. break;
  340. case V_0280A0_ARRAY_2D_TILED_THIN1:
  341. break;
  342. default:
  343. dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
  344. G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
  345. track->cb_color_info[i]);
  346. return -EINVAL;
  347. }
  348. if (!IS_ALIGNED(pitch, pitch_align)) {
  349. dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
  350. __func__, __LINE__, pitch, pitch_align, array_mode);
  351. return -EINVAL;
  352. }
  353. if (!IS_ALIGNED(height, height_align)) {
  354. dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
  355. __func__, __LINE__, height, height_align, array_mode);
  356. return -EINVAL;
  357. }
  358. if (!IS_ALIGNED(base_offset, base_align)) {
  359. dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
  360. base_offset, base_align, array_mode);
  361. return -EINVAL;
  362. }
  363. /* check offset */
  364. tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format);
  365. switch (array_mode) {
  366. default:
  367. case V_0280A0_ARRAY_LINEAR_GENERAL:
  368. case V_0280A0_ARRAY_LINEAR_ALIGNED:
  369. tmp += track->cb_color_view[i] & 0xFF;
  370. break;
  371. case V_0280A0_ARRAY_1D_TILED_THIN1:
  372. case V_0280A0_ARRAY_2D_TILED_THIN1:
  373. tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
  374. break;
  375. }
  376. if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
  377. if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
  378. /* the initial DDX does bad things with the CB size occasionally */
  379. /* it rounds up height too far for slice tile max but the BO is smaller */
  380. /* r600c,g also seem to flush at bad times in some apps resulting in
  381. * bogus values here. So for linear just allow anything to avoid breaking
  382. * broken userspace.
  383. */
  384. } else {
  385. dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big (%d %d) (%d %d %d)\n",
  386. __func__, i, array_mode,
  387. track->cb_color_bo_offset[i], tmp,
  388. radeon_bo_size(track->cb_color_bo[i]),
  389. pitch, height, r600_fmt_get_nblocksx(format, pitch),
  390. r600_fmt_get_nblocksy(format, height),
  391. r600_fmt_get_blocksize(format));
  392. return -EINVAL;
  393. }
  394. }
  395. /* limit max tile */
  396. tmp = (height * pitch) >> 6;
  397. if (tmp < slice_tile_max)
  398. slice_tile_max = tmp;
  399. tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
  400. S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
  401. ib[track->cb_color_size_idx[i]] = tmp;
  402. return 0;
  403. }
  404. static int r600_cs_track_check(struct radeon_cs_parser *p)
  405. {
  406. struct r600_cs_track *track = p->track;
  407. u32 tmp;
  408. int r, i;
  409. volatile u32 *ib = p->ib->ptr;
  410. /* on legacy kernel we don't perform advanced check */
  411. if (p->rdev == NULL)
  412. return 0;
  413. /* check streamout */
  414. if (track->vgt_strmout_en) {
  415. for (i = 0; i < 4; i++) {
  416. if (track->vgt_strmout_buffer_en & (1 << i)) {
  417. if (track->vgt_strmout_bo[i]) {
  418. u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
  419. (u64)track->vgt_strmout_size[i];
  420. if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
  421. DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
  422. i, offset,
  423. radeon_bo_size(track->vgt_strmout_bo[i]));
  424. return -EINVAL;
  425. }
  426. } else {
  427. dev_warn(p->dev, "No buffer for streamout %d\n", i);
  428. return -EINVAL;
  429. }
  430. }
  431. }
  432. }
  433. /* check that we have a cb for each enabled target, we don't check
  434. * shader_mask because it seems mesa isn't always setting it :(
  435. */
  436. tmp = track->cb_target_mask;
  437. for (i = 0; i < 8; i++) {
  438. if ((tmp >> (i * 4)) & 0xF) {
  439. /* at least one component is enabled */
  440. if (track->cb_color_bo[i] == NULL) {
  441. dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
  442. __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
  443. return -EINVAL;
  444. }
  445. /* perform rewrite of CB_COLOR[0-7]_SIZE */
  446. r = r600_cs_track_validate_cb(p, i);
  447. if (r)
  448. return r;
  449. }
  450. }
  451. /* Check depth buffer */
  452. if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
  453. G_028800_Z_ENABLE(track->db_depth_control)) {
  454. u32 nviews, bpe, ntiles, size, slice_tile_max;
  455. u32 height, height_align, pitch, pitch_align, depth_align;
  456. u64 base_offset, base_align;
  457. struct array_mode_checker array_check;
  458. int array_mode;
  459. if (track->db_bo == NULL) {
  460. dev_warn(p->dev, "z/stencil with no depth buffer\n");
  461. return -EINVAL;
  462. }
  463. if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
  464. dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
  465. return -EINVAL;
  466. }
  467. switch (G_028010_FORMAT(track->db_depth_info)) {
  468. case V_028010_DEPTH_16:
  469. bpe = 2;
  470. break;
  471. case V_028010_DEPTH_X8_24:
  472. case V_028010_DEPTH_8_24:
  473. case V_028010_DEPTH_X8_24_FLOAT:
  474. case V_028010_DEPTH_8_24_FLOAT:
  475. case V_028010_DEPTH_32_FLOAT:
  476. bpe = 4;
  477. break;
  478. case V_028010_DEPTH_X24_8_32_FLOAT:
  479. bpe = 8;
  480. break;
  481. default:
  482. dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
  483. return -EINVAL;
  484. }
  485. if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
  486. if (!track->db_depth_size_idx) {
  487. dev_warn(p->dev, "z/stencil buffer size not set\n");
  488. return -EINVAL;
  489. }
  490. tmp = radeon_bo_size(track->db_bo) - track->db_offset;
  491. tmp = (tmp / bpe) >> 6;
  492. if (!tmp) {
  493. dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
  494. track->db_depth_size, bpe, track->db_offset,
  495. radeon_bo_size(track->db_bo));
  496. return -EINVAL;
  497. }
  498. ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
  499. } else {
  500. size = radeon_bo_size(track->db_bo);
  501. /* pitch in pixels */
  502. pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
  503. slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
  504. slice_tile_max *= 64;
  505. height = slice_tile_max / pitch;
  506. if (height > 8192)
  507. height = 8192;
  508. base_offset = track->db_bo_mc + track->db_offset;
  509. array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
  510. array_check.array_mode = array_mode;
  511. array_check.group_size = track->group_size;
  512. array_check.nbanks = track->nbanks;
  513. array_check.npipes = track->npipes;
  514. array_check.nsamples = track->nsamples;
  515. array_check.blocksize = bpe;
  516. if (r600_get_array_mode_alignment(&array_check,
  517. &pitch_align, &height_align, &depth_align, &base_align)) {
  518. dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
  519. G_028010_ARRAY_MODE(track->db_depth_info),
  520. track->db_depth_info);
  521. return -EINVAL;
  522. }
  523. switch (array_mode) {
  524. case V_028010_ARRAY_1D_TILED_THIN1:
  525. /* don't break userspace */
  526. height &= ~0x7;
  527. break;
  528. case V_028010_ARRAY_2D_TILED_THIN1:
  529. break;
  530. default:
  531. dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
  532. G_028010_ARRAY_MODE(track->db_depth_info),
  533. track->db_depth_info);
  534. return -EINVAL;
  535. }
  536. if (!IS_ALIGNED(pitch, pitch_align)) {
  537. dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
  538. __func__, __LINE__, pitch, pitch_align, array_mode);
  539. return -EINVAL;
  540. }
  541. if (!IS_ALIGNED(height, height_align)) {
  542. dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
  543. __func__, __LINE__, height, height_align, array_mode);
  544. return -EINVAL;
  545. }
  546. if (!IS_ALIGNED(base_offset, base_align)) {
  547. dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i,
  548. base_offset, base_align, array_mode);
  549. return -EINVAL;
  550. }
  551. ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
  552. nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
  553. tmp = ntiles * bpe * 64 * nviews;
  554. if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
  555. dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
  556. array_mode,
  557. track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
  558. radeon_bo_size(track->db_bo));
  559. return -EINVAL;
  560. }
  561. }
  562. }
  563. return 0;
  564. }
  565. /**
  566. * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
  567. * @parser: parser structure holding parsing context.
  568. * @pkt: where to store packet informations
  569. *
  570. * Assume that chunk_ib_index is properly set. Will return -EINVAL
  571. * if packet is bigger than remaining ib size. or if packets is unknown.
  572. **/
  573. int r600_cs_packet_parse(struct radeon_cs_parser *p,
  574. struct radeon_cs_packet *pkt,
  575. unsigned idx)
  576. {
  577. struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
  578. uint32_t header;
  579. if (idx >= ib_chunk->length_dw) {
  580. DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
  581. idx, ib_chunk->length_dw);
  582. return -EINVAL;
  583. }
  584. header = radeon_get_ib_value(p, idx);
  585. pkt->idx = idx;
  586. pkt->type = CP_PACKET_GET_TYPE(header);
  587. pkt->count = CP_PACKET_GET_COUNT(header);
  588. pkt->one_reg_wr = 0;
  589. switch (pkt->type) {
  590. case PACKET_TYPE0:
  591. pkt->reg = CP_PACKET0_GET_REG(header);
  592. break;
  593. case PACKET_TYPE3:
  594. pkt->opcode = CP_PACKET3_GET_OPCODE(header);
  595. break;
  596. case PACKET_TYPE2:
  597. pkt->count = -1;
  598. break;
  599. default:
  600. DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
  601. return -EINVAL;
  602. }
  603. if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
  604. DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
  605. pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
  606. return -EINVAL;
  607. }
  608. return 0;
  609. }
  610. /**
  611. * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
  612. * @parser: parser structure holding parsing context.
  613. * @data: pointer to relocation data
  614. * @offset_start: starting offset
  615. * @offset_mask: offset mask (to align start offset on)
  616. * @reloc: reloc informations
  617. *
  618. * Check next packet is relocation packet3, do bo validation and compute
  619. * GPU offset using the provided start.
  620. **/
  621. static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  622. struct radeon_cs_reloc **cs_reloc)
  623. {
  624. struct radeon_cs_chunk *relocs_chunk;
  625. struct radeon_cs_packet p3reloc;
  626. unsigned idx;
  627. int r;
  628. if (p->chunk_relocs_idx == -1) {
  629. DRM_ERROR("No relocation chunk !\n");
  630. return -EINVAL;
  631. }
  632. *cs_reloc = NULL;
  633. relocs_chunk = &p->chunks[p->chunk_relocs_idx];
  634. r = r600_cs_packet_parse(p, &p3reloc, p->idx);
  635. if (r) {
  636. return r;
  637. }
  638. p->idx += p3reloc.count + 2;
  639. if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
  640. DRM_ERROR("No packet3 for relocation for packet at %d.\n",
  641. p3reloc.idx);
  642. return -EINVAL;
  643. }
  644. idx = radeon_get_ib_value(p, p3reloc.idx + 1);
  645. if (idx >= relocs_chunk->length_dw) {
  646. DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
  647. idx, relocs_chunk->length_dw);
  648. return -EINVAL;
  649. }
  650. /* FIXME: we assume reloc size is 4 dwords */
  651. *cs_reloc = p->relocs_ptr[(idx / 4)];
  652. return 0;
  653. }
  654. /**
  655. * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
  656. * @parser: parser structure holding parsing context.
  657. * @data: pointer to relocation data
  658. * @offset_start: starting offset
  659. * @offset_mask: offset mask (to align start offset on)
  660. * @reloc: reloc informations
  661. *
  662. * Check next packet is relocation packet3, do bo validation and compute
  663. * GPU offset using the provided start.
  664. **/
  665. static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  666. struct radeon_cs_reloc **cs_reloc)
  667. {
  668. struct radeon_cs_chunk *relocs_chunk;
  669. struct radeon_cs_packet p3reloc;
  670. unsigned idx;
  671. int r;
  672. if (p->chunk_relocs_idx == -1) {
  673. DRM_ERROR("No relocation chunk !\n");
  674. return -EINVAL;
  675. }
  676. *cs_reloc = NULL;
  677. relocs_chunk = &p->chunks[p->chunk_relocs_idx];
  678. r = r600_cs_packet_parse(p, &p3reloc, p->idx);
  679. if (r) {
  680. return r;
  681. }
  682. p->idx += p3reloc.count + 2;
  683. if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
  684. DRM_ERROR("No packet3 for relocation for packet at %d.\n",
  685. p3reloc.idx);
  686. return -EINVAL;
  687. }
  688. idx = radeon_get_ib_value(p, p3reloc.idx + 1);
  689. if (idx >= relocs_chunk->length_dw) {
  690. DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
  691. idx, relocs_chunk->length_dw);
  692. return -EINVAL;
  693. }
  694. *cs_reloc = p->relocs;
  695. (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
  696. (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
  697. return 0;
  698. }
  699. /**
  700. * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
  701. * @parser: parser structure holding parsing context.
  702. *
  703. * Check next packet is relocation packet3, do bo validation and compute
  704. * GPU offset using the provided start.
  705. **/
  706. static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
  707. {
  708. struct radeon_cs_packet p3reloc;
  709. int r;
  710. r = r600_cs_packet_parse(p, &p3reloc, p->idx);
  711. if (r) {
  712. return 0;
  713. }
  714. if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
  715. return 0;
  716. }
  717. return 1;
  718. }
  719. /**
  720. * r600_cs_packet_next_vline() - parse userspace VLINE packet
  721. * @parser: parser structure holding parsing context.
  722. *
  723. * Userspace sends a special sequence for VLINE waits.
  724. * PACKET0 - VLINE_START_END + value
  725. * PACKET3 - WAIT_REG_MEM poll vline status reg
  726. * RELOC (P3) - crtc_id in reloc.
  727. *
  728. * This function parses this and relocates the VLINE START END
  729. * and WAIT_REG_MEM packets to the correct crtc.
  730. * It also detects a switched off crtc and nulls out the
  731. * wait in that case.
  732. */
  733. static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
  734. {
  735. struct drm_mode_object *obj;
  736. struct drm_crtc *crtc;
  737. struct radeon_crtc *radeon_crtc;
  738. struct radeon_cs_packet p3reloc, wait_reg_mem;
  739. int crtc_id;
  740. int r;
  741. uint32_t header, h_idx, reg, wait_reg_mem_info;
  742. volatile uint32_t *ib;
  743. ib = p->ib->ptr;
  744. /* parse the WAIT_REG_MEM */
  745. r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
  746. if (r)
  747. return r;
  748. /* check its a WAIT_REG_MEM */
  749. if (wait_reg_mem.type != PACKET_TYPE3 ||
  750. wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
  751. DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
  752. return -EINVAL;
  753. }
  754. wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
  755. /* bit 4 is reg (0) or mem (1) */
  756. if (wait_reg_mem_info & 0x10) {
  757. DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
  758. return -EINVAL;
  759. }
  760. /* waiting for value to be equal */
  761. if ((wait_reg_mem_info & 0x7) != 0x3) {
  762. DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
  763. return -EINVAL;
  764. }
  765. if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
  766. DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
  767. return -EINVAL;
  768. }
  769. if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
  770. DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
  771. return -EINVAL;
  772. }
  773. /* jump over the NOP */
  774. r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
  775. if (r)
  776. return r;
  777. h_idx = p->idx - 2;
  778. p->idx += wait_reg_mem.count + 2;
  779. p->idx += p3reloc.count + 2;
  780. header = radeon_get_ib_value(p, h_idx);
  781. crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
  782. reg = CP_PACKET0_GET_REG(header);
  783. obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
  784. if (!obj) {
  785. DRM_ERROR("cannot find crtc %d\n", crtc_id);
  786. return -EINVAL;
  787. }
  788. crtc = obj_to_crtc(obj);
  789. radeon_crtc = to_radeon_crtc(crtc);
  790. crtc_id = radeon_crtc->crtc_id;
  791. if (!crtc->enabled) {
  792. /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
  793. ib[h_idx + 2] = PACKET2(0);
  794. ib[h_idx + 3] = PACKET2(0);
  795. ib[h_idx + 4] = PACKET2(0);
  796. ib[h_idx + 5] = PACKET2(0);
  797. ib[h_idx + 6] = PACKET2(0);
  798. ib[h_idx + 7] = PACKET2(0);
  799. ib[h_idx + 8] = PACKET2(0);
  800. } else if (crtc_id == 1) {
  801. switch (reg) {
  802. case AVIVO_D1MODE_VLINE_START_END:
  803. header &= ~R600_CP_PACKET0_REG_MASK;
  804. header |= AVIVO_D2MODE_VLINE_START_END >> 2;
  805. break;
  806. default:
  807. DRM_ERROR("unknown crtc reloc\n");
  808. return -EINVAL;
  809. }
  810. ib[h_idx] = header;
  811. ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
  812. }
  813. return 0;
  814. }
  815. static int r600_packet0_check(struct radeon_cs_parser *p,
  816. struct radeon_cs_packet *pkt,
  817. unsigned idx, unsigned reg)
  818. {
  819. int r;
  820. switch (reg) {
  821. case AVIVO_D1MODE_VLINE_START_END:
  822. r = r600_cs_packet_parse_vline(p);
  823. if (r) {
  824. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  825. idx, reg);
  826. return r;
  827. }
  828. break;
  829. default:
  830. printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
  831. reg, idx);
  832. return -EINVAL;
  833. }
  834. return 0;
  835. }
  836. static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
  837. struct radeon_cs_packet *pkt)
  838. {
  839. unsigned reg, i;
  840. unsigned idx;
  841. int r;
  842. idx = pkt->idx + 1;
  843. reg = pkt->reg;
  844. for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
  845. r = r600_packet0_check(p, pkt, idx, reg);
  846. if (r) {
  847. return r;
  848. }
  849. }
  850. return 0;
  851. }
  852. /**
  853. * r600_cs_check_reg() - check if register is authorized or not
  854. * @parser: parser structure holding parsing context
  855. * @reg: register we are testing
  856. * @idx: index into the cs buffer
  857. *
  858. * This function will test against r600_reg_safe_bm and return 0
  859. * if register is safe. If register is not flag as safe this function
  860. * will test it against a list of register needind special handling.
  861. */
  862. static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
  863. {
  864. struct r600_cs_track *track = (struct r600_cs_track *)p->track;
  865. struct radeon_cs_reloc *reloc;
  866. u32 m, i, tmp, *ib;
  867. int r;
  868. i = (reg >> 7);
  869. if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
  870. dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
  871. return -EINVAL;
  872. }
  873. m = 1 << ((reg >> 2) & 31);
  874. if (!(r600_reg_safe_bm[i] & m))
  875. return 0;
  876. ib = p->ib->ptr;
  877. switch (reg) {
  878. /* force following reg to 0 in an attempt to disable out buffer
  879. * which will need us to better understand how it works to perform
  880. * security check on it (Jerome)
  881. */
  882. case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
  883. case R_008C44_SQ_ESGS_RING_SIZE:
  884. case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
  885. case R_008C54_SQ_ESTMP_RING_SIZE:
  886. case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
  887. case R_008C74_SQ_FBUF_RING_SIZE:
  888. case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
  889. case R_008C5C_SQ_GSTMP_RING_SIZE:
  890. case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
  891. case R_008C4C_SQ_GSVS_RING_SIZE:
  892. case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
  893. case R_008C6C_SQ_PSTMP_RING_SIZE:
  894. case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
  895. case R_008C7C_SQ_REDUC_RING_SIZE:
  896. case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
  897. case R_008C64_SQ_VSTMP_RING_SIZE:
  898. case R_0288C8_SQ_GS_VERT_ITEMSIZE:
  899. /* get value to populate the IB don't remove */
  900. tmp =radeon_get_ib_value(p, idx);
  901. ib[idx] = 0;
  902. break;
  903. case SQ_CONFIG:
  904. track->sq_config = radeon_get_ib_value(p, idx);
  905. break;
  906. case R_028800_DB_DEPTH_CONTROL:
  907. track->db_depth_control = radeon_get_ib_value(p, idx);
  908. break;
  909. case R_028010_DB_DEPTH_INFO:
  910. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
  911. r600_cs_packet_next_is_pkt3_nop(p)) {
  912. r = r600_cs_packet_next_reloc(p, &reloc);
  913. if (r) {
  914. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  915. "0x%04X\n", reg);
  916. return -EINVAL;
  917. }
  918. track->db_depth_info = radeon_get_ib_value(p, idx);
  919. ib[idx] &= C_028010_ARRAY_MODE;
  920. track->db_depth_info &= C_028010_ARRAY_MODE;
  921. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
  922. ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
  923. track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
  924. } else {
  925. ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
  926. track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
  927. }
  928. } else
  929. track->db_depth_info = radeon_get_ib_value(p, idx);
  930. break;
  931. case R_028004_DB_DEPTH_VIEW:
  932. track->db_depth_view = radeon_get_ib_value(p, idx);
  933. break;
  934. case R_028000_DB_DEPTH_SIZE:
  935. track->db_depth_size = radeon_get_ib_value(p, idx);
  936. track->db_depth_size_idx = idx;
  937. break;
  938. case R_028AB0_VGT_STRMOUT_EN:
  939. track->vgt_strmout_en = radeon_get_ib_value(p, idx);
  940. break;
  941. case R_028B20_VGT_STRMOUT_BUFFER_EN:
  942. track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
  943. break;
  944. case VGT_STRMOUT_BUFFER_BASE_0:
  945. case VGT_STRMOUT_BUFFER_BASE_1:
  946. case VGT_STRMOUT_BUFFER_BASE_2:
  947. case VGT_STRMOUT_BUFFER_BASE_3:
  948. r = r600_cs_packet_next_reloc(p, &reloc);
  949. if (r) {
  950. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  951. "0x%04X\n", reg);
  952. return -EINVAL;
  953. }
  954. tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
  955. track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
  956. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  957. track->vgt_strmout_bo[tmp] = reloc->robj;
  958. track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
  959. break;
  960. case VGT_STRMOUT_BUFFER_SIZE_0:
  961. case VGT_STRMOUT_BUFFER_SIZE_1:
  962. case VGT_STRMOUT_BUFFER_SIZE_2:
  963. case VGT_STRMOUT_BUFFER_SIZE_3:
  964. tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
  965. /* size in register is DWs, convert to bytes */
  966. track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
  967. break;
  968. case CP_COHER_BASE:
  969. r = r600_cs_packet_next_reloc(p, &reloc);
  970. if (r) {
  971. dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
  972. "0x%04X\n", reg);
  973. return -EINVAL;
  974. }
  975. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  976. break;
  977. case R_028238_CB_TARGET_MASK:
  978. track->cb_target_mask = radeon_get_ib_value(p, idx);
  979. break;
  980. case R_02823C_CB_SHADER_MASK:
  981. track->cb_shader_mask = radeon_get_ib_value(p, idx);
  982. break;
  983. case R_028C04_PA_SC_AA_CONFIG:
  984. tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
  985. track->nsamples = 1 << tmp;
  986. break;
  987. case R_0280A0_CB_COLOR0_INFO:
  988. case R_0280A4_CB_COLOR1_INFO:
  989. case R_0280A8_CB_COLOR2_INFO:
  990. case R_0280AC_CB_COLOR3_INFO:
  991. case R_0280B0_CB_COLOR4_INFO:
  992. case R_0280B4_CB_COLOR5_INFO:
  993. case R_0280B8_CB_COLOR6_INFO:
  994. case R_0280BC_CB_COLOR7_INFO:
  995. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
  996. r600_cs_packet_next_is_pkt3_nop(p)) {
  997. r = r600_cs_packet_next_reloc(p, &reloc);
  998. if (r) {
  999. dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
  1000. return -EINVAL;
  1001. }
  1002. tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
  1003. track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
  1004. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
  1005. ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
  1006. track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
  1007. } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
  1008. ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
  1009. track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
  1010. }
  1011. } else {
  1012. tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
  1013. track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
  1014. }
  1015. break;
  1016. case R_028080_CB_COLOR0_VIEW:
  1017. case R_028084_CB_COLOR1_VIEW:
  1018. case R_028088_CB_COLOR2_VIEW:
  1019. case R_02808C_CB_COLOR3_VIEW:
  1020. case R_028090_CB_COLOR4_VIEW:
  1021. case R_028094_CB_COLOR5_VIEW:
  1022. case R_028098_CB_COLOR6_VIEW:
  1023. case R_02809C_CB_COLOR7_VIEW:
  1024. tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
  1025. track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
  1026. break;
  1027. case R_028060_CB_COLOR0_SIZE:
  1028. case R_028064_CB_COLOR1_SIZE:
  1029. case R_028068_CB_COLOR2_SIZE:
  1030. case R_02806C_CB_COLOR3_SIZE:
  1031. case R_028070_CB_COLOR4_SIZE:
  1032. case R_028074_CB_COLOR5_SIZE:
  1033. case R_028078_CB_COLOR6_SIZE:
  1034. case R_02807C_CB_COLOR7_SIZE:
  1035. tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
  1036. track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
  1037. track->cb_color_size_idx[tmp] = idx;
  1038. break;
  1039. /* This register were added late, there is userspace
  1040. * which does provide relocation for those but set
  1041. * 0 offset. In order to avoid breaking old userspace
  1042. * we detect this and set address to point to last
  1043. * CB_COLOR0_BASE, note that if userspace doesn't set
  1044. * CB_COLOR0_BASE before this register we will report
  1045. * error. Old userspace always set CB_COLOR0_BASE
  1046. * before any of this.
  1047. */
  1048. case R_0280E0_CB_COLOR0_FRAG:
  1049. case R_0280E4_CB_COLOR1_FRAG:
  1050. case R_0280E8_CB_COLOR2_FRAG:
  1051. case R_0280EC_CB_COLOR3_FRAG:
  1052. case R_0280F0_CB_COLOR4_FRAG:
  1053. case R_0280F4_CB_COLOR5_FRAG:
  1054. case R_0280F8_CB_COLOR6_FRAG:
  1055. case R_0280FC_CB_COLOR7_FRAG:
  1056. tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
  1057. if (!r600_cs_packet_next_is_pkt3_nop(p)) {
  1058. if (!track->cb_color_base_last[tmp]) {
  1059. dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
  1060. return -EINVAL;
  1061. }
  1062. ib[idx] = track->cb_color_base_last[tmp];
  1063. track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
  1064. } else {
  1065. r = r600_cs_packet_next_reloc(p, &reloc);
  1066. if (r) {
  1067. dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
  1068. return -EINVAL;
  1069. }
  1070. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1071. track->cb_color_frag_bo[tmp] = reloc->robj;
  1072. }
  1073. break;
  1074. case R_0280C0_CB_COLOR0_TILE:
  1075. case R_0280C4_CB_COLOR1_TILE:
  1076. case R_0280C8_CB_COLOR2_TILE:
  1077. case R_0280CC_CB_COLOR3_TILE:
  1078. case R_0280D0_CB_COLOR4_TILE:
  1079. case R_0280D4_CB_COLOR5_TILE:
  1080. case R_0280D8_CB_COLOR6_TILE:
  1081. case R_0280DC_CB_COLOR7_TILE:
  1082. tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
  1083. if (!r600_cs_packet_next_is_pkt3_nop(p)) {
  1084. if (!track->cb_color_base_last[tmp]) {
  1085. dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
  1086. return -EINVAL;
  1087. }
  1088. ib[idx] = track->cb_color_base_last[tmp];
  1089. track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
  1090. } else {
  1091. r = r600_cs_packet_next_reloc(p, &reloc);
  1092. if (r) {
  1093. dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
  1094. return -EINVAL;
  1095. }
  1096. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1097. track->cb_color_tile_bo[tmp] = reloc->robj;
  1098. }
  1099. break;
  1100. case CB_COLOR0_BASE:
  1101. case CB_COLOR1_BASE:
  1102. case CB_COLOR2_BASE:
  1103. case CB_COLOR3_BASE:
  1104. case CB_COLOR4_BASE:
  1105. case CB_COLOR5_BASE:
  1106. case CB_COLOR6_BASE:
  1107. case CB_COLOR7_BASE:
  1108. r = r600_cs_packet_next_reloc(p, &reloc);
  1109. if (r) {
  1110. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1111. "0x%04X\n", reg);
  1112. return -EINVAL;
  1113. }
  1114. tmp = (reg - CB_COLOR0_BASE) / 4;
  1115. track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
  1116. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1117. track->cb_color_base_last[tmp] = ib[idx];
  1118. track->cb_color_bo[tmp] = reloc->robj;
  1119. track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
  1120. break;
  1121. case DB_DEPTH_BASE:
  1122. r = r600_cs_packet_next_reloc(p, &reloc);
  1123. if (r) {
  1124. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1125. "0x%04X\n", reg);
  1126. return -EINVAL;
  1127. }
  1128. track->db_offset = radeon_get_ib_value(p, idx) << 8;
  1129. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1130. track->db_bo = reloc->robj;
  1131. track->db_bo_mc = reloc->lobj.gpu_offset;
  1132. break;
  1133. case DB_HTILE_DATA_BASE:
  1134. case SQ_PGM_START_FS:
  1135. case SQ_PGM_START_ES:
  1136. case SQ_PGM_START_VS:
  1137. case SQ_PGM_START_GS:
  1138. case SQ_PGM_START_PS:
  1139. case SQ_ALU_CONST_CACHE_GS_0:
  1140. case SQ_ALU_CONST_CACHE_GS_1:
  1141. case SQ_ALU_CONST_CACHE_GS_2:
  1142. case SQ_ALU_CONST_CACHE_GS_3:
  1143. case SQ_ALU_CONST_CACHE_GS_4:
  1144. case SQ_ALU_CONST_CACHE_GS_5:
  1145. case SQ_ALU_CONST_CACHE_GS_6:
  1146. case SQ_ALU_CONST_CACHE_GS_7:
  1147. case SQ_ALU_CONST_CACHE_GS_8:
  1148. case SQ_ALU_CONST_CACHE_GS_9:
  1149. case SQ_ALU_CONST_CACHE_GS_10:
  1150. case SQ_ALU_CONST_CACHE_GS_11:
  1151. case SQ_ALU_CONST_CACHE_GS_12:
  1152. case SQ_ALU_CONST_CACHE_GS_13:
  1153. case SQ_ALU_CONST_CACHE_GS_14:
  1154. case SQ_ALU_CONST_CACHE_GS_15:
  1155. case SQ_ALU_CONST_CACHE_PS_0:
  1156. case SQ_ALU_CONST_CACHE_PS_1:
  1157. case SQ_ALU_CONST_CACHE_PS_2:
  1158. case SQ_ALU_CONST_CACHE_PS_3:
  1159. case SQ_ALU_CONST_CACHE_PS_4:
  1160. case SQ_ALU_CONST_CACHE_PS_5:
  1161. case SQ_ALU_CONST_CACHE_PS_6:
  1162. case SQ_ALU_CONST_CACHE_PS_7:
  1163. case SQ_ALU_CONST_CACHE_PS_8:
  1164. case SQ_ALU_CONST_CACHE_PS_9:
  1165. case SQ_ALU_CONST_CACHE_PS_10:
  1166. case SQ_ALU_CONST_CACHE_PS_11:
  1167. case SQ_ALU_CONST_CACHE_PS_12:
  1168. case SQ_ALU_CONST_CACHE_PS_13:
  1169. case SQ_ALU_CONST_CACHE_PS_14:
  1170. case SQ_ALU_CONST_CACHE_PS_15:
  1171. case SQ_ALU_CONST_CACHE_VS_0:
  1172. case SQ_ALU_CONST_CACHE_VS_1:
  1173. case SQ_ALU_CONST_CACHE_VS_2:
  1174. case SQ_ALU_CONST_CACHE_VS_3:
  1175. case SQ_ALU_CONST_CACHE_VS_4:
  1176. case SQ_ALU_CONST_CACHE_VS_5:
  1177. case SQ_ALU_CONST_CACHE_VS_6:
  1178. case SQ_ALU_CONST_CACHE_VS_7:
  1179. case SQ_ALU_CONST_CACHE_VS_8:
  1180. case SQ_ALU_CONST_CACHE_VS_9:
  1181. case SQ_ALU_CONST_CACHE_VS_10:
  1182. case SQ_ALU_CONST_CACHE_VS_11:
  1183. case SQ_ALU_CONST_CACHE_VS_12:
  1184. case SQ_ALU_CONST_CACHE_VS_13:
  1185. case SQ_ALU_CONST_CACHE_VS_14:
  1186. case SQ_ALU_CONST_CACHE_VS_15:
  1187. r = r600_cs_packet_next_reloc(p, &reloc);
  1188. if (r) {
  1189. dev_warn(p->dev, "bad SET_CONTEXT_REG "
  1190. "0x%04X\n", reg);
  1191. return -EINVAL;
  1192. }
  1193. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1194. break;
  1195. case SX_MEMORY_EXPORT_BASE:
  1196. r = r600_cs_packet_next_reloc(p, &reloc);
  1197. if (r) {
  1198. dev_warn(p->dev, "bad SET_CONFIG_REG "
  1199. "0x%04X\n", reg);
  1200. return -EINVAL;
  1201. }
  1202. ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1203. break;
  1204. default:
  1205. dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
  1206. return -EINVAL;
  1207. }
  1208. return 0;
  1209. }
  1210. unsigned r600_mip_minify(unsigned size, unsigned level)
  1211. {
  1212. unsigned val;
  1213. val = max(1U, size >> level);
  1214. if (level > 0)
  1215. val = roundup_pow_of_two(val);
  1216. return val;
  1217. }
  1218. static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
  1219. unsigned w0, unsigned h0, unsigned d0, unsigned format,
  1220. unsigned block_align, unsigned height_align, unsigned base_align,
  1221. unsigned *l0_size, unsigned *mipmap_size)
  1222. {
  1223. unsigned offset, i, level;
  1224. unsigned width, height, depth, size;
  1225. unsigned blocksize;
  1226. unsigned nbx, nby;
  1227. unsigned nlevels = llevel - blevel + 1;
  1228. *l0_size = -1;
  1229. blocksize = r600_fmt_get_blocksize(format);
  1230. w0 = r600_mip_minify(w0, 0);
  1231. h0 = r600_mip_minify(h0, 0);
  1232. d0 = r600_mip_minify(d0, 0);
  1233. for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
  1234. width = r600_mip_minify(w0, i);
  1235. nbx = r600_fmt_get_nblocksx(format, width);
  1236. nbx = round_up(nbx, block_align);
  1237. height = r600_mip_minify(h0, i);
  1238. nby = r600_fmt_get_nblocksy(format, height);
  1239. nby = round_up(nby, height_align);
  1240. depth = r600_mip_minify(d0, i);
  1241. size = nbx * nby * blocksize;
  1242. if (nfaces)
  1243. size *= nfaces;
  1244. else
  1245. size *= depth;
  1246. if (i == 0)
  1247. *l0_size = size;
  1248. if (i == 0 || i == 1)
  1249. offset = round_up(offset, base_align);
  1250. offset += size;
  1251. }
  1252. *mipmap_size = offset;
  1253. if (llevel == 0)
  1254. *mipmap_size = *l0_size;
  1255. if (!blevel)
  1256. *mipmap_size -= *l0_size;
  1257. }
  1258. /**
  1259. * r600_check_texture_resource() - check if register is authorized or not
  1260. * @p: parser structure holding parsing context
  1261. * @idx: index into the cs buffer
  1262. * @texture: texture's bo structure
  1263. * @mipmap: mipmap's bo structure
  1264. *
  1265. * This function will check that the resource has valid field and that
  1266. * the texture and mipmap bo object are big enough to cover this resource.
  1267. */
  1268. static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
  1269. struct radeon_bo *texture,
  1270. struct radeon_bo *mipmap,
  1271. u64 base_offset,
  1272. u64 mip_offset,
  1273. u32 tiling_flags)
  1274. {
  1275. struct r600_cs_track *track = p->track;
  1276. u32 nfaces, llevel, blevel, w0, h0, d0;
  1277. u32 word0, word1, l0_size, mipmap_size, word2, word3;
  1278. u32 height_align, pitch, pitch_align, depth_align;
  1279. u32 array, barray, larray;
  1280. u64 base_align;
  1281. struct array_mode_checker array_check;
  1282. u32 format;
  1283. /* on legacy kernel we don't perform advanced check */
  1284. if (p->rdev == NULL)
  1285. return 0;
  1286. /* convert to bytes */
  1287. base_offset <<= 8;
  1288. mip_offset <<= 8;
  1289. word0 = radeon_get_ib_value(p, idx + 0);
  1290. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1291. if (tiling_flags & RADEON_TILING_MACRO)
  1292. word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
  1293. else if (tiling_flags & RADEON_TILING_MICRO)
  1294. word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
  1295. }
  1296. word1 = radeon_get_ib_value(p, idx + 1);
  1297. w0 = G_038000_TEX_WIDTH(word0) + 1;
  1298. h0 = G_038004_TEX_HEIGHT(word1) + 1;
  1299. d0 = G_038004_TEX_DEPTH(word1);
  1300. nfaces = 1;
  1301. switch (G_038000_DIM(word0)) {
  1302. case V_038000_SQ_TEX_DIM_1D:
  1303. case V_038000_SQ_TEX_DIM_2D:
  1304. case V_038000_SQ_TEX_DIM_3D:
  1305. break;
  1306. case V_038000_SQ_TEX_DIM_CUBEMAP:
  1307. if (p->family >= CHIP_RV770)
  1308. nfaces = 8;
  1309. else
  1310. nfaces = 6;
  1311. break;
  1312. case V_038000_SQ_TEX_DIM_1D_ARRAY:
  1313. case V_038000_SQ_TEX_DIM_2D_ARRAY:
  1314. array = 1;
  1315. break;
  1316. case V_038000_SQ_TEX_DIM_2D_MSAA:
  1317. case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
  1318. default:
  1319. dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
  1320. return -EINVAL;
  1321. }
  1322. format = G_038004_DATA_FORMAT(word1);
  1323. if (!r600_fmt_is_valid_texture(format, p->family)) {
  1324. dev_warn(p->dev, "%s:%d texture invalid format %d\n",
  1325. __func__, __LINE__, format);
  1326. return -EINVAL;
  1327. }
  1328. /* pitch in texels */
  1329. pitch = (G_038000_PITCH(word0) + 1) * 8;
  1330. array_check.array_mode = G_038000_TILE_MODE(word0);
  1331. array_check.group_size = track->group_size;
  1332. array_check.nbanks = track->nbanks;
  1333. array_check.npipes = track->npipes;
  1334. array_check.nsamples = 1;
  1335. array_check.blocksize = r600_fmt_get_blocksize(format);
  1336. if (r600_get_array_mode_alignment(&array_check,
  1337. &pitch_align, &height_align, &depth_align, &base_align)) {
  1338. dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
  1339. __func__, __LINE__, G_038000_TILE_MODE(word0));
  1340. return -EINVAL;
  1341. }
  1342. /* XXX check height as well... */
  1343. if (!IS_ALIGNED(pitch, pitch_align)) {
  1344. dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
  1345. __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
  1346. return -EINVAL;
  1347. }
  1348. if (!IS_ALIGNED(base_offset, base_align)) {
  1349. dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
  1350. __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
  1351. return -EINVAL;
  1352. }
  1353. if (!IS_ALIGNED(mip_offset, base_align)) {
  1354. dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
  1355. __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
  1356. return -EINVAL;
  1357. }
  1358. word2 = radeon_get_ib_value(p, idx + 2) << 8;
  1359. word3 = radeon_get_ib_value(p, idx + 3) << 8;
  1360. word0 = radeon_get_ib_value(p, idx + 4);
  1361. word1 = radeon_get_ib_value(p, idx + 5);
  1362. blevel = G_038010_BASE_LEVEL(word0);
  1363. llevel = G_038014_LAST_LEVEL(word1);
  1364. if (blevel > llevel) {
  1365. dev_warn(p->dev, "texture blevel %d > llevel %d\n",
  1366. blevel, llevel);
  1367. }
  1368. if (array == 1) {
  1369. barray = G_038014_BASE_ARRAY(word1);
  1370. larray = G_038014_LAST_ARRAY(word1);
  1371. nfaces = larray - barray + 1;
  1372. }
  1373. r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
  1374. pitch_align, height_align, base_align,
  1375. &l0_size, &mipmap_size);
  1376. /* using get ib will give us the offset into the texture bo */
  1377. if ((l0_size + word2) > radeon_bo_size(texture)) {
  1378. dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
  1379. w0, h0, pitch_align, height_align,
  1380. array_check.array_mode, format, word2,
  1381. l0_size, radeon_bo_size(texture));
  1382. dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
  1383. return -EINVAL;
  1384. }
  1385. /* using get ib will give us the offset into the mipmap bo */
  1386. word3 = radeon_get_ib_value(p, idx + 3) << 8;
  1387. if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
  1388. /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
  1389. w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
  1390. }
  1391. return 0;
  1392. }
  1393. static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
  1394. {
  1395. u32 m, i;
  1396. i = (reg >> 7);
  1397. if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
  1398. dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
  1399. return false;
  1400. }
  1401. m = 1 << ((reg >> 2) & 31);
  1402. if (!(r600_reg_safe_bm[i] & m))
  1403. return true;
  1404. dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
  1405. return false;
  1406. }
  1407. static int r600_packet3_check(struct radeon_cs_parser *p,
  1408. struct radeon_cs_packet *pkt)
  1409. {
  1410. struct radeon_cs_reloc *reloc;
  1411. struct r600_cs_track *track;
  1412. volatile u32 *ib;
  1413. unsigned idx;
  1414. unsigned i;
  1415. unsigned start_reg, end_reg, reg;
  1416. int r;
  1417. u32 idx_value;
  1418. track = (struct r600_cs_track *)p->track;
  1419. ib = p->ib->ptr;
  1420. idx = pkt->idx + 1;
  1421. idx_value = radeon_get_ib_value(p, idx);
  1422. switch (pkt->opcode) {
  1423. case PACKET3_SET_PREDICATION:
  1424. {
  1425. int pred_op;
  1426. int tmp;
  1427. if (pkt->count != 1) {
  1428. DRM_ERROR("bad SET PREDICATION\n");
  1429. return -EINVAL;
  1430. }
  1431. tmp = radeon_get_ib_value(p, idx + 1);
  1432. pred_op = (tmp >> 16) & 0x7;
  1433. /* for the clear predicate operation */
  1434. if (pred_op == 0)
  1435. return 0;
  1436. if (pred_op > 2) {
  1437. DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
  1438. return -EINVAL;
  1439. }
  1440. r = r600_cs_packet_next_reloc(p, &reloc);
  1441. if (r) {
  1442. DRM_ERROR("bad SET PREDICATION\n");
  1443. return -EINVAL;
  1444. }
  1445. ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1446. ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
  1447. }
  1448. break;
  1449. case PACKET3_START_3D_CMDBUF:
  1450. if (p->family >= CHIP_RV770 || pkt->count) {
  1451. DRM_ERROR("bad START_3D\n");
  1452. return -EINVAL;
  1453. }
  1454. break;
  1455. case PACKET3_CONTEXT_CONTROL:
  1456. if (pkt->count != 1) {
  1457. DRM_ERROR("bad CONTEXT_CONTROL\n");
  1458. return -EINVAL;
  1459. }
  1460. break;
  1461. case PACKET3_INDEX_TYPE:
  1462. case PACKET3_NUM_INSTANCES:
  1463. if (pkt->count) {
  1464. DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
  1465. return -EINVAL;
  1466. }
  1467. break;
  1468. case PACKET3_DRAW_INDEX:
  1469. if (pkt->count != 3) {
  1470. DRM_ERROR("bad DRAW_INDEX\n");
  1471. return -EINVAL;
  1472. }
  1473. r = r600_cs_packet_next_reloc(p, &reloc);
  1474. if (r) {
  1475. DRM_ERROR("bad DRAW_INDEX\n");
  1476. return -EINVAL;
  1477. }
  1478. ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1479. ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  1480. r = r600_cs_track_check(p);
  1481. if (r) {
  1482. dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
  1483. return r;
  1484. }
  1485. break;
  1486. case PACKET3_DRAW_INDEX_AUTO:
  1487. if (pkt->count != 1) {
  1488. DRM_ERROR("bad DRAW_INDEX_AUTO\n");
  1489. return -EINVAL;
  1490. }
  1491. r = r600_cs_track_check(p);
  1492. if (r) {
  1493. dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
  1494. return r;
  1495. }
  1496. break;
  1497. case PACKET3_DRAW_INDEX_IMMD_BE:
  1498. case PACKET3_DRAW_INDEX_IMMD:
  1499. if (pkt->count < 2) {
  1500. DRM_ERROR("bad DRAW_INDEX_IMMD\n");
  1501. return -EINVAL;
  1502. }
  1503. r = r600_cs_track_check(p);
  1504. if (r) {
  1505. dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
  1506. return r;
  1507. }
  1508. break;
  1509. case PACKET3_WAIT_REG_MEM:
  1510. if (pkt->count != 5) {
  1511. DRM_ERROR("bad WAIT_REG_MEM\n");
  1512. return -EINVAL;
  1513. }
  1514. /* bit 4 is reg (0) or mem (1) */
  1515. if (idx_value & 0x10) {
  1516. r = r600_cs_packet_next_reloc(p, &reloc);
  1517. if (r) {
  1518. DRM_ERROR("bad WAIT_REG_MEM\n");
  1519. return -EINVAL;
  1520. }
  1521. ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1522. ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  1523. }
  1524. break;
  1525. case PACKET3_SURFACE_SYNC:
  1526. if (pkt->count != 3) {
  1527. DRM_ERROR("bad SURFACE_SYNC\n");
  1528. return -EINVAL;
  1529. }
  1530. /* 0xffffffff/0x0 is flush all cache flag */
  1531. if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
  1532. radeon_get_ib_value(p, idx + 2) != 0) {
  1533. r = r600_cs_packet_next_reloc(p, &reloc);
  1534. if (r) {
  1535. DRM_ERROR("bad SURFACE_SYNC\n");
  1536. return -EINVAL;
  1537. }
  1538. ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1539. }
  1540. break;
  1541. case PACKET3_EVENT_WRITE:
  1542. if (pkt->count != 2 && pkt->count != 0) {
  1543. DRM_ERROR("bad EVENT_WRITE\n");
  1544. return -EINVAL;
  1545. }
  1546. if (pkt->count) {
  1547. r = r600_cs_packet_next_reloc(p, &reloc);
  1548. if (r) {
  1549. DRM_ERROR("bad EVENT_WRITE\n");
  1550. return -EINVAL;
  1551. }
  1552. ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1553. ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  1554. }
  1555. break;
  1556. case PACKET3_EVENT_WRITE_EOP:
  1557. if (pkt->count != 4) {
  1558. DRM_ERROR("bad EVENT_WRITE_EOP\n");
  1559. return -EINVAL;
  1560. }
  1561. r = r600_cs_packet_next_reloc(p, &reloc);
  1562. if (r) {
  1563. DRM_ERROR("bad EVENT_WRITE\n");
  1564. return -EINVAL;
  1565. }
  1566. ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1567. ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  1568. break;
  1569. case PACKET3_SET_CONFIG_REG:
  1570. start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
  1571. end_reg = 4 * pkt->count + start_reg - 4;
  1572. if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
  1573. (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
  1574. (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
  1575. DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
  1576. return -EINVAL;
  1577. }
  1578. for (i = 0; i < pkt->count; i++) {
  1579. reg = start_reg + (4 * i);
  1580. r = r600_cs_check_reg(p, reg, idx+1+i);
  1581. if (r)
  1582. return r;
  1583. }
  1584. break;
  1585. case PACKET3_SET_CONTEXT_REG:
  1586. start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
  1587. end_reg = 4 * pkt->count + start_reg - 4;
  1588. if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
  1589. (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
  1590. (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
  1591. DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
  1592. return -EINVAL;
  1593. }
  1594. for (i = 0; i < pkt->count; i++) {
  1595. reg = start_reg + (4 * i);
  1596. r = r600_cs_check_reg(p, reg, idx+1+i);
  1597. if (r)
  1598. return r;
  1599. }
  1600. break;
  1601. case PACKET3_SET_RESOURCE:
  1602. if (pkt->count % 7) {
  1603. DRM_ERROR("bad SET_RESOURCE\n");
  1604. return -EINVAL;
  1605. }
  1606. start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
  1607. end_reg = 4 * pkt->count + start_reg - 4;
  1608. if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
  1609. (start_reg >= PACKET3_SET_RESOURCE_END) ||
  1610. (end_reg >= PACKET3_SET_RESOURCE_END)) {
  1611. DRM_ERROR("bad SET_RESOURCE\n");
  1612. return -EINVAL;
  1613. }
  1614. for (i = 0; i < (pkt->count / 7); i++) {
  1615. struct radeon_bo *texture, *mipmap;
  1616. u32 size, offset, base_offset, mip_offset;
  1617. switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
  1618. case SQ_TEX_VTX_VALID_TEXTURE:
  1619. /* tex base */
  1620. r = r600_cs_packet_next_reloc(p, &reloc);
  1621. if (r) {
  1622. DRM_ERROR("bad SET_RESOURCE\n");
  1623. return -EINVAL;
  1624. }
  1625. base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1626. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1627. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
  1628. ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
  1629. else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
  1630. ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
  1631. }
  1632. texture = reloc->robj;
  1633. /* tex mip base */
  1634. r = r600_cs_packet_next_reloc(p, &reloc);
  1635. if (r) {
  1636. DRM_ERROR("bad SET_RESOURCE\n");
  1637. return -EINVAL;
  1638. }
  1639. mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
  1640. mipmap = reloc->robj;
  1641. r = r600_check_texture_resource(p, idx+(i*7)+1,
  1642. texture, mipmap,
  1643. base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
  1644. mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
  1645. reloc->lobj.tiling_flags);
  1646. if (r)
  1647. return r;
  1648. ib[idx+1+(i*7)+2] += base_offset;
  1649. ib[idx+1+(i*7)+3] += mip_offset;
  1650. break;
  1651. case SQ_TEX_VTX_VALID_BUFFER:
  1652. /* vtx base */
  1653. r = r600_cs_packet_next_reloc(p, &reloc);
  1654. if (r) {
  1655. DRM_ERROR("bad SET_RESOURCE\n");
  1656. return -EINVAL;
  1657. }
  1658. offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
  1659. size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
  1660. if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
  1661. /* force size to size of the buffer */
  1662. dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
  1663. size + offset, radeon_bo_size(reloc->robj));
  1664. ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
  1665. }
  1666. ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
  1667. ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  1668. break;
  1669. case SQ_TEX_VTX_INVALID_TEXTURE:
  1670. case SQ_TEX_VTX_INVALID_BUFFER:
  1671. default:
  1672. DRM_ERROR("bad SET_RESOURCE\n");
  1673. return -EINVAL;
  1674. }
  1675. }
  1676. break;
  1677. case PACKET3_SET_ALU_CONST:
  1678. if (track->sq_config & DX9_CONSTS) {
  1679. start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
  1680. end_reg = 4 * pkt->count + start_reg - 4;
  1681. if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
  1682. (start_reg >= PACKET3_SET_ALU_CONST_END) ||
  1683. (end_reg >= PACKET3_SET_ALU_CONST_END)) {
  1684. DRM_ERROR("bad SET_ALU_CONST\n");
  1685. return -EINVAL;
  1686. }
  1687. }
  1688. break;
  1689. case PACKET3_SET_BOOL_CONST:
  1690. start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
  1691. end_reg = 4 * pkt->count + start_reg - 4;
  1692. if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
  1693. (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
  1694. (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
  1695. DRM_ERROR("bad SET_BOOL_CONST\n");
  1696. return -EINVAL;
  1697. }
  1698. break;
  1699. case PACKET3_SET_LOOP_CONST:
  1700. start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
  1701. end_reg = 4 * pkt->count + start_reg - 4;
  1702. if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
  1703. (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
  1704. (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
  1705. DRM_ERROR("bad SET_LOOP_CONST\n");
  1706. return -EINVAL;
  1707. }
  1708. break;
  1709. case PACKET3_SET_CTL_CONST:
  1710. start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
  1711. end_reg = 4 * pkt->count + start_reg - 4;
  1712. if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
  1713. (start_reg >= PACKET3_SET_CTL_CONST_END) ||
  1714. (end_reg >= PACKET3_SET_CTL_CONST_END)) {
  1715. DRM_ERROR("bad SET_CTL_CONST\n");
  1716. return -EINVAL;
  1717. }
  1718. break;
  1719. case PACKET3_SET_SAMPLER:
  1720. if (pkt->count % 3) {
  1721. DRM_ERROR("bad SET_SAMPLER\n");
  1722. return -EINVAL;
  1723. }
  1724. start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
  1725. end_reg = 4 * pkt->count + start_reg - 4;
  1726. if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
  1727. (start_reg >= PACKET3_SET_SAMPLER_END) ||
  1728. (end_reg >= PACKET3_SET_SAMPLER_END)) {
  1729. DRM_ERROR("bad SET_SAMPLER\n");
  1730. return -EINVAL;
  1731. }
  1732. break;
  1733. case PACKET3_SURFACE_BASE_UPDATE:
  1734. if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
  1735. DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
  1736. return -EINVAL;
  1737. }
  1738. if (pkt->count) {
  1739. DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
  1740. return -EINVAL;
  1741. }
  1742. break;
  1743. case PACKET3_STRMOUT_BUFFER_UPDATE:
  1744. if (pkt->count != 4) {
  1745. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
  1746. return -EINVAL;
  1747. }
  1748. /* Updating memory at DST_ADDRESS. */
  1749. if (idx_value & 0x1) {
  1750. u64 offset;
  1751. r = r600_cs_packet_next_reloc(p, &reloc);
  1752. if (r) {
  1753. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
  1754. return -EINVAL;
  1755. }
  1756. offset = radeon_get_ib_value(p, idx+1);
  1757. offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
  1758. if ((offset + 4) > radeon_bo_size(reloc->robj)) {
  1759. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
  1760. offset + 4, radeon_bo_size(reloc->robj));
  1761. return -EINVAL;
  1762. }
  1763. ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1764. ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  1765. }
  1766. /* Reading data from SRC_ADDRESS. */
  1767. if (((idx_value >> 1) & 0x3) == 2) {
  1768. u64 offset;
  1769. r = r600_cs_packet_next_reloc(p, &reloc);
  1770. if (r) {
  1771. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
  1772. return -EINVAL;
  1773. }
  1774. offset = radeon_get_ib_value(p, idx+3);
  1775. offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
  1776. if ((offset + 4) > radeon_bo_size(reloc->robj)) {
  1777. DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
  1778. offset + 4, radeon_bo_size(reloc->robj));
  1779. return -EINVAL;
  1780. }
  1781. ib[idx+3] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1782. ib[idx+4] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  1783. }
  1784. break;
  1785. case PACKET3_COPY_DW:
  1786. if (pkt->count != 4) {
  1787. DRM_ERROR("bad COPY_DW (invalid count)\n");
  1788. return -EINVAL;
  1789. }
  1790. if (idx_value & 0x1) {
  1791. u64 offset;
  1792. /* SRC is memory. */
  1793. r = r600_cs_packet_next_reloc(p, &reloc);
  1794. if (r) {
  1795. DRM_ERROR("bad COPY_DW (missing src reloc)\n");
  1796. return -EINVAL;
  1797. }
  1798. offset = radeon_get_ib_value(p, idx+1);
  1799. offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
  1800. if ((offset + 4) > radeon_bo_size(reloc->robj)) {
  1801. DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
  1802. offset + 4, radeon_bo_size(reloc->robj));
  1803. return -EINVAL;
  1804. }
  1805. ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1806. ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  1807. } else {
  1808. /* SRC is a reg. */
  1809. reg = radeon_get_ib_value(p, idx+1) << 2;
  1810. if (!r600_is_safe_reg(p, reg, idx+1))
  1811. return -EINVAL;
  1812. }
  1813. if (idx_value & 0x2) {
  1814. u64 offset;
  1815. /* DST is memory. */
  1816. r = r600_cs_packet_next_reloc(p, &reloc);
  1817. if (r) {
  1818. DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
  1819. return -EINVAL;
  1820. }
  1821. offset = radeon_get_ib_value(p, idx+3);
  1822. offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
  1823. if ((offset + 4) > radeon_bo_size(reloc->robj)) {
  1824. DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
  1825. offset + 4, radeon_bo_size(reloc->robj));
  1826. return -EINVAL;
  1827. }
  1828. ib[idx+3] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
  1829. ib[idx+4] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
  1830. } else {
  1831. /* DST is a reg. */
  1832. reg = radeon_get_ib_value(p, idx+3) << 2;
  1833. if (!r600_is_safe_reg(p, reg, idx+3))
  1834. return -EINVAL;
  1835. }
  1836. break;
  1837. case PACKET3_NOP:
  1838. break;
  1839. default:
  1840. DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
  1841. return -EINVAL;
  1842. }
  1843. return 0;
  1844. }
  1845. int r600_cs_parse(struct radeon_cs_parser *p)
  1846. {
  1847. struct radeon_cs_packet pkt;
  1848. struct r600_cs_track *track;
  1849. int r;
  1850. if (p->track == NULL) {
  1851. /* initialize tracker, we are in kms */
  1852. track = kzalloc(sizeof(*track), GFP_KERNEL);
  1853. if (track == NULL)
  1854. return -ENOMEM;
  1855. r600_cs_track_init(track);
  1856. if (p->rdev->family < CHIP_RV770) {
  1857. track->npipes = p->rdev->config.r600.tiling_npipes;
  1858. track->nbanks = p->rdev->config.r600.tiling_nbanks;
  1859. track->group_size = p->rdev->config.r600.tiling_group_size;
  1860. } else if (p->rdev->family <= CHIP_RV740) {
  1861. track->npipes = p->rdev->config.rv770.tiling_npipes;
  1862. track->nbanks = p->rdev->config.rv770.tiling_nbanks;
  1863. track->group_size = p->rdev->config.rv770.tiling_group_size;
  1864. }
  1865. p->track = track;
  1866. }
  1867. do {
  1868. r = r600_cs_packet_parse(p, &pkt, p->idx);
  1869. if (r) {
  1870. kfree(p->track);
  1871. p->track = NULL;
  1872. return r;
  1873. }
  1874. p->idx += pkt.count + 2;
  1875. switch (pkt.type) {
  1876. case PACKET_TYPE0:
  1877. r = r600_cs_parse_packet0(p, &pkt);
  1878. break;
  1879. case PACKET_TYPE2:
  1880. break;
  1881. case PACKET_TYPE3:
  1882. r = r600_packet3_check(p, &pkt);
  1883. break;
  1884. default:
  1885. DRM_ERROR("Unknown packet type %d !\n", pkt.type);
  1886. kfree(p->track);
  1887. p->track = NULL;
  1888. return -EINVAL;
  1889. }
  1890. if (r) {
  1891. kfree(p->track);
  1892. p->track = NULL;
  1893. return r;
  1894. }
  1895. } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
  1896. #if 0
  1897. for (r = 0; r < p->ib->length_dw; r++) {
  1898. printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
  1899. mdelay(1);
  1900. }
  1901. #endif
  1902. kfree(p->track);
  1903. p->track = NULL;
  1904. return 0;
  1905. }
  1906. static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
  1907. {
  1908. if (p->chunk_relocs_idx == -1) {
  1909. return 0;
  1910. }
  1911. p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  1912. if (p->relocs == NULL) {
  1913. return -ENOMEM;
  1914. }
  1915. return 0;
  1916. }
  1917. /**
  1918. * cs_parser_fini() - clean parser states
  1919. * @parser: parser structure holding parsing context.
  1920. * @error: error number
  1921. *
  1922. * If error is set than unvalidate buffer, otherwise just free memory
  1923. * used by parsing context.
  1924. **/
  1925. static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
  1926. {
  1927. unsigned i;
  1928. kfree(parser->relocs);
  1929. for (i = 0; i < parser->nchunks; i++) {
  1930. kfree(parser->chunks[i].kdata);
  1931. kfree(parser->chunks[i].kpage[0]);
  1932. kfree(parser->chunks[i].kpage[1]);
  1933. }
  1934. kfree(parser->chunks);
  1935. kfree(parser->chunks_array);
  1936. }
  1937. int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
  1938. unsigned family, u32 *ib, int *l)
  1939. {
  1940. struct radeon_cs_parser parser;
  1941. struct radeon_cs_chunk *ib_chunk;
  1942. struct radeon_ib fake_ib;
  1943. struct r600_cs_track *track;
  1944. int r;
  1945. /* initialize tracker */
  1946. track = kzalloc(sizeof(*track), GFP_KERNEL);
  1947. if (track == NULL)
  1948. return -ENOMEM;
  1949. r600_cs_track_init(track);
  1950. r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
  1951. /* initialize parser */
  1952. memset(&parser, 0, sizeof(struct radeon_cs_parser));
  1953. parser.filp = filp;
  1954. parser.dev = &dev->pdev->dev;
  1955. parser.rdev = NULL;
  1956. parser.family = family;
  1957. parser.ib = &fake_ib;
  1958. parser.track = track;
  1959. fake_ib.ptr = ib;
  1960. r = radeon_cs_parser_init(&parser, data);
  1961. if (r) {
  1962. DRM_ERROR("Failed to initialize parser !\n");
  1963. r600_cs_parser_fini(&parser, r);
  1964. return r;
  1965. }
  1966. r = r600_cs_parser_relocs_legacy(&parser);
  1967. if (r) {
  1968. DRM_ERROR("Failed to parse relocation !\n");
  1969. r600_cs_parser_fini(&parser, r);
  1970. return r;
  1971. }
  1972. /* Copy the packet into the IB, the parser will read from the
  1973. * input memory (cached) and write to the IB (which can be
  1974. * uncached). */
  1975. ib_chunk = &parser.chunks[parser.chunk_ib_idx];
  1976. parser.ib->length_dw = ib_chunk->length_dw;
  1977. *l = parser.ib->length_dw;
  1978. r = r600_cs_parse(&parser);
  1979. if (r) {
  1980. DRM_ERROR("Invalid command stream !\n");
  1981. r600_cs_parser_fini(&parser, r);
  1982. return r;
  1983. }
  1984. r = radeon_cs_finish_pages(&parser);
  1985. if (r) {
  1986. DRM_ERROR("Invalid command stream !\n");
  1987. r600_cs_parser_fini(&parser, r);
  1988. return r;
  1989. }
  1990. r600_cs_parser_fini(&parser, r);
  1991. return r;
  1992. }
  1993. void r600_cs_legacy_init(void)
  1994. {
  1995. r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
  1996. }