Kconfig.cpu 2.7 KB

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  1. menu "Processor features"
  2. choice
  3. prompt "Endianess selection"
  4. default CPU_LITTLE_ENDIAN
  5. help
  6. Some SuperH machines can be configured for either little or big
  7. endian byte order. These modes require different kernels.
  8. config CPU_LITTLE_ENDIAN
  9. bool "Little Endian"
  10. config CPU_BIG_ENDIAN
  11. bool "Big Endian"
  12. endchoice
  13. config SH_FPU
  14. def_bool y
  15. prompt "FPU support"
  16. depends on CPU_HAS_FPU
  17. help
  18. Selecting this option will enable support for SH processors that
  19. have FPU units (ie, SH77xx).
  20. This option must be set in order to enable the FPU.
  21. config SH64_FPU_DENORM_FLUSH
  22. bool "Flush floating point denorms to zero"
  23. depends on SH_FPU && SUPERH64
  24. config SH_FPU_EMU
  25. def_bool n
  26. prompt "FPU emulation support"
  27. depends on !SH_FPU && EXPERIMENTAL
  28. help
  29. Selecting this option will enable support for software FPU emulation.
  30. Most SH-3 users will want to say Y here, whereas most SH-4 users will
  31. want to say N.
  32. config SH_DSP
  33. def_bool y
  34. prompt "DSP support"
  35. depends on CPU_HAS_DSP
  36. help
  37. Selecting this option will enable support for SH processors that
  38. have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP).
  39. This option must be set in order to enable the DSP.
  40. config SH_ADC
  41. def_bool y
  42. prompt "ADC support"
  43. depends on CPU_SH3
  44. help
  45. Selecting this option will allow the Linux kernel to use SH3 on-chip
  46. ADC module.
  47. If unsure, say N.
  48. config SH_STORE_QUEUES
  49. bool "Support for Store Queues"
  50. depends on CPU_SH4
  51. help
  52. Selecting this option will enable an in-kernel API for manipulating
  53. the store queues integrated in the SH-4 processors.
  54. config SPECULATIVE_EXECUTION
  55. bool "Speculative subroutine return"
  56. depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL
  57. help
  58. This enables support for a speculative instruction fetch for
  59. subroutine return. There are various pitfalls associated with
  60. this, as outlined in the SH7780 hardware manual.
  61. If unsure, say N.
  62. config SH64_USER_MISALIGNED_FIXUP
  63. def_bool y
  64. prompt "Fixup misaligned loads/stores occurring in user mode"
  65. depends on SUPERH64
  66. config SH64_ID2815_WORKAROUND
  67. bool "Include workaround for SH5-101 cut2 silicon defect ID2815"
  68. depends on CPU_SUBTYPE_SH5_101
  69. config CPU_HAS_INTEVT
  70. bool
  71. config CPU_HAS_MASKREG_IRQ
  72. bool
  73. config CPU_HAS_IPR_IRQ
  74. bool
  75. config CPU_HAS_SR_RB
  76. bool
  77. help
  78. This will enable the use of SR.RB register bank usage. Processors
  79. that are lacking this bit must have another method in place for
  80. accomplishing what is taken care of by the banked registers.
  81. See <file:Documentation/sh/register-banks.txt> for further
  82. information on SR.RB and register banking in the kernel in general.
  83. config CPU_HAS_PTEA
  84. bool
  85. config CPU_HAS_DSP
  86. bool
  87. config CPU_HAS_FPU
  88. bool
  89. endmenu