fsl_ifc_nand.c 32 KB

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  1. /*
  2. * Freescale Integrated Flash Controller NAND driver
  3. *
  4. * Copyright 2011-2012 Freescale Semiconductor, Inc
  5. *
  6. * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/module.h>
  23. #include <linux/types.h>
  24. #include <linux/init.h>
  25. #include <linux/kernel.h>
  26. #include <linux/slab.h>
  27. #include <linux/mtd/mtd.h>
  28. #include <linux/mtd/nand.h>
  29. #include <linux/mtd/partitions.h>
  30. #include <linux/mtd/nand_ecc.h>
  31. #include <asm/fsl_ifc.h>
  32. #define FSL_IFC_V1_1_0 0x01010000
  33. #define ERR_BYTE 0xFF /* Value returned for read
  34. bytes when read failed */
  35. #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
  36. for IFC NAND Machine */
  37. struct fsl_ifc_ctrl;
  38. /* mtd information per set */
  39. struct fsl_ifc_mtd {
  40. struct mtd_info mtd;
  41. struct nand_chip chip;
  42. struct fsl_ifc_ctrl *ctrl;
  43. struct device *dev;
  44. int bank; /* Chip select bank number */
  45. unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  46. u8 __iomem *vbase; /* Chip select base virtual address */
  47. };
  48. /* overview of the fsl ifc controller */
  49. struct fsl_ifc_nand_ctrl {
  50. struct nand_hw_control controller;
  51. struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
  52. u8 __iomem *addr; /* Address of assigned IFC buffer */
  53. unsigned int page; /* Last page written to / read from */
  54. unsigned int read_bytes;/* Number of bytes read during command */
  55. unsigned int column; /* Saved column from SEQIN */
  56. unsigned int index; /* Pointer to next byte to 'read' */
  57. unsigned int oob; /* Non zero if operating on OOB data */
  58. unsigned int eccread; /* Non zero for a full-page ECC read */
  59. unsigned int counter; /* counter for the initializations */
  60. unsigned int max_bitflips; /* Saved during READ0 cmd */
  61. };
  62. static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
  63. /* 512-byte page with 4-bit ECC, 8-bit */
  64. static struct nand_ecclayout oob_512_8bit_ecc4 = {
  65. .eccbytes = 8,
  66. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  67. .oobfree = { {0, 5}, {6, 2} },
  68. };
  69. /* 512-byte page with 4-bit ECC, 16-bit */
  70. static struct nand_ecclayout oob_512_16bit_ecc4 = {
  71. .eccbytes = 8,
  72. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  73. .oobfree = { {2, 6}, },
  74. };
  75. /* 2048-byte page size with 4-bit ECC */
  76. static struct nand_ecclayout oob_2048_ecc4 = {
  77. .eccbytes = 32,
  78. .eccpos = {
  79. 8, 9, 10, 11, 12, 13, 14, 15,
  80. 16, 17, 18, 19, 20, 21, 22, 23,
  81. 24, 25, 26, 27, 28, 29, 30, 31,
  82. 32, 33, 34, 35, 36, 37, 38, 39,
  83. },
  84. .oobfree = { {2, 6}, {40, 24} },
  85. };
  86. /* 4096-byte page size with 4-bit ECC */
  87. static struct nand_ecclayout oob_4096_ecc4 = {
  88. .eccbytes = 64,
  89. .eccpos = {
  90. 8, 9, 10, 11, 12, 13, 14, 15,
  91. 16, 17, 18, 19, 20, 21, 22, 23,
  92. 24, 25, 26, 27, 28, 29, 30, 31,
  93. 32, 33, 34, 35, 36, 37, 38, 39,
  94. 40, 41, 42, 43, 44, 45, 46, 47,
  95. 48, 49, 50, 51, 52, 53, 54, 55,
  96. 56, 57, 58, 59, 60, 61, 62, 63,
  97. 64, 65, 66, 67, 68, 69, 70, 71,
  98. },
  99. .oobfree = { {2, 6}, {72, 56} },
  100. };
  101. /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
  102. static struct nand_ecclayout oob_4096_ecc8 = {
  103. .eccbytes = 128,
  104. .eccpos = {
  105. 8, 9, 10, 11, 12, 13, 14, 15,
  106. 16, 17, 18, 19, 20, 21, 22, 23,
  107. 24, 25, 26, 27, 28, 29, 30, 31,
  108. 32, 33, 34, 35, 36, 37, 38, 39,
  109. 40, 41, 42, 43, 44, 45, 46, 47,
  110. 48, 49, 50, 51, 52, 53, 54, 55,
  111. 56, 57, 58, 59, 60, 61, 62, 63,
  112. 64, 65, 66, 67, 68, 69, 70, 71,
  113. 72, 73, 74, 75, 76, 77, 78, 79,
  114. 80, 81, 82, 83, 84, 85, 86, 87,
  115. 88, 89, 90, 91, 92, 93, 94, 95,
  116. 96, 97, 98, 99, 100, 101, 102, 103,
  117. 104, 105, 106, 107, 108, 109, 110, 111,
  118. 112, 113, 114, 115, 116, 117, 118, 119,
  119. 120, 121, 122, 123, 124, 125, 126, 127,
  120. 128, 129, 130, 131, 132, 133, 134, 135,
  121. },
  122. .oobfree = { {2, 6}, {136, 82} },
  123. };
  124. /* 8192-byte page size with 4-bit ECC */
  125. static struct nand_ecclayout oob_8192_ecc4 = {
  126. .eccbytes = 128,
  127. .eccpos = {
  128. 8, 9, 10, 11, 12, 13, 14, 15,
  129. 16, 17, 18, 19, 20, 21, 22, 23,
  130. 24, 25, 26, 27, 28, 29, 30, 31,
  131. 32, 33, 34, 35, 36, 37, 38, 39,
  132. 40, 41, 42, 43, 44, 45, 46, 47,
  133. 48, 49, 50, 51, 52, 53, 54, 55,
  134. 56, 57, 58, 59, 60, 61, 62, 63,
  135. 64, 65, 66, 67, 68, 69, 70, 71,
  136. 72, 73, 74, 75, 76, 77, 78, 79,
  137. 80, 81, 82, 83, 84, 85, 86, 87,
  138. 88, 89, 90, 91, 92, 93, 94, 95,
  139. 96, 97, 98, 99, 100, 101, 102, 103,
  140. 104, 105, 106, 107, 108, 109, 110, 111,
  141. 112, 113, 114, 115, 116, 117, 118, 119,
  142. 120, 121, 122, 123, 124, 125, 126, 127,
  143. 128, 129, 130, 131, 132, 133, 134, 135,
  144. },
  145. .oobfree = { {2, 6}, {136, 208} },
  146. };
  147. /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
  148. static struct nand_ecclayout oob_8192_ecc8 = {
  149. .eccbytes = 256,
  150. .eccpos = {
  151. 8, 9, 10, 11, 12, 13, 14, 15,
  152. 16, 17, 18, 19, 20, 21, 22, 23,
  153. 24, 25, 26, 27, 28, 29, 30, 31,
  154. 32, 33, 34, 35, 36, 37, 38, 39,
  155. 40, 41, 42, 43, 44, 45, 46, 47,
  156. 48, 49, 50, 51, 52, 53, 54, 55,
  157. 56, 57, 58, 59, 60, 61, 62, 63,
  158. 64, 65, 66, 67, 68, 69, 70, 71,
  159. 72, 73, 74, 75, 76, 77, 78, 79,
  160. 80, 81, 82, 83, 84, 85, 86, 87,
  161. 88, 89, 90, 91, 92, 93, 94, 95,
  162. 96, 97, 98, 99, 100, 101, 102, 103,
  163. 104, 105, 106, 107, 108, 109, 110, 111,
  164. 112, 113, 114, 115, 116, 117, 118, 119,
  165. 120, 121, 122, 123, 124, 125, 126, 127,
  166. 128, 129, 130, 131, 132, 133, 134, 135,
  167. 136, 137, 138, 139, 140, 141, 142, 143,
  168. 144, 145, 146, 147, 148, 149, 150, 151,
  169. 152, 153, 154, 155, 156, 157, 158, 159,
  170. 160, 161, 162, 163, 164, 165, 166, 167,
  171. 168, 169, 170, 171, 172, 173, 174, 175,
  172. 176, 177, 178, 179, 180, 181, 182, 183,
  173. 184, 185, 186, 187, 188, 189, 190, 191,
  174. 192, 193, 194, 195, 196, 197, 198, 199,
  175. 200, 201, 202, 203, 204, 205, 206, 207,
  176. 208, 209, 210, 211, 212, 213, 214, 215,
  177. 216, 217, 218, 219, 220, 221, 222, 223,
  178. 224, 225, 226, 227, 228, 229, 230, 231,
  179. 232, 233, 234, 235, 236, 237, 238, 239,
  180. 240, 241, 242, 243, 244, 245, 246, 247,
  181. 248, 249, 250, 251, 252, 253, 254, 255,
  182. 256, 257, 258, 259, 260, 261, 262, 263,
  183. },
  184. .oobfree = { {2, 6}, {264, 80} },
  185. };
  186. /*
  187. * Generic flash bbt descriptors
  188. */
  189. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  190. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  191. static struct nand_bbt_descr bbt_main_descr = {
  192. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  193. NAND_BBT_2BIT | NAND_BBT_VERSION,
  194. .offs = 2, /* 0 on 8-bit small page */
  195. .len = 4,
  196. .veroffs = 6,
  197. .maxblocks = 4,
  198. .pattern = bbt_pattern,
  199. };
  200. static struct nand_bbt_descr bbt_mirror_descr = {
  201. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  202. NAND_BBT_2BIT | NAND_BBT_VERSION,
  203. .offs = 2, /* 0 on 8-bit small page */
  204. .len = 4,
  205. .veroffs = 6,
  206. .maxblocks = 4,
  207. .pattern = mirror_pattern,
  208. };
  209. /*
  210. * Set up the IFC hardware block and page address fields, and the ifc nand
  211. * structure addr field to point to the correct IFC buffer in memory
  212. */
  213. static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  214. {
  215. struct nand_chip *chip = mtd->priv;
  216. struct fsl_ifc_mtd *priv = chip->priv;
  217. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  218. struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  219. int buf_num;
  220. ifc_nand_ctrl->page = page_addr;
  221. /* Program ROW0/COL0 */
  222. iowrite32be(page_addr, &ifc->ifc_nand.row0);
  223. iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
  224. buf_num = page_addr & priv->bufnum_mask;
  225. ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
  226. ifc_nand_ctrl->index = column;
  227. /* for OOB data point to the second half of the buffer */
  228. if (oob)
  229. ifc_nand_ctrl->index += mtd->writesize;
  230. }
  231. static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
  232. {
  233. struct nand_chip *chip = mtd->priv;
  234. struct fsl_ifc_mtd *priv = chip->priv;
  235. u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
  236. u32 __iomem *mainarea = (u32 __iomem *)addr;
  237. u8 __iomem *oob = addr + mtd->writesize;
  238. int i;
  239. for (i = 0; i < mtd->writesize / 4; i++) {
  240. if (__raw_readl(&mainarea[i]) != 0xffffffff)
  241. return 0;
  242. }
  243. for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
  244. int pos = chip->ecc.layout->eccpos[i];
  245. if (__raw_readb(&oob[pos]) != 0xff)
  246. return 0;
  247. }
  248. return 1;
  249. }
  250. /* returns nonzero if entire page is blank */
  251. static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  252. u32 *eccstat, unsigned int bufnum)
  253. {
  254. u32 reg = eccstat[bufnum / 4];
  255. int errors;
  256. errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
  257. return errors;
  258. }
  259. /*
  260. * execute IFC NAND command and wait for it to complete
  261. */
  262. static void fsl_ifc_run_command(struct mtd_info *mtd)
  263. {
  264. struct nand_chip *chip = mtd->priv;
  265. struct fsl_ifc_mtd *priv = chip->priv;
  266. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  267. struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
  268. struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  269. u32 eccstat[4];
  270. int i;
  271. /* set the chip select for NAND Transaction */
  272. iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,
  273. &ifc->ifc_nand.nand_csel);
  274. dev_vdbg(priv->dev,
  275. "%s: fir0=%08x fcr0=%08x\n",
  276. __func__,
  277. ioread32be(&ifc->ifc_nand.nand_fir0),
  278. ioread32be(&ifc->ifc_nand.nand_fcr0));
  279. ctrl->nand_stat = 0;
  280. /* start read/write seq */
  281. iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
  282. /* wait for command complete flag or timeout */
  283. wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
  284. IFC_TIMEOUT_MSECS * HZ/1000);
  285. /* ctrl->nand_stat will be updated from IRQ context */
  286. if (!ctrl->nand_stat)
  287. dev_err(priv->dev, "Controller is not responding\n");
  288. if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
  289. dev_err(priv->dev, "NAND Flash Timeout Error\n");
  290. if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
  291. dev_err(priv->dev, "NAND Flash Write Protect Error\n");
  292. nctrl->max_bitflips = 0;
  293. if (nctrl->eccread) {
  294. int errors;
  295. int bufnum = nctrl->page & priv->bufnum_mask;
  296. int sector = bufnum * chip->ecc.steps;
  297. int sector_end = sector + chip->ecc.steps - 1;
  298. for (i = sector / 4; i <= sector_end / 4; i++)
  299. eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);
  300. for (i = sector; i <= sector_end; i++) {
  301. errors = check_read_ecc(mtd, ctrl, eccstat, i);
  302. if (errors == 15) {
  303. /*
  304. * Uncorrectable error.
  305. * OK only if the whole page is blank.
  306. *
  307. * We disable ECCER reporting due to...
  308. * erratum IFC-A002770 -- so report it now if we
  309. * see an uncorrectable error in ECCSTAT.
  310. */
  311. if (!is_blank(mtd, bufnum))
  312. ctrl->nand_stat |=
  313. IFC_NAND_EVTER_STAT_ECCER;
  314. break;
  315. }
  316. mtd->ecc_stats.corrected += errors;
  317. nctrl->max_bitflips = max_t(unsigned int,
  318. nctrl->max_bitflips,
  319. errors);
  320. }
  321. nctrl->eccread = 0;
  322. }
  323. }
  324. static void fsl_ifc_do_read(struct nand_chip *chip,
  325. int oob,
  326. struct mtd_info *mtd)
  327. {
  328. struct fsl_ifc_mtd *priv = chip->priv;
  329. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  330. struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  331. /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
  332. if (mtd->writesize > 512) {
  333. iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  334. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  335. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  336. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  337. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
  338. &ifc->ifc_nand.nand_fir0);
  339. iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
  340. iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  341. (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
  342. &ifc->ifc_nand.nand_fcr0);
  343. } else {
  344. iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  345. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  346. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  347. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
  348. &ifc->ifc_nand.nand_fir0);
  349. iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
  350. if (oob)
  351. iowrite32be(NAND_CMD_READOOB <<
  352. IFC_NAND_FCR0_CMD0_SHIFT,
  353. &ifc->ifc_nand.nand_fcr0);
  354. else
  355. iowrite32be(NAND_CMD_READ0 <<
  356. IFC_NAND_FCR0_CMD0_SHIFT,
  357. &ifc->ifc_nand.nand_fcr0);
  358. }
  359. }
  360. /* cmdfunc send commands to the IFC NAND Machine */
  361. static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  362. int column, int page_addr) {
  363. struct nand_chip *chip = mtd->priv;
  364. struct fsl_ifc_mtd *priv = chip->priv;
  365. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  366. struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  367. /* clear the read buffer */
  368. ifc_nand_ctrl->read_bytes = 0;
  369. if (command != NAND_CMD_PAGEPROG)
  370. ifc_nand_ctrl->index = 0;
  371. switch (command) {
  372. /* READ0 read the entire buffer to use hardware ECC. */
  373. case NAND_CMD_READ0:
  374. iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
  375. set_addr(mtd, 0, page_addr, 0);
  376. ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  377. ifc_nand_ctrl->index += column;
  378. if (chip->ecc.mode == NAND_ECC_HW)
  379. ifc_nand_ctrl->eccread = 1;
  380. fsl_ifc_do_read(chip, 0, mtd);
  381. fsl_ifc_run_command(mtd);
  382. return;
  383. /* READOOB reads only the OOB because no ECC is performed. */
  384. case NAND_CMD_READOOB:
  385. iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
  386. set_addr(mtd, column, page_addr, 1);
  387. ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  388. fsl_ifc_do_read(chip, 1, mtd);
  389. fsl_ifc_run_command(mtd);
  390. return;
  391. case NAND_CMD_READID:
  392. case NAND_CMD_PARAM: {
  393. int timing = IFC_FIR_OP_RB;
  394. if (command == NAND_CMD_PARAM)
  395. timing = IFC_FIR_OP_RBCD;
  396. iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  397. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  398. (timing << IFC_NAND_FIR0_OP2_SHIFT),
  399. &ifc->ifc_nand.nand_fir0);
  400. iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,
  401. &ifc->ifc_nand.nand_fcr0);
  402. iowrite32be(column, &ifc->ifc_nand.row3);
  403. /*
  404. * although currently it's 8 bytes for READID, we always read
  405. * the maximum 256 bytes(for PARAM)
  406. */
  407. iowrite32be(256, &ifc->ifc_nand.nand_fbcr);
  408. ifc_nand_ctrl->read_bytes = 256;
  409. set_addr(mtd, 0, 0, 0);
  410. fsl_ifc_run_command(mtd);
  411. return;
  412. }
  413. /* ERASE1 stores the block and page address */
  414. case NAND_CMD_ERASE1:
  415. set_addr(mtd, 0, page_addr, 0);
  416. return;
  417. /* ERASE2 uses the block and page address from ERASE1 */
  418. case NAND_CMD_ERASE2:
  419. iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  420. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  421. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
  422. &ifc->ifc_nand.nand_fir0);
  423. iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
  424. (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
  425. &ifc->ifc_nand.nand_fcr0);
  426. iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
  427. ifc_nand_ctrl->read_bytes = 0;
  428. fsl_ifc_run_command(mtd);
  429. return;
  430. /* SEQIN sets up the addr buffer and all registers except the length */
  431. case NAND_CMD_SEQIN: {
  432. u32 nand_fcr0;
  433. ifc_nand_ctrl->column = column;
  434. ifc_nand_ctrl->oob = 0;
  435. if (mtd->writesize > 512) {
  436. nand_fcr0 =
  437. (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
  438. (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
  439. iowrite32be(
  440. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  441. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  442. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  443. (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
  444. (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT),
  445. &ifc->ifc_nand.nand_fir0);
  446. } else {
  447. nand_fcr0 = ((NAND_CMD_PAGEPROG <<
  448. IFC_NAND_FCR0_CMD1_SHIFT) |
  449. (NAND_CMD_SEQIN <<
  450. IFC_NAND_FCR0_CMD2_SHIFT));
  451. iowrite32be(
  452. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  453. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
  454. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  455. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
  456. (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
  457. &ifc->ifc_nand.nand_fir0);
  458. iowrite32be(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT,
  459. &ifc->ifc_nand.nand_fir1);
  460. if (column >= mtd->writesize)
  461. nand_fcr0 |=
  462. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
  463. else
  464. nand_fcr0 |=
  465. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
  466. }
  467. if (column >= mtd->writesize) {
  468. /* OOB area --> READOOB */
  469. column -= mtd->writesize;
  470. ifc_nand_ctrl->oob = 1;
  471. }
  472. iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
  473. set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
  474. return;
  475. }
  476. /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
  477. case NAND_CMD_PAGEPROG: {
  478. if (ifc_nand_ctrl->oob) {
  479. iowrite32be(ifc_nand_ctrl->index -
  480. ifc_nand_ctrl->column,
  481. &ifc->ifc_nand.nand_fbcr);
  482. } else {
  483. iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
  484. }
  485. fsl_ifc_run_command(mtd);
  486. return;
  487. }
  488. case NAND_CMD_STATUS:
  489. iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  490. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
  491. &ifc->ifc_nand.nand_fir0);
  492. iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
  493. &ifc->ifc_nand.nand_fcr0);
  494. iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
  495. set_addr(mtd, 0, 0, 0);
  496. ifc_nand_ctrl->read_bytes = 1;
  497. fsl_ifc_run_command(mtd);
  498. /*
  499. * The chip always seems to report that it is
  500. * write-protected, even when it is not.
  501. */
  502. setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
  503. return;
  504. case NAND_CMD_RESET:
  505. iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
  506. &ifc->ifc_nand.nand_fir0);
  507. iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
  508. &ifc->ifc_nand.nand_fcr0);
  509. fsl_ifc_run_command(mtd);
  510. return;
  511. default:
  512. dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
  513. __func__, command);
  514. }
  515. }
  516. static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
  517. {
  518. /* The hardware does not seem to support multiple
  519. * chips per bank.
  520. */
  521. }
  522. /*
  523. * Write buf to the IFC NAND Controller Data Buffer
  524. */
  525. static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  526. {
  527. struct nand_chip *chip = mtd->priv;
  528. struct fsl_ifc_mtd *priv = chip->priv;
  529. unsigned int bufsize = mtd->writesize + mtd->oobsize;
  530. if (len <= 0) {
  531. dev_err(priv->dev, "%s: len %d bytes", __func__, len);
  532. return;
  533. }
  534. if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
  535. dev_err(priv->dev,
  536. "%s: beyond end of buffer (%d requested, %u available)\n",
  537. __func__, len, bufsize - ifc_nand_ctrl->index);
  538. len = bufsize - ifc_nand_ctrl->index;
  539. }
  540. memcpy_toio(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index], buf, len);
  541. ifc_nand_ctrl->index += len;
  542. }
  543. /*
  544. * Read a byte from either the IFC hardware buffer
  545. * read function for 8-bit buswidth
  546. */
  547. static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
  548. {
  549. struct nand_chip *chip = mtd->priv;
  550. struct fsl_ifc_mtd *priv = chip->priv;
  551. /*
  552. * If there are still bytes in the IFC buffer, then use the
  553. * next byte.
  554. */
  555. if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes)
  556. return in_8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]);
  557. dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
  558. return ERR_BYTE;
  559. }
  560. /*
  561. * Read two bytes from the IFC hardware buffer
  562. * read function for 16-bit buswith
  563. */
  564. static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
  565. {
  566. struct nand_chip *chip = mtd->priv;
  567. struct fsl_ifc_mtd *priv = chip->priv;
  568. uint16_t data;
  569. /*
  570. * If there are still bytes in the IFC buffer, then use the
  571. * next byte.
  572. */
  573. if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
  574. data = in_be16((uint16_t __iomem *)&ifc_nand_ctrl->
  575. addr[ifc_nand_ctrl->index]);
  576. ifc_nand_ctrl->index += 2;
  577. return (uint8_t) data;
  578. }
  579. dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
  580. return ERR_BYTE;
  581. }
  582. /*
  583. * Read from the IFC Controller Data Buffer
  584. */
  585. static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  586. {
  587. struct nand_chip *chip = mtd->priv;
  588. struct fsl_ifc_mtd *priv = chip->priv;
  589. int avail;
  590. if (len < 0) {
  591. dev_err(priv->dev, "%s: len %d bytes", __func__, len);
  592. return;
  593. }
  594. avail = min((unsigned int)len,
  595. ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
  596. memcpy_fromio(buf, &ifc_nand_ctrl->addr[ifc_nand_ctrl->index], avail);
  597. ifc_nand_ctrl->index += avail;
  598. if (len > avail)
  599. dev_err(priv->dev,
  600. "%s: beyond end of buffer (%d requested, %d available)\n",
  601. __func__, len, avail);
  602. }
  603. /*
  604. * This function is called after Program and Erase Operations to
  605. * check for success or failure.
  606. */
  607. static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
  608. {
  609. struct fsl_ifc_mtd *priv = chip->priv;
  610. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  611. struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  612. u32 nand_fsr;
  613. /* Use READ_STATUS command, but wait for the device to be ready */
  614. iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  615. (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
  616. &ifc->ifc_nand.nand_fir0);
  617. iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
  618. &ifc->ifc_nand.nand_fcr0);
  619. iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
  620. set_addr(mtd, 0, 0, 0);
  621. ifc_nand_ctrl->read_bytes = 1;
  622. fsl_ifc_run_command(mtd);
  623. nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);
  624. /*
  625. * The chip always seems to report that it is
  626. * write-protected, even when it is not.
  627. */
  628. return nand_fsr | NAND_STATUS_WP;
  629. }
  630. static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  631. uint8_t *buf, int oob_required, int page)
  632. {
  633. struct fsl_ifc_mtd *priv = chip->priv;
  634. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  635. struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
  636. fsl_ifc_read_buf(mtd, buf, mtd->writesize);
  637. if (oob_required)
  638. fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  639. if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
  640. dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
  641. if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
  642. mtd->ecc_stats.failed++;
  643. return nctrl->max_bitflips;
  644. }
  645. /* ECC will be calculated automatically, and errors will be detected in
  646. * waitfunc.
  647. */
  648. static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  649. const uint8_t *buf, int oob_required)
  650. {
  651. fsl_ifc_write_buf(mtd, buf, mtd->writesize);
  652. fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  653. return 0;
  654. }
  655. static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
  656. {
  657. struct nand_chip *chip = mtd->priv;
  658. struct fsl_ifc_mtd *priv = chip->priv;
  659. dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
  660. chip->numchips);
  661. dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
  662. chip->chipsize);
  663. dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
  664. chip->pagemask);
  665. dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
  666. chip->chip_delay);
  667. dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
  668. chip->badblockpos);
  669. dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
  670. chip->chip_shift);
  671. dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
  672. chip->page_shift);
  673. dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
  674. chip->phys_erase_shift);
  675. dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
  676. chip->ecc.mode);
  677. dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
  678. chip->ecc.steps);
  679. dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
  680. chip->ecc.bytes);
  681. dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
  682. chip->ecc.total);
  683. dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
  684. chip->ecc.layout);
  685. dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
  686. dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
  687. dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
  688. mtd->erasesize);
  689. dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
  690. mtd->writesize);
  691. dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
  692. mtd->oobsize);
  693. return 0;
  694. }
  695. static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
  696. {
  697. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  698. struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  699. uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
  700. uint32_t cs = priv->bank;
  701. /* Save CSOR and CSOR_ext */
  702. csor = ioread32be(&ifc->csor_cs[cs].csor);
  703. csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);
  704. /* chage PageSize 8K and SpareSize 1K*/
  705. csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
  706. iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);
  707. iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);
  708. /* READID */
  709. iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  710. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  711. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
  712. &ifc->ifc_nand.nand_fir0);
  713. iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
  714. &ifc->ifc_nand.nand_fcr0);
  715. iowrite32be(0x0, &ifc->ifc_nand.row3);
  716. iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);
  717. /* Program ROW0/COL0 */
  718. iowrite32be(0x0, &ifc->ifc_nand.row0);
  719. iowrite32be(0x0, &ifc->ifc_nand.col0);
  720. /* set the chip select for NAND Transaction */
  721. iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
  722. /* start read seq */
  723. iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
  724. /* wait for command complete flag or timeout */
  725. wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
  726. IFC_TIMEOUT_MSECS * HZ/1000);
  727. if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
  728. printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
  729. /* Restore CSOR and CSOR_ext */
  730. iowrite32be(csor, &ifc->csor_cs[cs].csor);
  731. iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);
  732. }
  733. static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
  734. {
  735. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  736. struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  737. struct nand_chip *chip = &priv->chip;
  738. struct nand_ecclayout *layout;
  739. u32 csor, ver;
  740. /* Fill in fsl_ifc_mtd structure */
  741. priv->mtd.priv = chip;
  742. priv->mtd.owner = THIS_MODULE;
  743. /* fill in nand_chip structure */
  744. /* set up function call table */
  745. if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
  746. chip->read_byte = fsl_ifc_read_byte16;
  747. else
  748. chip->read_byte = fsl_ifc_read_byte;
  749. chip->write_buf = fsl_ifc_write_buf;
  750. chip->read_buf = fsl_ifc_read_buf;
  751. chip->select_chip = fsl_ifc_select_chip;
  752. chip->cmdfunc = fsl_ifc_cmdfunc;
  753. chip->waitfunc = fsl_ifc_wait;
  754. chip->bbt_td = &bbt_main_descr;
  755. chip->bbt_md = &bbt_mirror_descr;
  756. iowrite32be(0x0, &ifc->ifc_nand.ncfgr);
  757. /* set up nand options */
  758. chip->bbt_options = NAND_BBT_USE_FLASH;
  759. chip->options = NAND_NO_SUBPAGE_WRITE;
  760. if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
  761. chip->read_byte = fsl_ifc_read_byte16;
  762. chip->options |= NAND_BUSWIDTH_16;
  763. } else {
  764. chip->read_byte = fsl_ifc_read_byte;
  765. }
  766. chip->controller = &ifc_nand_ctrl->controller;
  767. chip->priv = priv;
  768. chip->ecc.read_page = fsl_ifc_read_page;
  769. chip->ecc.write_page = fsl_ifc_write_page;
  770. csor = ioread32be(&ifc->csor_cs[priv->bank].csor);
  771. /* Hardware generates ECC per 512 Bytes */
  772. chip->ecc.size = 512;
  773. chip->ecc.bytes = 8;
  774. chip->ecc.strength = 4;
  775. switch (csor & CSOR_NAND_PGS_MASK) {
  776. case CSOR_NAND_PGS_512:
  777. if (chip->options & NAND_BUSWIDTH_16) {
  778. layout = &oob_512_16bit_ecc4;
  779. } else {
  780. layout = &oob_512_8bit_ecc4;
  781. /* Avoid conflict with bad block marker */
  782. bbt_main_descr.offs = 0;
  783. bbt_mirror_descr.offs = 0;
  784. }
  785. priv->bufnum_mask = 15;
  786. break;
  787. case CSOR_NAND_PGS_2K:
  788. layout = &oob_2048_ecc4;
  789. priv->bufnum_mask = 3;
  790. break;
  791. case CSOR_NAND_PGS_4K:
  792. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  793. CSOR_NAND_ECC_MODE_4) {
  794. layout = &oob_4096_ecc4;
  795. } else {
  796. layout = &oob_4096_ecc8;
  797. chip->ecc.bytes = 16;
  798. chip->ecc.strength = 8;
  799. }
  800. priv->bufnum_mask = 1;
  801. break;
  802. case CSOR_NAND_PGS_8K:
  803. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  804. CSOR_NAND_ECC_MODE_4) {
  805. layout = &oob_8192_ecc4;
  806. } else {
  807. layout = &oob_8192_ecc8;
  808. chip->ecc.bytes = 16;
  809. chip->ecc.strength = 8;
  810. }
  811. priv->bufnum_mask = 0;
  812. break;
  813. default:
  814. dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
  815. return -ENODEV;
  816. }
  817. /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
  818. if (csor & CSOR_NAND_ECC_DEC_EN) {
  819. chip->ecc.mode = NAND_ECC_HW;
  820. chip->ecc.layout = layout;
  821. } else {
  822. chip->ecc.mode = NAND_ECC_SOFT;
  823. }
  824. ver = ioread32be(&ifc->ifc_rev);
  825. if (ver == FSL_IFC_V1_1_0)
  826. fsl_ifc_sram_init(priv);
  827. return 0;
  828. }
  829. static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
  830. {
  831. nand_release(&priv->mtd);
  832. kfree(priv->mtd.name);
  833. if (priv->vbase)
  834. iounmap(priv->vbase);
  835. ifc_nand_ctrl->chips[priv->bank] = NULL;
  836. return 0;
  837. }
  838. static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
  839. phys_addr_t addr)
  840. {
  841. u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);
  842. if (!(cspr & CSPR_V))
  843. return 0;
  844. if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
  845. return 0;
  846. return (cspr & CSPR_BA) == convert_ifc_address(addr);
  847. }
  848. static DEFINE_MUTEX(fsl_ifc_nand_mutex);
  849. static int fsl_ifc_nand_probe(struct platform_device *dev)
  850. {
  851. struct fsl_ifc_regs __iomem *ifc;
  852. struct fsl_ifc_mtd *priv;
  853. struct resource res;
  854. static const char *part_probe_types[]
  855. = { "cmdlinepart", "RedBoot", "ofpart", NULL };
  856. int ret;
  857. int bank;
  858. struct device_node *node = dev->dev.of_node;
  859. struct mtd_part_parser_data ppdata;
  860. ppdata.of_node = dev->dev.of_node;
  861. if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
  862. return -ENODEV;
  863. ifc = fsl_ifc_ctrl_dev->regs;
  864. /* get, allocate and map the memory resource */
  865. ret = of_address_to_resource(node, 0, &res);
  866. if (ret) {
  867. dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
  868. return ret;
  869. }
  870. /* find which chip select it is connected to */
  871. for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) {
  872. if (match_bank(ifc, bank, res.start))
  873. break;
  874. }
  875. if (bank >= FSL_IFC_BANK_COUNT) {
  876. dev_err(&dev->dev, "%s: address did not match any chip selects\n",
  877. __func__);
  878. return -ENODEV;
  879. }
  880. priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
  881. if (!priv)
  882. return -ENOMEM;
  883. mutex_lock(&fsl_ifc_nand_mutex);
  884. if (!fsl_ifc_ctrl_dev->nand) {
  885. ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
  886. if (!ifc_nand_ctrl) {
  887. dev_err(&dev->dev, "failed to allocate memory\n");
  888. mutex_unlock(&fsl_ifc_nand_mutex);
  889. return -ENOMEM;
  890. }
  891. ifc_nand_ctrl->read_bytes = 0;
  892. ifc_nand_ctrl->index = 0;
  893. ifc_nand_ctrl->addr = NULL;
  894. fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
  895. spin_lock_init(&ifc_nand_ctrl->controller.lock);
  896. init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
  897. } else {
  898. ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
  899. }
  900. mutex_unlock(&fsl_ifc_nand_mutex);
  901. ifc_nand_ctrl->chips[bank] = priv;
  902. priv->bank = bank;
  903. priv->ctrl = fsl_ifc_ctrl_dev;
  904. priv->dev = &dev->dev;
  905. priv->vbase = ioremap(res.start, resource_size(&res));
  906. if (!priv->vbase) {
  907. dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
  908. ret = -ENOMEM;
  909. goto err;
  910. }
  911. dev_set_drvdata(priv->dev, priv);
  912. iowrite32be(IFC_NAND_EVTER_EN_OPC_EN |
  913. IFC_NAND_EVTER_EN_FTOER_EN |
  914. IFC_NAND_EVTER_EN_WPER_EN,
  915. &ifc->ifc_nand.nand_evter_en);
  916. /* enable NAND Machine Interrupts */
  917. iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN |
  918. IFC_NAND_EVTER_INTR_FTOERIR_EN |
  919. IFC_NAND_EVTER_INTR_WPERIR_EN,
  920. &ifc->ifc_nand.nand_evter_intr_en);
  921. priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
  922. if (!priv->mtd.name) {
  923. ret = -ENOMEM;
  924. goto err;
  925. }
  926. ret = fsl_ifc_chip_init(priv);
  927. if (ret)
  928. goto err;
  929. ret = nand_scan_ident(&priv->mtd, 1, NULL);
  930. if (ret)
  931. goto err;
  932. ret = fsl_ifc_chip_init_tail(&priv->mtd);
  933. if (ret)
  934. goto err;
  935. ret = nand_scan_tail(&priv->mtd);
  936. if (ret)
  937. goto err;
  938. /* First look for RedBoot table or partitions on the command
  939. * line, these take precedence over device tree information */
  940. mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
  941. NULL, 0);
  942. dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
  943. (unsigned long long)res.start, priv->bank);
  944. return 0;
  945. err:
  946. fsl_ifc_chip_remove(priv);
  947. return ret;
  948. }
  949. static int fsl_ifc_nand_remove(struct platform_device *dev)
  950. {
  951. struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
  952. fsl_ifc_chip_remove(priv);
  953. mutex_lock(&fsl_ifc_nand_mutex);
  954. ifc_nand_ctrl->counter--;
  955. if (!ifc_nand_ctrl->counter) {
  956. fsl_ifc_ctrl_dev->nand = NULL;
  957. kfree(ifc_nand_ctrl);
  958. }
  959. mutex_unlock(&fsl_ifc_nand_mutex);
  960. return 0;
  961. }
  962. static const struct of_device_id fsl_ifc_nand_match[] = {
  963. {
  964. .compatible = "fsl,ifc-nand",
  965. },
  966. {}
  967. };
  968. static struct platform_driver fsl_ifc_nand_driver = {
  969. .driver = {
  970. .name = "fsl,ifc-nand",
  971. .owner = THIS_MODULE,
  972. .of_match_table = fsl_ifc_nand_match,
  973. },
  974. .probe = fsl_ifc_nand_probe,
  975. .remove = fsl_ifc_nand_remove,
  976. };
  977. module_platform_driver(fsl_ifc_nand_driver);
  978. MODULE_LICENSE("GPL");
  979. MODULE_AUTHOR("Freescale");
  980. MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");