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mach-bf548
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Kconfig

Kconfig 5.7 KB
Historique Raw

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  1. if (BF54x)
    2. 

  2. 

  3. menu "BF548 Specific Configuration"
    4. 

  4. 

  5. config DEB_DMA_URGENT
    6. 

  6. 	bool "DMA has priority over core for ext. accesses"
    7. 

  7. 	depends on BF54x
    8. 

  8. 	default n
    9. 

  9. 	help
    10. 

  10. 	  Treat any DEB1, DEB2 and DEB3 request as Urgent
    11. 

  11. 

  12. comment "Interrupt Priority Assignment"
    13. 

  13. menu "Priority"
    14. 

  14. 

  15. config IRQ_PLL_WAKEUP
    16. 

  16. 	int "IRQ_PLL_WAKEUP"
    17. 

  17. 	default 7
    18. 

  18. config IRQ_DMAC0_ERR
    19. 

  19. 	int "IRQ_DMAC0_ERR"
    20. 

  20. 	default 7
    21. 

  21. config IRQ_EPPI0_ERR
    22. 

  22. 	int "IRQ_EPPI0_ERR"
    23. 

  23. 	default 7
    24. 

  24. config IRQ_SPORT0_ERR
    25. 

  25. 	int "IRQ_SPORT0_ERR"
    26. 

  26. 	default 7
    27. 

  27. config IRQ_SPORT1_ERR
    28. 

  28. 	int "IRQ_SPORT1_ERR"
    29. 

  29. 	default 7
    30. 

  30. config IRQ_SPI0_ERR
    31. 

  31. 	int "IRQ_SPI0_ERR"
    32. 

  32. 	default 7
    33. 

  33. config IRQ_UART0_ERR
    34. 

  34. 	int "IRQ_UART0_ERR"
    35. 

  35. 	default 7
    36. 

  36. config IRQ_RTC
    37. 

  37. 	int "IRQ_RTC"
    38. 

  38. 	default 8
    39. 

  39. config IRQ_EPPI0
    40. 

  40. 	int "IRQ_EPPI0"
    41. 

  41. 	default 8
    42. 

  42. config IRQ_SPORT0_RX
    43. 

  43. 	int "IRQ_SPORT0_RX"
    44. 

  44. 	default 9
    45. 

  45. config IRQ_SPORT0_TX
    46. 

  46. 	int "IRQ_SPORT0_TX"
    47. 

  47. 	default 9
    48. 

  48. config IRQ_SPORT1_RX
    49. 

  49. 	int "IRQ_SPORT1_RX"
    50. 

  50. 	default 9
    51. 

  51. config IRQ_SPORT1_TX
    52. 

  52. 	int "IRQ_SPORT1_TX"
    53. 

  53. 	default 9
    54. 

  54. config IRQ_SPI0
    55. 

  55. 	int "IRQ_SPI0"
    56. 

  56. 	default 10
    57. 

  57. config IRQ_UART0_RX
    58. 

  58. 	int "IRQ_UART0_RX"
    59. 

  59. 	default 10
    60. 

  60. config IRQ_UART0_TX
    61. 

  61. 	int "IRQ_UART0_TX"
    62. 

  62. 	default 10
    63. 

  63. config IRQ_TIMER8
    64. 

  64. 	int "IRQ_TIMER8"
    65. 

  65. 	default 11
    66. 

  66. config IRQ_TIMER9
    67. 

  67. 	int "IRQ_TIMER9"
    68. 

  68. 	default 11
    69. 

  69. config IRQ_TIMER10
    70. 

  70. 	int "IRQ_TIMER10"
    71. 

  71. 	default 11
    72. 

  72. config IRQ_PINT0
    73. 

  73. 	int "IRQ_PINT0"
    74. 

  74. 	default 12
    75. 

  75. config IRQ_PINT1
    76. 

  76. 	int "IRQ_PINT0"
    77. 

  77. 	default 12
    78. 

  78. config IRQ_MDMAS0
    79. 

  79. 	int "IRQ_MDMAS0"
    80. 

  80. 	default 13
    81. 

  81. config IRQ_MDMAS1
    82. 

  82. 	int "IRQ_DMDMAS1"
    83. 

  83. 	default 13
    84. 

  84. config IRQ_WATCHDOG
    85. 

  85. 	int "IRQ_WATCHDOG"
    86. 

  86. 	default 13
    87. 

  87. config IRQ_DMAC1_ERR
    88. 

  88. 	int "IRQ_DMAC1_ERR"
    89. 

  89. 	default 7
    90. 

  90. config IRQ_SPORT2_ERR
    91. 

  91. 	int "IRQ_SPORT2_ERR"
    92. 

  92. 	default 7
    93. 

  93. config IRQ_SPORT3_ERR
    94. 

  94. 	int "IRQ_SPORT3_ERR"
    95. 

  95. 	default 7
    96. 

  96. config IRQ_MXVR_DATA
    97. 

  97. 	int "IRQ MXVR Data"
    98. 

  98. 	default 7
    99. 

  99. config IRQ_SPI1_ERR
    100. 

  100. 	int "IRQ_SPI1_ERR"
    101. 

  101. 	default 7
    102. 

  102. config IRQ_SPI2_ERR
    103. 

  103. 	int "IRQ_SPI2_ERR"
    104. 

  104. 	default 7
    105. 

  105. config IRQ_UART1_ERR
    106. 

  106. 	int "IRQ_UART1_ERR"
    107. 

  107. 	default 7
    108. 

  108. config IRQ_UART2_ERR
    109. 

  109. 	int "IRQ_UART2_ERR"
    110. 

  110. 	default 7
    111. 

  111. config IRQ_CAN0_ERR
    112. 

  112. 	int "IRQ_CAN0_ERR"
    113. 

  113. 	default 7
    114. 

  114. config IRQ_SPORT2_RX
    115. 

  115. 	int "IRQ_SPORT2_RX"
    116. 

  116. 	default 9
    117. 

  117. config IRQ_SPORT2_TX
    118. 

  118. 	int "IRQ_SPORT2_TX"
    119. 

  119. 	default 9
    120. 

  120. config IRQ_SPORT3_RX
    121. 

  121. 	int "IRQ_SPORT3_RX"
    122. 

  122. 	default 9
    123. 

  123. config IRQ_SPORT3_TX
    124. 

  124. 	int "IRQ_SPORT3_TX"
    125. 

  125. 	default 9
    126. 

  126. config IRQ_EPPI1
    127. 

  127. 	int "IRQ_EPPI1"
    128. 

  128. 	default 9
    129. 

  129. config IRQ_EPPI2
    130. 

  130. 	int "IRQ_EPPI2"
    131. 

  131. 	default 9
    132. 

  132. config IRQ_SPI1
    133. 

  133. 	int "IRQ_SPI1"
    134. 

  134. 	default 10
    135. 

  135. config IRQ_SPI2
    136. 

  136. 	int "IRQ_SPI2"
    137. 

  137. 	default 10
    138. 

  138. config IRQ_UART1_RX
    139. 

  139. 	int "IRQ_UART1_RX"
    140. 

  140. 	default 10
    141. 

  141. config IRQ_UART1_TX
    142. 

  142. 	int "IRQ_UART1_TX"
    143. 

  143. 	default 10
    144. 

  144. config IRQ_ATAPI_RX
    145. 

  145. 	int "IRQ_ATAPI_RX"
    146. 

  146. 	default 10
    147. 

  147. config IRQ_ATAPI_TX
    148. 

  148. 	int "IRQ_ATAPI_TX"
    149. 

  149. 	default 10
    150. 

  150. config IRQ_TWI0
    151. 

  151. 	int "IRQ_TWI0"
    152. 

  152. 	default 11
    153. 

  153. config IRQ_TWI1
    154. 

  154. 	int "IRQ_TWI1"
    155. 

  155. 	default 11
    156. 

  156. config IRQ_CAN0_RX
    157. 

  157. 	int "IRQ_CAN_RX"
    158. 

  158. 	default 11
    159. 

  159. config IRQ_CAN0_TX
    160. 

  160. 	int "IRQ_CAN_TX"
    161. 

  161. 	default 11
    162. 

  162. config IRQ_MDMAS2
    163. 

  163. 	int "IRQ_MDMAS2"
    164. 

  164. 	default 13
    165. 

  165. config IRQ_MDMAS3
    166. 

  166. 	int "IRQ_DMMAS3"
    167. 

  167. 	default 13
    168. 

  168. config IRQ_MXVR_ERR
    169. 

  169. 	int "IRQ_MXVR_ERR"
    170. 

  170. 	default 11
    171. 

  171. config IRQ_MXVR_MSG
    172. 

  172. 	int "IRQ_MXVR_MSG"
    173. 

  173. 	default 11
    174. 

  174. config IRQ_MXVR_PKT
    175. 

  175. 	int "IRQ_MXVR_PKT"
    176. 

  176. 	default 11
    177. 

  177. config IRQ_EPPI1_ERR
    178. 

  178. 	int "IRQ_EPPI1_ERR"
    179. 

  179. 	default 7
    180. 

  180. config IRQ_EPPI2_ERR
    181. 

  181. 	int "IRQ_EPPI2_ERR"
    182. 

  182. 	default 7
    183. 

  183. config IRQ_UART3_ERR
    184. 

  184. 	int "IRQ_UART3_ERR"
    185. 

  185. 	default 7
    186. 

  186. config IRQ_HOST_ERR
    187. 

  187. 	int "IRQ_HOST_ERR"
    188. 

  188. 	default 7
    189. 

  189. config IRQ_PIXC_ERR
    190. 

  190. 	int "IRQ_PIXC_ERR"
    191. 

  191. 	default 7
    192. 

  192. config IRQ_NFC_ERR
    193. 

  193. 	int "IRQ_NFC_ERR"
    194. 

  194. 	default 7
    195. 

  195. config IRQ_ATAPI_ERR
    196. 

  196. 	int "IRQ_ATAPI_ERR"
    197. 

  197. 	default 7
    198. 

  198. config IRQ_CAN1_ERR
    199. 

  199. 	int "IRQ_CAN1_ERR"
    200. 

  200. 	default 7
    201. 

  201. config IRQ_HS_DMA_ERR
    202. 

  202. 	int "IRQ Handshake DMA Status"
    203. 

  203. 	default 7
    204. 

  204. config IRQ_PIXC_IN0
    205. 

  205. 	int "IRQ PIXC IN0"
    206. 

  206. 	default 8
    207. 

  207. config IRQ_PIXC_IN1
    208. 

  208. 	int "IRQ PIXC IN1"
    209. 

  209. 	default 8
    210. 

  210. config IRQ_PIXC_OUT
    211. 

  211. 	int "IRQ PIXC OUT"
    212. 

  212. 	default 8
    213. 

  213. config IRQ_SDH
    214. 

  214. 	int "IRQ SDH"
    215. 

  215. 	default 8
    216. 

  216. config IRQ_CNT
    217. 

  217. 	int "IRQ CNT"
    218. 

  218. 	default 8
    219. 

  219. config IRQ_KEY
    220. 

  220. 	int "IRQ KEY"
    221. 

  221. 	default 8
    222. 

  222. config IRQ_CAN1_RX
    223. 

  223. 	int "IRQ CAN1 RX"
    224. 

  224. 	default 11
    225. 

  225. config IRQ_CAN1_TX
    226. 

  226. 	int "IRQ_CAN1_TX"
    227. 

  227. 	default 11
    228. 

  228. config IRQ_SDH_MASK0
    229. 

  229. 	int "IRQ_SDH_MASK0"
    230. 

  230. 	default 11
    231. 

  231. config IRQ_SDH_MASK1
    232. 

  232. 	int "IRQ_SDH_MASK1"
    233. 

  233. 	default 11
    234. 

  234. config IRQ_USB_INT0
    235. 

  235. 	int "IRQ USB INT0"
    236. 

  236. 	default 11
    237. 

  237. config IRQ_USB_INT1
    238. 

  238. 	int "IRQ USB INT1"
    239. 

  239. 	default 11
    240. 

  240. config IRQ_USB_INT2
    241. 

  241. 	int "IRQ USB INT2"
    242. 

  242. 	default 11
    243. 

  243. config IRQ_USB_DMA
    244. 

  244. 	int "IRQ USB DMA"
    245. 

  245. 	default 11
    246. 

  246. config IRQ_OTPSEC
    247. 

  247. 	int "IRQ OPTSEC"
    248. 

  248. 	default 11
    249. 

  249. config IRQ_TIMER0
    250. 

  250. 	int "IRQ_TIMER0"
    251. 

  251. 	default 11
    252. 

  252. config IRQ_TIMER1
    253. 

  253. 	int "IRQ_TIMER1"
    254. 

  254. 	default 11
    255. 

  255. config IRQ_TIMER2
    256. 

  256. 	int "IRQ_TIMER2"
    257. 

  257. 	default 11
    258. 

  258. config IRQ_TIMER3
    259. 

  259. 	int "IRQ_TIMER3"
    260. 

  260. 	default 11
    261. 

  261. config IRQ_TIMER4
    262. 

  262. 	int "IRQ_TIMER4"
    263. 

  263. 	default 11
    264. 

  264. config IRQ_TIMER5
    265. 

  265. 	int "IRQ_TIMER5"
    266. 

  266. 	default 11
    267. 

  267. config IRQ_TIMER6
    268. 

  268. 	int "IRQ_TIMER6"
    269. 

  269. 	default 11
    270. 

  270. config IRQ_TIMER7
    271. 

  271. 	int "IRQ_TIMER7"
    272. 

  272. 	default 11
    273. 

  273. config IRQ_PINT2
    274. 

  274. 	int "IRQ_PIN2"
    275. 

  275. 	default 11
    276. 

  276. config IRQ_PINT3
    277. 

  277. 	int "IRQ_PIN3"
    278. 

  278. 	default 11
    279. 

  279. 

  280. 	help
    281. 

  281. 	  Enter the priority numbers between 7-13 ONLY.  Others are Reserved.
    282. 

  282. 	  This applies to all the above.  It is not recommended to assign the
    283. 

  283. 	  highest priority number 7 to UART or any other device.
    284. 

  284. 

  285. endmenu
    286. 

  286. 

  287. comment "Pin Interrupt to Port Assignment"
    288. 

  288. menu "Assignment"
    289. 

  289. 

  290. config PINTx_REASSIGN
    291. 

  291. 	bool "Reprogram PINT Assignment"
    292. 

  292. 	default y
    293. 

  293. 	help
    294. 

  294. 	  The interrupt assignment registers controls the pin-to-interrupt
    295. 

  295. 	  assignment in a byte-wide manner. Each option allows you to select
    296. 

  296. 	  a set of pins (High/Low Byte) of an specific Port being mapped
    297. 

  297. 	  to one of the four PIN Interrupts IRQ_PINTx.
    298. 

  298. 

  299. 	  You shouldn't change any of these unless you know exactly what you're doing.
    300. 

  300. 	  Please consult the Blackfin BF54x Processor Hardware Reference Manual.
    301. 

  301. 

  302. config PINT0_ASSIGN
    303. 

  303. 	hex "PINT0_ASSIGN"
    304. 

  304. 	depends on PINTx_REASSIGN
    305. 

  305. 	default 0x00000101
    306. 

  306. config PINT1_ASSIGN
    307. 

  307. 	hex "PINT1_ASSIGN"
    308. 

  308. 	depends on PINTx_REASSIGN
    309. 

  309. 	default 0x01010000
    310. 

  310. config PINT2_ASSIGN
    311. 

  311. 	hex "PINT2_ASSIGN"
    312. 

  312. 	depends on PINTx_REASSIGN
    313. 

  313. 	default 0x07000101
    314. 

  314. config PINT3_ASSIGN
    315. 

  315. 	hex "PINT3_ASSIGN"
    316. 

  316. 	depends on PINTx_REASSIGN
    317. 

  317. 	default 0x02020303
    318. 

  318. 

  319. endmenu
    320. 

  320. 

  321. endmenu
    322. 

  322. 

  323. endif
    324.