hw.h 26 KB

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  1. /*
  2. * Copyright (c) 2008-2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef HW_H
  17. #define HW_H
  18. #include <linux/if_ether.h>
  19. #include <linux/delay.h>
  20. #include <linux/io.h>
  21. #include "mac.h"
  22. #include "ani.h"
  23. #include "eeprom.h"
  24. #include "calib.h"
  25. #include "reg.h"
  26. #include "phy.h"
  27. #include "btcoex.h"
  28. #include "ar9003_mac.h"
  29. #include "../regd.h"
  30. #include "../debug.h"
  31. #define ATHEROS_VENDOR_ID 0x168c
  32. #define AR5416_DEVID_PCI 0x0023
  33. #define AR5416_DEVID_PCIE 0x0024
  34. #define AR9160_DEVID_PCI 0x0027
  35. #define AR9280_DEVID_PCI 0x0029
  36. #define AR9280_DEVID_PCIE 0x002a
  37. #define AR9285_DEVID_PCIE 0x002b
  38. #define AR2427_DEVID_PCIE 0x002c
  39. #define AR9287_DEVID_PCI 0x002d
  40. #define AR9287_DEVID_PCIE 0x002e
  41. #define AR9300_DEVID_PCIE 0x0030
  42. #define AR5416_AR9100_DEVID 0x000b
  43. #define AR_SUBVENDOR_ID_NOG 0x0e11
  44. #define AR_SUBVENDOR_ID_NEW_A 0x7065
  45. #define AR5416_MAGIC 0x19641014
  46. #define AR9280_COEX2WIRE_SUBSYSID 0x309b
  47. #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
  48. #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
  49. #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
  50. #define ATH_DEFAULT_NOISE_FLOOR -95
  51. #define ATH9K_RSSI_BAD -128
  52. /* Register read/write primitives */
  53. #define REG_WRITE(_ah, _reg, _val) \
  54. ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
  55. #define REG_READ(_ah, _reg) \
  56. ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
  57. #define SM(_v, _f) (((_v) << _f##_S) & _f)
  58. #define MS(_v, _f) (((_v) & _f) >> _f##_S)
  59. #define REG_RMW(_a, _r, _set, _clr) \
  60. REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
  61. #define REG_RMW_FIELD(_a, _r, _f, _v) \
  62. REG_WRITE(_a, _r, \
  63. (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
  64. #define REG_READ_FIELD(_a, _r, _f) \
  65. (((REG_READ(_a, _r) & _f) >> _f##_S))
  66. #define REG_SET_BIT(_a, _r, _f) \
  67. REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
  68. #define REG_CLR_BIT(_a, _r, _f) \
  69. REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
  70. #define DO_DELAY(x) do { \
  71. if ((++(x) % 64) == 0) \
  72. udelay(1); \
  73. } while (0)
  74. #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
  75. int r; \
  76. for (r = 0; r < ((iniarray)->ia_rows); r++) { \
  77. REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
  78. INI_RA((iniarray), r, (column))); \
  79. DO_DELAY(regWr); \
  80. } \
  81. } while (0)
  82. #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
  83. #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
  84. #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
  85. #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
  86. #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
  87. #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
  88. #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
  89. #define AR_GPIOD_MASK 0x00001FFF
  90. #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
  91. #define BASE_ACTIVATE_DELAY 100
  92. #define RTC_PLL_SETTLE_DELAY 100
  93. #define COEF_SCALE_S 24
  94. #define HT40_CHANNEL_CENTER_SHIFT 10
  95. #define ATH9K_ANTENNA0_CHAINMASK 0x1
  96. #define ATH9K_ANTENNA1_CHAINMASK 0x2
  97. #define ATH9K_NUM_DMA_DEBUG_REGS 8
  98. #define ATH9K_NUM_QUEUES 10
  99. #define MAX_RATE_POWER 63
  100. #define AH_WAIT_TIMEOUT 100000 /* (us) */
  101. #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
  102. #define AH_TIME_QUANTUM 10
  103. #define AR_KEYTABLE_SIZE 128
  104. #define POWER_UP_TIME 10000
  105. #define SPUR_RSSI_THRESH 40
  106. #define CAB_TIMEOUT_VAL 10
  107. #define BEACON_TIMEOUT_VAL 10
  108. #define MIN_BEACON_TIMEOUT_VAL 1
  109. #define SLEEP_SLOP 3
  110. #define INIT_CONFIG_STATUS 0x00000000
  111. #define INIT_RSSI_THR 0x00000700
  112. #define INIT_BCON_CNTRL_REG 0x00000000
  113. #define TU_TO_USEC(_tu) ((_tu) << 10)
  114. #define ATH9K_HW_RX_HP_QDEPTH 16
  115. #define ATH9K_HW_RX_LP_QDEPTH 128
  116. enum ath_ini_subsys {
  117. ATH_INI_PRE = 0,
  118. ATH_INI_CORE,
  119. ATH_INI_POST,
  120. ATH_INI_NUM_SPLIT,
  121. };
  122. enum wireless_mode {
  123. ATH9K_MODE_11A = 0,
  124. ATH9K_MODE_11G,
  125. ATH9K_MODE_11NA_HT20,
  126. ATH9K_MODE_11NG_HT20,
  127. ATH9K_MODE_11NA_HT40PLUS,
  128. ATH9K_MODE_11NA_HT40MINUS,
  129. ATH9K_MODE_11NG_HT40PLUS,
  130. ATH9K_MODE_11NG_HT40MINUS,
  131. ATH9K_MODE_MAX,
  132. };
  133. enum ath9k_hw_caps {
  134. ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
  135. ATH9K_HW_CAP_MIC_CKIP = BIT(1),
  136. ATH9K_HW_CAP_MIC_TKIP = BIT(2),
  137. ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
  138. ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
  139. ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
  140. ATH9K_HW_CAP_VEOL = BIT(6),
  141. ATH9K_HW_CAP_BSSIDMASK = BIT(7),
  142. ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
  143. ATH9K_HW_CAP_HT = BIT(9),
  144. ATH9K_HW_CAP_GTT = BIT(10),
  145. ATH9K_HW_CAP_FASTCC = BIT(11),
  146. ATH9K_HW_CAP_RFSILENT = BIT(12),
  147. ATH9K_HW_CAP_CST = BIT(13),
  148. ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
  149. ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
  150. ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
  151. ATH9K_HW_CAP_EDMA = BIT(17),
  152. ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
  153. };
  154. enum ath9k_capability_type {
  155. ATH9K_CAP_CIPHER = 0,
  156. ATH9K_CAP_TKIP_MIC,
  157. ATH9K_CAP_TKIP_SPLIT,
  158. ATH9K_CAP_TXPOW,
  159. ATH9K_CAP_MCAST_KEYSRCH,
  160. ATH9K_CAP_DS
  161. };
  162. struct ath9k_hw_capabilities {
  163. u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
  164. DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
  165. u16 total_queues;
  166. u16 keycache_size;
  167. u16 low_5ghz_chan, high_5ghz_chan;
  168. u16 low_2ghz_chan, high_2ghz_chan;
  169. u16 rts_aggr_limit;
  170. u8 tx_chainmask;
  171. u8 rx_chainmask;
  172. u16 tx_triglevel_max;
  173. u16 reg_cap;
  174. u8 num_gpio_pins;
  175. u8 num_antcfg_2ghz;
  176. u8 num_antcfg_5ghz;
  177. u8 rx_hp_qdepth;
  178. u8 rx_lp_qdepth;
  179. u8 rx_status_len;
  180. u8 tx_desc_len;
  181. };
  182. struct ath9k_ops_config {
  183. int dma_beacon_response_time;
  184. int sw_beacon_response_time;
  185. int additional_swba_backoff;
  186. int ack_6mb;
  187. int cwm_ignore_extcca;
  188. u8 pcie_powersave_enable;
  189. u8 pcie_clock_req;
  190. u32 pcie_waen;
  191. u8 analog_shiftreg;
  192. u8 ht_enable;
  193. u32 ofdm_trig_low;
  194. u32 ofdm_trig_high;
  195. u32 cck_trig_high;
  196. u32 cck_trig_low;
  197. u32 enable_ani;
  198. int serialize_regmode;
  199. bool rx_intr_mitigation;
  200. bool tx_intr_mitigation;
  201. #define SPUR_DISABLE 0
  202. #define SPUR_ENABLE_IOCTL 1
  203. #define SPUR_ENABLE_EEPROM 2
  204. #define AR_EEPROM_MODAL_SPURS 5
  205. #define AR_SPUR_5413_1 1640
  206. #define AR_SPUR_5413_2 1200
  207. #define AR_NO_SPUR 0x8000
  208. #define AR_BASE_FREQ_2GHZ 2300
  209. #define AR_BASE_FREQ_5GHZ 4900
  210. #define AR_SPUR_FEEQ_BOUND_HT40 19
  211. #define AR_SPUR_FEEQ_BOUND_HT20 10
  212. int spurmode;
  213. u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
  214. u8 max_txtrig_level;
  215. };
  216. enum ath9k_int {
  217. ATH9K_INT_RX = 0x00000001,
  218. ATH9K_INT_RXDESC = 0x00000002,
  219. ATH9K_INT_RXHP = 0x00000001,
  220. ATH9K_INT_RXLP = 0x00000002,
  221. ATH9K_INT_RXNOFRM = 0x00000008,
  222. ATH9K_INT_RXEOL = 0x00000010,
  223. ATH9K_INT_RXORN = 0x00000020,
  224. ATH9K_INT_TX = 0x00000040,
  225. ATH9K_INT_TXDESC = 0x00000080,
  226. ATH9K_INT_TIM_TIMER = 0x00000100,
  227. ATH9K_INT_TXURN = 0x00000800,
  228. ATH9K_INT_MIB = 0x00001000,
  229. ATH9K_INT_RXPHY = 0x00004000,
  230. ATH9K_INT_RXKCM = 0x00008000,
  231. ATH9K_INT_SWBA = 0x00010000,
  232. ATH9K_INT_BMISS = 0x00040000,
  233. ATH9K_INT_BNR = 0x00100000,
  234. ATH9K_INT_TIM = 0x00200000,
  235. ATH9K_INT_DTIM = 0x00400000,
  236. ATH9K_INT_DTIMSYNC = 0x00800000,
  237. ATH9K_INT_GPIO = 0x01000000,
  238. ATH9K_INT_CABEND = 0x02000000,
  239. ATH9K_INT_TSFOOR = 0x04000000,
  240. ATH9K_INT_GENTIMER = 0x08000000,
  241. ATH9K_INT_CST = 0x10000000,
  242. ATH9K_INT_GTT = 0x20000000,
  243. ATH9K_INT_FATAL = 0x40000000,
  244. ATH9K_INT_GLOBAL = 0x80000000,
  245. ATH9K_INT_BMISC = ATH9K_INT_TIM |
  246. ATH9K_INT_DTIM |
  247. ATH9K_INT_DTIMSYNC |
  248. ATH9K_INT_TSFOOR |
  249. ATH9K_INT_CABEND,
  250. ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
  251. ATH9K_INT_RXDESC |
  252. ATH9K_INT_RXEOL |
  253. ATH9K_INT_RXORN |
  254. ATH9K_INT_TXURN |
  255. ATH9K_INT_TXDESC |
  256. ATH9K_INT_MIB |
  257. ATH9K_INT_RXPHY |
  258. ATH9K_INT_RXKCM |
  259. ATH9K_INT_SWBA |
  260. ATH9K_INT_BMISS |
  261. ATH9K_INT_GPIO,
  262. ATH9K_INT_NOCARD = 0xffffffff
  263. };
  264. #define CHANNEL_CW_INT 0x00002
  265. #define CHANNEL_CCK 0x00020
  266. #define CHANNEL_OFDM 0x00040
  267. #define CHANNEL_2GHZ 0x00080
  268. #define CHANNEL_5GHZ 0x00100
  269. #define CHANNEL_PASSIVE 0x00200
  270. #define CHANNEL_DYN 0x00400
  271. #define CHANNEL_HALF 0x04000
  272. #define CHANNEL_QUARTER 0x08000
  273. #define CHANNEL_HT20 0x10000
  274. #define CHANNEL_HT40PLUS 0x20000
  275. #define CHANNEL_HT40MINUS 0x40000
  276. #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
  277. #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
  278. #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
  279. #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
  280. #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
  281. #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
  282. #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
  283. #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
  284. #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
  285. #define CHANNEL_ALL \
  286. (CHANNEL_OFDM| \
  287. CHANNEL_CCK| \
  288. CHANNEL_2GHZ | \
  289. CHANNEL_5GHZ | \
  290. CHANNEL_HT20 | \
  291. CHANNEL_HT40PLUS | \
  292. CHANNEL_HT40MINUS)
  293. struct ath9k_channel {
  294. struct ieee80211_channel *chan;
  295. u16 channel;
  296. u32 channelFlags;
  297. u32 chanmode;
  298. int32_t CalValid;
  299. bool oneTimeCalsDone;
  300. int8_t iCoff;
  301. int8_t qCoff;
  302. int16_t rawNoiseFloor;
  303. };
  304. #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
  305. (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
  306. (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
  307. (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
  308. #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
  309. #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
  310. #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
  311. #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
  312. #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
  313. #define IS_CHAN_A_5MHZ_SPACED(_c) \
  314. ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
  315. (((_c)->channel % 20) != 0) && \
  316. (((_c)->channel % 10) != 0))
  317. /* These macros check chanmode and not channelFlags */
  318. #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
  319. #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
  320. ((_c)->chanmode == CHANNEL_G_HT20))
  321. #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
  322. ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
  323. ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
  324. ((_c)->chanmode == CHANNEL_G_HT40MINUS))
  325. #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
  326. enum ath9k_power_mode {
  327. ATH9K_PM_AWAKE = 0,
  328. ATH9K_PM_FULL_SLEEP,
  329. ATH9K_PM_NETWORK_SLEEP,
  330. ATH9K_PM_UNDEFINED
  331. };
  332. enum ath9k_tp_scale {
  333. ATH9K_TP_SCALE_MAX = 0,
  334. ATH9K_TP_SCALE_50,
  335. ATH9K_TP_SCALE_25,
  336. ATH9K_TP_SCALE_12,
  337. ATH9K_TP_SCALE_MIN
  338. };
  339. enum ser_reg_mode {
  340. SER_REG_MODE_OFF = 0,
  341. SER_REG_MODE_ON = 1,
  342. SER_REG_MODE_AUTO = 2,
  343. };
  344. enum ath9k_rx_qtype {
  345. ATH9K_RX_QUEUE_HP,
  346. ATH9K_RX_QUEUE_LP,
  347. ATH9K_RX_QUEUE_MAX,
  348. };
  349. struct ath9k_beacon_state {
  350. u32 bs_nexttbtt;
  351. u32 bs_nextdtim;
  352. u32 bs_intval;
  353. #define ATH9K_BEACON_PERIOD 0x0000ffff
  354. #define ATH9K_BEACON_ENA 0x00800000
  355. #define ATH9K_BEACON_RESET_TSF 0x01000000
  356. #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
  357. u32 bs_dtimperiod;
  358. u16 bs_cfpperiod;
  359. u16 bs_cfpmaxduration;
  360. u32 bs_cfpnext;
  361. u16 bs_timoffset;
  362. u16 bs_bmissthreshold;
  363. u32 bs_sleepduration;
  364. u32 bs_tsfoor_threshold;
  365. };
  366. struct chan_centers {
  367. u16 synth_center;
  368. u16 ctl_center;
  369. u16 ext_center;
  370. };
  371. enum {
  372. ATH9K_RESET_POWER_ON,
  373. ATH9K_RESET_WARM,
  374. ATH9K_RESET_COLD,
  375. };
  376. struct ath9k_hw_version {
  377. u32 magic;
  378. u16 devid;
  379. u16 subvendorid;
  380. u32 macVersion;
  381. u16 macRev;
  382. u16 phyRev;
  383. u16 analog5GhzRev;
  384. u16 analog2GhzRev;
  385. u16 subsysid;
  386. };
  387. /* Generic TSF timer definitions */
  388. #define ATH_MAX_GEN_TIMER 16
  389. #define AR_GENTMR_BIT(_index) (1 << (_index))
  390. /*
  391. * Using de Bruijin sequence to to look up 1's index in a 32 bit number
  392. * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
  393. */
  394. #define debruijn32 0x077CB531U
  395. struct ath_gen_timer_configuration {
  396. u32 next_addr;
  397. u32 period_addr;
  398. u32 mode_addr;
  399. u32 mode_mask;
  400. };
  401. struct ath_gen_timer {
  402. void (*trigger)(void *arg);
  403. void (*overflow)(void *arg);
  404. void *arg;
  405. u8 index;
  406. };
  407. struct ath_gen_timer_table {
  408. u32 gen_timer_index[32];
  409. struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
  410. union {
  411. unsigned long timer_bits;
  412. u16 val;
  413. } timer_mask;
  414. };
  415. /**
  416. * struct ath_hw_private_ops - callbacks used internally by hardware code
  417. *
  418. * This structure contains private callbacks designed to only be used internally
  419. * by the hardware core.
  420. *
  421. * @init_cal_settings: setup types of calibrations supported
  422. * @init_cal: starts actual calibration
  423. *
  424. * @init_mode_regs: Initializes mode registers
  425. * @init_mode_gain_regs: Initialize TX/RX gain registers
  426. * @macversion_supported: If this specific mac revision is supported
  427. *
  428. * @rf_set_freq: change frequency
  429. * @spur_mitigate_freq: spur mitigation
  430. * @rf_alloc_ext_banks:
  431. * @rf_free_ext_banks:
  432. * @set_rf_regs:
  433. * @compute_pll_control: compute the PLL control value to use for
  434. * AR_RTC_PLL_CONTROL for a given channel
  435. * @setup_calibration: set up calibration
  436. * @iscal_supported: used to query if a type of calibration is supported
  437. * @loadnf: load noise floor read from each chain on the CCA registers
  438. */
  439. struct ath_hw_private_ops {
  440. /* Calibration ops */
  441. void (*init_cal_settings)(struct ath_hw *ah);
  442. bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
  443. void (*init_mode_regs)(struct ath_hw *ah);
  444. void (*init_mode_gain_regs)(struct ath_hw *ah);
  445. bool (*macversion_supported)(u32 macversion);
  446. void (*setup_calibration)(struct ath_hw *ah,
  447. struct ath9k_cal_list *currCal);
  448. bool (*iscal_supported)(struct ath_hw *ah,
  449. enum ath9k_cal_types calType);
  450. /* PHY ops */
  451. int (*rf_set_freq)(struct ath_hw *ah,
  452. struct ath9k_channel *chan);
  453. void (*spur_mitigate_freq)(struct ath_hw *ah,
  454. struct ath9k_channel *chan);
  455. int (*rf_alloc_ext_banks)(struct ath_hw *ah);
  456. void (*rf_free_ext_banks)(struct ath_hw *ah);
  457. bool (*set_rf_regs)(struct ath_hw *ah,
  458. struct ath9k_channel *chan,
  459. u16 modesIndex);
  460. void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
  461. void (*init_bb)(struct ath_hw *ah,
  462. struct ath9k_channel *chan);
  463. int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
  464. void (*olc_init)(struct ath_hw *ah);
  465. void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
  466. void (*mark_phy_inactive)(struct ath_hw *ah);
  467. void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
  468. bool (*rfbus_req)(struct ath_hw *ah);
  469. void (*rfbus_done)(struct ath_hw *ah);
  470. void (*enable_rfkill)(struct ath_hw *ah);
  471. void (*restore_chainmask)(struct ath_hw *ah);
  472. void (*set_diversity)(struct ath_hw *ah, bool value);
  473. u32 (*compute_pll_control)(struct ath_hw *ah,
  474. struct ath9k_channel *chan);
  475. bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
  476. int param);
  477. void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
  478. void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
  479. };
  480. /**
  481. * struct ath_hw_ops - callbacks used by hardware code and driver code
  482. *
  483. * This structure contains callbacks designed to to be used internally by
  484. * hardware code and also by the lower level driver.
  485. *
  486. * @config_pci_powersave:
  487. * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
  488. */
  489. struct ath_hw_ops {
  490. void (*config_pci_powersave)(struct ath_hw *ah,
  491. int restore,
  492. int power_off);
  493. void (*rx_enable)(struct ath_hw *ah);
  494. void (*set_desc_link)(void *ds, u32 link);
  495. void (*get_desc_link)(void *ds, u32 **link);
  496. bool (*calibrate)(struct ath_hw *ah,
  497. struct ath9k_channel *chan,
  498. u8 rxchainmask,
  499. bool longcal);
  500. bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
  501. };
  502. struct ath_hw {
  503. struct ieee80211_hw *hw;
  504. struct ath_common common;
  505. struct ath9k_hw_version hw_version;
  506. struct ath9k_ops_config config;
  507. struct ath9k_hw_capabilities caps;
  508. struct ath9k_channel channels[38];
  509. struct ath9k_channel *curchan;
  510. union {
  511. struct ar5416_eeprom_def def;
  512. struct ar5416_eeprom_4k map4k;
  513. struct ar9287_eeprom map9287;
  514. struct ar9300_eeprom ar9300_eep;
  515. } eeprom;
  516. const struct eeprom_ops *eep_ops;
  517. bool sw_mgmt_crypto;
  518. bool is_pciexpress;
  519. bool need_an_top2_fixup;
  520. u16 tx_trig_level;
  521. s16 nf_2g_max;
  522. s16 nf_2g_min;
  523. s16 nf_5g_max;
  524. s16 nf_5g_min;
  525. u16 rfsilent;
  526. u32 rfkill_gpio;
  527. u32 rfkill_polarity;
  528. u32 ah_flags;
  529. bool htc_reset_init;
  530. enum nl80211_iftype opmode;
  531. enum ath9k_power_mode power_mode;
  532. struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
  533. struct ath9k_pacal_info pacal_info;
  534. struct ar5416Stats stats;
  535. struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
  536. int16_t curchan_rad_index;
  537. enum ath9k_int imask;
  538. u32 imrs2_reg;
  539. u32 txok_interrupt_mask;
  540. u32 txerr_interrupt_mask;
  541. u32 txdesc_interrupt_mask;
  542. u32 txeol_interrupt_mask;
  543. u32 txurn_interrupt_mask;
  544. bool chip_fullsleep;
  545. u32 atim_window;
  546. /* Calibration */
  547. enum ath9k_cal_types supp_cals;
  548. struct ath9k_cal_list iq_caldata;
  549. struct ath9k_cal_list adcgain_caldata;
  550. struct ath9k_cal_list adcdc_calinitdata;
  551. struct ath9k_cal_list adcdc_caldata;
  552. struct ath9k_cal_list tempCompCalData;
  553. struct ath9k_cal_list *cal_list;
  554. struct ath9k_cal_list *cal_list_last;
  555. struct ath9k_cal_list *cal_list_curr;
  556. #define totalPowerMeasI meas0.unsign
  557. #define totalPowerMeasQ meas1.unsign
  558. #define totalIqCorrMeas meas2.sign
  559. #define totalAdcIOddPhase meas0.unsign
  560. #define totalAdcIEvenPhase meas1.unsign
  561. #define totalAdcQOddPhase meas2.unsign
  562. #define totalAdcQEvenPhase meas3.unsign
  563. #define totalAdcDcOffsetIOddPhase meas0.sign
  564. #define totalAdcDcOffsetIEvenPhase meas1.sign
  565. #define totalAdcDcOffsetQOddPhase meas2.sign
  566. #define totalAdcDcOffsetQEvenPhase meas3.sign
  567. union {
  568. u32 unsign[AR5416_MAX_CHAINS];
  569. int32_t sign[AR5416_MAX_CHAINS];
  570. } meas0;
  571. union {
  572. u32 unsign[AR5416_MAX_CHAINS];
  573. int32_t sign[AR5416_MAX_CHAINS];
  574. } meas1;
  575. union {
  576. u32 unsign[AR5416_MAX_CHAINS];
  577. int32_t sign[AR5416_MAX_CHAINS];
  578. } meas2;
  579. union {
  580. u32 unsign[AR5416_MAX_CHAINS];
  581. int32_t sign[AR5416_MAX_CHAINS];
  582. } meas3;
  583. u16 cal_samples;
  584. u32 sta_id1_defaults;
  585. u32 misc_mode;
  586. enum {
  587. AUTO_32KHZ,
  588. USE_32KHZ,
  589. DONT_USE_32KHZ,
  590. } enable_32kHz_clock;
  591. /* Private to hardware code */
  592. struct ath_hw_private_ops private_ops;
  593. /* Accessed by the lower level driver */
  594. struct ath_hw_ops ops;
  595. /* Used to program the radio on non single-chip devices */
  596. u32 *analogBank0Data;
  597. u32 *analogBank1Data;
  598. u32 *analogBank2Data;
  599. u32 *analogBank3Data;
  600. u32 *analogBank6Data;
  601. u32 *analogBank6TPCData;
  602. u32 *analogBank7Data;
  603. u32 *addac5416_21;
  604. u32 *bank6Temp;
  605. int16_t txpower_indexoffset;
  606. int coverage_class;
  607. u32 beacon_interval;
  608. u32 slottime;
  609. u32 globaltxtimeout;
  610. /* ANI */
  611. u32 proc_phyerr;
  612. u32 aniperiod;
  613. struct ar5416AniState *curani;
  614. struct ar5416AniState ani[255];
  615. int totalSizeDesired[5];
  616. int coarse_high[5];
  617. int coarse_low[5];
  618. int firpwr[5];
  619. enum ath9k_ani_cmd ani_function;
  620. /* Bluetooth coexistance */
  621. struct ath_btcoex_hw btcoex_hw;
  622. u32 intr_txqs;
  623. u8 txchainmask;
  624. u8 rxchainmask;
  625. u32 originalGain[22];
  626. int initPDADC;
  627. int PDADCdelta;
  628. u8 led_pin;
  629. struct ar5416IniArray iniModes;
  630. struct ar5416IniArray iniCommon;
  631. struct ar5416IniArray iniBank0;
  632. struct ar5416IniArray iniBB_RfGain;
  633. struct ar5416IniArray iniBank1;
  634. struct ar5416IniArray iniBank2;
  635. struct ar5416IniArray iniBank3;
  636. struct ar5416IniArray iniBank6;
  637. struct ar5416IniArray iniBank6TPC;
  638. struct ar5416IniArray iniBank7;
  639. struct ar5416IniArray iniAddac;
  640. struct ar5416IniArray iniPcieSerdes;
  641. struct ar5416IniArray iniPcieSerdesLowPower;
  642. struct ar5416IniArray iniModesAdditional;
  643. struct ar5416IniArray iniModesRxGain;
  644. struct ar5416IniArray iniModesTxGain;
  645. struct ar5416IniArray iniModes_9271_1_0_only;
  646. struct ar5416IniArray iniCckfirNormal;
  647. struct ar5416IniArray iniCckfirJapan2484;
  648. struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
  649. struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
  650. struct ar5416IniArray iniModes_9271_ANI_reg;
  651. struct ar5416IniArray iniModes_high_power_tx_gain_9271;
  652. struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
  653. struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
  654. struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
  655. struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
  656. struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
  657. u32 intr_gen_timer_trigger;
  658. u32 intr_gen_timer_thresh;
  659. struct ath_gen_timer_table hw_gen_timers;
  660. };
  661. static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
  662. {
  663. return &ah->common;
  664. }
  665. static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
  666. {
  667. return &(ath9k_hw_common(ah)->regulatory);
  668. }
  669. static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
  670. {
  671. return &ah->private_ops;
  672. }
  673. static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
  674. {
  675. return &ah->ops;
  676. }
  677. /* Initialization, Detach, Reset */
  678. const char *ath9k_hw_probe(u16 vendorid, u16 devid);
  679. void ath9k_hw_deinit(struct ath_hw *ah);
  680. int ath9k_hw_init(struct ath_hw *ah);
  681. int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
  682. bool bChannelChange);
  683. int ath9k_hw_fill_cap_info(struct ath_hw *ah);
  684. bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
  685. u32 capability, u32 *result);
  686. bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
  687. u32 capability, u32 setting, int *status);
  688. u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
  689. /* Key Cache Management */
  690. bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
  691. bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
  692. bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
  693. const struct ath9k_keyval *k,
  694. const u8 *mac);
  695. bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
  696. /* GPIO / RFKILL / Antennae */
  697. void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
  698. u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
  699. void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
  700. u32 ah_signal_type);
  701. void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
  702. u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
  703. void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
  704. /* General Operation */
  705. bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
  706. u32 ath9k_hw_reverse_bits(u32 val, u32 n);
  707. bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
  708. u16 ath9k_hw_computetxtime(struct ath_hw *ah,
  709. u8 phy, int kbps,
  710. u32 frameLen, u16 rateix, bool shortPreamble);
  711. void ath9k_hw_get_channel_centers(struct ath_hw *ah,
  712. struct ath9k_channel *chan,
  713. struct chan_centers *centers);
  714. u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
  715. void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
  716. bool ath9k_hw_phy_disable(struct ath_hw *ah);
  717. bool ath9k_hw_disable(struct ath_hw *ah);
  718. void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
  719. void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
  720. void ath9k_hw_setopmode(struct ath_hw *ah);
  721. void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
  722. void ath9k_hw_setbssidmask(struct ath_hw *ah);
  723. void ath9k_hw_write_associd(struct ath_hw *ah);
  724. u64 ath9k_hw_gettsf64(struct ath_hw *ah);
  725. void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
  726. void ath9k_hw_reset_tsf(struct ath_hw *ah);
  727. void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
  728. u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
  729. void ath9k_hw_init_global_settings(struct ath_hw *ah);
  730. void ath9k_hw_set11nmac2040(struct ath_hw *ah);
  731. void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
  732. void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
  733. const struct ath9k_beacon_state *bs);
  734. bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
  735. /* Generic hw timer primitives */
  736. struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
  737. void (*trigger)(void *),
  738. void (*overflow)(void *),
  739. void *arg,
  740. u8 timer_index);
  741. void ath9k_hw_gen_timer_start(struct ath_hw *ah,
  742. struct ath_gen_timer *timer,
  743. u32 timer_next,
  744. u32 timer_period);
  745. void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
  746. void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
  747. void ath_gen_timer_isr(struct ath_hw *hw);
  748. u32 ath9k_hw_gettsf32(struct ath_hw *ah);
  749. void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
  750. /* HTC */
  751. void ath9k_hw_htc_resetinit(struct ath_hw *ah);
  752. /* PHY */
  753. void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
  754. u32 *coef_mantissa, u32 *coef_exponent);
  755. /*
  756. * Code Specific to AR5008, AR9001 or AR9002,
  757. * we stuff these here to avoid callbacks for AR9003.
  758. */
  759. void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
  760. int ar9002_hw_rf_claim(struct ath_hw *ah);
  761. /*
  762. * Code specifric to AR9003, we stuff these here to avoid callbacks
  763. * for older families
  764. */
  765. void ar9003_hw_set_nf_limits(struct ath_hw *ah);
  766. /* Hardware family op attach helpers */
  767. void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
  768. void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
  769. void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
  770. void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
  771. void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
  772. void ar9002_hw_attach_ops(struct ath_hw *ah);
  773. void ar9003_hw_attach_ops(struct ath_hw *ah);
  774. #define ATH_PCIE_CAP_LINK_CTRL 0x70
  775. #define ATH_PCIE_CAP_LINK_L0S 1
  776. #define ATH_PCIE_CAP_LINK_L1 2
  777. #endif