davinci_voicecodec.h 3.4 KB

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  1. /*
  2. * DaVinci Voice Codec Core Interface for TI platforms
  3. *
  4. * Copyright (C) 2010 Texas Instruments, Inc
  5. *
  6. * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
  23. #define __LINUX_MFD_DAVINIC_VOICECODEC_H_
  24. #include <linux/kernel.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/mfd/core.h>
  27. #include <linux/platform_data/edma.h>
  28. #include <mach/hardware.h>
  29. /*
  30. * Register values.
  31. */
  32. #define DAVINCI_VC_PID 0x00
  33. #define DAVINCI_VC_CTRL 0x04
  34. #define DAVINCI_VC_INTEN 0x08
  35. #define DAVINCI_VC_INTSTATUS 0x0c
  36. #define DAVINCI_VC_INTCLR 0x10
  37. #define DAVINCI_VC_EMUL_CTRL 0x14
  38. #define DAVINCI_VC_RFIFO 0x20
  39. #define DAVINCI_VC_WFIFO 0x24
  40. #define DAVINCI_VC_FIFOSTAT 0x28
  41. #define DAVINCI_VC_TST_CTRL 0x2C
  42. #define DAVINCI_VC_REG05 0x94
  43. #define DAVINCI_VC_REG09 0xA4
  44. #define DAVINCI_VC_REG12 0xB0
  45. /* DAVINCI_VC_CTRL bit fields */
  46. #define DAVINCI_VC_CTRL_MASK 0x5500
  47. #define DAVINCI_VC_CTRL_RSTADC BIT(0)
  48. #define DAVINCI_VC_CTRL_RSTDAC BIT(1)
  49. #define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
  50. #define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
  51. #define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
  52. #define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
  53. #define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
  54. #define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
  55. #define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
  56. #define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
  57. #define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
  58. #define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
  59. /* DAVINCI_VC_INT bit fields */
  60. #define DAVINCI_VC_INT_MASK 0x3F
  61. #define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
  62. #define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
  63. #define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
  64. #define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
  65. #define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
  66. #define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
  67. /* DAVINCI_VC_REG05 bit fields */
  68. #define DAVINCI_VC_REG05_PGA_GAIN 0x07
  69. /* DAVINCI_VC_REG09 bit fields */
  70. #define DAVINCI_VC_REG09_MUTE 0x40
  71. #define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
  72. /* DAVINCI_VC_REG12 bit fields */
  73. #define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
  74. #define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
  75. #define DAVINCI_VC_CELLS 2
  76. enum davinci_vc_cells {
  77. DAVINCI_VC_VCIF_CELL,
  78. DAVINCI_VC_CQ93VC_CELL,
  79. };
  80. struct davinci_vcif {
  81. struct platform_device *pdev;
  82. u32 dma_tx_channel;
  83. u32 dma_rx_channel;
  84. dma_addr_t dma_tx_addr;
  85. dma_addr_t dma_rx_addr;
  86. };
  87. struct cq93vc {
  88. struct platform_device *pdev;
  89. struct snd_soc_codec *codec;
  90. u32 sysclk;
  91. };
  92. struct davinci_vc;
  93. struct davinci_vc {
  94. /* Device data */
  95. struct device *dev;
  96. struct platform_device *pdev;
  97. struct clk *clk;
  98. /* Memory resources */
  99. void __iomem *base;
  100. /* MFD cells */
  101. struct mfd_cell cells[DAVINCI_VC_CELLS];
  102. /* Client devices */
  103. struct davinci_vcif davinci_vcif;
  104. struct cq93vc cq93vc;
  105. };
  106. #endif