bnx2x_main.c 343 KB

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  1. /* bnx2x_main.c: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. * UDP CSUM errata workaround by Arik Gendelman
  13. * Slowpath and fastpath rework by Vladislav Zolotarov
  14. * Statistics and Link management by Yitchak Gertner
  15. *
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/module.h>
  19. #include <linux/moduleparam.h>
  20. #include <linux/kernel.h>
  21. #include <linux/device.h> /* for dev_info() */
  22. #include <linux/timer.h>
  23. #include <linux/errno.h>
  24. #include <linux/ioport.h>
  25. #include <linux/slab.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/pci.h>
  28. #include <linux/init.h>
  29. #include <linux/netdevice.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/skbuff.h>
  32. #include <linux/dma-mapping.h>
  33. #include <linux/bitops.h>
  34. #include <linux/irq.h>
  35. #include <linux/delay.h>
  36. #include <asm/byteorder.h>
  37. #include <linux/time.h>
  38. #include <linux/ethtool.h>
  39. #include <linux/mii.h>
  40. #include <linux/if_vlan.h>
  41. #include <net/ip.h>
  42. #include <net/ipv6.h>
  43. #include <net/tcp.h>
  44. #include <net/checksum.h>
  45. #include <net/ip6_checksum.h>
  46. #include <linux/workqueue.h>
  47. #include <linux/crc32.h>
  48. #include <linux/crc32c.h>
  49. #include <linux/prefetch.h>
  50. #include <linux/zlib.h>
  51. #include <linux/io.h>
  52. #include <linux/semaphore.h>
  53. #include <linux/stringify.h>
  54. #include <linux/vmalloc.h>
  55. #include "bnx2x.h"
  56. #include "bnx2x_init.h"
  57. #include "bnx2x_init_ops.h"
  58. #include "bnx2x_cmn.h"
  59. #include "bnx2x_dcb.h"
  60. #include "bnx2x_sp.h"
  61. #include <linux/firmware.h>
  62. #include "bnx2x_fw_file_hdr.h"
  63. /* FW files */
  64. #define FW_FILE_VERSION \
  65. __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
  66. __stringify(BCM_5710_FW_MINOR_VERSION) "." \
  67. __stringify(BCM_5710_FW_REVISION_VERSION) "." \
  68. __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  69. #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  70. #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  71. #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  72. #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
  73. /* Time in jiffies before concluding the transmitter is hung */
  74. #define TX_TIMEOUT (5*HZ)
  75. static char version[] __devinitdata =
  76. "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  77. DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  78. MODULE_AUTHOR("Eliezer Tamir");
  79. MODULE_DESCRIPTION("Broadcom NetXtreme II "
  80. "BCM57710/57711/57711E/"
  81. "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  82. "57840/57840_MF Driver");
  83. MODULE_LICENSE("GPL");
  84. MODULE_VERSION(DRV_MODULE_VERSION);
  85. MODULE_FIRMWARE(FW_FILE_NAME_E1);
  86. MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  87. MODULE_FIRMWARE(FW_FILE_NAME_E2);
  88. int num_queues;
  89. module_param(num_queues, int, 0);
  90. MODULE_PARM_DESC(num_queues,
  91. " Set number of queues (default is as a number of CPUs)");
  92. static int disable_tpa;
  93. module_param(disable_tpa, int, 0);
  94. MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
  95. #define INT_MODE_INTx 1
  96. #define INT_MODE_MSI 2
  97. int int_mode;
  98. module_param(int_mode, int, 0);
  99. MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
  100. "(1 INT#x; 2 MSI)");
  101. static int dropless_fc;
  102. module_param(dropless_fc, int, 0);
  103. MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
  104. static int mrrs = -1;
  105. module_param(mrrs, int, 0);
  106. MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
  107. static int debug;
  108. module_param(debug, int, 0);
  109. MODULE_PARM_DESC(debug, " Default debug msglevel");
  110. struct workqueue_struct *bnx2x_wq;
  111. enum bnx2x_board_type {
  112. BCM57710 = 0,
  113. BCM57711,
  114. BCM57711E,
  115. BCM57712,
  116. BCM57712_MF,
  117. BCM57800,
  118. BCM57800_MF,
  119. BCM57810,
  120. BCM57810_MF,
  121. BCM57840_O,
  122. BCM57840_4_10,
  123. BCM57840_2_20,
  124. BCM57840_MFO,
  125. BCM57840_MF,
  126. BCM57811,
  127. BCM57811_MF
  128. };
  129. /* indexed by board_type, above */
  130. static struct {
  131. char *name;
  132. } board_info[] __devinitdata = {
  133. { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
  134. { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
  135. { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
  136. { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
  137. { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
  138. { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
  139. { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
  140. { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
  141. { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
  142. { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
  143. { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
  144. { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
  145. { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
  146. { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
  147. { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
  148. { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
  149. };
  150. #ifndef PCI_DEVICE_ID_NX2_57710
  151. #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
  152. #endif
  153. #ifndef PCI_DEVICE_ID_NX2_57711
  154. #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
  155. #endif
  156. #ifndef PCI_DEVICE_ID_NX2_57711E
  157. #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
  158. #endif
  159. #ifndef PCI_DEVICE_ID_NX2_57712
  160. #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
  161. #endif
  162. #ifndef PCI_DEVICE_ID_NX2_57712_MF
  163. #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
  164. #endif
  165. #ifndef PCI_DEVICE_ID_NX2_57800
  166. #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
  167. #endif
  168. #ifndef PCI_DEVICE_ID_NX2_57800_MF
  169. #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
  170. #endif
  171. #ifndef PCI_DEVICE_ID_NX2_57810
  172. #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
  173. #endif
  174. #ifndef PCI_DEVICE_ID_NX2_57810_MF
  175. #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
  176. #endif
  177. #ifndef PCI_DEVICE_ID_NX2_57840_O
  178. #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
  179. #endif
  180. #ifndef PCI_DEVICE_ID_NX2_57840_4_10
  181. #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
  182. #endif
  183. #ifndef PCI_DEVICE_ID_NX2_57840_2_20
  184. #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
  185. #endif
  186. #ifndef PCI_DEVICE_ID_NX2_57840_MFO
  187. #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
  188. #endif
  189. #ifndef PCI_DEVICE_ID_NX2_57840_MF
  190. #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
  191. #endif
  192. #ifndef PCI_DEVICE_ID_NX2_57811
  193. #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
  194. #endif
  195. #ifndef PCI_DEVICE_ID_NX2_57811_MF
  196. #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
  197. #endif
  198. static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
  199. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
  200. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
  201. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
  202. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
  203. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
  204. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
  205. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
  206. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
  207. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
  208. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
  209. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
  210. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
  211. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
  212. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
  213. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
  214. { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
  215. { 0 }
  216. };
  217. MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
  218. /* Global resources for unloading a previously loaded device */
  219. #define BNX2X_PREV_WAIT_NEEDED 1
  220. static DEFINE_SEMAPHORE(bnx2x_prev_sem);
  221. static LIST_HEAD(bnx2x_prev_list);
  222. /****************************************************************************
  223. * General service functions
  224. ****************************************************************************/
  225. static void __storm_memset_dma_mapping(struct bnx2x *bp,
  226. u32 addr, dma_addr_t mapping)
  227. {
  228. REG_WR(bp, addr, U64_LO(mapping));
  229. REG_WR(bp, addr + 4, U64_HI(mapping));
  230. }
  231. static void storm_memset_spq_addr(struct bnx2x *bp,
  232. dma_addr_t mapping, u16 abs_fid)
  233. {
  234. u32 addr = XSEM_REG_FAST_MEMORY +
  235. XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
  236. __storm_memset_dma_mapping(bp, addr, mapping);
  237. }
  238. static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
  239. u16 pf_id)
  240. {
  241. REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
  242. pf_id);
  243. REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
  244. pf_id);
  245. REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
  246. pf_id);
  247. REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
  248. pf_id);
  249. }
  250. static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
  251. u8 enable)
  252. {
  253. REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
  254. enable);
  255. REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
  256. enable);
  257. REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
  258. enable);
  259. REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
  260. enable);
  261. }
  262. static void storm_memset_eq_data(struct bnx2x *bp,
  263. struct event_ring_data *eq_data,
  264. u16 pfid)
  265. {
  266. size_t size = sizeof(struct event_ring_data);
  267. u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
  268. __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
  269. }
  270. static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
  271. u16 pfid)
  272. {
  273. u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
  274. REG_WR16(bp, addr, eq_prod);
  275. }
  276. /* used only at init
  277. * locking is done by mcp
  278. */
  279. static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
  280. {
  281. pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
  282. pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
  283. pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
  284. PCICFG_VENDOR_ID_OFFSET);
  285. }
  286. static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
  287. {
  288. u32 val;
  289. pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
  290. pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
  291. pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
  292. PCICFG_VENDOR_ID_OFFSET);
  293. return val;
  294. }
  295. #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
  296. #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
  297. #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
  298. #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
  299. #define DMAE_DP_DST_NONE "dst_addr [none]"
  300. /* copy command into DMAE command memory and set DMAE command go */
  301. void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
  302. {
  303. u32 cmd_offset;
  304. int i;
  305. cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
  306. for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
  307. REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
  308. }
  309. REG_WR(bp, dmae_reg_go_c[idx], 1);
  310. }
  311. u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
  312. {
  313. return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
  314. DMAE_CMD_C_ENABLE);
  315. }
  316. u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
  317. {
  318. return opcode & ~DMAE_CMD_SRC_RESET;
  319. }
  320. u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
  321. bool with_comp, u8 comp_type)
  322. {
  323. u32 opcode = 0;
  324. opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
  325. (dst_type << DMAE_COMMAND_DST_SHIFT));
  326. opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
  327. opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
  328. opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
  329. (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
  330. opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
  331. #ifdef __BIG_ENDIAN
  332. opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
  333. #else
  334. opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
  335. #endif
  336. if (with_comp)
  337. opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
  338. return opcode;
  339. }
  340. static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
  341. struct dmae_command *dmae,
  342. u8 src_type, u8 dst_type)
  343. {
  344. memset(dmae, 0, sizeof(struct dmae_command));
  345. /* set the opcode */
  346. dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
  347. true, DMAE_COMP_PCI);
  348. /* fill in the completion parameters */
  349. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
  350. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
  351. dmae->comp_val = DMAE_COMP_VAL;
  352. }
  353. /* issue a dmae command over the init-channel and wailt for completion */
  354. static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
  355. struct dmae_command *dmae)
  356. {
  357. u32 *wb_comp = bnx2x_sp(bp, wb_comp);
  358. int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
  359. int rc = 0;
  360. /*
  361. * Lock the dmae channel. Disable BHs to prevent a dead-lock
  362. * as long as this code is called both from syscall context and
  363. * from ndo_set_rx_mode() flow that may be called from BH.
  364. */
  365. spin_lock_bh(&bp->dmae_lock);
  366. /* reset completion */
  367. *wb_comp = 0;
  368. /* post the command on the channel used for initializations */
  369. bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
  370. /* wait for completion */
  371. udelay(5);
  372. while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
  373. if (!cnt ||
  374. (bp->recovery_state != BNX2X_RECOVERY_DONE &&
  375. bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
  376. BNX2X_ERR("DMAE timeout!\n");
  377. rc = DMAE_TIMEOUT;
  378. goto unlock;
  379. }
  380. cnt--;
  381. udelay(50);
  382. }
  383. if (*wb_comp & DMAE_PCI_ERR_FLAG) {
  384. BNX2X_ERR("DMAE PCI error!\n");
  385. rc = DMAE_PCI_ERROR;
  386. }
  387. unlock:
  388. spin_unlock_bh(&bp->dmae_lock);
  389. return rc;
  390. }
  391. void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
  392. u32 len32)
  393. {
  394. struct dmae_command dmae;
  395. if (!bp->dmae_ready) {
  396. u32 *data = bnx2x_sp(bp, wb_data[0]);
  397. if (CHIP_IS_E1(bp))
  398. bnx2x_init_ind_wr(bp, dst_addr, data, len32);
  399. else
  400. bnx2x_init_str_wr(bp, dst_addr, data, len32);
  401. return;
  402. }
  403. /* set opcode and fixed command fields */
  404. bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
  405. /* fill in addresses and len */
  406. dmae.src_addr_lo = U64_LO(dma_addr);
  407. dmae.src_addr_hi = U64_HI(dma_addr);
  408. dmae.dst_addr_lo = dst_addr >> 2;
  409. dmae.dst_addr_hi = 0;
  410. dmae.len = len32;
  411. /* issue the command and wait for completion */
  412. bnx2x_issue_dmae_with_comp(bp, &dmae);
  413. }
  414. void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
  415. {
  416. struct dmae_command dmae;
  417. if (!bp->dmae_ready) {
  418. u32 *data = bnx2x_sp(bp, wb_data[0]);
  419. int i;
  420. if (CHIP_IS_E1(bp))
  421. for (i = 0; i < len32; i++)
  422. data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
  423. else
  424. for (i = 0; i < len32; i++)
  425. data[i] = REG_RD(bp, src_addr + i*4);
  426. return;
  427. }
  428. /* set opcode and fixed command fields */
  429. bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
  430. /* fill in addresses and len */
  431. dmae.src_addr_lo = src_addr >> 2;
  432. dmae.src_addr_hi = 0;
  433. dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
  434. dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
  435. dmae.len = len32;
  436. /* issue the command and wait for completion */
  437. bnx2x_issue_dmae_with_comp(bp, &dmae);
  438. }
  439. static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
  440. u32 addr, u32 len)
  441. {
  442. int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
  443. int offset = 0;
  444. while (len > dmae_wr_max) {
  445. bnx2x_write_dmae(bp, phys_addr + offset,
  446. addr + offset, dmae_wr_max);
  447. offset += dmae_wr_max * 4;
  448. len -= dmae_wr_max;
  449. }
  450. bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
  451. }
  452. static int bnx2x_mc_assert(struct bnx2x *bp)
  453. {
  454. char last_idx;
  455. int i, rc = 0;
  456. u32 row0, row1, row2, row3;
  457. /* XSTORM */
  458. last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
  459. XSTORM_ASSERT_LIST_INDEX_OFFSET);
  460. if (last_idx)
  461. BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
  462. /* print the asserts */
  463. for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
  464. row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
  465. XSTORM_ASSERT_LIST_OFFSET(i));
  466. row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
  467. XSTORM_ASSERT_LIST_OFFSET(i) + 4);
  468. row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
  469. XSTORM_ASSERT_LIST_OFFSET(i) + 8);
  470. row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
  471. XSTORM_ASSERT_LIST_OFFSET(i) + 12);
  472. if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
  473. BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
  474. i, row3, row2, row1, row0);
  475. rc++;
  476. } else {
  477. break;
  478. }
  479. }
  480. /* TSTORM */
  481. last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
  482. TSTORM_ASSERT_LIST_INDEX_OFFSET);
  483. if (last_idx)
  484. BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
  485. /* print the asserts */
  486. for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
  487. row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
  488. TSTORM_ASSERT_LIST_OFFSET(i));
  489. row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
  490. TSTORM_ASSERT_LIST_OFFSET(i) + 4);
  491. row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
  492. TSTORM_ASSERT_LIST_OFFSET(i) + 8);
  493. row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
  494. TSTORM_ASSERT_LIST_OFFSET(i) + 12);
  495. if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
  496. BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
  497. i, row3, row2, row1, row0);
  498. rc++;
  499. } else {
  500. break;
  501. }
  502. }
  503. /* CSTORM */
  504. last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
  505. CSTORM_ASSERT_LIST_INDEX_OFFSET);
  506. if (last_idx)
  507. BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
  508. /* print the asserts */
  509. for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
  510. row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
  511. CSTORM_ASSERT_LIST_OFFSET(i));
  512. row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
  513. CSTORM_ASSERT_LIST_OFFSET(i) + 4);
  514. row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
  515. CSTORM_ASSERT_LIST_OFFSET(i) + 8);
  516. row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
  517. CSTORM_ASSERT_LIST_OFFSET(i) + 12);
  518. if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
  519. BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
  520. i, row3, row2, row1, row0);
  521. rc++;
  522. } else {
  523. break;
  524. }
  525. }
  526. /* USTORM */
  527. last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
  528. USTORM_ASSERT_LIST_INDEX_OFFSET);
  529. if (last_idx)
  530. BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
  531. /* print the asserts */
  532. for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
  533. row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
  534. USTORM_ASSERT_LIST_OFFSET(i));
  535. row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
  536. USTORM_ASSERT_LIST_OFFSET(i) + 4);
  537. row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
  538. USTORM_ASSERT_LIST_OFFSET(i) + 8);
  539. row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
  540. USTORM_ASSERT_LIST_OFFSET(i) + 12);
  541. if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
  542. BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
  543. i, row3, row2, row1, row0);
  544. rc++;
  545. } else {
  546. break;
  547. }
  548. }
  549. return rc;
  550. }
  551. void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
  552. {
  553. u32 addr, val;
  554. u32 mark, offset;
  555. __be32 data[9];
  556. int word;
  557. u32 trace_shmem_base;
  558. if (BP_NOMCP(bp)) {
  559. BNX2X_ERR("NO MCP - can not dump\n");
  560. return;
  561. }
  562. netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
  563. (bp->common.bc_ver & 0xff0000) >> 16,
  564. (bp->common.bc_ver & 0xff00) >> 8,
  565. (bp->common.bc_ver & 0xff));
  566. val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
  567. if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
  568. BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
  569. if (BP_PATH(bp) == 0)
  570. trace_shmem_base = bp->common.shmem_base;
  571. else
  572. trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
  573. addr = trace_shmem_base - 0x800;
  574. /* validate TRCB signature */
  575. mark = REG_RD(bp, addr);
  576. if (mark != MFW_TRACE_SIGNATURE) {
  577. BNX2X_ERR("Trace buffer signature is missing.");
  578. return ;
  579. }
  580. /* read cyclic buffer pointer */
  581. addr += 4;
  582. mark = REG_RD(bp, addr);
  583. mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
  584. + ((mark + 0x3) & ~0x3) - 0x08000000;
  585. printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
  586. printk("%s", lvl);
  587. for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
  588. for (word = 0; word < 8; word++)
  589. data[word] = htonl(REG_RD(bp, offset + 4*word));
  590. data[8] = 0x0;
  591. pr_cont("%s", (char *)data);
  592. }
  593. for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
  594. for (word = 0; word < 8; word++)
  595. data[word] = htonl(REG_RD(bp, offset + 4*word));
  596. data[8] = 0x0;
  597. pr_cont("%s", (char *)data);
  598. }
  599. printk("%s" "end of fw dump\n", lvl);
  600. }
  601. static void bnx2x_fw_dump(struct bnx2x *bp)
  602. {
  603. bnx2x_fw_dump_lvl(bp, KERN_ERR);
  604. }
  605. void bnx2x_panic_dump(struct bnx2x *bp)
  606. {
  607. int i;
  608. u16 j;
  609. struct hc_sp_status_block_data sp_sb_data;
  610. int func = BP_FUNC(bp);
  611. #ifdef BNX2X_STOP_ON_ERROR
  612. u16 start = 0, end = 0;
  613. u8 cos;
  614. #endif
  615. bp->stats_state = STATS_STATE_DISABLED;
  616. bp->eth_stats.unrecoverable_error++;
  617. DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
  618. BNX2X_ERR("begin crash dump -----------------\n");
  619. /* Indices */
  620. /* Common */
  621. BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
  622. bp->def_idx, bp->def_att_idx, bp->attn_state,
  623. bp->spq_prod_idx, bp->stats_counter);
  624. BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
  625. bp->def_status_blk->atten_status_block.attn_bits,
  626. bp->def_status_blk->atten_status_block.attn_bits_ack,
  627. bp->def_status_blk->atten_status_block.status_block_id,
  628. bp->def_status_blk->atten_status_block.attn_bits_index);
  629. BNX2X_ERR(" def (");
  630. for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
  631. pr_cont("0x%x%s",
  632. bp->def_status_blk->sp_sb.index_values[i],
  633. (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
  634. for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
  635. *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
  636. CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
  637. i*sizeof(u32));
  638. pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
  639. sp_sb_data.igu_sb_id,
  640. sp_sb_data.igu_seg_id,
  641. sp_sb_data.p_func.pf_id,
  642. sp_sb_data.p_func.vnic_id,
  643. sp_sb_data.p_func.vf_id,
  644. sp_sb_data.p_func.vf_valid,
  645. sp_sb_data.state);
  646. for_each_eth_queue(bp, i) {
  647. struct bnx2x_fastpath *fp = &bp->fp[i];
  648. int loop;
  649. struct hc_status_block_data_e2 sb_data_e2;
  650. struct hc_status_block_data_e1x sb_data_e1x;
  651. struct hc_status_block_sm *hc_sm_p =
  652. CHIP_IS_E1x(bp) ?
  653. sb_data_e1x.common.state_machine :
  654. sb_data_e2.common.state_machine;
  655. struct hc_index_data *hc_index_p =
  656. CHIP_IS_E1x(bp) ?
  657. sb_data_e1x.index_data :
  658. sb_data_e2.index_data;
  659. u8 data_size, cos;
  660. u32 *sb_data_p;
  661. struct bnx2x_fp_txdata txdata;
  662. /* Rx */
  663. BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
  664. i, fp->rx_bd_prod, fp->rx_bd_cons,
  665. fp->rx_comp_prod,
  666. fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
  667. BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
  668. fp->rx_sge_prod, fp->last_max_sge,
  669. le16_to_cpu(fp->fp_hc_idx));
  670. /* Tx */
  671. for_each_cos_in_tx_queue(fp, cos)
  672. {
  673. txdata = *fp->txdata_ptr[cos];
  674. BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
  675. i, txdata.tx_pkt_prod,
  676. txdata.tx_pkt_cons, txdata.tx_bd_prod,
  677. txdata.tx_bd_cons,
  678. le16_to_cpu(*txdata.tx_cons_sb));
  679. }
  680. loop = CHIP_IS_E1x(bp) ?
  681. HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
  682. /* host sb data */
  683. #ifdef BCM_CNIC
  684. if (IS_FCOE_FP(fp))
  685. continue;
  686. #endif
  687. BNX2X_ERR(" run indexes (");
  688. for (j = 0; j < HC_SB_MAX_SM; j++)
  689. pr_cont("0x%x%s",
  690. fp->sb_running_index[j],
  691. (j == HC_SB_MAX_SM - 1) ? ")" : " ");
  692. BNX2X_ERR(" indexes (");
  693. for (j = 0; j < loop; j++)
  694. pr_cont("0x%x%s",
  695. fp->sb_index_values[j],
  696. (j == loop - 1) ? ")" : " ");
  697. /* fw sb data */
  698. data_size = CHIP_IS_E1x(bp) ?
  699. sizeof(struct hc_status_block_data_e1x) :
  700. sizeof(struct hc_status_block_data_e2);
  701. data_size /= sizeof(u32);
  702. sb_data_p = CHIP_IS_E1x(bp) ?
  703. (u32 *)&sb_data_e1x :
  704. (u32 *)&sb_data_e2;
  705. /* copy sb data in here */
  706. for (j = 0; j < data_size; j++)
  707. *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
  708. CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
  709. j * sizeof(u32));
  710. if (!CHIP_IS_E1x(bp)) {
  711. pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
  712. sb_data_e2.common.p_func.pf_id,
  713. sb_data_e2.common.p_func.vf_id,
  714. sb_data_e2.common.p_func.vf_valid,
  715. sb_data_e2.common.p_func.vnic_id,
  716. sb_data_e2.common.same_igu_sb_1b,
  717. sb_data_e2.common.state);
  718. } else {
  719. pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
  720. sb_data_e1x.common.p_func.pf_id,
  721. sb_data_e1x.common.p_func.vf_id,
  722. sb_data_e1x.common.p_func.vf_valid,
  723. sb_data_e1x.common.p_func.vnic_id,
  724. sb_data_e1x.common.same_igu_sb_1b,
  725. sb_data_e1x.common.state);
  726. }
  727. /* SB_SMs data */
  728. for (j = 0; j < HC_SB_MAX_SM; j++) {
  729. pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
  730. j, hc_sm_p[j].__flags,
  731. hc_sm_p[j].igu_sb_id,
  732. hc_sm_p[j].igu_seg_id,
  733. hc_sm_p[j].time_to_expire,
  734. hc_sm_p[j].timer_value);
  735. }
  736. /* Indecies data */
  737. for (j = 0; j < loop; j++) {
  738. pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
  739. hc_index_p[j].flags,
  740. hc_index_p[j].timeout);
  741. }
  742. }
  743. #ifdef BNX2X_STOP_ON_ERROR
  744. /* Rings */
  745. /* Rx */
  746. for_each_rx_queue(bp, i) {
  747. struct bnx2x_fastpath *fp = &bp->fp[i];
  748. start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
  749. end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
  750. for (j = start; j != end; j = RX_BD(j + 1)) {
  751. u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
  752. struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
  753. BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
  754. i, j, rx_bd[1], rx_bd[0], sw_bd->data);
  755. }
  756. start = RX_SGE(fp->rx_sge_prod);
  757. end = RX_SGE(fp->last_max_sge);
  758. for (j = start; j != end; j = RX_SGE(j + 1)) {
  759. u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
  760. struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
  761. BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
  762. i, j, rx_sge[1], rx_sge[0], sw_page->page);
  763. }
  764. start = RCQ_BD(fp->rx_comp_cons - 10);
  765. end = RCQ_BD(fp->rx_comp_cons + 503);
  766. for (j = start; j != end; j = RCQ_BD(j + 1)) {
  767. u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
  768. BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
  769. i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
  770. }
  771. }
  772. /* Tx */
  773. for_each_tx_queue(bp, i) {
  774. struct bnx2x_fastpath *fp = &bp->fp[i];
  775. for_each_cos_in_tx_queue(fp, cos) {
  776. struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
  777. start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
  778. end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
  779. for (j = start; j != end; j = TX_BD(j + 1)) {
  780. struct sw_tx_bd *sw_bd =
  781. &txdata->tx_buf_ring[j];
  782. BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
  783. i, cos, j, sw_bd->skb,
  784. sw_bd->first_bd);
  785. }
  786. start = TX_BD(txdata->tx_bd_cons - 10);
  787. end = TX_BD(txdata->tx_bd_cons + 254);
  788. for (j = start; j != end; j = TX_BD(j + 1)) {
  789. u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
  790. BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
  791. i, cos, j, tx_bd[0], tx_bd[1],
  792. tx_bd[2], tx_bd[3]);
  793. }
  794. }
  795. }
  796. #endif
  797. bnx2x_fw_dump(bp);
  798. bnx2x_mc_assert(bp);
  799. BNX2X_ERR("end crash dump -----------------\n");
  800. }
  801. /*
  802. * FLR Support for E2
  803. *
  804. * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
  805. * initialization.
  806. */
  807. #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
  808. #define FLR_WAIT_INTERVAL 50 /* usec */
  809. #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
  810. struct pbf_pN_buf_regs {
  811. int pN;
  812. u32 init_crd;
  813. u32 crd;
  814. u32 crd_freed;
  815. };
  816. struct pbf_pN_cmd_regs {
  817. int pN;
  818. u32 lines_occup;
  819. u32 lines_freed;
  820. };
  821. static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
  822. struct pbf_pN_buf_regs *regs,
  823. u32 poll_count)
  824. {
  825. u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
  826. u32 cur_cnt = poll_count;
  827. crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
  828. crd = crd_start = REG_RD(bp, regs->crd);
  829. init_crd = REG_RD(bp, regs->init_crd);
  830. DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
  831. DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
  832. DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
  833. while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
  834. (init_crd - crd_start))) {
  835. if (cur_cnt--) {
  836. udelay(FLR_WAIT_INTERVAL);
  837. crd = REG_RD(bp, regs->crd);
  838. crd_freed = REG_RD(bp, regs->crd_freed);
  839. } else {
  840. DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
  841. regs->pN);
  842. DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
  843. regs->pN, crd);
  844. DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
  845. regs->pN, crd_freed);
  846. break;
  847. }
  848. }
  849. DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
  850. poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
  851. }
  852. static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
  853. struct pbf_pN_cmd_regs *regs,
  854. u32 poll_count)
  855. {
  856. u32 occup, to_free, freed, freed_start;
  857. u32 cur_cnt = poll_count;
  858. occup = to_free = REG_RD(bp, regs->lines_occup);
  859. freed = freed_start = REG_RD(bp, regs->lines_freed);
  860. DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
  861. DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
  862. while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
  863. if (cur_cnt--) {
  864. udelay(FLR_WAIT_INTERVAL);
  865. occup = REG_RD(bp, regs->lines_occup);
  866. freed = REG_RD(bp, regs->lines_freed);
  867. } else {
  868. DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
  869. regs->pN);
  870. DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
  871. regs->pN, occup);
  872. DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
  873. regs->pN, freed);
  874. break;
  875. }
  876. }
  877. DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
  878. poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
  879. }
  880. static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
  881. u32 expected, u32 poll_count)
  882. {
  883. u32 cur_cnt = poll_count;
  884. u32 val;
  885. while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
  886. udelay(FLR_WAIT_INTERVAL);
  887. return val;
  888. }
  889. static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
  890. char *msg, u32 poll_cnt)
  891. {
  892. u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
  893. if (val != 0) {
  894. BNX2X_ERR("%s usage count=%d\n", msg, val);
  895. return 1;
  896. }
  897. return 0;
  898. }
  899. static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
  900. {
  901. /* adjust polling timeout */
  902. if (CHIP_REV_IS_EMUL(bp))
  903. return FLR_POLL_CNT * 2000;
  904. if (CHIP_REV_IS_FPGA(bp))
  905. return FLR_POLL_CNT * 120;
  906. return FLR_POLL_CNT;
  907. }
  908. static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
  909. {
  910. struct pbf_pN_cmd_regs cmd_regs[] = {
  911. {0, (CHIP_IS_E3B0(bp)) ?
  912. PBF_REG_TQ_OCCUPANCY_Q0 :
  913. PBF_REG_P0_TQ_OCCUPANCY,
  914. (CHIP_IS_E3B0(bp)) ?
  915. PBF_REG_TQ_LINES_FREED_CNT_Q0 :
  916. PBF_REG_P0_TQ_LINES_FREED_CNT},
  917. {1, (CHIP_IS_E3B0(bp)) ?
  918. PBF_REG_TQ_OCCUPANCY_Q1 :
  919. PBF_REG_P1_TQ_OCCUPANCY,
  920. (CHIP_IS_E3B0(bp)) ?
  921. PBF_REG_TQ_LINES_FREED_CNT_Q1 :
  922. PBF_REG_P1_TQ_LINES_FREED_CNT},
  923. {4, (CHIP_IS_E3B0(bp)) ?
  924. PBF_REG_TQ_OCCUPANCY_LB_Q :
  925. PBF_REG_P4_TQ_OCCUPANCY,
  926. (CHIP_IS_E3B0(bp)) ?
  927. PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
  928. PBF_REG_P4_TQ_LINES_FREED_CNT}
  929. };
  930. struct pbf_pN_buf_regs buf_regs[] = {
  931. {0, (CHIP_IS_E3B0(bp)) ?
  932. PBF_REG_INIT_CRD_Q0 :
  933. PBF_REG_P0_INIT_CRD ,
  934. (CHIP_IS_E3B0(bp)) ?
  935. PBF_REG_CREDIT_Q0 :
  936. PBF_REG_P0_CREDIT,
  937. (CHIP_IS_E3B0(bp)) ?
  938. PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
  939. PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
  940. {1, (CHIP_IS_E3B0(bp)) ?
  941. PBF_REG_INIT_CRD_Q1 :
  942. PBF_REG_P1_INIT_CRD,
  943. (CHIP_IS_E3B0(bp)) ?
  944. PBF_REG_CREDIT_Q1 :
  945. PBF_REG_P1_CREDIT,
  946. (CHIP_IS_E3B0(bp)) ?
  947. PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
  948. PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
  949. {4, (CHIP_IS_E3B0(bp)) ?
  950. PBF_REG_INIT_CRD_LB_Q :
  951. PBF_REG_P4_INIT_CRD,
  952. (CHIP_IS_E3B0(bp)) ?
  953. PBF_REG_CREDIT_LB_Q :
  954. PBF_REG_P4_CREDIT,
  955. (CHIP_IS_E3B0(bp)) ?
  956. PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
  957. PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
  958. };
  959. int i;
  960. /* Verify the command queues are flushed P0, P1, P4 */
  961. for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
  962. bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
  963. /* Verify the transmission buffers are flushed P0, P1, P4 */
  964. for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
  965. bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
  966. }
  967. #define OP_GEN_PARAM(param) \
  968. (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
  969. #define OP_GEN_TYPE(type) \
  970. (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
  971. #define OP_GEN_AGG_VECT(index) \
  972. (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
  973. static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
  974. u32 poll_cnt)
  975. {
  976. struct sdm_op_gen op_gen = {0};
  977. u32 comp_addr = BAR_CSTRORM_INTMEM +
  978. CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
  979. int ret = 0;
  980. if (REG_RD(bp, comp_addr)) {
  981. BNX2X_ERR("Cleanup complete was not 0 before sending\n");
  982. return 1;
  983. }
  984. op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
  985. op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
  986. op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
  987. op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
  988. DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
  989. REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
  990. if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
  991. BNX2X_ERR("FW final cleanup did not succeed\n");
  992. DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
  993. (REG_RD(bp, comp_addr)));
  994. ret = 1;
  995. }
  996. /* Zero completion for nxt FLR */
  997. REG_WR(bp, comp_addr, 0);
  998. return ret;
  999. }
  1000. static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
  1001. {
  1002. u16 status;
  1003. pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
  1004. return status & PCI_EXP_DEVSTA_TRPND;
  1005. }
  1006. /* PF FLR specific routines
  1007. */
  1008. static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
  1009. {
  1010. /* wait for CFC PF usage-counter to zero (includes all the VFs) */
  1011. if (bnx2x_flr_clnup_poll_hw_counter(bp,
  1012. CFC_REG_NUM_LCIDS_INSIDE_PF,
  1013. "CFC PF usage counter timed out",
  1014. poll_cnt))
  1015. return 1;
  1016. /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
  1017. if (bnx2x_flr_clnup_poll_hw_counter(bp,
  1018. DORQ_REG_PF_USAGE_CNT,
  1019. "DQ PF usage counter timed out",
  1020. poll_cnt))
  1021. return 1;
  1022. /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
  1023. if (bnx2x_flr_clnup_poll_hw_counter(bp,
  1024. QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
  1025. "QM PF usage counter timed out",
  1026. poll_cnt))
  1027. return 1;
  1028. /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
  1029. if (bnx2x_flr_clnup_poll_hw_counter(bp,
  1030. TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
  1031. "Timers VNIC usage counter timed out",
  1032. poll_cnt))
  1033. return 1;
  1034. if (bnx2x_flr_clnup_poll_hw_counter(bp,
  1035. TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
  1036. "Timers NUM_SCANS usage counter timed out",
  1037. poll_cnt))
  1038. return 1;
  1039. /* Wait DMAE PF usage counter to zero */
  1040. if (bnx2x_flr_clnup_poll_hw_counter(bp,
  1041. dmae_reg_go_c[INIT_DMAE_C(bp)],
  1042. "DMAE dommand register timed out",
  1043. poll_cnt))
  1044. return 1;
  1045. return 0;
  1046. }
  1047. static void bnx2x_hw_enable_status(struct bnx2x *bp)
  1048. {
  1049. u32 val;
  1050. val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
  1051. DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
  1052. val = REG_RD(bp, PBF_REG_DISABLE_PF);
  1053. DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
  1054. val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
  1055. DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
  1056. val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
  1057. DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
  1058. val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
  1059. DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
  1060. val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
  1061. DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
  1062. val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
  1063. DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
  1064. val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
  1065. DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
  1066. val);
  1067. }
  1068. static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
  1069. {
  1070. u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
  1071. DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
  1072. /* Re-enable PF target read access */
  1073. REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
  1074. /* Poll HW usage counters */
  1075. DP(BNX2X_MSG_SP, "Polling usage counters\n");
  1076. if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
  1077. return -EBUSY;
  1078. /* Zero the igu 'trailing edge' and 'leading edge' */
  1079. /* Send the FW cleanup command */
  1080. if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
  1081. return -EBUSY;
  1082. /* ATC cleanup */
  1083. /* Verify TX hw is flushed */
  1084. bnx2x_tx_hw_flushed(bp, poll_cnt);
  1085. /* Wait 100ms (not adjusted according to platform) */
  1086. msleep(100);
  1087. /* Verify no pending pci transactions */
  1088. if (bnx2x_is_pcie_pending(bp->pdev))
  1089. BNX2X_ERR("PCIE Transactions still pending\n");
  1090. /* Debug */
  1091. bnx2x_hw_enable_status(bp);
  1092. /*
  1093. * Master enable - Due to WB DMAE writes performed before this
  1094. * register is re-initialized as part of the regular function init
  1095. */
  1096. REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
  1097. return 0;
  1098. }
  1099. static void bnx2x_hc_int_enable(struct bnx2x *bp)
  1100. {
  1101. int port = BP_PORT(bp);
  1102. u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
  1103. u32 val = REG_RD(bp, addr);
  1104. bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
  1105. bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
  1106. bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
  1107. if (msix) {
  1108. val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
  1109. HC_CONFIG_0_REG_INT_LINE_EN_0);
  1110. val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
  1111. HC_CONFIG_0_REG_ATTN_BIT_EN_0);
  1112. if (single_msix)
  1113. val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
  1114. } else if (msi) {
  1115. val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
  1116. val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
  1117. HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
  1118. HC_CONFIG_0_REG_ATTN_BIT_EN_0);
  1119. } else {
  1120. val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
  1121. HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
  1122. HC_CONFIG_0_REG_INT_LINE_EN_0 |
  1123. HC_CONFIG_0_REG_ATTN_BIT_EN_0);
  1124. if (!CHIP_IS_E1(bp)) {
  1125. DP(NETIF_MSG_IFUP,
  1126. "write %x to HC %d (addr 0x%x)\n", val, port, addr);
  1127. REG_WR(bp, addr, val);
  1128. val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
  1129. }
  1130. }
  1131. if (CHIP_IS_E1(bp))
  1132. REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
  1133. DP(NETIF_MSG_IFUP,
  1134. "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
  1135. (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
  1136. REG_WR(bp, addr, val);
  1137. /*
  1138. * Ensure that HC_CONFIG is written before leading/trailing edge config
  1139. */
  1140. mmiowb();
  1141. barrier();
  1142. if (!CHIP_IS_E1(bp)) {
  1143. /* init leading/trailing edge */
  1144. if (IS_MF(bp)) {
  1145. val = (0xee0f | (1 << (BP_VN(bp) + 4)));
  1146. if (bp->port.pmf)
  1147. /* enable nig and gpio3 attention */
  1148. val |= 0x1100;
  1149. } else
  1150. val = 0xffff;
  1151. REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
  1152. REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
  1153. }
  1154. /* Make sure that interrupts are indeed enabled from here on */
  1155. mmiowb();
  1156. }
  1157. static void bnx2x_igu_int_enable(struct bnx2x *bp)
  1158. {
  1159. u32 val;
  1160. bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
  1161. bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
  1162. bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
  1163. val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
  1164. if (msix) {
  1165. val &= ~(IGU_PF_CONF_INT_LINE_EN |
  1166. IGU_PF_CONF_SINGLE_ISR_EN);
  1167. val |= (IGU_PF_CONF_FUNC_EN |
  1168. IGU_PF_CONF_MSI_MSIX_EN |
  1169. IGU_PF_CONF_ATTN_BIT_EN);
  1170. if (single_msix)
  1171. val |= IGU_PF_CONF_SINGLE_ISR_EN;
  1172. } else if (msi) {
  1173. val &= ~IGU_PF_CONF_INT_LINE_EN;
  1174. val |= (IGU_PF_CONF_FUNC_EN |
  1175. IGU_PF_CONF_MSI_MSIX_EN |
  1176. IGU_PF_CONF_ATTN_BIT_EN |
  1177. IGU_PF_CONF_SINGLE_ISR_EN);
  1178. } else {
  1179. val &= ~IGU_PF_CONF_MSI_MSIX_EN;
  1180. val |= (IGU_PF_CONF_FUNC_EN |
  1181. IGU_PF_CONF_INT_LINE_EN |
  1182. IGU_PF_CONF_ATTN_BIT_EN |
  1183. IGU_PF_CONF_SINGLE_ISR_EN);
  1184. }
  1185. DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
  1186. val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
  1187. REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
  1188. if (val & IGU_PF_CONF_INT_LINE_EN)
  1189. pci_intx(bp->pdev, true);
  1190. barrier();
  1191. /* init leading/trailing edge */
  1192. if (IS_MF(bp)) {
  1193. val = (0xee0f | (1 << (BP_VN(bp) + 4)));
  1194. if (bp->port.pmf)
  1195. /* enable nig and gpio3 attention */
  1196. val |= 0x1100;
  1197. } else
  1198. val = 0xffff;
  1199. REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
  1200. REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
  1201. /* Make sure that interrupts are indeed enabled from here on */
  1202. mmiowb();
  1203. }
  1204. void bnx2x_int_enable(struct bnx2x *bp)
  1205. {
  1206. if (bp->common.int_block == INT_BLOCK_HC)
  1207. bnx2x_hc_int_enable(bp);
  1208. else
  1209. bnx2x_igu_int_enable(bp);
  1210. }
  1211. static void bnx2x_hc_int_disable(struct bnx2x *bp)
  1212. {
  1213. int port = BP_PORT(bp);
  1214. u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
  1215. u32 val = REG_RD(bp, addr);
  1216. /*
  1217. * in E1 we must use only PCI configuration space to disable
  1218. * MSI/MSIX capablility
  1219. * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
  1220. */
  1221. if (CHIP_IS_E1(bp)) {
  1222. /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
  1223. * Use mask register to prevent from HC sending interrupts
  1224. * after we exit the function
  1225. */
  1226. REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
  1227. val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
  1228. HC_CONFIG_0_REG_INT_LINE_EN_0 |
  1229. HC_CONFIG_0_REG_ATTN_BIT_EN_0);
  1230. } else
  1231. val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
  1232. HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
  1233. HC_CONFIG_0_REG_INT_LINE_EN_0 |
  1234. HC_CONFIG_0_REG_ATTN_BIT_EN_0);
  1235. DP(NETIF_MSG_IFDOWN,
  1236. "write %x to HC %d (addr 0x%x)\n",
  1237. val, port, addr);
  1238. /* flush all outstanding writes */
  1239. mmiowb();
  1240. REG_WR(bp, addr, val);
  1241. if (REG_RD(bp, addr) != val)
  1242. BNX2X_ERR("BUG! proper val not read from IGU!\n");
  1243. }
  1244. static void bnx2x_igu_int_disable(struct bnx2x *bp)
  1245. {
  1246. u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
  1247. val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
  1248. IGU_PF_CONF_INT_LINE_EN |
  1249. IGU_PF_CONF_ATTN_BIT_EN);
  1250. DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
  1251. /* flush all outstanding writes */
  1252. mmiowb();
  1253. REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
  1254. if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
  1255. BNX2X_ERR("BUG! proper val not read from IGU!\n");
  1256. }
  1257. void bnx2x_int_disable(struct bnx2x *bp)
  1258. {
  1259. if (bp->common.int_block == INT_BLOCK_HC)
  1260. bnx2x_hc_int_disable(bp);
  1261. else
  1262. bnx2x_igu_int_disable(bp);
  1263. }
  1264. void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
  1265. {
  1266. int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
  1267. int i, offset;
  1268. if (disable_hw)
  1269. /* prevent the HW from sending interrupts */
  1270. bnx2x_int_disable(bp);
  1271. /* make sure all ISRs are done */
  1272. if (msix) {
  1273. synchronize_irq(bp->msix_table[0].vector);
  1274. offset = 1;
  1275. #ifdef BCM_CNIC
  1276. offset++;
  1277. #endif
  1278. for_each_eth_queue(bp, i)
  1279. synchronize_irq(bp->msix_table[offset++].vector);
  1280. } else
  1281. synchronize_irq(bp->pdev->irq);
  1282. /* make sure sp_task is not running */
  1283. cancel_delayed_work(&bp->sp_task);
  1284. cancel_delayed_work(&bp->period_task);
  1285. flush_workqueue(bnx2x_wq);
  1286. }
  1287. /* fast path */
  1288. /*
  1289. * General service functions
  1290. */
  1291. /* Return true if succeeded to acquire the lock */
  1292. static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
  1293. {
  1294. u32 lock_status;
  1295. u32 resource_bit = (1 << resource);
  1296. int func = BP_FUNC(bp);
  1297. u32 hw_lock_control_reg;
  1298. DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
  1299. "Trying to take a lock on resource %d\n", resource);
  1300. /* Validating that the resource is within range */
  1301. if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
  1302. DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
  1303. "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
  1304. resource, HW_LOCK_MAX_RESOURCE_VALUE);
  1305. return false;
  1306. }
  1307. if (func <= 5)
  1308. hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
  1309. else
  1310. hw_lock_control_reg =
  1311. (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
  1312. /* Try to acquire the lock */
  1313. REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
  1314. lock_status = REG_RD(bp, hw_lock_control_reg);
  1315. if (lock_status & resource_bit)
  1316. return true;
  1317. DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
  1318. "Failed to get a lock on resource %d\n", resource);
  1319. return false;
  1320. }
  1321. /**
  1322. * bnx2x_get_leader_lock_resource - get the recovery leader resource id
  1323. *
  1324. * @bp: driver handle
  1325. *
  1326. * Returns the recovery leader resource id according to the engine this function
  1327. * belongs to. Currently only only 2 engines is supported.
  1328. */
  1329. static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
  1330. {
  1331. if (BP_PATH(bp))
  1332. return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
  1333. else
  1334. return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
  1335. }
  1336. /**
  1337. * bnx2x_trylock_leader_lock- try to aquire a leader lock.
  1338. *
  1339. * @bp: driver handle
  1340. *
  1341. * Tries to aquire a leader lock for current engine.
  1342. */
  1343. static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
  1344. {
  1345. return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
  1346. }
  1347. #ifdef BCM_CNIC
  1348. static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
  1349. #endif
  1350. void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
  1351. {
  1352. struct bnx2x *bp = fp->bp;
  1353. int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
  1354. int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
  1355. enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
  1356. struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
  1357. DP(BNX2X_MSG_SP,
  1358. "fp %d cid %d got ramrod #%d state is %x type is %d\n",
  1359. fp->index, cid, command, bp->state,
  1360. rr_cqe->ramrod_cqe.ramrod_type);
  1361. switch (command) {
  1362. case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
  1363. DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
  1364. drv_cmd = BNX2X_Q_CMD_UPDATE;
  1365. break;
  1366. case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
  1367. DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
  1368. drv_cmd = BNX2X_Q_CMD_SETUP;
  1369. break;
  1370. case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
  1371. DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
  1372. drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
  1373. break;
  1374. case (RAMROD_CMD_ID_ETH_HALT):
  1375. DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
  1376. drv_cmd = BNX2X_Q_CMD_HALT;
  1377. break;
  1378. case (RAMROD_CMD_ID_ETH_TERMINATE):
  1379. DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
  1380. drv_cmd = BNX2X_Q_CMD_TERMINATE;
  1381. break;
  1382. case (RAMROD_CMD_ID_ETH_EMPTY):
  1383. DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
  1384. drv_cmd = BNX2X_Q_CMD_EMPTY;
  1385. break;
  1386. default:
  1387. BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
  1388. command, fp->index);
  1389. return;
  1390. }
  1391. if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
  1392. q_obj->complete_cmd(bp, q_obj, drv_cmd))
  1393. /* q_obj->complete_cmd() failure means that this was
  1394. * an unexpected completion.
  1395. *
  1396. * In this case we don't want to increase the bp->spq_left
  1397. * because apparently we haven't sent this command the first
  1398. * place.
  1399. */
  1400. #ifdef BNX2X_STOP_ON_ERROR
  1401. bnx2x_panic();
  1402. #else
  1403. return;
  1404. #endif
  1405. smp_mb__before_atomic_inc();
  1406. atomic_inc(&bp->cq_spq_left);
  1407. /* push the change in bp->spq_left and towards the memory */
  1408. smp_mb__after_atomic_inc();
  1409. DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
  1410. if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
  1411. (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
  1412. /* if Q update ramrod is completed for last Q in AFEX vif set
  1413. * flow, then ACK MCP at the end
  1414. *
  1415. * mark pending ACK to MCP bit.
  1416. * prevent case that both bits are cleared.
  1417. * At the end of load/unload driver checks that
  1418. * sp_state is cleaerd, and this order prevents
  1419. * races
  1420. */
  1421. smp_mb__before_clear_bit();
  1422. set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
  1423. wmb();
  1424. clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
  1425. smp_mb__after_clear_bit();
  1426. /* schedule workqueue to send ack to MCP */
  1427. queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
  1428. }
  1429. return;
  1430. }
  1431. void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
  1432. u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
  1433. {
  1434. u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
  1435. bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
  1436. start);
  1437. }
  1438. irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
  1439. {
  1440. struct bnx2x *bp = netdev_priv(dev_instance);
  1441. u16 status = bnx2x_ack_int(bp);
  1442. u16 mask;
  1443. int i;
  1444. u8 cos;
  1445. /* Return here if interrupt is shared and it's not for us */
  1446. if (unlikely(status == 0)) {
  1447. DP(NETIF_MSG_INTR, "not our interrupt!\n");
  1448. return IRQ_NONE;
  1449. }
  1450. DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
  1451. #ifdef BNX2X_STOP_ON_ERROR
  1452. if (unlikely(bp->panic))
  1453. return IRQ_HANDLED;
  1454. #endif
  1455. for_each_eth_queue(bp, i) {
  1456. struct bnx2x_fastpath *fp = &bp->fp[i];
  1457. mask = 0x2 << (fp->index + CNIC_PRESENT);
  1458. if (status & mask) {
  1459. /* Handle Rx or Tx according to SB id */
  1460. prefetch(fp->rx_cons_sb);
  1461. for_each_cos_in_tx_queue(fp, cos)
  1462. prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
  1463. prefetch(&fp->sb_running_index[SM_RX_ID]);
  1464. napi_schedule(&bnx2x_fp(bp, fp->index, napi));
  1465. status &= ~mask;
  1466. }
  1467. }
  1468. #ifdef BCM_CNIC
  1469. mask = 0x2;
  1470. if (status & (mask | 0x1)) {
  1471. struct cnic_ops *c_ops = NULL;
  1472. if (likely(bp->state == BNX2X_STATE_OPEN)) {
  1473. rcu_read_lock();
  1474. c_ops = rcu_dereference(bp->cnic_ops);
  1475. if (c_ops)
  1476. c_ops->cnic_handler(bp->cnic_data, NULL);
  1477. rcu_read_unlock();
  1478. }
  1479. status &= ~mask;
  1480. }
  1481. #endif
  1482. if (unlikely(status & 0x1)) {
  1483. queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
  1484. status &= ~0x1;
  1485. if (!status)
  1486. return IRQ_HANDLED;
  1487. }
  1488. if (unlikely(status))
  1489. DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
  1490. status);
  1491. return IRQ_HANDLED;
  1492. }
  1493. /* Link */
  1494. /*
  1495. * General service functions
  1496. */
  1497. int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
  1498. {
  1499. u32 lock_status;
  1500. u32 resource_bit = (1 << resource);
  1501. int func = BP_FUNC(bp);
  1502. u32 hw_lock_control_reg;
  1503. int cnt;
  1504. /* Validating that the resource is within range */
  1505. if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
  1506. BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
  1507. resource, HW_LOCK_MAX_RESOURCE_VALUE);
  1508. return -EINVAL;
  1509. }
  1510. if (func <= 5) {
  1511. hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
  1512. } else {
  1513. hw_lock_control_reg =
  1514. (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
  1515. }
  1516. /* Validating that the resource is not already taken */
  1517. lock_status = REG_RD(bp, hw_lock_control_reg);
  1518. if (lock_status & resource_bit) {
  1519. BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
  1520. lock_status, resource_bit);
  1521. return -EEXIST;
  1522. }
  1523. /* Try for 5 second every 5ms */
  1524. for (cnt = 0; cnt < 1000; cnt++) {
  1525. /* Try to acquire the lock */
  1526. REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
  1527. lock_status = REG_RD(bp, hw_lock_control_reg);
  1528. if (lock_status & resource_bit)
  1529. return 0;
  1530. msleep(5);
  1531. }
  1532. BNX2X_ERR("Timeout\n");
  1533. return -EAGAIN;
  1534. }
  1535. int bnx2x_release_leader_lock(struct bnx2x *bp)
  1536. {
  1537. return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
  1538. }
  1539. int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
  1540. {
  1541. u32 lock_status;
  1542. u32 resource_bit = (1 << resource);
  1543. int func = BP_FUNC(bp);
  1544. u32 hw_lock_control_reg;
  1545. /* Validating that the resource is within range */
  1546. if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
  1547. BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
  1548. resource, HW_LOCK_MAX_RESOURCE_VALUE);
  1549. return -EINVAL;
  1550. }
  1551. if (func <= 5) {
  1552. hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
  1553. } else {
  1554. hw_lock_control_reg =
  1555. (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
  1556. }
  1557. /* Validating that the resource is currently taken */
  1558. lock_status = REG_RD(bp, hw_lock_control_reg);
  1559. if (!(lock_status & resource_bit)) {
  1560. BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
  1561. lock_status, resource_bit);
  1562. return -EFAULT;
  1563. }
  1564. REG_WR(bp, hw_lock_control_reg, resource_bit);
  1565. return 0;
  1566. }
  1567. int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
  1568. {
  1569. /* The GPIO should be swapped if swap register is set and active */
  1570. int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
  1571. REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
  1572. int gpio_shift = gpio_num +
  1573. (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
  1574. u32 gpio_mask = (1 << gpio_shift);
  1575. u32 gpio_reg;
  1576. int value;
  1577. if (gpio_num > MISC_REGISTERS_GPIO_3) {
  1578. BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
  1579. return -EINVAL;
  1580. }
  1581. /* read GPIO value */
  1582. gpio_reg = REG_RD(bp, MISC_REG_GPIO);
  1583. /* get the requested pin value */
  1584. if ((gpio_reg & gpio_mask) == gpio_mask)
  1585. value = 1;
  1586. else
  1587. value = 0;
  1588. DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
  1589. return value;
  1590. }
  1591. int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
  1592. {
  1593. /* The GPIO should be swapped if swap register is set and active */
  1594. int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
  1595. REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
  1596. int gpio_shift = gpio_num +
  1597. (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
  1598. u32 gpio_mask = (1 << gpio_shift);
  1599. u32 gpio_reg;
  1600. if (gpio_num > MISC_REGISTERS_GPIO_3) {
  1601. BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
  1602. return -EINVAL;
  1603. }
  1604. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
  1605. /* read GPIO and mask except the float bits */
  1606. gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
  1607. switch (mode) {
  1608. case MISC_REGISTERS_GPIO_OUTPUT_LOW:
  1609. DP(NETIF_MSG_LINK,
  1610. "Set GPIO %d (shift %d) -> output low\n",
  1611. gpio_num, gpio_shift);
  1612. /* clear FLOAT and set CLR */
  1613. gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
  1614. gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
  1615. break;
  1616. case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
  1617. DP(NETIF_MSG_LINK,
  1618. "Set GPIO %d (shift %d) -> output high\n",
  1619. gpio_num, gpio_shift);
  1620. /* clear FLOAT and set SET */
  1621. gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
  1622. gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
  1623. break;
  1624. case MISC_REGISTERS_GPIO_INPUT_HI_Z:
  1625. DP(NETIF_MSG_LINK,
  1626. "Set GPIO %d (shift %d) -> input\n",
  1627. gpio_num, gpio_shift);
  1628. /* set FLOAT */
  1629. gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
  1630. break;
  1631. default:
  1632. break;
  1633. }
  1634. REG_WR(bp, MISC_REG_GPIO, gpio_reg);
  1635. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
  1636. return 0;
  1637. }
  1638. int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
  1639. {
  1640. u32 gpio_reg = 0;
  1641. int rc = 0;
  1642. /* Any port swapping should be handled by caller. */
  1643. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
  1644. /* read GPIO and mask except the float bits */
  1645. gpio_reg = REG_RD(bp, MISC_REG_GPIO);
  1646. gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
  1647. gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
  1648. gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
  1649. switch (mode) {
  1650. case MISC_REGISTERS_GPIO_OUTPUT_LOW:
  1651. DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
  1652. /* set CLR */
  1653. gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
  1654. break;
  1655. case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
  1656. DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
  1657. /* set SET */
  1658. gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
  1659. break;
  1660. case MISC_REGISTERS_GPIO_INPUT_HI_Z:
  1661. DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
  1662. /* set FLOAT */
  1663. gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
  1664. break;
  1665. default:
  1666. BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
  1667. rc = -EINVAL;
  1668. break;
  1669. }
  1670. if (rc == 0)
  1671. REG_WR(bp, MISC_REG_GPIO, gpio_reg);
  1672. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
  1673. return rc;
  1674. }
  1675. int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
  1676. {
  1677. /* The GPIO should be swapped if swap register is set and active */
  1678. int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
  1679. REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
  1680. int gpio_shift = gpio_num +
  1681. (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
  1682. u32 gpio_mask = (1 << gpio_shift);
  1683. u32 gpio_reg;
  1684. if (gpio_num > MISC_REGISTERS_GPIO_3) {
  1685. BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
  1686. return -EINVAL;
  1687. }
  1688. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
  1689. /* read GPIO int */
  1690. gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
  1691. switch (mode) {
  1692. case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
  1693. DP(NETIF_MSG_LINK,
  1694. "Clear GPIO INT %d (shift %d) -> output low\n",
  1695. gpio_num, gpio_shift);
  1696. /* clear SET and set CLR */
  1697. gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
  1698. gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
  1699. break;
  1700. case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
  1701. DP(NETIF_MSG_LINK,
  1702. "Set GPIO INT %d (shift %d) -> output high\n",
  1703. gpio_num, gpio_shift);
  1704. /* clear CLR and set SET */
  1705. gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
  1706. gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
  1707. break;
  1708. default:
  1709. break;
  1710. }
  1711. REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
  1712. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
  1713. return 0;
  1714. }
  1715. static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
  1716. {
  1717. u32 spio_mask = (1 << spio_num);
  1718. u32 spio_reg;
  1719. if ((spio_num < MISC_REGISTERS_SPIO_4) ||
  1720. (spio_num > MISC_REGISTERS_SPIO_7)) {
  1721. BNX2X_ERR("Invalid SPIO %d\n", spio_num);
  1722. return -EINVAL;
  1723. }
  1724. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
  1725. /* read SPIO and mask except the float bits */
  1726. spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
  1727. switch (mode) {
  1728. case MISC_REGISTERS_SPIO_OUTPUT_LOW:
  1729. DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
  1730. /* clear FLOAT and set CLR */
  1731. spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
  1732. spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
  1733. break;
  1734. case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
  1735. DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
  1736. /* clear FLOAT and set SET */
  1737. spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
  1738. spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
  1739. break;
  1740. case MISC_REGISTERS_SPIO_INPUT_HI_Z:
  1741. DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
  1742. /* set FLOAT */
  1743. spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
  1744. break;
  1745. default:
  1746. break;
  1747. }
  1748. REG_WR(bp, MISC_REG_SPIO, spio_reg);
  1749. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
  1750. return 0;
  1751. }
  1752. void bnx2x_calc_fc_adv(struct bnx2x *bp)
  1753. {
  1754. u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
  1755. switch (bp->link_vars.ieee_fc &
  1756. MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
  1757. case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
  1758. bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
  1759. ADVERTISED_Pause);
  1760. break;
  1761. case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
  1762. bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
  1763. ADVERTISED_Pause);
  1764. break;
  1765. case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
  1766. bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
  1767. break;
  1768. default:
  1769. bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
  1770. ADVERTISED_Pause);
  1771. break;
  1772. }
  1773. }
  1774. u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
  1775. {
  1776. if (!BP_NOMCP(bp)) {
  1777. u8 rc;
  1778. int cfx_idx = bnx2x_get_link_cfg_idx(bp);
  1779. u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
  1780. /*
  1781. * Initialize link parameters structure variables
  1782. * It is recommended to turn off RX FC for jumbo frames
  1783. * for better performance
  1784. */
  1785. if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
  1786. bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
  1787. else
  1788. bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
  1789. bnx2x_acquire_phy_lock(bp);
  1790. if (load_mode == LOAD_DIAG) {
  1791. struct link_params *lp = &bp->link_params;
  1792. lp->loopback_mode = LOOPBACK_XGXS;
  1793. /* do PHY loopback at 10G speed, if possible */
  1794. if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
  1795. if (lp->speed_cap_mask[cfx_idx] &
  1796. PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
  1797. lp->req_line_speed[cfx_idx] =
  1798. SPEED_10000;
  1799. else
  1800. lp->req_line_speed[cfx_idx] =
  1801. SPEED_1000;
  1802. }
  1803. }
  1804. if (load_mode == LOAD_LOOPBACK_EXT) {
  1805. struct link_params *lp = &bp->link_params;
  1806. lp->loopback_mode = LOOPBACK_EXT;
  1807. }
  1808. rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
  1809. bnx2x_release_phy_lock(bp);
  1810. bnx2x_calc_fc_adv(bp);
  1811. if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
  1812. bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
  1813. bnx2x_link_report(bp);
  1814. } else
  1815. queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
  1816. bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
  1817. return rc;
  1818. }
  1819. BNX2X_ERR("Bootcode is missing - can not initialize link\n");
  1820. return -EINVAL;
  1821. }
  1822. void bnx2x_link_set(struct bnx2x *bp)
  1823. {
  1824. if (!BP_NOMCP(bp)) {
  1825. bnx2x_acquire_phy_lock(bp);
  1826. bnx2x_phy_init(&bp->link_params, &bp->link_vars);
  1827. bnx2x_release_phy_lock(bp);
  1828. bnx2x_calc_fc_adv(bp);
  1829. } else
  1830. BNX2X_ERR("Bootcode is missing - can not set link\n");
  1831. }
  1832. static void bnx2x__link_reset(struct bnx2x *bp)
  1833. {
  1834. if (!BP_NOMCP(bp)) {
  1835. bnx2x_acquire_phy_lock(bp);
  1836. bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
  1837. bnx2x_release_phy_lock(bp);
  1838. } else
  1839. BNX2X_ERR("Bootcode is missing - can not reset link\n");
  1840. }
  1841. void bnx2x_force_link_reset(struct bnx2x *bp)
  1842. {
  1843. bnx2x_acquire_phy_lock(bp);
  1844. bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
  1845. bnx2x_release_phy_lock(bp);
  1846. }
  1847. u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
  1848. {
  1849. u8 rc = 0;
  1850. if (!BP_NOMCP(bp)) {
  1851. bnx2x_acquire_phy_lock(bp);
  1852. rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
  1853. is_serdes);
  1854. bnx2x_release_phy_lock(bp);
  1855. } else
  1856. BNX2X_ERR("Bootcode is missing - can not test link\n");
  1857. return rc;
  1858. }
  1859. /* Calculates the sum of vn_min_rates.
  1860. It's needed for further normalizing of the min_rates.
  1861. Returns:
  1862. sum of vn_min_rates.
  1863. or
  1864. 0 - if all the min_rates are 0.
  1865. In the later case fainess algorithm should be deactivated.
  1866. If not all min_rates are zero then those that are zeroes will be set to 1.
  1867. */
  1868. static void bnx2x_calc_vn_min(struct bnx2x *bp,
  1869. struct cmng_init_input *input)
  1870. {
  1871. int all_zero = 1;
  1872. int vn;
  1873. for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
  1874. u32 vn_cfg = bp->mf_config[vn];
  1875. u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
  1876. FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
  1877. /* Skip hidden vns */
  1878. if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
  1879. vn_min_rate = 0;
  1880. /* If min rate is zero - set it to 1 */
  1881. else if (!vn_min_rate)
  1882. vn_min_rate = DEF_MIN_RATE;
  1883. else
  1884. all_zero = 0;
  1885. input->vnic_min_rate[vn] = vn_min_rate;
  1886. }
  1887. /* if ETS or all min rates are zeros - disable fairness */
  1888. if (BNX2X_IS_ETS_ENABLED(bp)) {
  1889. input->flags.cmng_enables &=
  1890. ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
  1891. DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
  1892. } else if (all_zero) {
  1893. input->flags.cmng_enables &=
  1894. ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
  1895. DP(NETIF_MSG_IFUP,
  1896. "All MIN values are zeroes fairness will be disabled\n");
  1897. } else
  1898. input->flags.cmng_enables |=
  1899. CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
  1900. }
  1901. static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
  1902. struct cmng_init_input *input)
  1903. {
  1904. u16 vn_max_rate;
  1905. u32 vn_cfg = bp->mf_config[vn];
  1906. if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
  1907. vn_max_rate = 0;
  1908. else {
  1909. u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
  1910. if (IS_MF_SI(bp)) {
  1911. /* maxCfg in percents of linkspeed */
  1912. vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
  1913. } else /* SD modes */
  1914. /* maxCfg is absolute in 100Mb units */
  1915. vn_max_rate = maxCfg * 100;
  1916. }
  1917. DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
  1918. input->vnic_max_rate[vn] = vn_max_rate;
  1919. }
  1920. static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
  1921. {
  1922. if (CHIP_REV_IS_SLOW(bp))
  1923. return CMNG_FNS_NONE;
  1924. if (IS_MF(bp))
  1925. return CMNG_FNS_MINMAX;
  1926. return CMNG_FNS_NONE;
  1927. }
  1928. void bnx2x_read_mf_cfg(struct bnx2x *bp)
  1929. {
  1930. int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
  1931. if (BP_NOMCP(bp))
  1932. return; /* what should be the default bvalue in this case */
  1933. /* For 2 port configuration the absolute function number formula
  1934. * is:
  1935. * abs_func = 2 * vn + BP_PORT + BP_PATH
  1936. *
  1937. * and there are 4 functions per port
  1938. *
  1939. * For 4 port configuration it is
  1940. * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
  1941. *
  1942. * and there are 2 functions per port
  1943. */
  1944. for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
  1945. int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
  1946. if (func >= E1H_FUNC_MAX)
  1947. break;
  1948. bp->mf_config[vn] =
  1949. MF_CFG_RD(bp, func_mf_config[func].config);
  1950. }
  1951. if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
  1952. DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
  1953. bp->flags |= MF_FUNC_DIS;
  1954. } else {
  1955. DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
  1956. bp->flags &= ~MF_FUNC_DIS;
  1957. }
  1958. }
  1959. static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
  1960. {
  1961. struct cmng_init_input input;
  1962. memset(&input, 0, sizeof(struct cmng_init_input));
  1963. input.port_rate = bp->link_vars.line_speed;
  1964. if (cmng_type == CMNG_FNS_MINMAX) {
  1965. int vn;
  1966. /* read mf conf from shmem */
  1967. if (read_cfg)
  1968. bnx2x_read_mf_cfg(bp);
  1969. /* vn_weight_sum and enable fairness if not 0 */
  1970. bnx2x_calc_vn_min(bp, &input);
  1971. /* calculate and set min-max rate for each vn */
  1972. if (bp->port.pmf)
  1973. for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
  1974. bnx2x_calc_vn_max(bp, vn, &input);
  1975. /* always enable rate shaping and fairness */
  1976. input.flags.cmng_enables |=
  1977. CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
  1978. bnx2x_init_cmng(&input, &bp->cmng);
  1979. return;
  1980. }
  1981. /* rate shaping and fairness are disabled */
  1982. DP(NETIF_MSG_IFUP,
  1983. "rate shaping and fairness are disabled\n");
  1984. }
  1985. static void storm_memset_cmng(struct bnx2x *bp,
  1986. struct cmng_init *cmng,
  1987. u8 port)
  1988. {
  1989. int vn;
  1990. size_t size = sizeof(struct cmng_struct_per_port);
  1991. u32 addr = BAR_XSTRORM_INTMEM +
  1992. XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
  1993. __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
  1994. for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
  1995. int func = func_by_vn(bp, vn);
  1996. addr = BAR_XSTRORM_INTMEM +
  1997. XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
  1998. size = sizeof(struct rate_shaping_vars_per_vn);
  1999. __storm_memset_struct(bp, addr, size,
  2000. (u32 *)&cmng->vnic.vnic_max_rate[vn]);
  2001. addr = BAR_XSTRORM_INTMEM +
  2002. XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
  2003. size = sizeof(struct fairness_vars_per_vn);
  2004. __storm_memset_struct(bp, addr, size,
  2005. (u32 *)&cmng->vnic.vnic_min_rate[vn]);
  2006. }
  2007. }
  2008. /* This function is called upon link interrupt */
  2009. static void bnx2x_link_attn(struct bnx2x *bp)
  2010. {
  2011. /* Make sure that we are synced with the current statistics */
  2012. bnx2x_stats_handle(bp, STATS_EVENT_STOP);
  2013. bnx2x_link_update(&bp->link_params, &bp->link_vars);
  2014. if (bp->link_vars.link_up) {
  2015. /* dropless flow control */
  2016. if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
  2017. int port = BP_PORT(bp);
  2018. u32 pause_enabled = 0;
  2019. if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
  2020. pause_enabled = 1;
  2021. REG_WR(bp, BAR_USTRORM_INTMEM +
  2022. USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
  2023. pause_enabled);
  2024. }
  2025. if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
  2026. struct host_port_stats *pstats;
  2027. pstats = bnx2x_sp(bp, port_stats);
  2028. /* reset old mac stats */
  2029. memset(&(pstats->mac_stx[0]), 0,
  2030. sizeof(struct mac_stx));
  2031. }
  2032. if (bp->state == BNX2X_STATE_OPEN)
  2033. bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
  2034. }
  2035. if (bp->link_vars.link_up && bp->link_vars.line_speed) {
  2036. int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
  2037. if (cmng_fns != CMNG_FNS_NONE) {
  2038. bnx2x_cmng_fns_init(bp, false, cmng_fns);
  2039. storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
  2040. } else
  2041. /* rate shaping and fairness are disabled */
  2042. DP(NETIF_MSG_IFUP,
  2043. "single function mode without fairness\n");
  2044. }
  2045. __bnx2x_link_report(bp);
  2046. if (IS_MF(bp))
  2047. bnx2x_link_sync_notify(bp);
  2048. }
  2049. void bnx2x__link_status_update(struct bnx2x *bp)
  2050. {
  2051. if (bp->state != BNX2X_STATE_OPEN)
  2052. return;
  2053. /* read updated dcb configuration */
  2054. bnx2x_dcbx_pmf_update(bp);
  2055. bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
  2056. if (bp->link_vars.link_up)
  2057. bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
  2058. else
  2059. bnx2x_stats_handle(bp, STATS_EVENT_STOP);
  2060. /* indicate link status */
  2061. bnx2x_link_report(bp);
  2062. }
  2063. static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
  2064. u16 vlan_val, u8 allowed_prio)
  2065. {
  2066. struct bnx2x_func_state_params func_params = {0};
  2067. struct bnx2x_func_afex_update_params *f_update_params =
  2068. &func_params.params.afex_update;
  2069. func_params.f_obj = &bp->func_obj;
  2070. func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
  2071. /* no need to wait for RAMROD completion, so don't
  2072. * set RAMROD_COMP_WAIT flag
  2073. */
  2074. f_update_params->vif_id = vifid;
  2075. f_update_params->afex_default_vlan = vlan_val;
  2076. f_update_params->allowed_priorities = allowed_prio;
  2077. /* if ramrod can not be sent, response to MCP immediately */
  2078. if (bnx2x_func_state_change(bp, &func_params) < 0)
  2079. bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
  2080. return 0;
  2081. }
  2082. static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
  2083. u16 vif_index, u8 func_bit_map)
  2084. {
  2085. struct bnx2x_func_state_params func_params = {0};
  2086. struct bnx2x_func_afex_viflists_params *update_params =
  2087. &func_params.params.afex_viflists;
  2088. int rc;
  2089. u32 drv_msg_code;
  2090. /* validate only LIST_SET and LIST_GET are received from switch */
  2091. if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
  2092. BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
  2093. cmd_type);
  2094. func_params.f_obj = &bp->func_obj;
  2095. func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
  2096. /* set parameters according to cmd_type */
  2097. update_params->afex_vif_list_command = cmd_type;
  2098. update_params->vif_list_index = cpu_to_le16(vif_index);
  2099. update_params->func_bit_map =
  2100. (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
  2101. update_params->func_to_clear = 0;
  2102. drv_msg_code =
  2103. (cmd_type == VIF_LIST_RULE_GET) ?
  2104. DRV_MSG_CODE_AFEX_LISTGET_ACK :
  2105. DRV_MSG_CODE_AFEX_LISTSET_ACK;
  2106. /* if ramrod can not be sent, respond to MCP immediately for
  2107. * SET and GET requests (other are not triggered from MCP)
  2108. */
  2109. rc = bnx2x_func_state_change(bp, &func_params);
  2110. if (rc < 0)
  2111. bnx2x_fw_command(bp, drv_msg_code, 0);
  2112. return 0;
  2113. }
  2114. static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
  2115. {
  2116. struct afex_stats afex_stats;
  2117. u32 func = BP_ABS_FUNC(bp);
  2118. u32 mf_config;
  2119. u16 vlan_val;
  2120. u32 vlan_prio;
  2121. u16 vif_id;
  2122. u8 allowed_prio;
  2123. u8 vlan_mode;
  2124. u32 addr_to_write, vifid, addrs, stats_type, i;
  2125. if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
  2126. vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
  2127. DP(BNX2X_MSG_MCP,
  2128. "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
  2129. bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
  2130. }
  2131. if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
  2132. vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
  2133. addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
  2134. DP(BNX2X_MSG_MCP,
  2135. "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
  2136. vifid, addrs);
  2137. bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
  2138. addrs);
  2139. }
  2140. if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
  2141. addr_to_write = SHMEM2_RD(bp,
  2142. afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
  2143. stats_type = SHMEM2_RD(bp,
  2144. afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
  2145. DP(BNX2X_MSG_MCP,
  2146. "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
  2147. addr_to_write);
  2148. bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
  2149. /* write response to scratchpad, for MCP */
  2150. for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
  2151. REG_WR(bp, addr_to_write + i*sizeof(u32),
  2152. *(((u32 *)(&afex_stats))+i));
  2153. /* send ack message to MCP */
  2154. bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
  2155. }
  2156. if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
  2157. mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
  2158. bp->mf_config[BP_VN(bp)] = mf_config;
  2159. DP(BNX2X_MSG_MCP,
  2160. "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
  2161. mf_config);
  2162. /* if VIF_SET is "enabled" */
  2163. if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
  2164. /* set rate limit directly to internal RAM */
  2165. struct cmng_init_input cmng_input;
  2166. struct rate_shaping_vars_per_vn m_rs_vn;
  2167. size_t size = sizeof(struct rate_shaping_vars_per_vn);
  2168. u32 addr = BAR_XSTRORM_INTMEM +
  2169. XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
  2170. bp->mf_config[BP_VN(bp)] = mf_config;
  2171. bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
  2172. m_rs_vn.vn_counter.rate =
  2173. cmng_input.vnic_max_rate[BP_VN(bp)];
  2174. m_rs_vn.vn_counter.quota =
  2175. (m_rs_vn.vn_counter.rate *
  2176. RS_PERIODIC_TIMEOUT_USEC) / 8;
  2177. __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
  2178. /* read relevant values from mf_cfg struct in shmem */
  2179. vif_id =
  2180. (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
  2181. FUNC_MF_CFG_E1HOV_TAG_MASK) >>
  2182. FUNC_MF_CFG_E1HOV_TAG_SHIFT;
  2183. vlan_val =
  2184. (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
  2185. FUNC_MF_CFG_AFEX_VLAN_MASK) >>
  2186. FUNC_MF_CFG_AFEX_VLAN_SHIFT;
  2187. vlan_prio = (mf_config &
  2188. FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
  2189. FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
  2190. vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
  2191. vlan_mode =
  2192. (MF_CFG_RD(bp,
  2193. func_mf_config[func].afex_config) &
  2194. FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
  2195. FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
  2196. allowed_prio =
  2197. (MF_CFG_RD(bp,
  2198. func_mf_config[func].afex_config) &
  2199. FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
  2200. FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
  2201. /* send ramrod to FW, return in case of failure */
  2202. if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
  2203. allowed_prio))
  2204. return;
  2205. bp->afex_def_vlan_tag = vlan_val;
  2206. bp->afex_vlan_mode = vlan_mode;
  2207. } else {
  2208. /* notify link down because BP->flags is disabled */
  2209. bnx2x_link_report(bp);
  2210. /* send INVALID VIF ramrod to FW */
  2211. bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
  2212. /* Reset the default afex VLAN */
  2213. bp->afex_def_vlan_tag = -1;
  2214. }
  2215. }
  2216. }
  2217. static void bnx2x_pmf_update(struct bnx2x *bp)
  2218. {
  2219. int port = BP_PORT(bp);
  2220. u32 val;
  2221. bp->port.pmf = 1;
  2222. DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
  2223. /*
  2224. * We need the mb() to ensure the ordering between the writing to
  2225. * bp->port.pmf here and reading it from the bnx2x_periodic_task().
  2226. */
  2227. smp_mb();
  2228. /* queue a periodic task */
  2229. queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
  2230. bnx2x_dcbx_pmf_update(bp);
  2231. /* enable nig attention */
  2232. val = (0xff0f | (1 << (BP_VN(bp) + 4)));
  2233. if (bp->common.int_block == INT_BLOCK_HC) {
  2234. REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
  2235. REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
  2236. } else if (!CHIP_IS_E1x(bp)) {
  2237. REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
  2238. REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
  2239. }
  2240. bnx2x_stats_handle(bp, STATS_EVENT_PMF);
  2241. }
  2242. /* end of Link */
  2243. /* slow path */
  2244. /*
  2245. * General service functions
  2246. */
  2247. /* send the MCP a request, block until there is a reply */
  2248. u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
  2249. {
  2250. int mb_idx = BP_FW_MB_IDX(bp);
  2251. u32 seq;
  2252. u32 rc = 0;
  2253. u32 cnt = 1;
  2254. u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
  2255. mutex_lock(&bp->fw_mb_mutex);
  2256. seq = ++bp->fw_seq;
  2257. SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
  2258. SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
  2259. DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
  2260. (command | seq), param);
  2261. do {
  2262. /* let the FW do it's magic ... */
  2263. msleep(delay);
  2264. rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
  2265. /* Give the FW up to 5 second (500*10ms) */
  2266. } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
  2267. DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
  2268. cnt*delay, rc, seq);
  2269. /* is this a reply to our command? */
  2270. if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
  2271. rc &= FW_MSG_CODE_MASK;
  2272. else {
  2273. /* FW BUG! */
  2274. BNX2X_ERR("FW failed to respond!\n");
  2275. bnx2x_fw_dump(bp);
  2276. rc = 0;
  2277. }
  2278. mutex_unlock(&bp->fw_mb_mutex);
  2279. return rc;
  2280. }
  2281. static void storm_memset_func_cfg(struct bnx2x *bp,
  2282. struct tstorm_eth_function_common_config *tcfg,
  2283. u16 abs_fid)
  2284. {
  2285. size_t size = sizeof(struct tstorm_eth_function_common_config);
  2286. u32 addr = BAR_TSTRORM_INTMEM +
  2287. TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
  2288. __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
  2289. }
  2290. void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
  2291. {
  2292. if (CHIP_IS_E1x(bp)) {
  2293. struct tstorm_eth_function_common_config tcfg = {0};
  2294. storm_memset_func_cfg(bp, &tcfg, p->func_id);
  2295. }
  2296. /* Enable the function in the FW */
  2297. storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
  2298. storm_memset_func_en(bp, p->func_id, 1);
  2299. /* spq */
  2300. if (p->func_flgs & FUNC_FLG_SPQ) {
  2301. storm_memset_spq_addr(bp, p->spq_map, p->func_id);
  2302. REG_WR(bp, XSEM_REG_FAST_MEMORY +
  2303. XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
  2304. }
  2305. }
  2306. /**
  2307. * bnx2x_get_tx_only_flags - Return common flags
  2308. *
  2309. * @bp device handle
  2310. * @fp queue handle
  2311. * @zero_stats TRUE if statistics zeroing is needed
  2312. *
  2313. * Return the flags that are common for the Tx-only and not normal connections.
  2314. */
  2315. static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
  2316. struct bnx2x_fastpath *fp,
  2317. bool zero_stats)
  2318. {
  2319. unsigned long flags = 0;
  2320. /* PF driver will always initialize the Queue to an ACTIVE state */
  2321. __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
  2322. /* tx only connections collect statistics (on the same index as the
  2323. * parent connection). The statistics are zeroed when the parent
  2324. * connection is initialized.
  2325. */
  2326. __set_bit(BNX2X_Q_FLG_STATS, &flags);
  2327. if (zero_stats)
  2328. __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
  2329. return flags;
  2330. }
  2331. static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
  2332. struct bnx2x_fastpath *fp,
  2333. bool leading)
  2334. {
  2335. unsigned long flags = 0;
  2336. /* calculate other queue flags */
  2337. if (IS_MF_SD(bp))
  2338. __set_bit(BNX2X_Q_FLG_OV, &flags);
  2339. if (IS_FCOE_FP(fp)) {
  2340. __set_bit(BNX2X_Q_FLG_FCOE, &flags);
  2341. /* For FCoE - force usage of default priority (for afex) */
  2342. __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
  2343. }
  2344. if (!fp->disable_tpa) {
  2345. __set_bit(BNX2X_Q_FLG_TPA, &flags);
  2346. __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
  2347. if (fp->mode == TPA_MODE_GRO)
  2348. __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
  2349. }
  2350. if (leading) {
  2351. __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
  2352. __set_bit(BNX2X_Q_FLG_MCAST, &flags);
  2353. }
  2354. /* Always set HW VLAN stripping */
  2355. __set_bit(BNX2X_Q_FLG_VLAN, &flags);
  2356. /* configure silent vlan removal */
  2357. if (IS_MF_AFEX(bp))
  2358. __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
  2359. return flags | bnx2x_get_common_flags(bp, fp, true);
  2360. }
  2361. static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
  2362. struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
  2363. u8 cos)
  2364. {
  2365. gen_init->stat_id = bnx2x_stats_id(fp);
  2366. gen_init->spcl_id = fp->cl_id;
  2367. /* Always use mini-jumbo MTU for FCoE L2 ring */
  2368. if (IS_FCOE_FP(fp))
  2369. gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
  2370. else
  2371. gen_init->mtu = bp->dev->mtu;
  2372. gen_init->cos = cos;
  2373. }
  2374. static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
  2375. struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
  2376. struct bnx2x_rxq_setup_params *rxq_init)
  2377. {
  2378. u8 max_sge = 0;
  2379. u16 sge_sz = 0;
  2380. u16 tpa_agg_size = 0;
  2381. if (!fp->disable_tpa) {
  2382. pause->sge_th_lo = SGE_TH_LO(bp);
  2383. pause->sge_th_hi = SGE_TH_HI(bp);
  2384. /* validate SGE ring has enough to cross high threshold */
  2385. WARN_ON(bp->dropless_fc &&
  2386. pause->sge_th_hi + FW_PREFETCH_CNT >
  2387. MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
  2388. tpa_agg_size = min_t(u32,
  2389. (min_t(u32, 8, MAX_SKB_FRAGS) *
  2390. SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
  2391. max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
  2392. SGE_PAGE_SHIFT;
  2393. max_sge = ((max_sge + PAGES_PER_SGE - 1) &
  2394. (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
  2395. sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
  2396. 0xffff);
  2397. }
  2398. /* pause - not for e1 */
  2399. if (!CHIP_IS_E1(bp)) {
  2400. pause->bd_th_lo = BD_TH_LO(bp);
  2401. pause->bd_th_hi = BD_TH_HI(bp);
  2402. pause->rcq_th_lo = RCQ_TH_LO(bp);
  2403. pause->rcq_th_hi = RCQ_TH_HI(bp);
  2404. /*
  2405. * validate that rings have enough entries to cross
  2406. * high thresholds
  2407. */
  2408. WARN_ON(bp->dropless_fc &&
  2409. pause->bd_th_hi + FW_PREFETCH_CNT >
  2410. bp->rx_ring_size);
  2411. WARN_ON(bp->dropless_fc &&
  2412. pause->rcq_th_hi + FW_PREFETCH_CNT >
  2413. NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
  2414. pause->pri_map = 1;
  2415. }
  2416. /* rxq setup */
  2417. rxq_init->dscr_map = fp->rx_desc_mapping;
  2418. rxq_init->sge_map = fp->rx_sge_mapping;
  2419. rxq_init->rcq_map = fp->rx_comp_mapping;
  2420. rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
  2421. /* This should be a maximum number of data bytes that may be
  2422. * placed on the BD (not including paddings).
  2423. */
  2424. rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
  2425. BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
  2426. rxq_init->cl_qzone_id = fp->cl_qzone_id;
  2427. rxq_init->tpa_agg_sz = tpa_agg_size;
  2428. rxq_init->sge_buf_sz = sge_sz;
  2429. rxq_init->max_sges_pkt = max_sge;
  2430. rxq_init->rss_engine_id = BP_FUNC(bp);
  2431. rxq_init->mcast_engine_id = BP_FUNC(bp);
  2432. /* Maximum number or simultaneous TPA aggregation for this Queue.
  2433. *
  2434. * For PF Clients it should be the maximum avaliable number.
  2435. * VF driver(s) may want to define it to a smaller value.
  2436. */
  2437. rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
  2438. rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
  2439. rxq_init->fw_sb_id = fp->fw_sb_id;
  2440. if (IS_FCOE_FP(fp))
  2441. rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
  2442. else
  2443. rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
  2444. /* configure silent vlan removal
  2445. * if multi function mode is afex, then mask default vlan
  2446. */
  2447. if (IS_MF_AFEX(bp)) {
  2448. rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
  2449. rxq_init->silent_removal_mask = VLAN_VID_MASK;
  2450. }
  2451. }
  2452. static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
  2453. struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
  2454. u8 cos)
  2455. {
  2456. txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
  2457. txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
  2458. txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
  2459. txq_init->fw_sb_id = fp->fw_sb_id;
  2460. /*
  2461. * set the tss leading client id for TX classfication ==
  2462. * leading RSS client id
  2463. */
  2464. txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
  2465. if (IS_FCOE_FP(fp)) {
  2466. txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
  2467. txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
  2468. }
  2469. }
  2470. static void bnx2x_pf_init(struct bnx2x *bp)
  2471. {
  2472. struct bnx2x_func_init_params func_init = {0};
  2473. struct event_ring_data eq_data = { {0} };
  2474. u16 flags;
  2475. if (!CHIP_IS_E1x(bp)) {
  2476. /* reset IGU PF statistics: MSIX + ATTN */
  2477. /* PF */
  2478. REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
  2479. BNX2X_IGU_STAS_MSG_VF_CNT*4 +
  2480. (CHIP_MODE_IS_4_PORT(bp) ?
  2481. BP_FUNC(bp) : BP_VN(bp))*4, 0);
  2482. /* ATTN */
  2483. REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
  2484. BNX2X_IGU_STAS_MSG_VF_CNT*4 +
  2485. BNX2X_IGU_STAS_MSG_PF_CNT*4 +
  2486. (CHIP_MODE_IS_4_PORT(bp) ?
  2487. BP_FUNC(bp) : BP_VN(bp))*4, 0);
  2488. }
  2489. /* function setup flags */
  2490. flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
  2491. /* This flag is relevant for E1x only.
  2492. * E2 doesn't have a TPA configuration in a function level.
  2493. */
  2494. flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
  2495. func_init.func_flgs = flags;
  2496. func_init.pf_id = BP_FUNC(bp);
  2497. func_init.func_id = BP_FUNC(bp);
  2498. func_init.spq_map = bp->spq_mapping;
  2499. func_init.spq_prod = bp->spq_prod_idx;
  2500. bnx2x_func_init(bp, &func_init);
  2501. memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
  2502. /*
  2503. * Congestion management values depend on the link rate
  2504. * There is no active link so initial link rate is set to 10 Gbps.
  2505. * When the link comes up The congestion management values are
  2506. * re-calculated according to the actual link rate.
  2507. */
  2508. bp->link_vars.line_speed = SPEED_10000;
  2509. bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
  2510. /* Only the PMF sets the HW */
  2511. if (bp->port.pmf)
  2512. storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
  2513. /* init Event Queue */
  2514. eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
  2515. eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
  2516. eq_data.producer = bp->eq_prod;
  2517. eq_data.index_id = HC_SP_INDEX_EQ_CONS;
  2518. eq_data.sb_id = DEF_SB_ID;
  2519. storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
  2520. }
  2521. static void bnx2x_e1h_disable(struct bnx2x *bp)
  2522. {
  2523. int port = BP_PORT(bp);
  2524. bnx2x_tx_disable(bp);
  2525. REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
  2526. }
  2527. static void bnx2x_e1h_enable(struct bnx2x *bp)
  2528. {
  2529. int port = BP_PORT(bp);
  2530. REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
  2531. /* Tx queue should be only reenabled */
  2532. netif_tx_wake_all_queues(bp->dev);
  2533. /*
  2534. * Should not call netif_carrier_on since it will be called if the link
  2535. * is up when checking for link state
  2536. */
  2537. }
  2538. #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
  2539. static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
  2540. {
  2541. struct eth_stats_info *ether_stat =
  2542. &bp->slowpath->drv_info_to_mcp.ether_stat;
  2543. strlcpy(ether_stat->version, DRV_MODULE_VERSION,
  2544. ETH_STAT_INFO_VERSION_LEN);
  2545. bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
  2546. DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
  2547. ether_stat->mac_local);
  2548. ether_stat->mtu_size = bp->dev->mtu;
  2549. if (bp->dev->features & NETIF_F_RXCSUM)
  2550. ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
  2551. if (bp->dev->features & NETIF_F_TSO)
  2552. ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
  2553. ether_stat->feature_flags |= bp->common.boot_mode;
  2554. ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
  2555. ether_stat->txq_size = bp->tx_ring_size;
  2556. ether_stat->rxq_size = bp->rx_ring_size;
  2557. }
  2558. static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
  2559. {
  2560. #ifdef BCM_CNIC
  2561. struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
  2562. struct fcoe_stats_info *fcoe_stat =
  2563. &bp->slowpath->drv_info_to_mcp.fcoe_stat;
  2564. memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
  2565. bp->fip_mac, ETH_ALEN);
  2566. fcoe_stat->qos_priority =
  2567. app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
  2568. /* insert FCoE stats from ramrod response */
  2569. if (!NO_FCOE(bp)) {
  2570. struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
  2571. &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
  2572. tstorm_queue_statistics;
  2573. struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
  2574. &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
  2575. xstorm_queue_statistics;
  2576. struct fcoe_statistics_params *fw_fcoe_stat =
  2577. &bp->fw_stats_data->fcoe;
  2578. ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
  2579. fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
  2580. ADD_64(fcoe_stat->rx_bytes_hi,
  2581. fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
  2582. fcoe_stat->rx_bytes_lo,
  2583. fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
  2584. ADD_64(fcoe_stat->rx_bytes_hi,
  2585. fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
  2586. fcoe_stat->rx_bytes_lo,
  2587. fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
  2588. ADD_64(fcoe_stat->rx_bytes_hi,
  2589. fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
  2590. fcoe_stat->rx_bytes_lo,
  2591. fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
  2592. ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
  2593. fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
  2594. ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
  2595. fcoe_q_tstorm_stats->rcv_ucast_pkts);
  2596. ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
  2597. fcoe_q_tstorm_stats->rcv_bcast_pkts);
  2598. ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
  2599. fcoe_q_tstorm_stats->rcv_mcast_pkts);
  2600. ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
  2601. fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
  2602. ADD_64(fcoe_stat->tx_bytes_hi,
  2603. fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
  2604. fcoe_stat->tx_bytes_lo,
  2605. fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
  2606. ADD_64(fcoe_stat->tx_bytes_hi,
  2607. fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
  2608. fcoe_stat->tx_bytes_lo,
  2609. fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
  2610. ADD_64(fcoe_stat->tx_bytes_hi,
  2611. fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
  2612. fcoe_stat->tx_bytes_lo,
  2613. fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
  2614. ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
  2615. fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
  2616. ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
  2617. fcoe_q_xstorm_stats->ucast_pkts_sent);
  2618. ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
  2619. fcoe_q_xstorm_stats->bcast_pkts_sent);
  2620. ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
  2621. fcoe_q_xstorm_stats->mcast_pkts_sent);
  2622. }
  2623. /* ask L5 driver to add data to the struct */
  2624. bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
  2625. #endif
  2626. }
  2627. static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
  2628. {
  2629. #ifdef BCM_CNIC
  2630. struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
  2631. struct iscsi_stats_info *iscsi_stat =
  2632. &bp->slowpath->drv_info_to_mcp.iscsi_stat;
  2633. memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
  2634. bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
  2635. iscsi_stat->qos_priority =
  2636. app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
  2637. /* ask L5 driver to add data to the struct */
  2638. bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
  2639. #endif
  2640. }
  2641. /* called due to MCP event (on pmf):
  2642. * reread new bandwidth configuration
  2643. * configure FW
  2644. * notify others function about the change
  2645. */
  2646. static void bnx2x_config_mf_bw(struct bnx2x *bp)
  2647. {
  2648. if (bp->link_vars.link_up) {
  2649. bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
  2650. bnx2x_link_sync_notify(bp);
  2651. }
  2652. storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
  2653. }
  2654. static void bnx2x_set_mf_bw(struct bnx2x *bp)
  2655. {
  2656. bnx2x_config_mf_bw(bp);
  2657. bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
  2658. }
  2659. static void bnx2x_handle_eee_event(struct bnx2x *bp)
  2660. {
  2661. DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
  2662. bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
  2663. }
  2664. static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
  2665. {
  2666. enum drv_info_opcode op_code;
  2667. u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
  2668. /* if drv_info version supported by MFW doesn't match - send NACK */
  2669. if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
  2670. bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
  2671. return;
  2672. }
  2673. op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
  2674. DRV_INFO_CONTROL_OP_CODE_SHIFT;
  2675. memset(&bp->slowpath->drv_info_to_mcp, 0,
  2676. sizeof(union drv_info_to_mcp));
  2677. switch (op_code) {
  2678. case ETH_STATS_OPCODE:
  2679. bnx2x_drv_info_ether_stat(bp);
  2680. break;
  2681. case FCOE_STATS_OPCODE:
  2682. bnx2x_drv_info_fcoe_stat(bp);
  2683. break;
  2684. case ISCSI_STATS_OPCODE:
  2685. bnx2x_drv_info_iscsi_stat(bp);
  2686. break;
  2687. default:
  2688. /* if op code isn't supported - send NACK */
  2689. bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
  2690. return;
  2691. }
  2692. /* if we got drv_info attn from MFW then these fields are defined in
  2693. * shmem2 for sure
  2694. */
  2695. SHMEM2_WR(bp, drv_info_host_addr_lo,
  2696. U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
  2697. SHMEM2_WR(bp, drv_info_host_addr_hi,
  2698. U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
  2699. bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
  2700. }
  2701. static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
  2702. {
  2703. DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
  2704. if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
  2705. /*
  2706. * This is the only place besides the function initialization
  2707. * where the bp->flags can change so it is done without any
  2708. * locks
  2709. */
  2710. if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
  2711. DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
  2712. bp->flags |= MF_FUNC_DIS;
  2713. bnx2x_e1h_disable(bp);
  2714. } else {
  2715. DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
  2716. bp->flags &= ~MF_FUNC_DIS;
  2717. bnx2x_e1h_enable(bp);
  2718. }
  2719. dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
  2720. }
  2721. if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
  2722. bnx2x_config_mf_bw(bp);
  2723. dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
  2724. }
  2725. /* Report results to MCP */
  2726. if (dcc_event)
  2727. bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
  2728. else
  2729. bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
  2730. }
  2731. /* must be called under the spq lock */
  2732. static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
  2733. {
  2734. struct eth_spe *next_spe = bp->spq_prod_bd;
  2735. if (bp->spq_prod_bd == bp->spq_last_bd) {
  2736. bp->spq_prod_bd = bp->spq;
  2737. bp->spq_prod_idx = 0;
  2738. DP(BNX2X_MSG_SP, "end of spq\n");
  2739. } else {
  2740. bp->spq_prod_bd++;
  2741. bp->spq_prod_idx++;
  2742. }
  2743. return next_spe;
  2744. }
  2745. /* must be called under the spq lock */
  2746. static void bnx2x_sp_prod_update(struct bnx2x *bp)
  2747. {
  2748. int func = BP_FUNC(bp);
  2749. /*
  2750. * Make sure that BD data is updated before writing the producer:
  2751. * BD data is written to the memory, the producer is read from the
  2752. * memory, thus we need a full memory barrier to ensure the ordering.
  2753. */
  2754. mb();
  2755. REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
  2756. bp->spq_prod_idx);
  2757. mmiowb();
  2758. }
  2759. /**
  2760. * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
  2761. *
  2762. * @cmd: command to check
  2763. * @cmd_type: command type
  2764. */
  2765. static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
  2766. {
  2767. if ((cmd_type == NONE_CONNECTION_TYPE) ||
  2768. (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
  2769. (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
  2770. (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
  2771. (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
  2772. (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
  2773. (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
  2774. return true;
  2775. else
  2776. return false;
  2777. }
  2778. /**
  2779. * bnx2x_sp_post - place a single command on an SP ring
  2780. *
  2781. * @bp: driver handle
  2782. * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
  2783. * @cid: SW CID the command is related to
  2784. * @data_hi: command private data address (high 32 bits)
  2785. * @data_lo: command private data address (low 32 bits)
  2786. * @cmd_type: command type (e.g. NONE, ETH)
  2787. *
  2788. * SP data is handled as if it's always an address pair, thus data fields are
  2789. * not swapped to little endian in upper functions. Instead this function swaps
  2790. * data as if it's two u32 fields.
  2791. */
  2792. int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
  2793. u32 data_hi, u32 data_lo, int cmd_type)
  2794. {
  2795. struct eth_spe *spe;
  2796. u16 type;
  2797. bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
  2798. #ifdef BNX2X_STOP_ON_ERROR
  2799. if (unlikely(bp->panic)) {
  2800. BNX2X_ERR("Can't post SP when there is panic\n");
  2801. return -EIO;
  2802. }
  2803. #endif
  2804. spin_lock_bh(&bp->spq_lock);
  2805. if (common) {
  2806. if (!atomic_read(&bp->eq_spq_left)) {
  2807. BNX2X_ERR("BUG! EQ ring full!\n");
  2808. spin_unlock_bh(&bp->spq_lock);
  2809. bnx2x_panic();
  2810. return -EBUSY;
  2811. }
  2812. } else if (!atomic_read(&bp->cq_spq_left)) {
  2813. BNX2X_ERR("BUG! SPQ ring full!\n");
  2814. spin_unlock_bh(&bp->spq_lock);
  2815. bnx2x_panic();
  2816. return -EBUSY;
  2817. }
  2818. spe = bnx2x_sp_get_next(bp);
  2819. /* CID needs port number to be encoded int it */
  2820. spe->hdr.conn_and_cmd_data =
  2821. cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
  2822. HW_CID(bp, cid));
  2823. type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  2824. type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
  2825. SPE_HDR_FUNCTION_ID);
  2826. spe->hdr.type = cpu_to_le16(type);
  2827. spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
  2828. spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
  2829. /*
  2830. * It's ok if the actual decrement is issued towards the memory
  2831. * somewhere between the spin_lock and spin_unlock. Thus no
  2832. * more explict memory barrier is needed.
  2833. */
  2834. if (common)
  2835. atomic_dec(&bp->eq_spq_left);
  2836. else
  2837. atomic_dec(&bp->cq_spq_left);
  2838. DP(BNX2X_MSG_SP,
  2839. "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
  2840. bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
  2841. (u32)(U64_LO(bp->spq_mapping) +
  2842. (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
  2843. HW_CID(bp, cid), data_hi, data_lo, type,
  2844. atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
  2845. bnx2x_sp_prod_update(bp);
  2846. spin_unlock_bh(&bp->spq_lock);
  2847. return 0;
  2848. }
  2849. /* acquire split MCP access lock register */
  2850. static int bnx2x_acquire_alr(struct bnx2x *bp)
  2851. {
  2852. u32 j, val;
  2853. int rc = 0;
  2854. might_sleep();
  2855. for (j = 0; j < 1000; j++) {
  2856. val = (1UL << 31);
  2857. REG_WR(bp, GRCBASE_MCP + 0x9c, val);
  2858. val = REG_RD(bp, GRCBASE_MCP + 0x9c);
  2859. if (val & (1L << 31))
  2860. break;
  2861. msleep(5);
  2862. }
  2863. if (!(val & (1L << 31))) {
  2864. BNX2X_ERR("Cannot acquire MCP access lock register\n");
  2865. rc = -EBUSY;
  2866. }
  2867. return rc;
  2868. }
  2869. /* release split MCP access lock register */
  2870. static void bnx2x_release_alr(struct bnx2x *bp)
  2871. {
  2872. REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
  2873. }
  2874. #define BNX2X_DEF_SB_ATT_IDX 0x0001
  2875. #define BNX2X_DEF_SB_IDX 0x0002
  2876. static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
  2877. {
  2878. struct host_sp_status_block *def_sb = bp->def_status_blk;
  2879. u16 rc = 0;
  2880. barrier(); /* status block is written to by the chip */
  2881. if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
  2882. bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
  2883. rc |= BNX2X_DEF_SB_ATT_IDX;
  2884. }
  2885. if (bp->def_idx != def_sb->sp_sb.running_index) {
  2886. bp->def_idx = def_sb->sp_sb.running_index;
  2887. rc |= BNX2X_DEF_SB_IDX;
  2888. }
  2889. /* Do not reorder: indecies reading should complete before handling */
  2890. barrier();
  2891. return rc;
  2892. }
  2893. /*
  2894. * slow path service functions
  2895. */
  2896. static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
  2897. {
  2898. int port = BP_PORT(bp);
  2899. u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
  2900. MISC_REG_AEU_MASK_ATTN_FUNC_0;
  2901. u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
  2902. NIG_REG_MASK_INTERRUPT_PORT0;
  2903. u32 aeu_mask;
  2904. u32 nig_mask = 0;
  2905. u32 reg_addr;
  2906. if (bp->attn_state & asserted)
  2907. BNX2X_ERR("IGU ERROR\n");
  2908. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
  2909. aeu_mask = REG_RD(bp, aeu_addr);
  2910. DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
  2911. aeu_mask, asserted);
  2912. aeu_mask &= ~(asserted & 0x3ff);
  2913. DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
  2914. REG_WR(bp, aeu_addr, aeu_mask);
  2915. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
  2916. DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
  2917. bp->attn_state |= asserted;
  2918. DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
  2919. if (asserted & ATTN_HARD_WIRED_MASK) {
  2920. if (asserted & ATTN_NIG_FOR_FUNC) {
  2921. bnx2x_acquire_phy_lock(bp);
  2922. /* save nig interrupt mask */
  2923. nig_mask = REG_RD(bp, nig_int_mask_addr);
  2924. /* If nig_mask is not set, no need to call the update
  2925. * function.
  2926. */
  2927. if (nig_mask) {
  2928. REG_WR(bp, nig_int_mask_addr, 0);
  2929. bnx2x_link_attn(bp);
  2930. }
  2931. /* handle unicore attn? */
  2932. }
  2933. if (asserted & ATTN_SW_TIMER_4_FUNC)
  2934. DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
  2935. if (asserted & GPIO_2_FUNC)
  2936. DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
  2937. if (asserted & GPIO_3_FUNC)
  2938. DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
  2939. if (asserted & GPIO_4_FUNC)
  2940. DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
  2941. if (port == 0) {
  2942. if (asserted & ATTN_GENERAL_ATTN_1) {
  2943. DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
  2944. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
  2945. }
  2946. if (asserted & ATTN_GENERAL_ATTN_2) {
  2947. DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
  2948. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
  2949. }
  2950. if (asserted & ATTN_GENERAL_ATTN_3) {
  2951. DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
  2952. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
  2953. }
  2954. } else {
  2955. if (asserted & ATTN_GENERAL_ATTN_4) {
  2956. DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
  2957. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
  2958. }
  2959. if (asserted & ATTN_GENERAL_ATTN_5) {
  2960. DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
  2961. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
  2962. }
  2963. if (asserted & ATTN_GENERAL_ATTN_6) {
  2964. DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
  2965. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
  2966. }
  2967. }
  2968. } /* if hardwired */
  2969. if (bp->common.int_block == INT_BLOCK_HC)
  2970. reg_addr = (HC_REG_COMMAND_REG + port*32 +
  2971. COMMAND_REG_ATTN_BITS_SET);
  2972. else
  2973. reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
  2974. DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
  2975. (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
  2976. REG_WR(bp, reg_addr, asserted);
  2977. /* now set back the mask */
  2978. if (asserted & ATTN_NIG_FOR_FUNC) {
  2979. REG_WR(bp, nig_int_mask_addr, nig_mask);
  2980. bnx2x_release_phy_lock(bp);
  2981. }
  2982. }
  2983. static void bnx2x_fan_failure(struct bnx2x *bp)
  2984. {
  2985. int port = BP_PORT(bp);
  2986. u32 ext_phy_config;
  2987. /* mark the failure */
  2988. ext_phy_config =
  2989. SHMEM_RD(bp,
  2990. dev_info.port_hw_config[port].external_phy_config);
  2991. ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
  2992. ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
  2993. SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
  2994. ext_phy_config);
  2995. /* log the failure */
  2996. netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
  2997. "Please contact OEM Support for assistance\n");
  2998. /*
  2999. * Scheudle device reset (unload)
  3000. * This is due to some boards consuming sufficient power when driver is
  3001. * up to overheat if fan fails.
  3002. */
  3003. smp_mb__before_clear_bit();
  3004. set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
  3005. smp_mb__after_clear_bit();
  3006. schedule_delayed_work(&bp->sp_rtnl_task, 0);
  3007. }
  3008. static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
  3009. {
  3010. int port = BP_PORT(bp);
  3011. int reg_offset;
  3012. u32 val;
  3013. reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
  3014. MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
  3015. if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
  3016. val = REG_RD(bp, reg_offset);
  3017. val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
  3018. REG_WR(bp, reg_offset, val);
  3019. BNX2X_ERR("SPIO5 hw attention\n");
  3020. /* Fan failure attention */
  3021. bnx2x_hw_reset_phy(&bp->link_params);
  3022. bnx2x_fan_failure(bp);
  3023. }
  3024. if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
  3025. bnx2x_acquire_phy_lock(bp);
  3026. bnx2x_handle_module_detect_int(&bp->link_params);
  3027. bnx2x_release_phy_lock(bp);
  3028. }
  3029. if (attn & HW_INTERRUT_ASSERT_SET_0) {
  3030. val = REG_RD(bp, reg_offset);
  3031. val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
  3032. REG_WR(bp, reg_offset, val);
  3033. BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
  3034. (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
  3035. bnx2x_panic();
  3036. }
  3037. }
  3038. static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
  3039. {
  3040. u32 val;
  3041. if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
  3042. val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
  3043. BNX2X_ERR("DB hw attention 0x%x\n", val);
  3044. /* DORQ discard attention */
  3045. if (val & 0x2)
  3046. BNX2X_ERR("FATAL error from DORQ\n");
  3047. }
  3048. if (attn & HW_INTERRUT_ASSERT_SET_1) {
  3049. int port = BP_PORT(bp);
  3050. int reg_offset;
  3051. reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
  3052. MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
  3053. val = REG_RD(bp, reg_offset);
  3054. val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
  3055. REG_WR(bp, reg_offset, val);
  3056. BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
  3057. (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
  3058. bnx2x_panic();
  3059. }
  3060. }
  3061. static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
  3062. {
  3063. u32 val;
  3064. if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
  3065. val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
  3066. BNX2X_ERR("CFC hw attention 0x%x\n", val);
  3067. /* CFC error attention */
  3068. if (val & 0x2)
  3069. BNX2X_ERR("FATAL error from CFC\n");
  3070. }
  3071. if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
  3072. val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
  3073. BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
  3074. /* RQ_USDMDP_FIFO_OVERFLOW */
  3075. if (val & 0x18000)
  3076. BNX2X_ERR("FATAL error from PXP\n");
  3077. if (!CHIP_IS_E1x(bp)) {
  3078. val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
  3079. BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
  3080. }
  3081. }
  3082. if (attn & HW_INTERRUT_ASSERT_SET_2) {
  3083. int port = BP_PORT(bp);
  3084. int reg_offset;
  3085. reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
  3086. MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
  3087. val = REG_RD(bp, reg_offset);
  3088. val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
  3089. REG_WR(bp, reg_offset, val);
  3090. BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
  3091. (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
  3092. bnx2x_panic();
  3093. }
  3094. }
  3095. static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
  3096. {
  3097. u32 val;
  3098. if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
  3099. if (attn & BNX2X_PMF_LINK_ASSERT) {
  3100. int func = BP_FUNC(bp);
  3101. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
  3102. bnx2x_read_mf_cfg(bp);
  3103. bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
  3104. func_mf_config[BP_ABS_FUNC(bp)].config);
  3105. val = SHMEM_RD(bp,
  3106. func_mb[BP_FW_MB_IDX(bp)].drv_status);
  3107. if (val & DRV_STATUS_DCC_EVENT_MASK)
  3108. bnx2x_dcc_event(bp,
  3109. (val & DRV_STATUS_DCC_EVENT_MASK));
  3110. if (val & DRV_STATUS_SET_MF_BW)
  3111. bnx2x_set_mf_bw(bp);
  3112. if (val & DRV_STATUS_DRV_INFO_REQ)
  3113. bnx2x_handle_drv_info_req(bp);
  3114. if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
  3115. bnx2x_pmf_update(bp);
  3116. if (bp->port.pmf &&
  3117. (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
  3118. bp->dcbx_enabled > 0)
  3119. /* start dcbx state machine */
  3120. bnx2x_dcbx_set_params(bp,
  3121. BNX2X_DCBX_STATE_NEG_RECEIVED);
  3122. if (val & DRV_STATUS_AFEX_EVENT_MASK)
  3123. bnx2x_handle_afex_cmd(bp,
  3124. val & DRV_STATUS_AFEX_EVENT_MASK);
  3125. if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
  3126. bnx2x_handle_eee_event(bp);
  3127. if (bp->link_vars.periodic_flags &
  3128. PERIODIC_FLAGS_LINK_EVENT) {
  3129. /* sync with link */
  3130. bnx2x_acquire_phy_lock(bp);
  3131. bp->link_vars.periodic_flags &=
  3132. ~PERIODIC_FLAGS_LINK_EVENT;
  3133. bnx2x_release_phy_lock(bp);
  3134. if (IS_MF(bp))
  3135. bnx2x_link_sync_notify(bp);
  3136. bnx2x_link_report(bp);
  3137. }
  3138. /* Always call it here: bnx2x_link_report() will
  3139. * prevent the link indication duplication.
  3140. */
  3141. bnx2x__link_status_update(bp);
  3142. } else if (attn & BNX2X_MC_ASSERT_BITS) {
  3143. BNX2X_ERR("MC assert!\n");
  3144. bnx2x_mc_assert(bp);
  3145. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
  3146. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
  3147. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
  3148. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
  3149. bnx2x_panic();
  3150. } else if (attn & BNX2X_MCP_ASSERT) {
  3151. BNX2X_ERR("MCP assert!\n");
  3152. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
  3153. bnx2x_fw_dump(bp);
  3154. } else
  3155. BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
  3156. }
  3157. if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
  3158. BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
  3159. if (attn & BNX2X_GRC_TIMEOUT) {
  3160. val = CHIP_IS_E1(bp) ? 0 :
  3161. REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
  3162. BNX2X_ERR("GRC time-out 0x%08x\n", val);
  3163. }
  3164. if (attn & BNX2X_GRC_RSV) {
  3165. val = CHIP_IS_E1(bp) ? 0 :
  3166. REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
  3167. BNX2X_ERR("GRC reserved 0x%08x\n", val);
  3168. }
  3169. REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
  3170. }
  3171. }
  3172. /*
  3173. * Bits map:
  3174. * 0-7 - Engine0 load counter.
  3175. * 8-15 - Engine1 load counter.
  3176. * 16 - Engine0 RESET_IN_PROGRESS bit.
  3177. * 17 - Engine1 RESET_IN_PROGRESS bit.
  3178. * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
  3179. * on the engine
  3180. * 19 - Engine1 ONE_IS_LOADED.
  3181. * 20 - Chip reset flow bit. When set none-leader must wait for both engines
  3182. * leader to complete (check for both RESET_IN_PROGRESS bits and not for
  3183. * just the one belonging to its engine).
  3184. *
  3185. */
  3186. #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
  3187. #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
  3188. #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
  3189. #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
  3190. #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
  3191. #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
  3192. #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
  3193. #define BNX2X_GLOBAL_RESET_BIT 0x00040000
  3194. /*
  3195. * Set the GLOBAL_RESET bit.
  3196. *
  3197. * Should be run under rtnl lock
  3198. */
  3199. void bnx2x_set_reset_global(struct bnx2x *bp)
  3200. {
  3201. u32 val;
  3202. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3203. val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
  3204. REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
  3205. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3206. }
  3207. /*
  3208. * Clear the GLOBAL_RESET bit.
  3209. *
  3210. * Should be run under rtnl lock
  3211. */
  3212. static void bnx2x_clear_reset_global(struct bnx2x *bp)
  3213. {
  3214. u32 val;
  3215. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3216. val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
  3217. REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
  3218. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3219. }
  3220. /*
  3221. * Checks the GLOBAL_RESET bit.
  3222. *
  3223. * should be run under rtnl lock
  3224. */
  3225. static bool bnx2x_reset_is_global(struct bnx2x *bp)
  3226. {
  3227. u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
  3228. DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
  3229. return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
  3230. }
  3231. /*
  3232. * Clear RESET_IN_PROGRESS bit for the current engine.
  3233. *
  3234. * Should be run under rtnl lock
  3235. */
  3236. static void bnx2x_set_reset_done(struct bnx2x *bp)
  3237. {
  3238. u32 val;
  3239. u32 bit = BP_PATH(bp) ?
  3240. BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
  3241. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3242. val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
  3243. /* Clear the bit */
  3244. val &= ~bit;
  3245. REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
  3246. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3247. }
  3248. /*
  3249. * Set RESET_IN_PROGRESS for the current engine.
  3250. *
  3251. * should be run under rtnl lock
  3252. */
  3253. void bnx2x_set_reset_in_progress(struct bnx2x *bp)
  3254. {
  3255. u32 val;
  3256. u32 bit = BP_PATH(bp) ?
  3257. BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
  3258. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3259. val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
  3260. /* Set the bit */
  3261. val |= bit;
  3262. REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
  3263. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3264. }
  3265. /*
  3266. * Checks the RESET_IN_PROGRESS bit for the given engine.
  3267. * should be run under rtnl lock
  3268. */
  3269. bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
  3270. {
  3271. u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
  3272. u32 bit = engine ?
  3273. BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
  3274. /* return false if bit is set */
  3275. return (val & bit) ? false : true;
  3276. }
  3277. /*
  3278. * set pf load for the current pf.
  3279. *
  3280. * should be run under rtnl lock
  3281. */
  3282. void bnx2x_set_pf_load(struct bnx2x *bp)
  3283. {
  3284. u32 val1, val;
  3285. u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
  3286. BNX2X_PATH0_LOAD_CNT_MASK;
  3287. u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
  3288. BNX2X_PATH0_LOAD_CNT_SHIFT;
  3289. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3290. val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
  3291. DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
  3292. /* get the current counter value */
  3293. val1 = (val & mask) >> shift;
  3294. /* set bit of that PF */
  3295. val1 |= (1 << bp->pf_num);
  3296. /* clear the old value */
  3297. val &= ~mask;
  3298. /* set the new one */
  3299. val |= ((val1 << shift) & mask);
  3300. REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
  3301. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3302. }
  3303. /**
  3304. * bnx2x_clear_pf_load - clear pf load mark
  3305. *
  3306. * @bp: driver handle
  3307. *
  3308. * Should be run under rtnl lock.
  3309. * Decrements the load counter for the current engine. Returns
  3310. * whether other functions are still loaded
  3311. */
  3312. bool bnx2x_clear_pf_load(struct bnx2x *bp)
  3313. {
  3314. u32 val1, val;
  3315. u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
  3316. BNX2X_PATH0_LOAD_CNT_MASK;
  3317. u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
  3318. BNX2X_PATH0_LOAD_CNT_SHIFT;
  3319. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3320. val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
  3321. DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
  3322. /* get the current counter value */
  3323. val1 = (val & mask) >> shift;
  3324. /* clear bit of that PF */
  3325. val1 &= ~(1 << bp->pf_num);
  3326. /* clear the old value */
  3327. val &= ~mask;
  3328. /* set the new one */
  3329. val |= ((val1 << shift) & mask);
  3330. REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
  3331. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
  3332. return val1 != 0;
  3333. }
  3334. /*
  3335. * Read the load status for the current engine.
  3336. *
  3337. * should be run under rtnl lock
  3338. */
  3339. static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
  3340. {
  3341. u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
  3342. BNX2X_PATH0_LOAD_CNT_MASK);
  3343. u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
  3344. BNX2X_PATH0_LOAD_CNT_SHIFT);
  3345. u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
  3346. DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
  3347. val = (val & mask) >> shift;
  3348. DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
  3349. engine, val);
  3350. return val != 0;
  3351. }
  3352. static void _print_next_block(int idx, const char *blk)
  3353. {
  3354. pr_cont("%s%s", idx ? ", " : "", blk);
  3355. }
  3356. static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
  3357. bool print)
  3358. {
  3359. int i = 0;
  3360. u32 cur_bit = 0;
  3361. for (i = 0; sig; i++) {
  3362. cur_bit = ((u32)0x1 << i);
  3363. if (sig & cur_bit) {
  3364. switch (cur_bit) {
  3365. case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
  3366. if (print)
  3367. _print_next_block(par_num++, "BRB");
  3368. break;
  3369. case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
  3370. if (print)
  3371. _print_next_block(par_num++, "PARSER");
  3372. break;
  3373. case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
  3374. if (print)
  3375. _print_next_block(par_num++, "TSDM");
  3376. break;
  3377. case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
  3378. if (print)
  3379. _print_next_block(par_num++,
  3380. "SEARCHER");
  3381. break;
  3382. case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
  3383. if (print)
  3384. _print_next_block(par_num++, "TCM");
  3385. break;
  3386. case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
  3387. if (print)
  3388. _print_next_block(par_num++, "TSEMI");
  3389. break;
  3390. case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
  3391. if (print)
  3392. _print_next_block(par_num++, "XPB");
  3393. break;
  3394. }
  3395. /* Clear the bit */
  3396. sig &= ~cur_bit;
  3397. }
  3398. }
  3399. return par_num;
  3400. }
  3401. static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
  3402. bool *global, bool print)
  3403. {
  3404. int i = 0;
  3405. u32 cur_bit = 0;
  3406. for (i = 0; sig; i++) {
  3407. cur_bit = ((u32)0x1 << i);
  3408. if (sig & cur_bit) {
  3409. switch (cur_bit) {
  3410. case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
  3411. if (print)
  3412. _print_next_block(par_num++, "PBF");
  3413. break;
  3414. case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
  3415. if (print)
  3416. _print_next_block(par_num++, "QM");
  3417. break;
  3418. case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
  3419. if (print)
  3420. _print_next_block(par_num++, "TM");
  3421. break;
  3422. case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
  3423. if (print)
  3424. _print_next_block(par_num++, "XSDM");
  3425. break;
  3426. case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
  3427. if (print)
  3428. _print_next_block(par_num++, "XCM");
  3429. break;
  3430. case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
  3431. if (print)
  3432. _print_next_block(par_num++, "XSEMI");
  3433. break;
  3434. case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
  3435. if (print)
  3436. _print_next_block(par_num++,
  3437. "DOORBELLQ");
  3438. break;
  3439. case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
  3440. if (print)
  3441. _print_next_block(par_num++, "NIG");
  3442. break;
  3443. case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
  3444. if (print)
  3445. _print_next_block(par_num++,
  3446. "VAUX PCI CORE");
  3447. *global = true;
  3448. break;
  3449. case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
  3450. if (print)
  3451. _print_next_block(par_num++, "DEBUG");
  3452. break;
  3453. case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
  3454. if (print)
  3455. _print_next_block(par_num++, "USDM");
  3456. break;
  3457. case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
  3458. if (print)
  3459. _print_next_block(par_num++, "UCM");
  3460. break;
  3461. case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
  3462. if (print)
  3463. _print_next_block(par_num++, "USEMI");
  3464. break;
  3465. case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
  3466. if (print)
  3467. _print_next_block(par_num++, "UPB");
  3468. break;
  3469. case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
  3470. if (print)
  3471. _print_next_block(par_num++, "CSDM");
  3472. break;
  3473. case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
  3474. if (print)
  3475. _print_next_block(par_num++, "CCM");
  3476. break;
  3477. }
  3478. /* Clear the bit */
  3479. sig &= ~cur_bit;
  3480. }
  3481. }
  3482. return par_num;
  3483. }
  3484. static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
  3485. bool print)
  3486. {
  3487. int i = 0;
  3488. u32 cur_bit = 0;
  3489. for (i = 0; sig; i++) {
  3490. cur_bit = ((u32)0x1 << i);
  3491. if (sig & cur_bit) {
  3492. switch (cur_bit) {
  3493. case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
  3494. if (print)
  3495. _print_next_block(par_num++, "CSEMI");
  3496. break;
  3497. case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
  3498. if (print)
  3499. _print_next_block(par_num++, "PXP");
  3500. break;
  3501. case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
  3502. if (print)
  3503. _print_next_block(par_num++,
  3504. "PXPPCICLOCKCLIENT");
  3505. break;
  3506. case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
  3507. if (print)
  3508. _print_next_block(par_num++, "CFC");
  3509. break;
  3510. case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
  3511. if (print)
  3512. _print_next_block(par_num++, "CDU");
  3513. break;
  3514. case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
  3515. if (print)
  3516. _print_next_block(par_num++, "DMAE");
  3517. break;
  3518. case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
  3519. if (print)
  3520. _print_next_block(par_num++, "IGU");
  3521. break;
  3522. case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
  3523. if (print)
  3524. _print_next_block(par_num++, "MISC");
  3525. break;
  3526. }
  3527. /* Clear the bit */
  3528. sig &= ~cur_bit;
  3529. }
  3530. }
  3531. return par_num;
  3532. }
  3533. static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
  3534. bool *global, bool print)
  3535. {
  3536. int i = 0;
  3537. u32 cur_bit = 0;
  3538. for (i = 0; sig; i++) {
  3539. cur_bit = ((u32)0x1 << i);
  3540. if (sig & cur_bit) {
  3541. switch (cur_bit) {
  3542. case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
  3543. if (print)
  3544. _print_next_block(par_num++, "MCP ROM");
  3545. *global = true;
  3546. break;
  3547. case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
  3548. if (print)
  3549. _print_next_block(par_num++,
  3550. "MCP UMP RX");
  3551. *global = true;
  3552. break;
  3553. case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
  3554. if (print)
  3555. _print_next_block(par_num++,
  3556. "MCP UMP TX");
  3557. *global = true;
  3558. break;
  3559. case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
  3560. if (print)
  3561. _print_next_block(par_num++,
  3562. "MCP SCPAD");
  3563. *global = true;
  3564. break;
  3565. }
  3566. /* Clear the bit */
  3567. sig &= ~cur_bit;
  3568. }
  3569. }
  3570. return par_num;
  3571. }
  3572. static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
  3573. bool print)
  3574. {
  3575. int i = 0;
  3576. u32 cur_bit = 0;
  3577. for (i = 0; sig; i++) {
  3578. cur_bit = ((u32)0x1 << i);
  3579. if (sig & cur_bit) {
  3580. switch (cur_bit) {
  3581. case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
  3582. if (print)
  3583. _print_next_block(par_num++, "PGLUE_B");
  3584. break;
  3585. case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
  3586. if (print)
  3587. _print_next_block(par_num++, "ATC");
  3588. break;
  3589. }
  3590. /* Clear the bit */
  3591. sig &= ~cur_bit;
  3592. }
  3593. }
  3594. return par_num;
  3595. }
  3596. static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
  3597. u32 *sig)
  3598. {
  3599. if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
  3600. (sig[1] & HW_PRTY_ASSERT_SET_1) ||
  3601. (sig[2] & HW_PRTY_ASSERT_SET_2) ||
  3602. (sig[3] & HW_PRTY_ASSERT_SET_3) ||
  3603. (sig[4] & HW_PRTY_ASSERT_SET_4)) {
  3604. int par_num = 0;
  3605. DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
  3606. "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
  3607. sig[0] & HW_PRTY_ASSERT_SET_0,
  3608. sig[1] & HW_PRTY_ASSERT_SET_1,
  3609. sig[2] & HW_PRTY_ASSERT_SET_2,
  3610. sig[3] & HW_PRTY_ASSERT_SET_3,
  3611. sig[4] & HW_PRTY_ASSERT_SET_4);
  3612. if (print)
  3613. netdev_err(bp->dev,
  3614. "Parity errors detected in blocks: ");
  3615. par_num = bnx2x_check_blocks_with_parity0(
  3616. sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
  3617. par_num = bnx2x_check_blocks_with_parity1(
  3618. sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
  3619. par_num = bnx2x_check_blocks_with_parity2(
  3620. sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
  3621. par_num = bnx2x_check_blocks_with_parity3(
  3622. sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
  3623. par_num = bnx2x_check_blocks_with_parity4(
  3624. sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
  3625. if (print)
  3626. pr_cont("\n");
  3627. return true;
  3628. } else
  3629. return false;
  3630. }
  3631. /**
  3632. * bnx2x_chk_parity_attn - checks for parity attentions.
  3633. *
  3634. * @bp: driver handle
  3635. * @global: true if there was a global attention
  3636. * @print: show parity attention in syslog
  3637. */
  3638. bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
  3639. {
  3640. struct attn_route attn = { {0} };
  3641. int port = BP_PORT(bp);
  3642. attn.sig[0] = REG_RD(bp,
  3643. MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
  3644. port*4);
  3645. attn.sig[1] = REG_RD(bp,
  3646. MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
  3647. port*4);
  3648. attn.sig[2] = REG_RD(bp,
  3649. MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
  3650. port*4);
  3651. attn.sig[3] = REG_RD(bp,
  3652. MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
  3653. port*4);
  3654. if (!CHIP_IS_E1x(bp))
  3655. attn.sig[4] = REG_RD(bp,
  3656. MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
  3657. port*4);
  3658. return bnx2x_parity_attn(bp, global, print, attn.sig);
  3659. }
  3660. static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
  3661. {
  3662. u32 val;
  3663. if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
  3664. val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
  3665. BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
  3666. if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
  3667. BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
  3668. if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
  3669. BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
  3670. if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
  3671. BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
  3672. if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
  3673. BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
  3674. if (val &
  3675. PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
  3676. BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
  3677. if (val &
  3678. PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
  3679. BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
  3680. if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
  3681. BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
  3682. if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
  3683. BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
  3684. if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
  3685. BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
  3686. }
  3687. if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
  3688. val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
  3689. BNX2X_ERR("ATC hw attention 0x%x\n", val);
  3690. if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
  3691. BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
  3692. if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
  3693. BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
  3694. if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
  3695. BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
  3696. if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
  3697. BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
  3698. if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
  3699. BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
  3700. if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
  3701. BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
  3702. }
  3703. if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
  3704. AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
  3705. BNX2X_ERR("FATAL parity attention set4 0x%x\n",
  3706. (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
  3707. AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
  3708. }
  3709. }
  3710. static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
  3711. {
  3712. struct attn_route attn, *group_mask;
  3713. int port = BP_PORT(bp);
  3714. int index;
  3715. u32 reg_addr;
  3716. u32 val;
  3717. u32 aeu_mask;
  3718. bool global = false;
  3719. /* need to take HW lock because MCP or other port might also
  3720. try to handle this event */
  3721. bnx2x_acquire_alr(bp);
  3722. if (bnx2x_chk_parity_attn(bp, &global, true)) {
  3723. #ifndef BNX2X_STOP_ON_ERROR
  3724. bp->recovery_state = BNX2X_RECOVERY_INIT;
  3725. schedule_delayed_work(&bp->sp_rtnl_task, 0);
  3726. /* Disable HW interrupts */
  3727. bnx2x_int_disable(bp);
  3728. /* In case of parity errors don't handle attentions so that
  3729. * other function would "see" parity errors.
  3730. */
  3731. #else
  3732. bnx2x_panic();
  3733. #endif
  3734. bnx2x_release_alr(bp);
  3735. return;
  3736. }
  3737. attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
  3738. attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
  3739. attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
  3740. attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
  3741. if (!CHIP_IS_E1x(bp))
  3742. attn.sig[4] =
  3743. REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
  3744. else
  3745. attn.sig[4] = 0;
  3746. DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
  3747. attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
  3748. for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
  3749. if (deasserted & (1 << index)) {
  3750. group_mask = &bp->attn_group[index];
  3751. DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
  3752. index,
  3753. group_mask->sig[0], group_mask->sig[1],
  3754. group_mask->sig[2], group_mask->sig[3],
  3755. group_mask->sig[4]);
  3756. bnx2x_attn_int_deasserted4(bp,
  3757. attn.sig[4] & group_mask->sig[4]);
  3758. bnx2x_attn_int_deasserted3(bp,
  3759. attn.sig[3] & group_mask->sig[3]);
  3760. bnx2x_attn_int_deasserted1(bp,
  3761. attn.sig[1] & group_mask->sig[1]);
  3762. bnx2x_attn_int_deasserted2(bp,
  3763. attn.sig[2] & group_mask->sig[2]);
  3764. bnx2x_attn_int_deasserted0(bp,
  3765. attn.sig[0] & group_mask->sig[0]);
  3766. }
  3767. }
  3768. bnx2x_release_alr(bp);
  3769. if (bp->common.int_block == INT_BLOCK_HC)
  3770. reg_addr = (HC_REG_COMMAND_REG + port*32 +
  3771. COMMAND_REG_ATTN_BITS_CLR);
  3772. else
  3773. reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
  3774. val = ~deasserted;
  3775. DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
  3776. (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
  3777. REG_WR(bp, reg_addr, val);
  3778. if (~bp->attn_state & deasserted)
  3779. BNX2X_ERR("IGU ERROR\n");
  3780. reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
  3781. MISC_REG_AEU_MASK_ATTN_FUNC_0;
  3782. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
  3783. aeu_mask = REG_RD(bp, reg_addr);
  3784. DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
  3785. aeu_mask, deasserted);
  3786. aeu_mask |= (deasserted & 0x3ff);
  3787. DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
  3788. REG_WR(bp, reg_addr, aeu_mask);
  3789. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
  3790. DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
  3791. bp->attn_state &= ~deasserted;
  3792. DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
  3793. }
  3794. static void bnx2x_attn_int(struct bnx2x *bp)
  3795. {
  3796. /* read local copy of bits */
  3797. u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
  3798. attn_bits);
  3799. u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
  3800. attn_bits_ack);
  3801. u32 attn_state = bp->attn_state;
  3802. /* look for changed bits */
  3803. u32 asserted = attn_bits & ~attn_ack & ~attn_state;
  3804. u32 deasserted = ~attn_bits & attn_ack & attn_state;
  3805. DP(NETIF_MSG_HW,
  3806. "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
  3807. attn_bits, attn_ack, asserted, deasserted);
  3808. if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
  3809. BNX2X_ERR("BAD attention state\n");
  3810. /* handle bits that were raised */
  3811. if (asserted)
  3812. bnx2x_attn_int_asserted(bp, asserted);
  3813. if (deasserted)
  3814. bnx2x_attn_int_deasserted(bp, deasserted);
  3815. }
  3816. void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
  3817. u16 index, u8 op, u8 update)
  3818. {
  3819. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
  3820. bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
  3821. igu_addr);
  3822. }
  3823. static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
  3824. {
  3825. /* No memory barriers */
  3826. storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
  3827. mmiowb(); /* keep prod updates ordered */
  3828. }
  3829. #ifdef BCM_CNIC
  3830. static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
  3831. union event_ring_elem *elem)
  3832. {
  3833. u8 err = elem->message.error;
  3834. if (!bp->cnic_eth_dev.starting_cid ||
  3835. (cid < bp->cnic_eth_dev.starting_cid &&
  3836. cid != bp->cnic_eth_dev.iscsi_l2_cid))
  3837. return 1;
  3838. DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
  3839. if (unlikely(err)) {
  3840. BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
  3841. cid);
  3842. bnx2x_panic_dump(bp);
  3843. }
  3844. bnx2x_cnic_cfc_comp(bp, cid, err);
  3845. return 0;
  3846. }
  3847. #endif
  3848. static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
  3849. {
  3850. struct bnx2x_mcast_ramrod_params rparam;
  3851. int rc;
  3852. memset(&rparam, 0, sizeof(rparam));
  3853. rparam.mcast_obj = &bp->mcast_obj;
  3854. netif_addr_lock_bh(bp->dev);
  3855. /* Clear pending state for the last command */
  3856. bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
  3857. /* If there are pending mcast commands - send them */
  3858. if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
  3859. rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
  3860. if (rc < 0)
  3861. BNX2X_ERR("Failed to send pending mcast commands: %d\n",
  3862. rc);
  3863. }
  3864. netif_addr_unlock_bh(bp->dev);
  3865. }
  3866. static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
  3867. union event_ring_elem *elem)
  3868. {
  3869. unsigned long ramrod_flags = 0;
  3870. int rc = 0;
  3871. u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
  3872. struct bnx2x_vlan_mac_obj *vlan_mac_obj;
  3873. /* Always push next commands out, don't wait here */
  3874. __set_bit(RAMROD_CONT, &ramrod_flags);
  3875. switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
  3876. case BNX2X_FILTER_MAC_PENDING:
  3877. DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
  3878. #ifdef BCM_CNIC
  3879. if (cid == BNX2X_ISCSI_ETH_CID(bp))
  3880. vlan_mac_obj = &bp->iscsi_l2_mac_obj;
  3881. else
  3882. #endif
  3883. vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
  3884. break;
  3885. case BNX2X_FILTER_MCAST_PENDING:
  3886. DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
  3887. /* This is only relevant for 57710 where multicast MACs are
  3888. * configured as unicast MACs using the same ramrod.
  3889. */
  3890. bnx2x_handle_mcast_eqe(bp);
  3891. return;
  3892. default:
  3893. BNX2X_ERR("Unsupported classification command: %d\n",
  3894. elem->message.data.eth_event.echo);
  3895. return;
  3896. }
  3897. rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
  3898. if (rc < 0)
  3899. BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
  3900. else if (rc > 0)
  3901. DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
  3902. }
  3903. #ifdef BCM_CNIC
  3904. static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
  3905. #endif
  3906. static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
  3907. {
  3908. netif_addr_lock_bh(bp->dev);
  3909. clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
  3910. /* Send rx_mode command again if was requested */
  3911. if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
  3912. bnx2x_set_storm_rx_mode(bp);
  3913. #ifdef BCM_CNIC
  3914. else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
  3915. &bp->sp_state))
  3916. bnx2x_set_iscsi_eth_rx_mode(bp, true);
  3917. else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
  3918. &bp->sp_state))
  3919. bnx2x_set_iscsi_eth_rx_mode(bp, false);
  3920. #endif
  3921. netif_addr_unlock_bh(bp->dev);
  3922. }
  3923. static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
  3924. union event_ring_elem *elem)
  3925. {
  3926. if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
  3927. DP(BNX2X_MSG_SP,
  3928. "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
  3929. elem->message.data.vif_list_event.func_bit_map);
  3930. bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
  3931. elem->message.data.vif_list_event.func_bit_map);
  3932. } else if (elem->message.data.vif_list_event.echo ==
  3933. VIF_LIST_RULE_SET) {
  3934. DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
  3935. bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
  3936. }
  3937. }
  3938. /* called with rtnl_lock */
  3939. static void bnx2x_after_function_update(struct bnx2x *bp)
  3940. {
  3941. int q, rc;
  3942. struct bnx2x_fastpath *fp;
  3943. struct bnx2x_queue_state_params queue_params = {NULL};
  3944. struct bnx2x_queue_update_params *q_update_params =
  3945. &queue_params.params.update;
  3946. /* Send Q update command with afex vlan removal values for all Qs */
  3947. queue_params.cmd = BNX2X_Q_CMD_UPDATE;
  3948. /* set silent vlan removal values according to vlan mode */
  3949. __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
  3950. &q_update_params->update_flags);
  3951. __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
  3952. &q_update_params->update_flags);
  3953. __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
  3954. /* in access mode mark mask and value are 0 to strip all vlans */
  3955. if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
  3956. q_update_params->silent_removal_value = 0;
  3957. q_update_params->silent_removal_mask = 0;
  3958. } else {
  3959. q_update_params->silent_removal_value =
  3960. (bp->afex_def_vlan_tag & VLAN_VID_MASK);
  3961. q_update_params->silent_removal_mask = VLAN_VID_MASK;
  3962. }
  3963. for_each_eth_queue(bp, q) {
  3964. /* Set the appropriate Queue object */
  3965. fp = &bp->fp[q];
  3966. queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
  3967. /* send the ramrod */
  3968. rc = bnx2x_queue_state_change(bp, &queue_params);
  3969. if (rc < 0)
  3970. BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
  3971. q);
  3972. }
  3973. #ifdef BCM_CNIC
  3974. if (!NO_FCOE(bp)) {
  3975. fp = &bp->fp[FCOE_IDX(bp)];
  3976. queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
  3977. /* clear pending completion bit */
  3978. __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
  3979. /* mark latest Q bit */
  3980. smp_mb__before_clear_bit();
  3981. set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
  3982. smp_mb__after_clear_bit();
  3983. /* send Q update ramrod for FCoE Q */
  3984. rc = bnx2x_queue_state_change(bp, &queue_params);
  3985. if (rc < 0)
  3986. BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
  3987. q);
  3988. } else {
  3989. /* If no FCoE ring - ACK MCP now */
  3990. bnx2x_link_report(bp);
  3991. bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
  3992. }
  3993. #else
  3994. /* If no FCoE ring - ACK MCP now */
  3995. bnx2x_link_report(bp);
  3996. bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
  3997. #endif /* BCM_CNIC */
  3998. }
  3999. static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
  4000. struct bnx2x *bp, u32 cid)
  4001. {
  4002. DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
  4003. #ifdef BCM_CNIC
  4004. if (cid == BNX2X_FCOE_ETH_CID(bp))
  4005. return &bnx2x_fcoe_sp_obj(bp, q_obj);
  4006. else
  4007. #endif
  4008. return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
  4009. }
  4010. static void bnx2x_eq_int(struct bnx2x *bp)
  4011. {
  4012. u16 hw_cons, sw_cons, sw_prod;
  4013. union event_ring_elem *elem;
  4014. u32 cid;
  4015. u8 opcode;
  4016. int spqe_cnt = 0;
  4017. struct bnx2x_queue_sp_obj *q_obj;
  4018. struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
  4019. struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
  4020. hw_cons = le16_to_cpu(*bp->eq_cons_sb);
  4021. /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
  4022. * when we get the the next-page we nned to adjust so the loop
  4023. * condition below will be met. The next element is the size of a
  4024. * regular element and hence incrementing by 1
  4025. */
  4026. if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
  4027. hw_cons++;
  4028. /* This function may never run in parallel with itself for a
  4029. * specific bp, thus there is no need in "paired" read memory
  4030. * barrier here.
  4031. */
  4032. sw_cons = bp->eq_cons;
  4033. sw_prod = bp->eq_prod;
  4034. DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
  4035. hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
  4036. for (; sw_cons != hw_cons;
  4037. sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
  4038. elem = &bp->eq_ring[EQ_DESC(sw_cons)];
  4039. cid = SW_CID(elem->message.data.cfc_del_event.cid);
  4040. opcode = elem->message.opcode;
  4041. /* handle eq element */
  4042. switch (opcode) {
  4043. case EVENT_RING_OPCODE_STAT_QUERY:
  4044. DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
  4045. "got statistics comp event %d\n",
  4046. bp->stats_comp++);
  4047. /* nothing to do with stats comp */
  4048. goto next_spqe;
  4049. case EVENT_RING_OPCODE_CFC_DEL:
  4050. /* handle according to cid range */
  4051. /*
  4052. * we may want to verify here that the bp state is
  4053. * HALTING
  4054. */
  4055. DP(BNX2X_MSG_SP,
  4056. "got delete ramrod for MULTI[%d]\n", cid);
  4057. #ifdef BCM_CNIC
  4058. if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
  4059. goto next_spqe;
  4060. #endif
  4061. q_obj = bnx2x_cid_to_q_obj(bp, cid);
  4062. if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
  4063. break;
  4064. goto next_spqe;
  4065. case EVENT_RING_OPCODE_STOP_TRAFFIC:
  4066. DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
  4067. if (f_obj->complete_cmd(bp, f_obj,
  4068. BNX2X_F_CMD_TX_STOP))
  4069. break;
  4070. bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
  4071. goto next_spqe;
  4072. case EVENT_RING_OPCODE_START_TRAFFIC:
  4073. DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
  4074. if (f_obj->complete_cmd(bp, f_obj,
  4075. BNX2X_F_CMD_TX_START))
  4076. break;
  4077. bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
  4078. goto next_spqe;
  4079. case EVENT_RING_OPCODE_FUNCTION_UPDATE:
  4080. DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
  4081. "AFEX: ramrod completed FUNCTION_UPDATE\n");
  4082. f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE);
  4083. /* We will perform the Queues update from sp_rtnl task
  4084. * as all Queue SP operations should run under
  4085. * rtnl_lock.
  4086. */
  4087. smp_mb__before_clear_bit();
  4088. set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
  4089. &bp->sp_rtnl_state);
  4090. smp_mb__after_clear_bit();
  4091. schedule_delayed_work(&bp->sp_rtnl_task, 0);
  4092. goto next_spqe;
  4093. case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
  4094. f_obj->complete_cmd(bp, f_obj,
  4095. BNX2X_F_CMD_AFEX_VIFLISTS);
  4096. bnx2x_after_afex_vif_lists(bp, elem);
  4097. goto next_spqe;
  4098. case EVENT_RING_OPCODE_FUNCTION_START:
  4099. DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
  4100. "got FUNC_START ramrod\n");
  4101. if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
  4102. break;
  4103. goto next_spqe;
  4104. case EVENT_RING_OPCODE_FUNCTION_STOP:
  4105. DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
  4106. "got FUNC_STOP ramrod\n");
  4107. if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
  4108. break;
  4109. goto next_spqe;
  4110. }
  4111. switch (opcode | bp->state) {
  4112. case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
  4113. BNX2X_STATE_OPEN):
  4114. case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
  4115. BNX2X_STATE_OPENING_WAIT4_PORT):
  4116. cid = elem->message.data.eth_event.echo &
  4117. BNX2X_SWCID_MASK;
  4118. DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
  4119. cid);
  4120. rss_raw->clear_pending(rss_raw);
  4121. break;
  4122. case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
  4123. case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
  4124. case (EVENT_RING_OPCODE_SET_MAC |
  4125. BNX2X_STATE_CLOSING_WAIT4_HALT):
  4126. case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
  4127. BNX2X_STATE_OPEN):
  4128. case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
  4129. BNX2X_STATE_DIAG):
  4130. case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
  4131. BNX2X_STATE_CLOSING_WAIT4_HALT):
  4132. DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
  4133. bnx2x_handle_classification_eqe(bp, elem);
  4134. break;
  4135. case (EVENT_RING_OPCODE_MULTICAST_RULES |
  4136. BNX2X_STATE_OPEN):
  4137. case (EVENT_RING_OPCODE_MULTICAST_RULES |
  4138. BNX2X_STATE_DIAG):
  4139. case (EVENT_RING_OPCODE_MULTICAST_RULES |
  4140. BNX2X_STATE_CLOSING_WAIT4_HALT):
  4141. DP(BNX2X_MSG_SP, "got mcast ramrod\n");
  4142. bnx2x_handle_mcast_eqe(bp);
  4143. break;
  4144. case (EVENT_RING_OPCODE_FILTERS_RULES |
  4145. BNX2X_STATE_OPEN):
  4146. case (EVENT_RING_OPCODE_FILTERS_RULES |
  4147. BNX2X_STATE_DIAG):
  4148. case (EVENT_RING_OPCODE_FILTERS_RULES |
  4149. BNX2X_STATE_CLOSING_WAIT4_HALT):
  4150. DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
  4151. bnx2x_handle_rx_mode_eqe(bp);
  4152. break;
  4153. default:
  4154. /* unknown event log error and continue */
  4155. BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
  4156. elem->message.opcode, bp->state);
  4157. }
  4158. next_spqe:
  4159. spqe_cnt++;
  4160. } /* for */
  4161. smp_mb__before_atomic_inc();
  4162. atomic_add(spqe_cnt, &bp->eq_spq_left);
  4163. bp->eq_cons = sw_cons;
  4164. bp->eq_prod = sw_prod;
  4165. /* Make sure that above mem writes were issued towards the memory */
  4166. smp_wmb();
  4167. /* update producer */
  4168. bnx2x_update_eq_prod(bp, bp->eq_prod);
  4169. }
  4170. static void bnx2x_sp_task(struct work_struct *work)
  4171. {
  4172. struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
  4173. u16 status;
  4174. status = bnx2x_update_dsb_idx(bp);
  4175. /* if (status == 0) */
  4176. /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
  4177. DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
  4178. /* HW attentions */
  4179. if (status & BNX2X_DEF_SB_ATT_IDX) {
  4180. bnx2x_attn_int(bp);
  4181. status &= ~BNX2X_DEF_SB_ATT_IDX;
  4182. }
  4183. /* SP events: STAT_QUERY and others */
  4184. if (status & BNX2X_DEF_SB_IDX) {
  4185. #ifdef BCM_CNIC
  4186. struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
  4187. if ((!NO_FCOE(bp)) &&
  4188. (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
  4189. /*
  4190. * Prevent local bottom-halves from running as
  4191. * we are going to change the local NAPI list.
  4192. */
  4193. local_bh_disable();
  4194. napi_schedule(&bnx2x_fcoe(bp, napi));
  4195. local_bh_enable();
  4196. }
  4197. #endif
  4198. /* Handle EQ completions */
  4199. bnx2x_eq_int(bp);
  4200. bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
  4201. le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
  4202. status &= ~BNX2X_DEF_SB_IDX;
  4203. }
  4204. if (unlikely(status))
  4205. DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
  4206. status);
  4207. bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
  4208. le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
  4209. /* afex - poll to check if VIFSET_ACK should be sent to MFW */
  4210. if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
  4211. &bp->sp_state)) {
  4212. bnx2x_link_report(bp);
  4213. bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
  4214. }
  4215. }
  4216. irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
  4217. {
  4218. struct net_device *dev = dev_instance;
  4219. struct bnx2x *bp = netdev_priv(dev);
  4220. bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
  4221. IGU_INT_DISABLE, 0);
  4222. #ifdef BNX2X_STOP_ON_ERROR
  4223. if (unlikely(bp->panic))
  4224. return IRQ_HANDLED;
  4225. #endif
  4226. #ifdef BCM_CNIC
  4227. {
  4228. struct cnic_ops *c_ops;
  4229. rcu_read_lock();
  4230. c_ops = rcu_dereference(bp->cnic_ops);
  4231. if (c_ops)
  4232. c_ops->cnic_handler(bp->cnic_data, NULL);
  4233. rcu_read_unlock();
  4234. }
  4235. #endif
  4236. queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
  4237. return IRQ_HANDLED;
  4238. }
  4239. /* end of slow path */
  4240. void bnx2x_drv_pulse(struct bnx2x *bp)
  4241. {
  4242. SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
  4243. bp->fw_drv_pulse_wr_seq);
  4244. }
  4245. static void bnx2x_timer(unsigned long data)
  4246. {
  4247. struct bnx2x *bp = (struct bnx2x *) data;
  4248. if (!netif_running(bp->dev))
  4249. return;
  4250. if (!BP_NOMCP(bp)) {
  4251. int mb_idx = BP_FW_MB_IDX(bp);
  4252. u32 drv_pulse;
  4253. u32 mcp_pulse;
  4254. ++bp->fw_drv_pulse_wr_seq;
  4255. bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
  4256. /* TBD - add SYSTEM_TIME */
  4257. drv_pulse = bp->fw_drv_pulse_wr_seq;
  4258. bnx2x_drv_pulse(bp);
  4259. mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
  4260. MCP_PULSE_SEQ_MASK);
  4261. /* The delta between driver pulse and mcp response
  4262. * should be 1 (before mcp response) or 0 (after mcp response)
  4263. */
  4264. if ((drv_pulse != mcp_pulse) &&
  4265. (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
  4266. /* someone lost a heartbeat... */
  4267. BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
  4268. drv_pulse, mcp_pulse);
  4269. }
  4270. }
  4271. if (bp->state == BNX2X_STATE_OPEN)
  4272. bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
  4273. mod_timer(&bp->timer, jiffies + bp->current_interval);
  4274. }
  4275. /* end of Statistics */
  4276. /* nic init */
  4277. /*
  4278. * nic init service functions
  4279. */
  4280. static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
  4281. {
  4282. u32 i;
  4283. if (!(len%4) && !(addr%4))
  4284. for (i = 0; i < len; i += 4)
  4285. REG_WR(bp, addr + i, fill);
  4286. else
  4287. for (i = 0; i < len; i++)
  4288. REG_WR8(bp, addr + i, fill);
  4289. }
  4290. /* helper: writes FP SP data to FW - data_size in dwords */
  4291. static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
  4292. int fw_sb_id,
  4293. u32 *sb_data_p,
  4294. u32 data_size)
  4295. {
  4296. int index;
  4297. for (index = 0; index < data_size; index++)
  4298. REG_WR(bp, BAR_CSTRORM_INTMEM +
  4299. CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
  4300. sizeof(u32)*index,
  4301. *(sb_data_p + index));
  4302. }
  4303. static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
  4304. {
  4305. u32 *sb_data_p;
  4306. u32 data_size = 0;
  4307. struct hc_status_block_data_e2 sb_data_e2;
  4308. struct hc_status_block_data_e1x sb_data_e1x;
  4309. /* disable the function first */
  4310. if (!CHIP_IS_E1x(bp)) {
  4311. memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
  4312. sb_data_e2.common.state = SB_DISABLED;
  4313. sb_data_e2.common.p_func.vf_valid = false;
  4314. sb_data_p = (u32 *)&sb_data_e2;
  4315. data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
  4316. } else {
  4317. memset(&sb_data_e1x, 0,
  4318. sizeof(struct hc_status_block_data_e1x));
  4319. sb_data_e1x.common.state = SB_DISABLED;
  4320. sb_data_e1x.common.p_func.vf_valid = false;
  4321. sb_data_p = (u32 *)&sb_data_e1x;
  4322. data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
  4323. }
  4324. bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
  4325. bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
  4326. CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
  4327. CSTORM_STATUS_BLOCK_SIZE);
  4328. bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
  4329. CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
  4330. CSTORM_SYNC_BLOCK_SIZE);
  4331. }
  4332. /* helper: writes SP SB data to FW */
  4333. static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
  4334. struct hc_sp_status_block_data *sp_sb_data)
  4335. {
  4336. int func = BP_FUNC(bp);
  4337. int i;
  4338. for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
  4339. REG_WR(bp, BAR_CSTRORM_INTMEM +
  4340. CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
  4341. i*sizeof(u32),
  4342. *((u32 *)sp_sb_data + i));
  4343. }
  4344. static void bnx2x_zero_sp_sb(struct bnx2x *bp)
  4345. {
  4346. int func = BP_FUNC(bp);
  4347. struct hc_sp_status_block_data sp_sb_data;
  4348. memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
  4349. sp_sb_data.state = SB_DISABLED;
  4350. sp_sb_data.p_func.vf_valid = false;
  4351. bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
  4352. bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
  4353. CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
  4354. CSTORM_SP_STATUS_BLOCK_SIZE);
  4355. bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
  4356. CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
  4357. CSTORM_SP_SYNC_BLOCK_SIZE);
  4358. }
  4359. static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
  4360. int igu_sb_id, int igu_seg_id)
  4361. {
  4362. hc_sm->igu_sb_id = igu_sb_id;
  4363. hc_sm->igu_seg_id = igu_seg_id;
  4364. hc_sm->timer_value = 0xFF;
  4365. hc_sm->time_to_expire = 0xFFFFFFFF;
  4366. }
  4367. /* allocates state machine ids. */
  4368. static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
  4369. {
  4370. /* zero out state machine indices */
  4371. /* rx indices */
  4372. index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
  4373. /* tx indices */
  4374. index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
  4375. index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
  4376. index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
  4377. index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
  4378. /* map indices */
  4379. /* rx indices */
  4380. index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
  4381. SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
  4382. /* tx indices */
  4383. index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
  4384. SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
  4385. index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
  4386. SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
  4387. index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
  4388. SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
  4389. index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
  4390. SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
  4391. }
  4392. static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
  4393. u8 vf_valid, int fw_sb_id, int igu_sb_id)
  4394. {
  4395. int igu_seg_id;
  4396. struct hc_status_block_data_e2 sb_data_e2;
  4397. struct hc_status_block_data_e1x sb_data_e1x;
  4398. struct hc_status_block_sm *hc_sm_p;
  4399. int data_size;
  4400. u32 *sb_data_p;
  4401. if (CHIP_INT_MODE_IS_BC(bp))
  4402. igu_seg_id = HC_SEG_ACCESS_NORM;
  4403. else
  4404. igu_seg_id = IGU_SEG_ACCESS_NORM;
  4405. bnx2x_zero_fp_sb(bp, fw_sb_id);
  4406. if (!CHIP_IS_E1x(bp)) {
  4407. memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
  4408. sb_data_e2.common.state = SB_ENABLED;
  4409. sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
  4410. sb_data_e2.common.p_func.vf_id = vfid;
  4411. sb_data_e2.common.p_func.vf_valid = vf_valid;
  4412. sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
  4413. sb_data_e2.common.same_igu_sb_1b = true;
  4414. sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
  4415. sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
  4416. hc_sm_p = sb_data_e2.common.state_machine;
  4417. sb_data_p = (u32 *)&sb_data_e2;
  4418. data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
  4419. bnx2x_map_sb_state_machines(sb_data_e2.index_data);
  4420. } else {
  4421. memset(&sb_data_e1x, 0,
  4422. sizeof(struct hc_status_block_data_e1x));
  4423. sb_data_e1x.common.state = SB_ENABLED;
  4424. sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
  4425. sb_data_e1x.common.p_func.vf_id = 0xff;
  4426. sb_data_e1x.common.p_func.vf_valid = false;
  4427. sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
  4428. sb_data_e1x.common.same_igu_sb_1b = true;
  4429. sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
  4430. sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
  4431. hc_sm_p = sb_data_e1x.common.state_machine;
  4432. sb_data_p = (u32 *)&sb_data_e1x;
  4433. data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
  4434. bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
  4435. }
  4436. bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
  4437. igu_sb_id, igu_seg_id);
  4438. bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
  4439. igu_sb_id, igu_seg_id);
  4440. DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
  4441. /* write indecies to HW */
  4442. bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
  4443. }
  4444. static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
  4445. u16 tx_usec, u16 rx_usec)
  4446. {
  4447. bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
  4448. false, rx_usec);
  4449. bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
  4450. HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
  4451. tx_usec);
  4452. bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
  4453. HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
  4454. tx_usec);
  4455. bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
  4456. HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
  4457. tx_usec);
  4458. }
  4459. static void bnx2x_init_def_sb(struct bnx2x *bp)
  4460. {
  4461. struct host_sp_status_block *def_sb = bp->def_status_blk;
  4462. dma_addr_t mapping = bp->def_status_blk_mapping;
  4463. int igu_sp_sb_index;
  4464. int igu_seg_id;
  4465. int port = BP_PORT(bp);
  4466. int func = BP_FUNC(bp);
  4467. int reg_offset, reg_offset_en5;
  4468. u64 section;
  4469. int index;
  4470. struct hc_sp_status_block_data sp_sb_data;
  4471. memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
  4472. if (CHIP_INT_MODE_IS_BC(bp)) {
  4473. igu_sp_sb_index = DEF_SB_IGU_ID;
  4474. igu_seg_id = HC_SEG_ACCESS_DEF;
  4475. } else {
  4476. igu_sp_sb_index = bp->igu_dsb_id;
  4477. igu_seg_id = IGU_SEG_ACCESS_DEF;
  4478. }
  4479. /* ATTN */
  4480. section = ((u64)mapping) + offsetof(struct host_sp_status_block,
  4481. atten_status_block);
  4482. def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
  4483. bp->attn_state = 0;
  4484. reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
  4485. MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
  4486. reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
  4487. MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
  4488. for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
  4489. int sindex;
  4490. /* take care of sig[0]..sig[4] */
  4491. for (sindex = 0; sindex < 4; sindex++)
  4492. bp->attn_group[index].sig[sindex] =
  4493. REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
  4494. if (!CHIP_IS_E1x(bp))
  4495. /*
  4496. * enable5 is separate from the rest of the registers,
  4497. * and therefore the address skip is 4
  4498. * and not 16 between the different groups
  4499. */
  4500. bp->attn_group[index].sig[4] = REG_RD(bp,
  4501. reg_offset_en5 + 0x4*index);
  4502. else
  4503. bp->attn_group[index].sig[4] = 0;
  4504. }
  4505. if (bp->common.int_block == INT_BLOCK_HC) {
  4506. reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
  4507. HC_REG_ATTN_MSG0_ADDR_L);
  4508. REG_WR(bp, reg_offset, U64_LO(section));
  4509. REG_WR(bp, reg_offset + 4, U64_HI(section));
  4510. } else if (!CHIP_IS_E1x(bp)) {
  4511. REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
  4512. REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
  4513. }
  4514. section = ((u64)mapping) + offsetof(struct host_sp_status_block,
  4515. sp_sb);
  4516. bnx2x_zero_sp_sb(bp);
  4517. sp_sb_data.state = SB_ENABLED;
  4518. sp_sb_data.host_sb_addr.lo = U64_LO(section);
  4519. sp_sb_data.host_sb_addr.hi = U64_HI(section);
  4520. sp_sb_data.igu_sb_id = igu_sp_sb_index;
  4521. sp_sb_data.igu_seg_id = igu_seg_id;
  4522. sp_sb_data.p_func.pf_id = func;
  4523. sp_sb_data.p_func.vnic_id = BP_VN(bp);
  4524. sp_sb_data.p_func.vf_id = 0xff;
  4525. bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
  4526. bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
  4527. }
  4528. void bnx2x_update_coalesce(struct bnx2x *bp)
  4529. {
  4530. int i;
  4531. for_each_eth_queue(bp, i)
  4532. bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
  4533. bp->tx_ticks, bp->rx_ticks);
  4534. }
  4535. static void bnx2x_init_sp_ring(struct bnx2x *bp)
  4536. {
  4537. spin_lock_init(&bp->spq_lock);
  4538. atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
  4539. bp->spq_prod_idx = 0;
  4540. bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
  4541. bp->spq_prod_bd = bp->spq;
  4542. bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
  4543. }
  4544. static void bnx2x_init_eq_ring(struct bnx2x *bp)
  4545. {
  4546. int i;
  4547. for (i = 1; i <= NUM_EQ_PAGES; i++) {
  4548. union event_ring_elem *elem =
  4549. &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
  4550. elem->next_page.addr.hi =
  4551. cpu_to_le32(U64_HI(bp->eq_mapping +
  4552. BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
  4553. elem->next_page.addr.lo =
  4554. cpu_to_le32(U64_LO(bp->eq_mapping +
  4555. BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
  4556. }
  4557. bp->eq_cons = 0;
  4558. bp->eq_prod = NUM_EQ_DESC;
  4559. bp->eq_cons_sb = BNX2X_EQ_INDEX;
  4560. /* we want a warning message before it gets rought... */
  4561. atomic_set(&bp->eq_spq_left,
  4562. min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
  4563. }
  4564. /* called with netif_addr_lock_bh() */
  4565. void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
  4566. unsigned long rx_mode_flags,
  4567. unsigned long rx_accept_flags,
  4568. unsigned long tx_accept_flags,
  4569. unsigned long ramrod_flags)
  4570. {
  4571. struct bnx2x_rx_mode_ramrod_params ramrod_param;
  4572. int rc;
  4573. memset(&ramrod_param, 0, sizeof(ramrod_param));
  4574. /* Prepare ramrod parameters */
  4575. ramrod_param.cid = 0;
  4576. ramrod_param.cl_id = cl_id;
  4577. ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
  4578. ramrod_param.func_id = BP_FUNC(bp);
  4579. ramrod_param.pstate = &bp->sp_state;
  4580. ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
  4581. ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
  4582. ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
  4583. set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
  4584. ramrod_param.ramrod_flags = ramrod_flags;
  4585. ramrod_param.rx_mode_flags = rx_mode_flags;
  4586. ramrod_param.rx_accept_flags = rx_accept_flags;
  4587. ramrod_param.tx_accept_flags = tx_accept_flags;
  4588. rc = bnx2x_config_rx_mode(bp, &ramrod_param);
  4589. if (rc < 0) {
  4590. BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
  4591. return;
  4592. }
  4593. }
  4594. /* called with netif_addr_lock_bh() */
  4595. void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
  4596. {
  4597. unsigned long rx_mode_flags = 0, ramrod_flags = 0;
  4598. unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
  4599. #ifdef BCM_CNIC
  4600. if (!NO_FCOE(bp))
  4601. /* Configure rx_mode of FCoE Queue */
  4602. __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
  4603. #endif
  4604. switch (bp->rx_mode) {
  4605. case BNX2X_RX_MODE_NONE:
  4606. /*
  4607. * 'drop all' supersedes any accept flags that may have been
  4608. * passed to the function.
  4609. */
  4610. break;
  4611. case BNX2X_RX_MODE_NORMAL:
  4612. __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
  4613. __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
  4614. __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
  4615. /* internal switching mode */
  4616. __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
  4617. __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
  4618. __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
  4619. break;
  4620. case BNX2X_RX_MODE_ALLMULTI:
  4621. __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
  4622. __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
  4623. __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
  4624. /* internal switching mode */
  4625. __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
  4626. __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
  4627. __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
  4628. break;
  4629. case BNX2X_RX_MODE_PROMISC:
  4630. /* According to deffinition of SI mode, iface in promisc mode
  4631. * should receive matched and unmatched (in resolution of port)
  4632. * unicast packets.
  4633. */
  4634. __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
  4635. __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
  4636. __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
  4637. __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
  4638. /* internal switching mode */
  4639. __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
  4640. __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
  4641. if (IS_MF_SI(bp))
  4642. __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
  4643. else
  4644. __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
  4645. break;
  4646. default:
  4647. BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
  4648. return;
  4649. }
  4650. if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
  4651. __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
  4652. __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
  4653. }
  4654. __set_bit(RAMROD_RX, &ramrod_flags);
  4655. __set_bit(RAMROD_TX, &ramrod_flags);
  4656. bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
  4657. tx_accept_flags, ramrod_flags);
  4658. }
  4659. static void bnx2x_init_internal_common(struct bnx2x *bp)
  4660. {
  4661. int i;
  4662. if (IS_MF_SI(bp))
  4663. /*
  4664. * In switch independent mode, the TSTORM needs to accept
  4665. * packets that failed classification, since approximate match
  4666. * mac addresses aren't written to NIG LLH
  4667. */
  4668. REG_WR8(bp, BAR_TSTRORM_INTMEM +
  4669. TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
  4670. else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
  4671. REG_WR8(bp, BAR_TSTRORM_INTMEM +
  4672. TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
  4673. /* Zero this manually as its initialization is
  4674. currently missing in the initTool */
  4675. for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
  4676. REG_WR(bp, BAR_USTRORM_INTMEM +
  4677. USTORM_AGG_DATA_OFFSET + i * 4, 0);
  4678. if (!CHIP_IS_E1x(bp)) {
  4679. REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
  4680. CHIP_INT_MODE_IS_BC(bp) ?
  4681. HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
  4682. }
  4683. }
  4684. static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
  4685. {
  4686. switch (load_code) {
  4687. case FW_MSG_CODE_DRV_LOAD_COMMON:
  4688. case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
  4689. bnx2x_init_internal_common(bp);
  4690. /* no break */
  4691. case FW_MSG_CODE_DRV_LOAD_PORT:
  4692. /* nothing to do */
  4693. /* no break */
  4694. case FW_MSG_CODE_DRV_LOAD_FUNCTION:
  4695. /* internal memory per function is
  4696. initialized inside bnx2x_pf_init */
  4697. break;
  4698. default:
  4699. BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
  4700. break;
  4701. }
  4702. }
  4703. static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
  4704. {
  4705. return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
  4706. }
  4707. static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
  4708. {
  4709. return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
  4710. }
  4711. static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
  4712. {
  4713. if (CHIP_IS_E1x(fp->bp))
  4714. return BP_L_ID(fp->bp) + fp->index;
  4715. else /* We want Client ID to be the same as IGU SB ID for 57712 */
  4716. return bnx2x_fp_igu_sb_id(fp);
  4717. }
  4718. static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
  4719. {
  4720. struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
  4721. u8 cos;
  4722. unsigned long q_type = 0;
  4723. u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
  4724. fp->rx_queue = fp_idx;
  4725. fp->cid = fp_idx;
  4726. fp->cl_id = bnx2x_fp_cl_id(fp);
  4727. fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
  4728. fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
  4729. /* qZone id equals to FW (per path) client id */
  4730. fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
  4731. /* init shortcut */
  4732. fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
  4733. /* Setup SB indicies */
  4734. fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
  4735. /* Configure Queue State object */
  4736. __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
  4737. __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
  4738. BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
  4739. /* init tx data */
  4740. for_each_cos_in_tx_queue(fp, cos) {
  4741. bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
  4742. CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
  4743. FP_COS_TO_TXQ(fp, cos, bp),
  4744. BNX2X_TX_SB_INDEX_BASE + cos, fp);
  4745. cids[cos] = fp->txdata_ptr[cos]->cid;
  4746. }
  4747. bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
  4748. fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
  4749. bnx2x_sp_mapping(bp, q_rdata), q_type);
  4750. /**
  4751. * Configure classification DBs: Always enable Tx switching
  4752. */
  4753. bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
  4754. DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
  4755. fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
  4756. fp->igu_sb_id);
  4757. bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
  4758. fp->fw_sb_id, fp->igu_sb_id);
  4759. bnx2x_update_fpsb_idx(fp);
  4760. }
  4761. static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
  4762. {
  4763. int i;
  4764. for (i = 1; i <= NUM_TX_RINGS; i++) {
  4765. struct eth_tx_next_bd *tx_next_bd =
  4766. &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
  4767. tx_next_bd->addr_hi =
  4768. cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
  4769. BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
  4770. tx_next_bd->addr_lo =
  4771. cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
  4772. BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
  4773. }
  4774. SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
  4775. txdata->tx_db.data.zero_fill1 = 0;
  4776. txdata->tx_db.data.prod = 0;
  4777. txdata->tx_pkt_prod = 0;
  4778. txdata->tx_pkt_cons = 0;
  4779. txdata->tx_bd_prod = 0;
  4780. txdata->tx_bd_cons = 0;
  4781. txdata->tx_pkt = 0;
  4782. }
  4783. static void bnx2x_init_tx_rings(struct bnx2x *bp)
  4784. {
  4785. int i;
  4786. u8 cos;
  4787. for_each_tx_queue(bp, i)
  4788. for_each_cos_in_tx_queue(&bp->fp[i], cos)
  4789. bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
  4790. }
  4791. void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
  4792. {
  4793. int i;
  4794. for_each_eth_queue(bp, i)
  4795. bnx2x_init_eth_fp(bp, i);
  4796. #ifdef BCM_CNIC
  4797. if (!NO_FCOE(bp))
  4798. bnx2x_init_fcoe_fp(bp);
  4799. bnx2x_init_sb(bp, bp->cnic_sb_mapping,
  4800. BNX2X_VF_ID_INVALID, false,
  4801. bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
  4802. #endif
  4803. /* Initialize MOD_ABS interrupts */
  4804. bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
  4805. bp->common.shmem_base, bp->common.shmem2_base,
  4806. BP_PORT(bp));
  4807. /* ensure status block indices were read */
  4808. rmb();
  4809. bnx2x_init_def_sb(bp);
  4810. bnx2x_update_dsb_idx(bp);
  4811. bnx2x_init_rx_rings(bp);
  4812. bnx2x_init_tx_rings(bp);
  4813. bnx2x_init_sp_ring(bp);
  4814. bnx2x_init_eq_ring(bp);
  4815. bnx2x_init_internal(bp, load_code);
  4816. bnx2x_pf_init(bp);
  4817. bnx2x_stats_init(bp);
  4818. /* flush all before enabling interrupts */
  4819. mb();
  4820. mmiowb();
  4821. bnx2x_int_enable(bp);
  4822. /* Check for SPIO5 */
  4823. bnx2x_attn_int_deasserted0(bp,
  4824. REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
  4825. AEU_INPUTS_ATTN_BITS_SPIO5);
  4826. }
  4827. /* end of nic init */
  4828. /*
  4829. * gzip service functions
  4830. */
  4831. static int bnx2x_gunzip_init(struct bnx2x *bp)
  4832. {
  4833. bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
  4834. &bp->gunzip_mapping, GFP_KERNEL);
  4835. if (bp->gunzip_buf == NULL)
  4836. goto gunzip_nomem1;
  4837. bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
  4838. if (bp->strm == NULL)
  4839. goto gunzip_nomem2;
  4840. bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
  4841. if (bp->strm->workspace == NULL)
  4842. goto gunzip_nomem3;
  4843. return 0;
  4844. gunzip_nomem3:
  4845. kfree(bp->strm);
  4846. bp->strm = NULL;
  4847. gunzip_nomem2:
  4848. dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
  4849. bp->gunzip_mapping);
  4850. bp->gunzip_buf = NULL;
  4851. gunzip_nomem1:
  4852. BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
  4853. return -ENOMEM;
  4854. }
  4855. static void bnx2x_gunzip_end(struct bnx2x *bp)
  4856. {
  4857. if (bp->strm) {
  4858. vfree(bp->strm->workspace);
  4859. kfree(bp->strm);
  4860. bp->strm = NULL;
  4861. }
  4862. if (bp->gunzip_buf) {
  4863. dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
  4864. bp->gunzip_mapping);
  4865. bp->gunzip_buf = NULL;
  4866. }
  4867. }
  4868. static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
  4869. {
  4870. int n, rc;
  4871. /* check gzip header */
  4872. if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
  4873. BNX2X_ERR("Bad gzip header\n");
  4874. return -EINVAL;
  4875. }
  4876. n = 10;
  4877. #define FNAME 0x8
  4878. if (zbuf[3] & FNAME)
  4879. while ((zbuf[n++] != 0) && (n < len));
  4880. bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
  4881. bp->strm->avail_in = len - n;
  4882. bp->strm->next_out = bp->gunzip_buf;
  4883. bp->strm->avail_out = FW_BUF_SIZE;
  4884. rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
  4885. if (rc != Z_OK)
  4886. return rc;
  4887. rc = zlib_inflate(bp->strm, Z_FINISH);
  4888. if ((rc != Z_OK) && (rc != Z_STREAM_END))
  4889. netdev_err(bp->dev, "Firmware decompression error: %s\n",
  4890. bp->strm->msg);
  4891. bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
  4892. if (bp->gunzip_outlen & 0x3)
  4893. netdev_err(bp->dev,
  4894. "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
  4895. bp->gunzip_outlen);
  4896. bp->gunzip_outlen >>= 2;
  4897. zlib_inflateEnd(bp->strm);
  4898. if (rc == Z_STREAM_END)
  4899. return 0;
  4900. return rc;
  4901. }
  4902. /* nic load/unload */
  4903. /*
  4904. * General service functions
  4905. */
  4906. /* send a NIG loopback debug packet */
  4907. static void bnx2x_lb_pckt(struct bnx2x *bp)
  4908. {
  4909. u32 wb_write[3];
  4910. /* Ethernet source and destination addresses */
  4911. wb_write[0] = 0x55555555;
  4912. wb_write[1] = 0x55555555;
  4913. wb_write[2] = 0x20; /* SOP */
  4914. REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
  4915. /* NON-IP protocol */
  4916. wb_write[0] = 0x09000000;
  4917. wb_write[1] = 0x55555555;
  4918. wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
  4919. REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
  4920. }
  4921. /* some of the internal memories
  4922. * are not directly readable from the driver
  4923. * to test them we send debug packets
  4924. */
  4925. static int bnx2x_int_mem_test(struct bnx2x *bp)
  4926. {
  4927. int factor;
  4928. int count, i;
  4929. u32 val = 0;
  4930. if (CHIP_REV_IS_FPGA(bp))
  4931. factor = 120;
  4932. else if (CHIP_REV_IS_EMUL(bp))
  4933. factor = 200;
  4934. else
  4935. factor = 1;
  4936. /* Disable inputs of parser neighbor blocks */
  4937. REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
  4938. REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
  4939. REG_WR(bp, CFC_REG_DEBUG0, 0x1);
  4940. REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
  4941. /* Write 0 to parser credits for CFC search request */
  4942. REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
  4943. /* send Ethernet packet */
  4944. bnx2x_lb_pckt(bp);
  4945. /* TODO do i reset NIG statistic? */
  4946. /* Wait until NIG register shows 1 packet of size 0x10 */
  4947. count = 1000 * factor;
  4948. while (count) {
  4949. bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
  4950. val = *bnx2x_sp(bp, wb_data[0]);
  4951. if (val == 0x10)
  4952. break;
  4953. msleep(10);
  4954. count--;
  4955. }
  4956. if (val != 0x10) {
  4957. BNX2X_ERR("NIG timeout val = 0x%x\n", val);
  4958. return -1;
  4959. }
  4960. /* Wait until PRS register shows 1 packet */
  4961. count = 1000 * factor;
  4962. while (count) {
  4963. val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
  4964. if (val == 1)
  4965. break;
  4966. msleep(10);
  4967. count--;
  4968. }
  4969. if (val != 0x1) {
  4970. BNX2X_ERR("PRS timeout val = 0x%x\n", val);
  4971. return -2;
  4972. }
  4973. /* Reset and init BRB, PRS */
  4974. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
  4975. msleep(50);
  4976. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
  4977. msleep(50);
  4978. bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
  4979. bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
  4980. DP(NETIF_MSG_HW, "part2\n");
  4981. /* Disable inputs of parser neighbor blocks */
  4982. REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
  4983. REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
  4984. REG_WR(bp, CFC_REG_DEBUG0, 0x1);
  4985. REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
  4986. /* Write 0 to parser credits for CFC search request */
  4987. REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
  4988. /* send 10 Ethernet packets */
  4989. for (i = 0; i < 10; i++)
  4990. bnx2x_lb_pckt(bp);
  4991. /* Wait until NIG register shows 10 + 1
  4992. packets of size 11*0x10 = 0xb0 */
  4993. count = 1000 * factor;
  4994. while (count) {
  4995. bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
  4996. val = *bnx2x_sp(bp, wb_data[0]);
  4997. if (val == 0xb0)
  4998. break;
  4999. msleep(10);
  5000. count--;
  5001. }
  5002. if (val != 0xb0) {
  5003. BNX2X_ERR("NIG timeout val = 0x%x\n", val);
  5004. return -3;
  5005. }
  5006. /* Wait until PRS register shows 2 packets */
  5007. val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
  5008. if (val != 2)
  5009. BNX2X_ERR("PRS timeout val = 0x%x\n", val);
  5010. /* Write 1 to parser credits for CFC search request */
  5011. REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
  5012. /* Wait until PRS register shows 3 packets */
  5013. msleep(10 * factor);
  5014. /* Wait until NIG register shows 1 packet of size 0x10 */
  5015. val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
  5016. if (val != 3)
  5017. BNX2X_ERR("PRS timeout val = 0x%x\n", val);
  5018. /* clear NIG EOP FIFO */
  5019. for (i = 0; i < 11; i++)
  5020. REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
  5021. val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
  5022. if (val != 1) {
  5023. BNX2X_ERR("clear of NIG failed\n");
  5024. return -4;
  5025. }
  5026. /* Reset and init BRB, PRS, NIG */
  5027. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
  5028. msleep(50);
  5029. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
  5030. msleep(50);
  5031. bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
  5032. bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
  5033. #ifndef BCM_CNIC
  5034. /* set NIC mode */
  5035. REG_WR(bp, PRS_REG_NIC_MODE, 1);
  5036. #endif
  5037. /* Enable inputs of parser neighbor blocks */
  5038. REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
  5039. REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
  5040. REG_WR(bp, CFC_REG_DEBUG0, 0x0);
  5041. REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
  5042. DP(NETIF_MSG_HW, "done\n");
  5043. return 0; /* OK */
  5044. }
  5045. static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
  5046. {
  5047. REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
  5048. if (!CHIP_IS_E1x(bp))
  5049. REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
  5050. else
  5051. REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
  5052. REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
  5053. REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
  5054. /*
  5055. * mask read length error interrupts in brb for parser
  5056. * (parsing unit and 'checksum and crc' unit)
  5057. * these errors are legal (PU reads fixed length and CAC can cause
  5058. * read length error on truncated packets)
  5059. */
  5060. REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
  5061. REG_WR(bp, QM_REG_QM_INT_MASK, 0);
  5062. REG_WR(bp, TM_REG_TM_INT_MASK, 0);
  5063. REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
  5064. REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
  5065. REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
  5066. /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
  5067. /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
  5068. REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
  5069. REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
  5070. REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
  5071. /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
  5072. /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
  5073. REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
  5074. REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
  5075. REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
  5076. REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
  5077. /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
  5078. /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
  5079. if (CHIP_REV_IS_FPGA(bp))
  5080. REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
  5081. else if (!CHIP_IS_E1x(bp))
  5082. REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
  5083. (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
  5084. | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
  5085. | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
  5086. | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
  5087. | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
  5088. else
  5089. REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
  5090. REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
  5091. REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
  5092. REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
  5093. /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
  5094. if (!CHIP_IS_E1x(bp))
  5095. /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
  5096. REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
  5097. REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
  5098. REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
  5099. /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
  5100. REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
  5101. }
  5102. static void bnx2x_reset_common(struct bnx2x *bp)
  5103. {
  5104. u32 val = 0x1400;
  5105. /* reset_common */
  5106. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
  5107. 0xd3ffff7f);
  5108. if (CHIP_IS_E3(bp)) {
  5109. val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
  5110. val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
  5111. }
  5112. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
  5113. }
  5114. static void bnx2x_setup_dmae(struct bnx2x *bp)
  5115. {
  5116. bp->dmae_ready = 0;
  5117. spin_lock_init(&bp->dmae_lock);
  5118. }
  5119. static void bnx2x_init_pxp(struct bnx2x *bp)
  5120. {
  5121. u16 devctl;
  5122. int r_order, w_order;
  5123. pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
  5124. DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
  5125. w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
  5126. if (bp->mrrs == -1)
  5127. r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
  5128. else {
  5129. DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
  5130. r_order = bp->mrrs;
  5131. }
  5132. bnx2x_init_pxp_arb(bp, r_order, w_order);
  5133. }
  5134. static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
  5135. {
  5136. int is_required;
  5137. u32 val;
  5138. int port;
  5139. if (BP_NOMCP(bp))
  5140. return;
  5141. is_required = 0;
  5142. val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
  5143. SHARED_HW_CFG_FAN_FAILURE_MASK;
  5144. if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
  5145. is_required = 1;
  5146. /*
  5147. * The fan failure mechanism is usually related to the PHY type since
  5148. * the power consumption of the board is affected by the PHY. Currently,
  5149. * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
  5150. */
  5151. else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
  5152. for (port = PORT_0; port < PORT_MAX; port++) {
  5153. is_required |=
  5154. bnx2x_fan_failure_det_req(
  5155. bp,
  5156. bp->common.shmem_base,
  5157. bp->common.shmem2_base,
  5158. port);
  5159. }
  5160. DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
  5161. if (is_required == 0)
  5162. return;
  5163. /* Fan failure is indicated by SPIO 5 */
  5164. bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
  5165. MISC_REGISTERS_SPIO_INPUT_HI_Z);
  5166. /* set to active low mode */
  5167. val = REG_RD(bp, MISC_REG_SPIO_INT);
  5168. val |= ((1 << MISC_REGISTERS_SPIO_5) <<
  5169. MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
  5170. REG_WR(bp, MISC_REG_SPIO_INT, val);
  5171. /* enable interrupt to signal the IGU */
  5172. val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
  5173. val |= (1 << MISC_REGISTERS_SPIO_5);
  5174. REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
  5175. }
  5176. static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
  5177. {
  5178. u32 offset = 0;
  5179. if (CHIP_IS_E1(bp))
  5180. return;
  5181. if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
  5182. return;
  5183. switch (BP_ABS_FUNC(bp)) {
  5184. case 0:
  5185. offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
  5186. break;
  5187. case 1:
  5188. offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
  5189. break;
  5190. case 2:
  5191. offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
  5192. break;
  5193. case 3:
  5194. offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
  5195. break;
  5196. case 4:
  5197. offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
  5198. break;
  5199. case 5:
  5200. offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
  5201. break;
  5202. case 6:
  5203. offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
  5204. break;
  5205. case 7:
  5206. offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
  5207. break;
  5208. default:
  5209. return;
  5210. }
  5211. REG_WR(bp, offset, pretend_func_num);
  5212. REG_RD(bp, offset);
  5213. DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
  5214. }
  5215. void bnx2x_pf_disable(struct bnx2x *bp)
  5216. {
  5217. u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
  5218. val &= ~IGU_PF_CONF_FUNC_EN;
  5219. REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
  5220. REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
  5221. REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
  5222. }
  5223. static void bnx2x__common_init_phy(struct bnx2x *bp)
  5224. {
  5225. u32 shmem_base[2], shmem2_base[2];
  5226. shmem_base[0] = bp->common.shmem_base;
  5227. shmem2_base[0] = bp->common.shmem2_base;
  5228. if (!CHIP_IS_E1x(bp)) {
  5229. shmem_base[1] =
  5230. SHMEM2_RD(bp, other_shmem_base_addr);
  5231. shmem2_base[1] =
  5232. SHMEM2_RD(bp, other_shmem2_base_addr);
  5233. }
  5234. bnx2x_acquire_phy_lock(bp);
  5235. bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
  5236. bp->common.chip_id);
  5237. bnx2x_release_phy_lock(bp);
  5238. }
  5239. /**
  5240. * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
  5241. *
  5242. * @bp: driver handle
  5243. */
  5244. static int bnx2x_init_hw_common(struct bnx2x *bp)
  5245. {
  5246. u32 val;
  5247. DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
  5248. /*
  5249. * take the UNDI lock to protect undi_unload flow from accessing
  5250. * registers while we're resetting the chip
  5251. */
  5252. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
  5253. bnx2x_reset_common(bp);
  5254. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
  5255. val = 0xfffc;
  5256. if (CHIP_IS_E3(bp)) {
  5257. val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
  5258. val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
  5259. }
  5260. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
  5261. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
  5262. bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
  5263. if (!CHIP_IS_E1x(bp)) {
  5264. u8 abs_func_id;
  5265. /**
  5266. * 4-port mode or 2-port mode we need to turn of master-enable
  5267. * for everyone, after that, turn it back on for self.
  5268. * so, we disregard multi-function or not, and always disable
  5269. * for all functions on the given path, this means 0,2,4,6 for
  5270. * path 0 and 1,3,5,7 for path 1
  5271. */
  5272. for (abs_func_id = BP_PATH(bp);
  5273. abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
  5274. if (abs_func_id == BP_ABS_FUNC(bp)) {
  5275. REG_WR(bp,
  5276. PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
  5277. 1);
  5278. continue;
  5279. }
  5280. bnx2x_pretend_func(bp, abs_func_id);
  5281. /* clear pf enable */
  5282. bnx2x_pf_disable(bp);
  5283. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  5284. }
  5285. }
  5286. bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
  5287. if (CHIP_IS_E1(bp)) {
  5288. /* enable HW interrupt from PXP on USDM overflow
  5289. bit 16 on INT_MASK_0 */
  5290. REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
  5291. }
  5292. bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
  5293. bnx2x_init_pxp(bp);
  5294. #ifdef __BIG_ENDIAN
  5295. REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
  5296. REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
  5297. REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
  5298. REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
  5299. REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
  5300. /* make sure this value is 0 */
  5301. REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
  5302. /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
  5303. REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
  5304. REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
  5305. REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
  5306. REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
  5307. #endif
  5308. bnx2x_ilt_init_page_size(bp, INITOP_SET);
  5309. if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
  5310. REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
  5311. /* let the HW do it's magic ... */
  5312. msleep(100);
  5313. /* finish PXP init */
  5314. val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
  5315. if (val != 1) {
  5316. BNX2X_ERR("PXP2 CFG failed\n");
  5317. return -EBUSY;
  5318. }
  5319. val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
  5320. if (val != 1) {
  5321. BNX2X_ERR("PXP2 RD_INIT failed\n");
  5322. return -EBUSY;
  5323. }
  5324. /* Timers bug workaround E2 only. We need to set the entire ILT to
  5325. * have entries with value "0" and valid bit on.
  5326. * This needs to be done by the first PF that is loaded in a path
  5327. * (i.e. common phase)
  5328. */
  5329. if (!CHIP_IS_E1x(bp)) {
  5330. /* In E2 there is a bug in the timers block that can cause function 6 / 7
  5331. * (i.e. vnic3) to start even if it is marked as "scan-off".
  5332. * This occurs when a different function (func2,3) is being marked
  5333. * as "scan-off". Real-life scenario for example: if a driver is being
  5334. * load-unloaded while func6,7 are down. This will cause the timer to access
  5335. * the ilt, translate to a logical address and send a request to read/write.
  5336. * Since the ilt for the function that is down is not valid, this will cause
  5337. * a translation error which is unrecoverable.
  5338. * The Workaround is intended to make sure that when this happens nothing fatal
  5339. * will occur. The workaround:
  5340. * 1. First PF driver which loads on a path will:
  5341. * a. After taking the chip out of reset, by using pretend,
  5342. * it will write "0" to the following registers of
  5343. * the other vnics.
  5344. * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
  5345. * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
  5346. * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
  5347. * And for itself it will write '1' to
  5348. * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
  5349. * dmae-operations (writing to pram for example.)
  5350. * note: can be done for only function 6,7 but cleaner this
  5351. * way.
  5352. * b. Write zero+valid to the entire ILT.
  5353. * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
  5354. * VNIC3 (of that port). The range allocated will be the
  5355. * entire ILT. This is needed to prevent ILT range error.
  5356. * 2. Any PF driver load flow:
  5357. * a. ILT update with the physical addresses of the allocated
  5358. * logical pages.
  5359. * b. Wait 20msec. - note that this timeout is needed to make
  5360. * sure there are no requests in one of the PXP internal
  5361. * queues with "old" ILT addresses.
  5362. * c. PF enable in the PGLC.
  5363. * d. Clear the was_error of the PF in the PGLC. (could have
  5364. * occured while driver was down)
  5365. * e. PF enable in the CFC (WEAK + STRONG)
  5366. * f. Timers scan enable
  5367. * 3. PF driver unload flow:
  5368. * a. Clear the Timers scan_en.
  5369. * b. Polling for scan_on=0 for that PF.
  5370. * c. Clear the PF enable bit in the PXP.
  5371. * d. Clear the PF enable in the CFC (WEAK + STRONG)
  5372. * e. Write zero+valid to all ILT entries (The valid bit must
  5373. * stay set)
  5374. * f. If this is VNIC 3 of a port then also init
  5375. * first_timers_ilt_entry to zero and last_timers_ilt_entry
  5376. * to the last enrty in the ILT.
  5377. *
  5378. * Notes:
  5379. * Currently the PF error in the PGLC is non recoverable.
  5380. * In the future the there will be a recovery routine for this error.
  5381. * Currently attention is masked.
  5382. * Having an MCP lock on the load/unload process does not guarantee that
  5383. * there is no Timer disable during Func6/7 enable. This is because the
  5384. * Timers scan is currently being cleared by the MCP on FLR.
  5385. * Step 2.d can be done only for PF6/7 and the driver can also check if
  5386. * there is error before clearing it. But the flow above is simpler and
  5387. * more general.
  5388. * All ILT entries are written by zero+valid and not just PF6/7
  5389. * ILT entries since in the future the ILT entries allocation for
  5390. * PF-s might be dynamic.
  5391. */
  5392. struct ilt_client_info ilt_cli;
  5393. struct bnx2x_ilt ilt;
  5394. memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
  5395. memset(&ilt, 0, sizeof(struct bnx2x_ilt));
  5396. /* initialize dummy TM client */
  5397. ilt_cli.start = 0;
  5398. ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
  5399. ilt_cli.client_num = ILT_CLIENT_TM;
  5400. /* Step 1: set zeroes to all ilt page entries with valid bit on
  5401. * Step 2: set the timers first/last ilt entry to point
  5402. * to the entire range to prevent ILT range error for 3rd/4th
  5403. * vnic (this code assumes existance of the vnic)
  5404. *
  5405. * both steps performed by call to bnx2x_ilt_client_init_op()
  5406. * with dummy TM client
  5407. *
  5408. * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
  5409. * and his brother are split registers
  5410. */
  5411. bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
  5412. bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
  5413. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  5414. REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
  5415. REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
  5416. REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
  5417. }
  5418. REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
  5419. REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
  5420. if (!CHIP_IS_E1x(bp)) {
  5421. int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
  5422. (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
  5423. bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
  5424. bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
  5425. /* let the HW do it's magic ... */
  5426. do {
  5427. msleep(200);
  5428. val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
  5429. } while (factor-- && (val != 1));
  5430. if (val != 1) {
  5431. BNX2X_ERR("ATC_INIT failed\n");
  5432. return -EBUSY;
  5433. }
  5434. }
  5435. bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
  5436. /* clean the DMAE memory */
  5437. bp->dmae_ready = 1;
  5438. bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
  5439. bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
  5440. bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
  5441. bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
  5442. bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
  5443. bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
  5444. bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
  5445. bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
  5446. bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
  5447. bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
  5448. /* QM queues pointers table */
  5449. bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
  5450. /* soft reset pulse */
  5451. REG_WR(bp, QM_REG_SOFT_RESET, 1);
  5452. REG_WR(bp, QM_REG_SOFT_RESET, 0);
  5453. #ifdef BCM_CNIC
  5454. bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
  5455. #endif
  5456. bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
  5457. REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
  5458. if (!CHIP_REV_IS_SLOW(bp))
  5459. /* enable hw interrupt from doorbell Q */
  5460. REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
  5461. bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
  5462. bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
  5463. REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
  5464. if (!CHIP_IS_E1(bp))
  5465. REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
  5466. if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
  5467. if (IS_MF_AFEX(bp)) {
  5468. /* configure that VNTag and VLAN headers must be
  5469. * received in afex mode
  5470. */
  5471. REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
  5472. REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
  5473. REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
  5474. REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
  5475. REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
  5476. } else {
  5477. /* Bit-map indicating which L2 hdrs may appear
  5478. * after the basic Ethernet header
  5479. */
  5480. REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
  5481. bp->path_has_ovlan ? 7 : 6);
  5482. }
  5483. }
  5484. bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
  5485. bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
  5486. bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
  5487. bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
  5488. if (!CHIP_IS_E1x(bp)) {
  5489. /* reset VFC memories */
  5490. REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
  5491. VFC_MEMORIES_RST_REG_CAM_RST |
  5492. VFC_MEMORIES_RST_REG_RAM_RST);
  5493. REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
  5494. VFC_MEMORIES_RST_REG_CAM_RST |
  5495. VFC_MEMORIES_RST_REG_RAM_RST);
  5496. msleep(20);
  5497. }
  5498. bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
  5499. bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
  5500. bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
  5501. bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
  5502. /* sync semi rtc */
  5503. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
  5504. 0x80000000);
  5505. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
  5506. 0x80000000);
  5507. bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
  5508. bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
  5509. bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
  5510. if (!CHIP_IS_E1x(bp)) {
  5511. if (IS_MF_AFEX(bp)) {
  5512. /* configure that VNTag and VLAN headers must be
  5513. * sent in afex mode
  5514. */
  5515. REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
  5516. REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
  5517. REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
  5518. REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
  5519. REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
  5520. } else {
  5521. REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
  5522. bp->path_has_ovlan ? 7 : 6);
  5523. }
  5524. }
  5525. REG_WR(bp, SRC_REG_SOFT_RST, 1);
  5526. bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
  5527. #ifdef BCM_CNIC
  5528. REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
  5529. REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
  5530. REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
  5531. REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
  5532. REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
  5533. REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
  5534. REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
  5535. REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
  5536. REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
  5537. REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
  5538. #endif
  5539. REG_WR(bp, SRC_REG_SOFT_RST, 0);
  5540. if (sizeof(union cdu_context) != 1024)
  5541. /* we currently assume that a context is 1024 bytes */
  5542. dev_alert(&bp->pdev->dev,
  5543. "please adjust the size of cdu_context(%ld)\n",
  5544. (long)sizeof(union cdu_context));
  5545. bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
  5546. val = (4 << 24) + (0 << 12) + 1024;
  5547. REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
  5548. bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
  5549. REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
  5550. /* enable context validation interrupt from CFC */
  5551. REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
  5552. /* set the thresholds to prevent CFC/CDU race */
  5553. REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
  5554. bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
  5555. if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
  5556. REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
  5557. bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
  5558. bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
  5559. /* Reset PCIE errors for debug */
  5560. REG_WR(bp, 0x2814, 0xffffffff);
  5561. REG_WR(bp, 0x3820, 0xffffffff);
  5562. if (!CHIP_IS_E1x(bp)) {
  5563. REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
  5564. (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
  5565. PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
  5566. REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
  5567. (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
  5568. PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
  5569. PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
  5570. REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
  5571. (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
  5572. PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
  5573. PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
  5574. }
  5575. bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
  5576. if (!CHIP_IS_E1(bp)) {
  5577. /* in E3 this done in per-port section */
  5578. if (!CHIP_IS_E3(bp))
  5579. REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
  5580. }
  5581. if (CHIP_IS_E1H(bp))
  5582. /* not applicable for E2 (and above ...) */
  5583. REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
  5584. if (CHIP_REV_IS_SLOW(bp))
  5585. msleep(200);
  5586. /* finish CFC init */
  5587. val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
  5588. if (val != 1) {
  5589. BNX2X_ERR("CFC LL_INIT failed\n");
  5590. return -EBUSY;
  5591. }
  5592. val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
  5593. if (val != 1) {
  5594. BNX2X_ERR("CFC AC_INIT failed\n");
  5595. return -EBUSY;
  5596. }
  5597. val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
  5598. if (val != 1) {
  5599. BNX2X_ERR("CFC CAM_INIT failed\n");
  5600. return -EBUSY;
  5601. }
  5602. REG_WR(bp, CFC_REG_DEBUG0, 0);
  5603. if (CHIP_IS_E1(bp)) {
  5604. /* read NIG statistic
  5605. to see if this is our first up since powerup */
  5606. bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
  5607. val = *bnx2x_sp(bp, wb_data[0]);
  5608. /* do internal memory self test */
  5609. if ((val == 0) && bnx2x_int_mem_test(bp)) {
  5610. BNX2X_ERR("internal mem self test failed\n");
  5611. return -EBUSY;
  5612. }
  5613. }
  5614. bnx2x_setup_fan_failure_detection(bp);
  5615. /* clear PXP2 attentions */
  5616. REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
  5617. bnx2x_enable_blocks_attention(bp);
  5618. bnx2x_enable_blocks_parity(bp);
  5619. if (!BP_NOMCP(bp)) {
  5620. if (CHIP_IS_E1x(bp))
  5621. bnx2x__common_init_phy(bp);
  5622. } else
  5623. BNX2X_ERR("Bootcode is missing - can not initialize link\n");
  5624. return 0;
  5625. }
  5626. /**
  5627. * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
  5628. *
  5629. * @bp: driver handle
  5630. */
  5631. static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
  5632. {
  5633. int rc = bnx2x_init_hw_common(bp);
  5634. if (rc)
  5635. return rc;
  5636. /* In E2 2-PORT mode, same ext phy is used for the two paths */
  5637. if (!BP_NOMCP(bp))
  5638. bnx2x__common_init_phy(bp);
  5639. return 0;
  5640. }
  5641. static int bnx2x_init_hw_port(struct bnx2x *bp)
  5642. {
  5643. int port = BP_PORT(bp);
  5644. int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
  5645. u32 low, high;
  5646. u32 val;
  5647. DP(NETIF_MSG_HW, "starting port init port %d\n", port);
  5648. REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
  5649. bnx2x_init_block(bp, BLOCK_MISC, init_phase);
  5650. bnx2x_init_block(bp, BLOCK_PXP, init_phase);
  5651. bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
  5652. /* Timers bug workaround: disables the pf_master bit in pglue at
  5653. * common phase, we need to enable it here before any dmae access are
  5654. * attempted. Therefore we manually added the enable-master to the
  5655. * port phase (it also happens in the function phase)
  5656. */
  5657. if (!CHIP_IS_E1x(bp))
  5658. REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
  5659. bnx2x_init_block(bp, BLOCK_ATC, init_phase);
  5660. bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
  5661. bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
  5662. bnx2x_init_block(bp, BLOCK_QM, init_phase);
  5663. bnx2x_init_block(bp, BLOCK_TCM, init_phase);
  5664. bnx2x_init_block(bp, BLOCK_UCM, init_phase);
  5665. bnx2x_init_block(bp, BLOCK_CCM, init_phase);
  5666. bnx2x_init_block(bp, BLOCK_XCM, init_phase);
  5667. /* QM cid (connection) count */
  5668. bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
  5669. #ifdef BCM_CNIC
  5670. bnx2x_init_block(bp, BLOCK_TM, init_phase);
  5671. REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
  5672. REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
  5673. #endif
  5674. bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
  5675. bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
  5676. if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
  5677. if (IS_MF(bp))
  5678. low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
  5679. else if (bp->dev->mtu > 4096) {
  5680. if (bp->flags & ONE_PORT_FLAG)
  5681. low = 160;
  5682. else {
  5683. val = bp->dev->mtu;
  5684. /* (24*1024 + val*4)/256 */
  5685. low = 96 + (val/64) +
  5686. ((val % 64) ? 1 : 0);
  5687. }
  5688. } else
  5689. low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
  5690. high = low + 56; /* 14*1024/256 */
  5691. REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
  5692. REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
  5693. }
  5694. if (CHIP_MODE_IS_4_PORT(bp))
  5695. REG_WR(bp, (BP_PORT(bp) ?
  5696. BRB1_REG_MAC_GUARANTIED_1 :
  5697. BRB1_REG_MAC_GUARANTIED_0), 40);
  5698. bnx2x_init_block(bp, BLOCK_PRS, init_phase);
  5699. if (CHIP_IS_E3B0(bp)) {
  5700. if (IS_MF_AFEX(bp)) {
  5701. /* configure headers for AFEX mode */
  5702. REG_WR(bp, BP_PORT(bp) ?
  5703. PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
  5704. PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
  5705. REG_WR(bp, BP_PORT(bp) ?
  5706. PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
  5707. PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
  5708. REG_WR(bp, BP_PORT(bp) ?
  5709. PRS_REG_MUST_HAVE_HDRS_PORT_1 :
  5710. PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
  5711. } else {
  5712. /* Ovlan exists only if we are in multi-function +
  5713. * switch-dependent mode, in switch-independent there
  5714. * is no ovlan headers
  5715. */
  5716. REG_WR(bp, BP_PORT(bp) ?
  5717. PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
  5718. PRS_REG_HDRS_AFTER_BASIC_PORT_0,
  5719. (bp->path_has_ovlan ? 7 : 6));
  5720. }
  5721. }
  5722. bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
  5723. bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
  5724. bnx2x_init_block(bp, BLOCK_USDM, init_phase);
  5725. bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
  5726. bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
  5727. bnx2x_init_block(bp, BLOCK_USEM, init_phase);
  5728. bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
  5729. bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
  5730. bnx2x_init_block(bp, BLOCK_UPB, init_phase);
  5731. bnx2x_init_block(bp, BLOCK_XPB, init_phase);
  5732. bnx2x_init_block(bp, BLOCK_PBF, init_phase);
  5733. if (CHIP_IS_E1x(bp)) {
  5734. /* configure PBF to work without PAUSE mtu 9000 */
  5735. REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
  5736. /* update threshold */
  5737. REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
  5738. /* update init credit */
  5739. REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
  5740. /* probe changes */
  5741. REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
  5742. udelay(50);
  5743. REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
  5744. }
  5745. #ifdef BCM_CNIC
  5746. bnx2x_init_block(bp, BLOCK_SRC, init_phase);
  5747. #endif
  5748. bnx2x_init_block(bp, BLOCK_CDU, init_phase);
  5749. bnx2x_init_block(bp, BLOCK_CFC, init_phase);
  5750. if (CHIP_IS_E1(bp)) {
  5751. REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
  5752. REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
  5753. }
  5754. bnx2x_init_block(bp, BLOCK_HC, init_phase);
  5755. bnx2x_init_block(bp, BLOCK_IGU, init_phase);
  5756. bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
  5757. /* init aeu_mask_attn_func_0/1:
  5758. * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
  5759. * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
  5760. * bits 4-7 are used for "per vn group attention" */
  5761. val = IS_MF(bp) ? 0xF7 : 0x7;
  5762. /* Enable DCBX attention for all but E1 */
  5763. val |= CHIP_IS_E1(bp) ? 0 : 0x10;
  5764. REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
  5765. bnx2x_init_block(bp, BLOCK_NIG, init_phase);
  5766. if (!CHIP_IS_E1x(bp)) {
  5767. /* Bit-map indicating which L2 hdrs may appear after the
  5768. * basic Ethernet header
  5769. */
  5770. if (IS_MF_AFEX(bp))
  5771. REG_WR(bp, BP_PORT(bp) ?
  5772. NIG_REG_P1_HDRS_AFTER_BASIC :
  5773. NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
  5774. else
  5775. REG_WR(bp, BP_PORT(bp) ?
  5776. NIG_REG_P1_HDRS_AFTER_BASIC :
  5777. NIG_REG_P0_HDRS_AFTER_BASIC,
  5778. IS_MF_SD(bp) ? 7 : 6);
  5779. if (CHIP_IS_E3(bp))
  5780. REG_WR(bp, BP_PORT(bp) ?
  5781. NIG_REG_LLH1_MF_MODE :
  5782. NIG_REG_LLH_MF_MODE, IS_MF(bp));
  5783. }
  5784. if (!CHIP_IS_E3(bp))
  5785. REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
  5786. if (!CHIP_IS_E1(bp)) {
  5787. /* 0x2 disable mf_ov, 0x1 enable */
  5788. REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
  5789. (IS_MF_SD(bp) ? 0x1 : 0x2));
  5790. if (!CHIP_IS_E1x(bp)) {
  5791. val = 0;
  5792. switch (bp->mf_mode) {
  5793. case MULTI_FUNCTION_SD:
  5794. val = 1;
  5795. break;
  5796. case MULTI_FUNCTION_SI:
  5797. case MULTI_FUNCTION_AFEX:
  5798. val = 2;
  5799. break;
  5800. }
  5801. REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
  5802. NIG_REG_LLH0_CLS_TYPE), val);
  5803. }
  5804. {
  5805. REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
  5806. REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
  5807. REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
  5808. }
  5809. }
  5810. /* If SPIO5 is set to generate interrupts, enable it for this port */
  5811. val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
  5812. if (val & (1 << MISC_REGISTERS_SPIO_5)) {
  5813. u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
  5814. MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
  5815. val = REG_RD(bp, reg_addr);
  5816. val |= AEU_INPUTS_ATTN_BITS_SPIO5;
  5817. REG_WR(bp, reg_addr, val);
  5818. }
  5819. return 0;
  5820. }
  5821. static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
  5822. {
  5823. int reg;
  5824. u32 wb_write[2];
  5825. if (CHIP_IS_E1(bp))
  5826. reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
  5827. else
  5828. reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
  5829. wb_write[0] = ONCHIP_ADDR1(addr);
  5830. wb_write[1] = ONCHIP_ADDR2(addr);
  5831. REG_WR_DMAE(bp, reg, wb_write, 2);
  5832. }
  5833. static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
  5834. u8 idu_sb_id, bool is_Pf)
  5835. {
  5836. u32 data, ctl, cnt = 100;
  5837. u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
  5838. u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
  5839. u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
  5840. u32 sb_bit = 1 << (idu_sb_id%32);
  5841. u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
  5842. u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
  5843. /* Not supported in BC mode */
  5844. if (CHIP_INT_MODE_IS_BC(bp))
  5845. return;
  5846. data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
  5847. << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
  5848. IGU_REGULAR_CLEANUP_SET |
  5849. IGU_REGULAR_BCLEANUP;
  5850. ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
  5851. func_encode << IGU_CTRL_REG_FID_SHIFT |
  5852. IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
  5853. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  5854. data, igu_addr_data);
  5855. REG_WR(bp, igu_addr_data, data);
  5856. mmiowb();
  5857. barrier();
  5858. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  5859. ctl, igu_addr_ctl);
  5860. REG_WR(bp, igu_addr_ctl, ctl);
  5861. mmiowb();
  5862. barrier();
  5863. /* wait for clean up to finish */
  5864. while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
  5865. msleep(20);
  5866. if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
  5867. DP(NETIF_MSG_HW,
  5868. "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
  5869. idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
  5870. }
  5871. }
  5872. static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
  5873. {
  5874. bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
  5875. }
  5876. static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
  5877. {
  5878. u32 i, base = FUNC_ILT_BASE(func);
  5879. for (i = base; i < base + ILT_PER_FUNC; i++)
  5880. bnx2x_ilt_wr(bp, i, 0);
  5881. }
  5882. static int bnx2x_init_hw_func(struct bnx2x *bp)
  5883. {
  5884. int port = BP_PORT(bp);
  5885. int func = BP_FUNC(bp);
  5886. int init_phase = PHASE_PF0 + func;
  5887. struct bnx2x_ilt *ilt = BP_ILT(bp);
  5888. u16 cdu_ilt_start;
  5889. u32 addr, val;
  5890. u32 main_mem_base, main_mem_size, main_mem_prty_clr;
  5891. int i, main_mem_width, rc;
  5892. DP(NETIF_MSG_HW, "starting func init func %d\n", func);
  5893. /* FLR cleanup - hmmm */
  5894. if (!CHIP_IS_E1x(bp)) {
  5895. rc = bnx2x_pf_flr_clnup(bp);
  5896. if (rc)
  5897. return rc;
  5898. }
  5899. /* set MSI reconfigure capability */
  5900. if (bp->common.int_block == INT_BLOCK_HC) {
  5901. addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
  5902. val = REG_RD(bp, addr);
  5903. val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
  5904. REG_WR(bp, addr, val);
  5905. }
  5906. bnx2x_init_block(bp, BLOCK_PXP, init_phase);
  5907. bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
  5908. ilt = BP_ILT(bp);
  5909. cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
  5910. for (i = 0; i < L2_ILT_LINES(bp); i++) {
  5911. ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
  5912. ilt->lines[cdu_ilt_start + i].page_mapping =
  5913. bp->context[i].cxt_mapping;
  5914. ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
  5915. }
  5916. bnx2x_ilt_init_op(bp, INITOP_SET);
  5917. #ifdef BCM_CNIC
  5918. bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
  5919. /* T1 hash bits value determines the T1 number of entries */
  5920. REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
  5921. #endif
  5922. #ifndef BCM_CNIC
  5923. /* set NIC mode */
  5924. REG_WR(bp, PRS_REG_NIC_MODE, 1);
  5925. #endif /* BCM_CNIC */
  5926. if (!CHIP_IS_E1x(bp)) {
  5927. u32 pf_conf = IGU_PF_CONF_FUNC_EN;
  5928. /* Turn on a single ISR mode in IGU if driver is going to use
  5929. * INT#x or MSI
  5930. */
  5931. if (!(bp->flags & USING_MSIX_FLAG))
  5932. pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
  5933. /*
  5934. * Timers workaround bug: function init part.
  5935. * Need to wait 20msec after initializing ILT,
  5936. * needed to make sure there are no requests in
  5937. * one of the PXP internal queues with "old" ILT addresses
  5938. */
  5939. msleep(20);
  5940. /*
  5941. * Master enable - Due to WB DMAE writes performed before this
  5942. * register is re-initialized as part of the regular function
  5943. * init
  5944. */
  5945. REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
  5946. /* Enable the function in IGU */
  5947. REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
  5948. }
  5949. bp->dmae_ready = 1;
  5950. bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
  5951. if (!CHIP_IS_E1x(bp))
  5952. REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
  5953. bnx2x_init_block(bp, BLOCK_ATC, init_phase);
  5954. bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
  5955. bnx2x_init_block(bp, BLOCK_NIG, init_phase);
  5956. bnx2x_init_block(bp, BLOCK_SRC, init_phase);
  5957. bnx2x_init_block(bp, BLOCK_MISC, init_phase);
  5958. bnx2x_init_block(bp, BLOCK_TCM, init_phase);
  5959. bnx2x_init_block(bp, BLOCK_UCM, init_phase);
  5960. bnx2x_init_block(bp, BLOCK_CCM, init_phase);
  5961. bnx2x_init_block(bp, BLOCK_XCM, init_phase);
  5962. bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
  5963. bnx2x_init_block(bp, BLOCK_USEM, init_phase);
  5964. bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
  5965. bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
  5966. if (!CHIP_IS_E1x(bp))
  5967. REG_WR(bp, QM_REG_PF_EN, 1);
  5968. if (!CHIP_IS_E1x(bp)) {
  5969. REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
  5970. REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
  5971. REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
  5972. REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
  5973. }
  5974. bnx2x_init_block(bp, BLOCK_QM, init_phase);
  5975. bnx2x_init_block(bp, BLOCK_TM, init_phase);
  5976. bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
  5977. bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
  5978. bnx2x_init_block(bp, BLOCK_PRS, init_phase);
  5979. bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
  5980. bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
  5981. bnx2x_init_block(bp, BLOCK_USDM, init_phase);
  5982. bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
  5983. bnx2x_init_block(bp, BLOCK_UPB, init_phase);
  5984. bnx2x_init_block(bp, BLOCK_XPB, init_phase);
  5985. bnx2x_init_block(bp, BLOCK_PBF, init_phase);
  5986. if (!CHIP_IS_E1x(bp))
  5987. REG_WR(bp, PBF_REG_DISABLE_PF, 0);
  5988. bnx2x_init_block(bp, BLOCK_CDU, init_phase);
  5989. bnx2x_init_block(bp, BLOCK_CFC, init_phase);
  5990. if (!CHIP_IS_E1x(bp))
  5991. REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
  5992. if (IS_MF(bp)) {
  5993. REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
  5994. REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
  5995. }
  5996. bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
  5997. /* HC init per function */
  5998. if (bp->common.int_block == INT_BLOCK_HC) {
  5999. if (CHIP_IS_E1H(bp)) {
  6000. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
  6001. REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
  6002. REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
  6003. }
  6004. bnx2x_init_block(bp, BLOCK_HC, init_phase);
  6005. } else {
  6006. int num_segs, sb_idx, prod_offset;
  6007. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
  6008. if (!CHIP_IS_E1x(bp)) {
  6009. REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
  6010. REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
  6011. }
  6012. bnx2x_init_block(bp, BLOCK_IGU, init_phase);
  6013. if (!CHIP_IS_E1x(bp)) {
  6014. int dsb_idx = 0;
  6015. /**
  6016. * Producer memory:
  6017. * E2 mode: address 0-135 match to the mapping memory;
  6018. * 136 - PF0 default prod; 137 - PF1 default prod;
  6019. * 138 - PF2 default prod; 139 - PF3 default prod;
  6020. * 140 - PF0 attn prod; 141 - PF1 attn prod;
  6021. * 142 - PF2 attn prod; 143 - PF3 attn prod;
  6022. * 144-147 reserved.
  6023. *
  6024. * E1.5 mode - In backward compatible mode;
  6025. * for non default SB; each even line in the memory
  6026. * holds the U producer and each odd line hold
  6027. * the C producer. The first 128 producers are for
  6028. * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
  6029. * producers are for the DSB for each PF.
  6030. * Each PF has five segments: (the order inside each
  6031. * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
  6032. * 132-135 C prods; 136-139 X prods; 140-143 T prods;
  6033. * 144-147 attn prods;
  6034. */
  6035. /* non-default-status-blocks */
  6036. num_segs = CHIP_INT_MODE_IS_BC(bp) ?
  6037. IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
  6038. for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
  6039. prod_offset = (bp->igu_base_sb + sb_idx) *
  6040. num_segs;
  6041. for (i = 0; i < num_segs; i++) {
  6042. addr = IGU_REG_PROD_CONS_MEMORY +
  6043. (prod_offset + i) * 4;
  6044. REG_WR(bp, addr, 0);
  6045. }
  6046. /* send consumer update with value 0 */
  6047. bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
  6048. USTORM_ID, 0, IGU_INT_NOP, 1);
  6049. bnx2x_igu_clear_sb(bp,
  6050. bp->igu_base_sb + sb_idx);
  6051. }
  6052. /* default-status-blocks */
  6053. num_segs = CHIP_INT_MODE_IS_BC(bp) ?
  6054. IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
  6055. if (CHIP_MODE_IS_4_PORT(bp))
  6056. dsb_idx = BP_FUNC(bp);
  6057. else
  6058. dsb_idx = BP_VN(bp);
  6059. prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
  6060. IGU_BC_BASE_DSB_PROD + dsb_idx :
  6061. IGU_NORM_BASE_DSB_PROD + dsb_idx);
  6062. /*
  6063. * igu prods come in chunks of E1HVN_MAX (4) -
  6064. * does not matters what is the current chip mode
  6065. */
  6066. for (i = 0; i < (num_segs * E1HVN_MAX);
  6067. i += E1HVN_MAX) {
  6068. addr = IGU_REG_PROD_CONS_MEMORY +
  6069. (prod_offset + i)*4;
  6070. REG_WR(bp, addr, 0);
  6071. }
  6072. /* send consumer update with 0 */
  6073. if (CHIP_INT_MODE_IS_BC(bp)) {
  6074. bnx2x_ack_sb(bp, bp->igu_dsb_id,
  6075. USTORM_ID, 0, IGU_INT_NOP, 1);
  6076. bnx2x_ack_sb(bp, bp->igu_dsb_id,
  6077. CSTORM_ID, 0, IGU_INT_NOP, 1);
  6078. bnx2x_ack_sb(bp, bp->igu_dsb_id,
  6079. XSTORM_ID, 0, IGU_INT_NOP, 1);
  6080. bnx2x_ack_sb(bp, bp->igu_dsb_id,
  6081. TSTORM_ID, 0, IGU_INT_NOP, 1);
  6082. bnx2x_ack_sb(bp, bp->igu_dsb_id,
  6083. ATTENTION_ID, 0, IGU_INT_NOP, 1);
  6084. } else {
  6085. bnx2x_ack_sb(bp, bp->igu_dsb_id,
  6086. USTORM_ID, 0, IGU_INT_NOP, 1);
  6087. bnx2x_ack_sb(bp, bp->igu_dsb_id,
  6088. ATTENTION_ID, 0, IGU_INT_NOP, 1);
  6089. }
  6090. bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
  6091. /* !!! these should become driver const once
  6092. rf-tool supports split-68 const */
  6093. REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
  6094. REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
  6095. REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
  6096. REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
  6097. REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
  6098. REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
  6099. }
  6100. }
  6101. /* Reset PCIE errors for debug */
  6102. REG_WR(bp, 0x2114, 0xffffffff);
  6103. REG_WR(bp, 0x2120, 0xffffffff);
  6104. if (CHIP_IS_E1x(bp)) {
  6105. main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
  6106. main_mem_base = HC_REG_MAIN_MEMORY +
  6107. BP_PORT(bp) * (main_mem_size * 4);
  6108. main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
  6109. main_mem_width = 8;
  6110. val = REG_RD(bp, main_mem_prty_clr);
  6111. if (val)
  6112. DP(NETIF_MSG_HW,
  6113. "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
  6114. val);
  6115. /* Clear "false" parity errors in MSI-X table */
  6116. for (i = main_mem_base;
  6117. i < main_mem_base + main_mem_size * 4;
  6118. i += main_mem_width) {
  6119. bnx2x_read_dmae(bp, i, main_mem_width / 4);
  6120. bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
  6121. i, main_mem_width / 4);
  6122. }
  6123. /* Clear HC parity attention */
  6124. REG_RD(bp, main_mem_prty_clr);
  6125. }
  6126. #ifdef BNX2X_STOP_ON_ERROR
  6127. /* Enable STORMs SP logging */
  6128. REG_WR8(bp, BAR_USTRORM_INTMEM +
  6129. USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
  6130. REG_WR8(bp, BAR_TSTRORM_INTMEM +
  6131. TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
  6132. REG_WR8(bp, BAR_CSTRORM_INTMEM +
  6133. CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
  6134. REG_WR8(bp, BAR_XSTRORM_INTMEM +
  6135. XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
  6136. #endif
  6137. bnx2x_phy_probe(&bp->link_params);
  6138. return 0;
  6139. }
  6140. void bnx2x_free_mem(struct bnx2x *bp)
  6141. {
  6142. int i;
  6143. /* fastpath */
  6144. bnx2x_free_fp_mem(bp);
  6145. /* end of fastpath */
  6146. BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
  6147. sizeof(struct host_sp_status_block));
  6148. BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
  6149. bp->fw_stats_data_sz + bp->fw_stats_req_sz);
  6150. BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
  6151. sizeof(struct bnx2x_slowpath));
  6152. for (i = 0; i < L2_ILT_LINES(bp); i++)
  6153. BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
  6154. bp->context[i].size);
  6155. bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
  6156. BNX2X_FREE(bp->ilt->lines);
  6157. #ifdef BCM_CNIC
  6158. if (!CHIP_IS_E1x(bp))
  6159. BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
  6160. sizeof(struct host_hc_status_block_e2));
  6161. else
  6162. BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
  6163. sizeof(struct host_hc_status_block_e1x));
  6164. BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
  6165. #endif
  6166. BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
  6167. BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
  6168. BCM_PAGE_SIZE * NUM_EQ_PAGES);
  6169. }
  6170. static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
  6171. {
  6172. int num_groups;
  6173. int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
  6174. /* number of queues for statistics is number of eth queues + FCoE */
  6175. u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
  6176. /* Total number of FW statistics requests =
  6177. * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
  6178. * num of queues
  6179. */
  6180. bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
  6181. /* Request is built from stats_query_header and an array of
  6182. * stats_query_cmd_group each of which contains
  6183. * STATS_QUERY_CMD_COUNT rules. The real number or requests is
  6184. * configured in the stats_query_header.
  6185. */
  6186. num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
  6187. (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
  6188. bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
  6189. num_groups * sizeof(struct stats_query_cmd_group);
  6190. /* Data for statistics requests + stats_conter
  6191. *
  6192. * stats_counter holds per-STORM counters that are incremented
  6193. * when STORM has finished with the current request.
  6194. *
  6195. * memory for FCoE offloaded statistics are counted anyway,
  6196. * even if they will not be sent.
  6197. */
  6198. bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
  6199. sizeof(struct per_pf_stats) +
  6200. sizeof(struct fcoe_statistics_params) +
  6201. sizeof(struct per_queue_stats) * num_queue_stats +
  6202. sizeof(struct stats_counter);
  6203. BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
  6204. bp->fw_stats_data_sz + bp->fw_stats_req_sz);
  6205. /* Set shortcuts */
  6206. bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
  6207. bp->fw_stats_req_mapping = bp->fw_stats_mapping;
  6208. bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
  6209. ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
  6210. bp->fw_stats_data_mapping = bp->fw_stats_mapping +
  6211. bp->fw_stats_req_sz;
  6212. return 0;
  6213. alloc_mem_err:
  6214. BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
  6215. bp->fw_stats_data_sz + bp->fw_stats_req_sz);
  6216. BNX2X_ERR("Can't allocate memory\n");
  6217. return -ENOMEM;
  6218. }
  6219. int bnx2x_alloc_mem(struct bnx2x *bp)
  6220. {
  6221. int i, allocated, context_size;
  6222. #ifdef BCM_CNIC
  6223. if (!CHIP_IS_E1x(bp))
  6224. /* size = the status block + ramrod buffers */
  6225. BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
  6226. sizeof(struct host_hc_status_block_e2));
  6227. else
  6228. BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
  6229. sizeof(struct host_hc_status_block_e1x));
  6230. /* allocate searcher T2 table */
  6231. BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
  6232. #endif
  6233. BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
  6234. sizeof(struct host_sp_status_block));
  6235. BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
  6236. sizeof(struct bnx2x_slowpath));
  6237. #ifdef BCM_CNIC
  6238. /* write address to which L5 should insert its values */
  6239. bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp;
  6240. #endif
  6241. /* Allocated memory for FW statistics */
  6242. if (bnx2x_alloc_fw_stats_mem(bp))
  6243. goto alloc_mem_err;
  6244. /* Allocate memory for CDU context:
  6245. * This memory is allocated separately and not in the generic ILT
  6246. * functions because CDU differs in few aspects:
  6247. * 1. There are multiple entities allocating memory for context -
  6248. * 'regular' driver, CNIC and SRIOV driver. Each separately controls
  6249. * its own ILT lines.
  6250. * 2. Since CDU page-size is not a single 4KB page (which is the case
  6251. * for the other ILT clients), to be efficient we want to support
  6252. * allocation of sub-page-size in the last entry.
  6253. * 3. Context pointers are used by the driver to pass to FW / update
  6254. * the context (for the other ILT clients the pointers are used just to
  6255. * free the memory during unload).
  6256. */
  6257. context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
  6258. for (i = 0, allocated = 0; allocated < context_size; i++) {
  6259. bp->context[i].size = min(CDU_ILT_PAGE_SZ,
  6260. (context_size - allocated));
  6261. BNX2X_PCI_ALLOC(bp->context[i].vcxt,
  6262. &bp->context[i].cxt_mapping,
  6263. bp->context[i].size);
  6264. allocated += bp->context[i].size;
  6265. }
  6266. BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
  6267. if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
  6268. goto alloc_mem_err;
  6269. /* Slow path ring */
  6270. BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
  6271. /* EQ */
  6272. BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
  6273. BCM_PAGE_SIZE * NUM_EQ_PAGES);
  6274. /* fastpath */
  6275. /* need to be done at the end, since it's self adjusting to amount
  6276. * of memory available for RSS queues
  6277. */
  6278. if (bnx2x_alloc_fp_mem(bp))
  6279. goto alloc_mem_err;
  6280. return 0;
  6281. alloc_mem_err:
  6282. bnx2x_free_mem(bp);
  6283. BNX2X_ERR("Can't allocate memory\n");
  6284. return -ENOMEM;
  6285. }
  6286. /*
  6287. * Init service functions
  6288. */
  6289. int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
  6290. struct bnx2x_vlan_mac_obj *obj, bool set,
  6291. int mac_type, unsigned long *ramrod_flags)
  6292. {
  6293. int rc;
  6294. struct bnx2x_vlan_mac_ramrod_params ramrod_param;
  6295. memset(&ramrod_param, 0, sizeof(ramrod_param));
  6296. /* Fill general parameters */
  6297. ramrod_param.vlan_mac_obj = obj;
  6298. ramrod_param.ramrod_flags = *ramrod_flags;
  6299. /* Fill a user request section if needed */
  6300. if (!test_bit(RAMROD_CONT, ramrod_flags)) {
  6301. memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
  6302. __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
  6303. /* Set the command: ADD or DEL */
  6304. if (set)
  6305. ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
  6306. else
  6307. ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
  6308. }
  6309. rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
  6310. if (rc == -EEXIST) {
  6311. DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
  6312. /* do not treat adding same MAC as error */
  6313. rc = 0;
  6314. } else if (rc < 0)
  6315. BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
  6316. return rc;
  6317. }
  6318. int bnx2x_del_all_macs(struct bnx2x *bp,
  6319. struct bnx2x_vlan_mac_obj *mac_obj,
  6320. int mac_type, bool wait_for_comp)
  6321. {
  6322. int rc;
  6323. unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
  6324. /* Wait for completion of requested */
  6325. if (wait_for_comp)
  6326. __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
  6327. /* Set the mac type of addresses we want to clear */
  6328. __set_bit(mac_type, &vlan_mac_flags);
  6329. rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
  6330. if (rc < 0)
  6331. BNX2X_ERR("Failed to delete MACs: %d\n", rc);
  6332. return rc;
  6333. }
  6334. int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
  6335. {
  6336. unsigned long ramrod_flags = 0;
  6337. #ifdef BCM_CNIC
  6338. if (is_zero_ether_addr(bp->dev->dev_addr) &&
  6339. (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
  6340. DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
  6341. "Ignoring Zero MAC for STORAGE SD mode\n");
  6342. return 0;
  6343. }
  6344. #endif
  6345. DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
  6346. __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
  6347. /* Eth MAC is set on RSS leading client (fp[0]) */
  6348. return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
  6349. set, BNX2X_ETH_MAC, &ramrod_flags);
  6350. }
  6351. int bnx2x_setup_leading(struct bnx2x *bp)
  6352. {
  6353. return bnx2x_setup_queue(bp, &bp->fp[0], 1);
  6354. }
  6355. /**
  6356. * bnx2x_set_int_mode - configure interrupt mode
  6357. *
  6358. * @bp: driver handle
  6359. *
  6360. * In case of MSI-X it will also try to enable MSI-X.
  6361. */
  6362. void bnx2x_set_int_mode(struct bnx2x *bp)
  6363. {
  6364. switch (int_mode) {
  6365. case INT_MODE_MSI:
  6366. bnx2x_enable_msi(bp);
  6367. /* falling through... */
  6368. case INT_MODE_INTx:
  6369. bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
  6370. BNX2X_DEV_INFO("set number of queues to 1\n");
  6371. break;
  6372. default:
  6373. /* if we can't use MSI-X we only need one fp,
  6374. * so try to enable MSI-X with the requested number of fp's
  6375. * and fallback to MSI or legacy INTx with one fp
  6376. */
  6377. if (bnx2x_enable_msix(bp) ||
  6378. bp->flags & USING_SINGLE_MSIX_FLAG) {
  6379. /* failed to enable multiple MSI-X */
  6380. BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
  6381. bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
  6382. bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
  6383. /* Try to enable MSI */
  6384. if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
  6385. !(bp->flags & DISABLE_MSI_FLAG))
  6386. bnx2x_enable_msi(bp);
  6387. }
  6388. break;
  6389. }
  6390. }
  6391. /* must be called prioir to any HW initializations */
  6392. static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
  6393. {
  6394. return L2_ILT_LINES(bp);
  6395. }
  6396. void bnx2x_ilt_set_info(struct bnx2x *bp)
  6397. {
  6398. struct ilt_client_info *ilt_client;
  6399. struct bnx2x_ilt *ilt = BP_ILT(bp);
  6400. u16 line = 0;
  6401. ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
  6402. DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
  6403. /* CDU */
  6404. ilt_client = &ilt->clients[ILT_CLIENT_CDU];
  6405. ilt_client->client_num = ILT_CLIENT_CDU;
  6406. ilt_client->page_size = CDU_ILT_PAGE_SZ;
  6407. ilt_client->flags = ILT_CLIENT_SKIP_MEM;
  6408. ilt_client->start = line;
  6409. line += bnx2x_cid_ilt_lines(bp);
  6410. #ifdef BCM_CNIC
  6411. line += CNIC_ILT_LINES;
  6412. #endif
  6413. ilt_client->end = line - 1;
  6414. DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
  6415. ilt_client->start,
  6416. ilt_client->end,
  6417. ilt_client->page_size,
  6418. ilt_client->flags,
  6419. ilog2(ilt_client->page_size >> 12));
  6420. /* QM */
  6421. if (QM_INIT(bp->qm_cid_count)) {
  6422. ilt_client = &ilt->clients[ILT_CLIENT_QM];
  6423. ilt_client->client_num = ILT_CLIENT_QM;
  6424. ilt_client->page_size = QM_ILT_PAGE_SZ;
  6425. ilt_client->flags = 0;
  6426. ilt_client->start = line;
  6427. /* 4 bytes for each cid */
  6428. line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
  6429. QM_ILT_PAGE_SZ);
  6430. ilt_client->end = line - 1;
  6431. DP(NETIF_MSG_IFUP,
  6432. "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
  6433. ilt_client->start,
  6434. ilt_client->end,
  6435. ilt_client->page_size,
  6436. ilt_client->flags,
  6437. ilog2(ilt_client->page_size >> 12));
  6438. }
  6439. /* SRC */
  6440. ilt_client = &ilt->clients[ILT_CLIENT_SRC];
  6441. #ifdef BCM_CNIC
  6442. ilt_client->client_num = ILT_CLIENT_SRC;
  6443. ilt_client->page_size = SRC_ILT_PAGE_SZ;
  6444. ilt_client->flags = 0;
  6445. ilt_client->start = line;
  6446. line += SRC_ILT_LINES;
  6447. ilt_client->end = line - 1;
  6448. DP(NETIF_MSG_IFUP,
  6449. "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
  6450. ilt_client->start,
  6451. ilt_client->end,
  6452. ilt_client->page_size,
  6453. ilt_client->flags,
  6454. ilog2(ilt_client->page_size >> 12));
  6455. #else
  6456. ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
  6457. #endif
  6458. /* TM */
  6459. ilt_client = &ilt->clients[ILT_CLIENT_TM];
  6460. #ifdef BCM_CNIC
  6461. ilt_client->client_num = ILT_CLIENT_TM;
  6462. ilt_client->page_size = TM_ILT_PAGE_SZ;
  6463. ilt_client->flags = 0;
  6464. ilt_client->start = line;
  6465. line += TM_ILT_LINES;
  6466. ilt_client->end = line - 1;
  6467. DP(NETIF_MSG_IFUP,
  6468. "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
  6469. ilt_client->start,
  6470. ilt_client->end,
  6471. ilt_client->page_size,
  6472. ilt_client->flags,
  6473. ilog2(ilt_client->page_size >> 12));
  6474. #else
  6475. ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
  6476. #endif
  6477. BUG_ON(line > ILT_MAX_LINES);
  6478. }
  6479. /**
  6480. * bnx2x_pf_q_prep_init - prepare INIT transition parameters
  6481. *
  6482. * @bp: driver handle
  6483. * @fp: pointer to fastpath
  6484. * @init_params: pointer to parameters structure
  6485. *
  6486. * parameters configured:
  6487. * - HC configuration
  6488. * - Queue's CDU context
  6489. */
  6490. static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
  6491. struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
  6492. {
  6493. u8 cos;
  6494. int cxt_index, cxt_offset;
  6495. /* FCoE Queue uses Default SB, thus has no HC capabilities */
  6496. if (!IS_FCOE_FP(fp)) {
  6497. __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
  6498. __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
  6499. /* If HC is supporterd, enable host coalescing in the transition
  6500. * to INIT state.
  6501. */
  6502. __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
  6503. __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
  6504. /* HC rate */
  6505. init_params->rx.hc_rate = bp->rx_ticks ?
  6506. (1000000 / bp->rx_ticks) : 0;
  6507. init_params->tx.hc_rate = bp->tx_ticks ?
  6508. (1000000 / bp->tx_ticks) : 0;
  6509. /* FW SB ID */
  6510. init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
  6511. fp->fw_sb_id;
  6512. /*
  6513. * CQ index among the SB indices: FCoE clients uses the default
  6514. * SB, therefore it's different.
  6515. */
  6516. init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
  6517. init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
  6518. }
  6519. /* set maximum number of COSs supported by this queue */
  6520. init_params->max_cos = fp->max_cos;
  6521. DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
  6522. fp->index, init_params->max_cos);
  6523. /* set the context pointers queue object */
  6524. for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
  6525. cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
  6526. cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
  6527. ILT_PAGE_CIDS);
  6528. init_params->cxts[cos] =
  6529. &bp->context[cxt_index].vcxt[cxt_offset].eth;
  6530. }
  6531. }
  6532. int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
  6533. struct bnx2x_queue_state_params *q_params,
  6534. struct bnx2x_queue_setup_tx_only_params *tx_only_params,
  6535. int tx_index, bool leading)
  6536. {
  6537. memset(tx_only_params, 0, sizeof(*tx_only_params));
  6538. /* Set the command */
  6539. q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
  6540. /* Set tx-only QUEUE flags: don't zero statistics */
  6541. tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
  6542. /* choose the index of the cid to send the slow path on */
  6543. tx_only_params->cid_index = tx_index;
  6544. /* Set general TX_ONLY_SETUP parameters */
  6545. bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
  6546. /* Set Tx TX_ONLY_SETUP parameters */
  6547. bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
  6548. DP(NETIF_MSG_IFUP,
  6549. "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
  6550. tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
  6551. q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
  6552. tx_only_params->gen_params.spcl_id, tx_only_params->flags);
  6553. /* send the ramrod */
  6554. return bnx2x_queue_state_change(bp, q_params);
  6555. }
  6556. /**
  6557. * bnx2x_setup_queue - setup queue
  6558. *
  6559. * @bp: driver handle
  6560. * @fp: pointer to fastpath
  6561. * @leading: is leading
  6562. *
  6563. * This function performs 2 steps in a Queue state machine
  6564. * actually: 1) RESET->INIT 2) INIT->SETUP
  6565. */
  6566. int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
  6567. bool leading)
  6568. {
  6569. struct bnx2x_queue_state_params q_params = {NULL};
  6570. struct bnx2x_queue_setup_params *setup_params =
  6571. &q_params.params.setup;
  6572. struct bnx2x_queue_setup_tx_only_params *tx_only_params =
  6573. &q_params.params.tx_only;
  6574. int rc;
  6575. u8 tx_index;
  6576. DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
  6577. /* reset IGU state skip FCoE L2 queue */
  6578. if (!IS_FCOE_FP(fp))
  6579. bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
  6580. IGU_INT_ENABLE, 0);
  6581. q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
  6582. /* We want to wait for completion in this context */
  6583. __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
  6584. /* Prepare the INIT parameters */
  6585. bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
  6586. /* Set the command */
  6587. q_params.cmd = BNX2X_Q_CMD_INIT;
  6588. /* Change the state to INIT */
  6589. rc = bnx2x_queue_state_change(bp, &q_params);
  6590. if (rc) {
  6591. BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
  6592. return rc;
  6593. }
  6594. DP(NETIF_MSG_IFUP, "init complete\n");
  6595. /* Now move the Queue to the SETUP state... */
  6596. memset(setup_params, 0, sizeof(*setup_params));
  6597. /* Set QUEUE flags */
  6598. setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
  6599. /* Set general SETUP parameters */
  6600. bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
  6601. FIRST_TX_COS_INDEX);
  6602. bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
  6603. &setup_params->rxq_params);
  6604. bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
  6605. FIRST_TX_COS_INDEX);
  6606. /* Set the command */
  6607. q_params.cmd = BNX2X_Q_CMD_SETUP;
  6608. /* Change the state to SETUP */
  6609. rc = bnx2x_queue_state_change(bp, &q_params);
  6610. if (rc) {
  6611. BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
  6612. return rc;
  6613. }
  6614. /* loop through the relevant tx-only indices */
  6615. for (tx_index = FIRST_TX_ONLY_COS_INDEX;
  6616. tx_index < fp->max_cos;
  6617. tx_index++) {
  6618. /* prepare and send tx-only ramrod*/
  6619. rc = bnx2x_setup_tx_only(bp, fp, &q_params,
  6620. tx_only_params, tx_index, leading);
  6621. if (rc) {
  6622. BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
  6623. fp->index, tx_index);
  6624. return rc;
  6625. }
  6626. }
  6627. return rc;
  6628. }
  6629. static int bnx2x_stop_queue(struct bnx2x *bp, int index)
  6630. {
  6631. struct bnx2x_fastpath *fp = &bp->fp[index];
  6632. struct bnx2x_fp_txdata *txdata;
  6633. struct bnx2x_queue_state_params q_params = {NULL};
  6634. int rc, tx_index;
  6635. DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
  6636. q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
  6637. /* We want to wait for completion in this context */
  6638. __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
  6639. /* close tx-only connections */
  6640. for (tx_index = FIRST_TX_ONLY_COS_INDEX;
  6641. tx_index < fp->max_cos;
  6642. tx_index++){
  6643. /* ascertain this is a normal queue*/
  6644. txdata = fp->txdata_ptr[tx_index];
  6645. DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
  6646. txdata->txq_index);
  6647. /* send halt terminate on tx-only connection */
  6648. q_params.cmd = BNX2X_Q_CMD_TERMINATE;
  6649. memset(&q_params.params.terminate, 0,
  6650. sizeof(q_params.params.terminate));
  6651. q_params.params.terminate.cid_index = tx_index;
  6652. rc = bnx2x_queue_state_change(bp, &q_params);
  6653. if (rc)
  6654. return rc;
  6655. /* send halt terminate on tx-only connection */
  6656. q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
  6657. memset(&q_params.params.cfc_del, 0,
  6658. sizeof(q_params.params.cfc_del));
  6659. q_params.params.cfc_del.cid_index = tx_index;
  6660. rc = bnx2x_queue_state_change(bp, &q_params);
  6661. if (rc)
  6662. return rc;
  6663. }
  6664. /* Stop the primary connection: */
  6665. /* ...halt the connection */
  6666. q_params.cmd = BNX2X_Q_CMD_HALT;
  6667. rc = bnx2x_queue_state_change(bp, &q_params);
  6668. if (rc)
  6669. return rc;
  6670. /* ...terminate the connection */
  6671. q_params.cmd = BNX2X_Q_CMD_TERMINATE;
  6672. memset(&q_params.params.terminate, 0,
  6673. sizeof(q_params.params.terminate));
  6674. q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
  6675. rc = bnx2x_queue_state_change(bp, &q_params);
  6676. if (rc)
  6677. return rc;
  6678. /* ...delete cfc entry */
  6679. q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
  6680. memset(&q_params.params.cfc_del, 0,
  6681. sizeof(q_params.params.cfc_del));
  6682. q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
  6683. return bnx2x_queue_state_change(bp, &q_params);
  6684. }
  6685. static void bnx2x_reset_func(struct bnx2x *bp)
  6686. {
  6687. int port = BP_PORT(bp);
  6688. int func = BP_FUNC(bp);
  6689. int i;
  6690. /* Disable the function in the FW */
  6691. REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
  6692. REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
  6693. REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
  6694. REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
  6695. /* FP SBs */
  6696. for_each_eth_queue(bp, i) {
  6697. struct bnx2x_fastpath *fp = &bp->fp[i];
  6698. REG_WR8(bp, BAR_CSTRORM_INTMEM +
  6699. CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
  6700. SB_DISABLED);
  6701. }
  6702. #ifdef BCM_CNIC
  6703. /* CNIC SB */
  6704. REG_WR8(bp, BAR_CSTRORM_INTMEM +
  6705. CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
  6706. SB_DISABLED);
  6707. #endif
  6708. /* SP SB */
  6709. REG_WR8(bp, BAR_CSTRORM_INTMEM +
  6710. CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
  6711. SB_DISABLED);
  6712. for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
  6713. REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
  6714. 0);
  6715. /* Configure IGU */
  6716. if (bp->common.int_block == INT_BLOCK_HC) {
  6717. REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
  6718. REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
  6719. } else {
  6720. REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
  6721. REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
  6722. }
  6723. #ifdef BCM_CNIC
  6724. /* Disable Timer scan */
  6725. REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
  6726. /*
  6727. * Wait for at least 10ms and up to 2 second for the timers scan to
  6728. * complete
  6729. */
  6730. for (i = 0; i < 200; i++) {
  6731. msleep(10);
  6732. if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
  6733. break;
  6734. }
  6735. #endif
  6736. /* Clear ILT */
  6737. bnx2x_clear_func_ilt(bp, func);
  6738. /* Timers workaround bug for E2: if this is vnic-3,
  6739. * we need to set the entire ilt range for this timers.
  6740. */
  6741. if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
  6742. struct ilt_client_info ilt_cli;
  6743. /* use dummy TM client */
  6744. memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
  6745. ilt_cli.start = 0;
  6746. ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
  6747. ilt_cli.client_num = ILT_CLIENT_TM;
  6748. bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
  6749. }
  6750. /* this assumes that reset_port() called before reset_func()*/
  6751. if (!CHIP_IS_E1x(bp))
  6752. bnx2x_pf_disable(bp);
  6753. bp->dmae_ready = 0;
  6754. }
  6755. static void bnx2x_reset_port(struct bnx2x *bp)
  6756. {
  6757. int port = BP_PORT(bp);
  6758. u32 val;
  6759. /* Reset physical Link */
  6760. bnx2x__link_reset(bp);
  6761. REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
  6762. /* Do not rcv packets to BRB */
  6763. REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
  6764. /* Do not direct rcv packets that are not for MCP to the BRB */
  6765. REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
  6766. NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
  6767. /* Configure AEU */
  6768. REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
  6769. msleep(100);
  6770. /* Check for BRB port occupancy */
  6771. val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
  6772. if (val)
  6773. DP(NETIF_MSG_IFDOWN,
  6774. "BRB1 is not empty %d blocks are occupied\n", val);
  6775. /* TODO: Close Doorbell port? */
  6776. }
  6777. static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
  6778. {
  6779. struct bnx2x_func_state_params func_params = {NULL};
  6780. /* Prepare parameters for function state transitions */
  6781. __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
  6782. func_params.f_obj = &bp->func_obj;
  6783. func_params.cmd = BNX2X_F_CMD_HW_RESET;
  6784. func_params.params.hw_init.load_phase = load_code;
  6785. return bnx2x_func_state_change(bp, &func_params);
  6786. }
  6787. static int bnx2x_func_stop(struct bnx2x *bp)
  6788. {
  6789. struct bnx2x_func_state_params func_params = {NULL};
  6790. int rc;
  6791. /* Prepare parameters for function state transitions */
  6792. __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
  6793. func_params.f_obj = &bp->func_obj;
  6794. func_params.cmd = BNX2X_F_CMD_STOP;
  6795. /*
  6796. * Try to stop the function the 'good way'. If fails (in case
  6797. * of a parity error during bnx2x_chip_cleanup()) and we are
  6798. * not in a debug mode, perform a state transaction in order to
  6799. * enable further HW_RESET transaction.
  6800. */
  6801. rc = bnx2x_func_state_change(bp, &func_params);
  6802. if (rc) {
  6803. #ifdef BNX2X_STOP_ON_ERROR
  6804. return rc;
  6805. #else
  6806. BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
  6807. __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
  6808. return bnx2x_func_state_change(bp, &func_params);
  6809. #endif
  6810. }
  6811. return 0;
  6812. }
  6813. /**
  6814. * bnx2x_send_unload_req - request unload mode from the MCP.
  6815. *
  6816. * @bp: driver handle
  6817. * @unload_mode: requested function's unload mode
  6818. *
  6819. * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
  6820. */
  6821. u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
  6822. {
  6823. u32 reset_code = 0;
  6824. int port = BP_PORT(bp);
  6825. /* Select the UNLOAD request mode */
  6826. if (unload_mode == UNLOAD_NORMAL)
  6827. reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
  6828. else if (bp->flags & NO_WOL_FLAG)
  6829. reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
  6830. else if (bp->wol) {
  6831. u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
  6832. u8 *mac_addr = bp->dev->dev_addr;
  6833. u32 val;
  6834. u16 pmc;
  6835. /* The mac address is written to entries 1-4 to
  6836. * preserve entry 0 which is used by the PMF
  6837. */
  6838. u8 entry = (BP_VN(bp) + 1)*8;
  6839. val = (mac_addr[0] << 8) | mac_addr[1];
  6840. EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
  6841. val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
  6842. (mac_addr[4] << 8) | mac_addr[5];
  6843. EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
  6844. /* Enable the PME and clear the status */
  6845. pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
  6846. pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
  6847. pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
  6848. reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
  6849. } else
  6850. reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
  6851. /* Send the request to the MCP */
  6852. if (!BP_NOMCP(bp))
  6853. reset_code = bnx2x_fw_command(bp, reset_code, 0);
  6854. else {
  6855. int path = BP_PATH(bp);
  6856. DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
  6857. path, load_count[path][0], load_count[path][1],
  6858. load_count[path][2]);
  6859. load_count[path][0]--;
  6860. load_count[path][1 + port]--;
  6861. DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
  6862. path, load_count[path][0], load_count[path][1],
  6863. load_count[path][2]);
  6864. if (load_count[path][0] == 0)
  6865. reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
  6866. else if (load_count[path][1 + port] == 0)
  6867. reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
  6868. else
  6869. reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
  6870. }
  6871. return reset_code;
  6872. }
  6873. /**
  6874. * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
  6875. *
  6876. * @bp: driver handle
  6877. * @keep_link: true iff link should be kept up
  6878. */
  6879. void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
  6880. {
  6881. u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
  6882. /* Report UNLOAD_DONE to MCP */
  6883. if (!BP_NOMCP(bp))
  6884. bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
  6885. }
  6886. static int bnx2x_func_wait_started(struct bnx2x *bp)
  6887. {
  6888. int tout = 50;
  6889. int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
  6890. if (!bp->port.pmf)
  6891. return 0;
  6892. /*
  6893. * (assumption: No Attention from MCP at this stage)
  6894. * PMF probably in the middle of TXdisable/enable transaction
  6895. * 1. Sync IRS for default SB
  6896. * 2. Sync SP queue - this guarantes us that attention handling started
  6897. * 3. Wait, that TXdisable/enable transaction completes
  6898. *
  6899. * 1+2 guranty that if DCBx attention was scheduled it already changed
  6900. * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
  6901. * received complettion for the transaction the state is TX_STOPPED.
  6902. * State will return to STARTED after completion of TX_STOPPED-->STARTED
  6903. * transaction.
  6904. */
  6905. /* make sure default SB ISR is done */
  6906. if (msix)
  6907. synchronize_irq(bp->msix_table[0].vector);
  6908. else
  6909. synchronize_irq(bp->pdev->irq);
  6910. flush_workqueue(bnx2x_wq);
  6911. while (bnx2x_func_get_state(bp, &bp->func_obj) !=
  6912. BNX2X_F_STATE_STARTED && tout--)
  6913. msleep(20);
  6914. if (bnx2x_func_get_state(bp, &bp->func_obj) !=
  6915. BNX2X_F_STATE_STARTED) {
  6916. #ifdef BNX2X_STOP_ON_ERROR
  6917. BNX2X_ERR("Wrong function state\n");
  6918. return -EBUSY;
  6919. #else
  6920. /*
  6921. * Failed to complete the transaction in a "good way"
  6922. * Force both transactions with CLR bit
  6923. */
  6924. struct bnx2x_func_state_params func_params = {NULL};
  6925. DP(NETIF_MSG_IFDOWN,
  6926. "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
  6927. func_params.f_obj = &bp->func_obj;
  6928. __set_bit(RAMROD_DRV_CLR_ONLY,
  6929. &func_params.ramrod_flags);
  6930. /* STARTED-->TX_ST0PPED */
  6931. func_params.cmd = BNX2X_F_CMD_TX_STOP;
  6932. bnx2x_func_state_change(bp, &func_params);
  6933. /* TX_ST0PPED-->STARTED */
  6934. func_params.cmd = BNX2X_F_CMD_TX_START;
  6935. return bnx2x_func_state_change(bp, &func_params);
  6936. #endif
  6937. }
  6938. return 0;
  6939. }
  6940. void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
  6941. {
  6942. int port = BP_PORT(bp);
  6943. int i, rc = 0;
  6944. u8 cos;
  6945. struct bnx2x_mcast_ramrod_params rparam = {NULL};
  6946. u32 reset_code;
  6947. /* Wait until tx fastpath tasks complete */
  6948. for_each_tx_queue(bp, i) {
  6949. struct bnx2x_fastpath *fp = &bp->fp[i];
  6950. for_each_cos_in_tx_queue(fp, cos)
  6951. rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
  6952. #ifdef BNX2X_STOP_ON_ERROR
  6953. if (rc)
  6954. return;
  6955. #endif
  6956. }
  6957. /* Give HW time to discard old tx messages */
  6958. usleep_range(1000, 1000);
  6959. /* Clean all ETH MACs */
  6960. rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
  6961. false);
  6962. if (rc < 0)
  6963. BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
  6964. /* Clean up UC list */
  6965. rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
  6966. true);
  6967. if (rc < 0)
  6968. BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
  6969. rc);
  6970. /* Disable LLH */
  6971. if (!CHIP_IS_E1(bp))
  6972. REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
  6973. /* Set "drop all" (stop Rx).
  6974. * We need to take a netif_addr_lock() here in order to prevent
  6975. * a race between the completion code and this code.
  6976. */
  6977. netif_addr_lock_bh(bp->dev);
  6978. /* Schedule the rx_mode command */
  6979. if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
  6980. set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
  6981. else
  6982. bnx2x_set_storm_rx_mode(bp);
  6983. /* Cleanup multicast configuration */
  6984. rparam.mcast_obj = &bp->mcast_obj;
  6985. rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
  6986. if (rc < 0)
  6987. BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
  6988. netif_addr_unlock_bh(bp->dev);
  6989. /*
  6990. * Send the UNLOAD_REQUEST to the MCP. This will return if
  6991. * this function should perform FUNC, PORT or COMMON HW
  6992. * reset.
  6993. */
  6994. reset_code = bnx2x_send_unload_req(bp, unload_mode);
  6995. /*
  6996. * (assumption: No Attention from MCP at this stage)
  6997. * PMF probably in the middle of TXdisable/enable transaction
  6998. */
  6999. rc = bnx2x_func_wait_started(bp);
  7000. if (rc) {
  7001. BNX2X_ERR("bnx2x_func_wait_started failed\n");
  7002. #ifdef BNX2X_STOP_ON_ERROR
  7003. return;
  7004. #endif
  7005. }
  7006. /* Close multi and leading connections
  7007. * Completions for ramrods are collected in a synchronous way
  7008. */
  7009. for_each_queue(bp, i)
  7010. if (bnx2x_stop_queue(bp, i))
  7011. #ifdef BNX2X_STOP_ON_ERROR
  7012. return;
  7013. #else
  7014. goto unload_error;
  7015. #endif
  7016. /* If SP settings didn't get completed so far - something
  7017. * very wrong has happen.
  7018. */
  7019. if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
  7020. BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
  7021. #ifndef BNX2X_STOP_ON_ERROR
  7022. unload_error:
  7023. #endif
  7024. rc = bnx2x_func_stop(bp);
  7025. if (rc) {
  7026. BNX2X_ERR("Function stop failed!\n");
  7027. #ifdef BNX2X_STOP_ON_ERROR
  7028. return;
  7029. #endif
  7030. }
  7031. /* Disable HW interrupts, NAPI */
  7032. bnx2x_netif_stop(bp, 1);
  7033. /* Delete all NAPI objects */
  7034. bnx2x_del_all_napi(bp);
  7035. /* Release IRQs */
  7036. bnx2x_free_irq(bp);
  7037. /* Reset the chip */
  7038. rc = bnx2x_reset_hw(bp, reset_code);
  7039. if (rc)
  7040. BNX2X_ERR("HW_RESET failed\n");
  7041. /* Report UNLOAD_DONE to MCP */
  7042. bnx2x_send_unload_done(bp, keep_link);
  7043. }
  7044. void bnx2x_disable_close_the_gate(struct bnx2x *bp)
  7045. {
  7046. u32 val;
  7047. DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
  7048. if (CHIP_IS_E1(bp)) {
  7049. int port = BP_PORT(bp);
  7050. u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
  7051. MISC_REG_AEU_MASK_ATTN_FUNC_0;
  7052. val = REG_RD(bp, addr);
  7053. val &= ~(0x300);
  7054. REG_WR(bp, addr, val);
  7055. } else {
  7056. val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
  7057. val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
  7058. MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
  7059. REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
  7060. }
  7061. }
  7062. /* Close gates #2, #3 and #4: */
  7063. static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
  7064. {
  7065. u32 val;
  7066. /* Gates #2 and #4a are closed/opened for "not E1" only */
  7067. if (!CHIP_IS_E1(bp)) {
  7068. /* #4 */
  7069. REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
  7070. /* #2 */
  7071. REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
  7072. }
  7073. /* #3 */
  7074. if (CHIP_IS_E1x(bp)) {
  7075. /* Prevent interrupts from HC on both ports */
  7076. val = REG_RD(bp, HC_REG_CONFIG_1);
  7077. REG_WR(bp, HC_REG_CONFIG_1,
  7078. (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
  7079. (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
  7080. val = REG_RD(bp, HC_REG_CONFIG_0);
  7081. REG_WR(bp, HC_REG_CONFIG_0,
  7082. (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
  7083. (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
  7084. } else {
  7085. /* Prevent incomming interrupts in IGU */
  7086. val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
  7087. REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
  7088. (!close) ?
  7089. (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
  7090. (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
  7091. }
  7092. DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
  7093. close ? "closing" : "opening");
  7094. mmiowb();
  7095. }
  7096. #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
  7097. static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
  7098. {
  7099. /* Do some magic... */
  7100. u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
  7101. *magic_val = val & SHARED_MF_CLP_MAGIC;
  7102. MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
  7103. }
  7104. /**
  7105. * bnx2x_clp_reset_done - restore the value of the `magic' bit.
  7106. *
  7107. * @bp: driver handle
  7108. * @magic_val: old value of the `magic' bit.
  7109. */
  7110. static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
  7111. {
  7112. /* Restore the `magic' bit value... */
  7113. u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
  7114. MF_CFG_WR(bp, shared_mf_config.clp_mb,
  7115. (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
  7116. }
  7117. /**
  7118. * bnx2x_reset_mcp_prep - prepare for MCP reset.
  7119. *
  7120. * @bp: driver handle
  7121. * @magic_val: old value of 'magic' bit.
  7122. *
  7123. * Takes care of CLP configurations.
  7124. */
  7125. static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
  7126. {
  7127. u32 shmem;
  7128. u32 validity_offset;
  7129. DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
  7130. /* Set `magic' bit in order to save MF config */
  7131. if (!CHIP_IS_E1(bp))
  7132. bnx2x_clp_reset_prep(bp, magic_val);
  7133. /* Get shmem offset */
  7134. shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
  7135. validity_offset = offsetof(struct shmem_region, validity_map[0]);
  7136. /* Clear validity map flags */
  7137. if (shmem > 0)
  7138. REG_WR(bp, shmem + validity_offset, 0);
  7139. }
  7140. #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
  7141. #define MCP_ONE_TIMEOUT 100 /* 100 ms */
  7142. /**
  7143. * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
  7144. *
  7145. * @bp: driver handle
  7146. */
  7147. static void bnx2x_mcp_wait_one(struct bnx2x *bp)
  7148. {
  7149. /* special handling for emulation and FPGA,
  7150. wait 10 times longer */
  7151. if (CHIP_REV_IS_SLOW(bp))
  7152. msleep(MCP_ONE_TIMEOUT*10);
  7153. else
  7154. msleep(MCP_ONE_TIMEOUT);
  7155. }
  7156. /*
  7157. * initializes bp->common.shmem_base and waits for validity signature to appear
  7158. */
  7159. static int bnx2x_init_shmem(struct bnx2x *bp)
  7160. {
  7161. int cnt = 0;
  7162. u32 val = 0;
  7163. do {
  7164. bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
  7165. if (bp->common.shmem_base) {
  7166. val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
  7167. if (val & SHR_MEM_VALIDITY_MB)
  7168. return 0;
  7169. }
  7170. bnx2x_mcp_wait_one(bp);
  7171. } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
  7172. BNX2X_ERR("BAD MCP validity signature\n");
  7173. return -ENODEV;
  7174. }
  7175. static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
  7176. {
  7177. int rc = bnx2x_init_shmem(bp);
  7178. /* Restore the `magic' bit value */
  7179. if (!CHIP_IS_E1(bp))
  7180. bnx2x_clp_reset_done(bp, magic_val);
  7181. return rc;
  7182. }
  7183. static void bnx2x_pxp_prep(struct bnx2x *bp)
  7184. {
  7185. if (!CHIP_IS_E1(bp)) {
  7186. REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
  7187. REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
  7188. mmiowb();
  7189. }
  7190. }
  7191. /*
  7192. * Reset the whole chip except for:
  7193. * - PCIE core
  7194. * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
  7195. * one reset bit)
  7196. * - IGU
  7197. * - MISC (including AEU)
  7198. * - GRC
  7199. * - RBCN, RBCP
  7200. */
  7201. static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
  7202. {
  7203. u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
  7204. u32 global_bits2, stay_reset2;
  7205. /*
  7206. * Bits that have to be set in reset_mask2 if we want to reset 'global'
  7207. * (per chip) blocks.
  7208. */
  7209. global_bits2 =
  7210. MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
  7211. MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
  7212. /* Don't reset the following blocks */
  7213. not_reset_mask1 =
  7214. MISC_REGISTERS_RESET_REG_1_RST_HC |
  7215. MISC_REGISTERS_RESET_REG_1_RST_PXPV |
  7216. MISC_REGISTERS_RESET_REG_1_RST_PXP;
  7217. not_reset_mask2 =
  7218. MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
  7219. MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
  7220. MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
  7221. MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
  7222. MISC_REGISTERS_RESET_REG_2_RST_RBCN |
  7223. MISC_REGISTERS_RESET_REG_2_RST_GRC |
  7224. MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
  7225. MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
  7226. MISC_REGISTERS_RESET_REG_2_RST_ATC |
  7227. MISC_REGISTERS_RESET_REG_2_PGLC;
  7228. /*
  7229. * Keep the following blocks in reset:
  7230. * - all xxMACs are handled by the bnx2x_link code.
  7231. */
  7232. stay_reset2 =
  7233. MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
  7234. MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
  7235. MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
  7236. MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
  7237. MISC_REGISTERS_RESET_REG_2_UMAC0 |
  7238. MISC_REGISTERS_RESET_REG_2_UMAC1 |
  7239. MISC_REGISTERS_RESET_REG_2_XMAC |
  7240. MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
  7241. /* Full reset masks according to the chip */
  7242. reset_mask1 = 0xffffffff;
  7243. if (CHIP_IS_E1(bp))
  7244. reset_mask2 = 0xffff;
  7245. else if (CHIP_IS_E1H(bp))
  7246. reset_mask2 = 0x1ffff;
  7247. else if (CHIP_IS_E2(bp))
  7248. reset_mask2 = 0xfffff;
  7249. else /* CHIP_IS_E3 */
  7250. reset_mask2 = 0x3ffffff;
  7251. /* Don't reset global blocks unless we need to */
  7252. if (!global)
  7253. reset_mask2 &= ~global_bits2;
  7254. /*
  7255. * In case of attention in the QM, we need to reset PXP
  7256. * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
  7257. * because otherwise QM reset would release 'close the gates' shortly
  7258. * before resetting the PXP, then the PSWRQ would send a write
  7259. * request to PGLUE. Then when PXP is reset, PGLUE would try to
  7260. * read the payload data from PSWWR, but PSWWR would not
  7261. * respond. The write queue in PGLUE would stuck, dmae commands
  7262. * would not return. Therefore it's important to reset the second
  7263. * reset register (containing the
  7264. * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
  7265. * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
  7266. * bit).
  7267. */
  7268. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
  7269. reset_mask2 & (~not_reset_mask2));
  7270. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
  7271. reset_mask1 & (~not_reset_mask1));
  7272. barrier();
  7273. mmiowb();
  7274. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
  7275. reset_mask2 & (~stay_reset2));
  7276. barrier();
  7277. mmiowb();
  7278. REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
  7279. mmiowb();
  7280. }
  7281. /**
  7282. * bnx2x_er_poll_igu_vq - poll for pending writes bit.
  7283. * It should get cleared in no more than 1s.
  7284. *
  7285. * @bp: driver handle
  7286. *
  7287. * It should get cleared in no more than 1s. Returns 0 if
  7288. * pending writes bit gets cleared.
  7289. */
  7290. static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
  7291. {
  7292. u32 cnt = 1000;
  7293. u32 pend_bits = 0;
  7294. do {
  7295. pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
  7296. if (pend_bits == 0)
  7297. break;
  7298. usleep_range(1000, 1000);
  7299. } while (cnt-- > 0);
  7300. if (cnt <= 0) {
  7301. BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
  7302. pend_bits);
  7303. return -EBUSY;
  7304. }
  7305. return 0;
  7306. }
  7307. static int bnx2x_process_kill(struct bnx2x *bp, bool global)
  7308. {
  7309. int cnt = 1000;
  7310. u32 val = 0;
  7311. u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
  7312. /* Empty the Tetris buffer, wait for 1s */
  7313. do {
  7314. sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
  7315. blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
  7316. port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
  7317. port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
  7318. pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
  7319. if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
  7320. ((port_is_idle_0 & 0x1) == 0x1) &&
  7321. ((port_is_idle_1 & 0x1) == 0x1) &&
  7322. (pgl_exp_rom2 == 0xffffffff))
  7323. break;
  7324. usleep_range(1000, 1000);
  7325. } while (cnt-- > 0);
  7326. if (cnt <= 0) {
  7327. BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
  7328. BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
  7329. sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
  7330. pgl_exp_rom2);
  7331. return -EAGAIN;
  7332. }
  7333. barrier();
  7334. /* Close gates #2, #3 and #4 */
  7335. bnx2x_set_234_gates(bp, true);
  7336. /* Poll for IGU VQs for 57712 and newer chips */
  7337. if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
  7338. return -EAGAIN;
  7339. /* TBD: Indicate that "process kill" is in progress to MCP */
  7340. /* Clear "unprepared" bit */
  7341. REG_WR(bp, MISC_REG_UNPREPARED, 0);
  7342. barrier();
  7343. /* Make sure all is written to the chip before the reset */
  7344. mmiowb();
  7345. /* Wait for 1ms to empty GLUE and PCI-E core queues,
  7346. * PSWHST, GRC and PSWRD Tetris buffer.
  7347. */
  7348. usleep_range(1000, 1000);
  7349. /* Prepare to chip reset: */
  7350. /* MCP */
  7351. if (global)
  7352. bnx2x_reset_mcp_prep(bp, &val);
  7353. /* PXP */
  7354. bnx2x_pxp_prep(bp);
  7355. barrier();
  7356. /* reset the chip */
  7357. bnx2x_process_kill_chip_reset(bp, global);
  7358. barrier();
  7359. /* Recover after reset: */
  7360. /* MCP */
  7361. if (global && bnx2x_reset_mcp_comp(bp, val))
  7362. return -EAGAIN;
  7363. /* TBD: Add resetting the NO_MCP mode DB here */
  7364. /* PXP */
  7365. bnx2x_pxp_prep(bp);
  7366. /* Open the gates #2, #3 and #4 */
  7367. bnx2x_set_234_gates(bp, false);
  7368. /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
  7369. * reset state, re-enable attentions. */
  7370. return 0;
  7371. }
  7372. int bnx2x_leader_reset(struct bnx2x *bp)
  7373. {
  7374. int rc = 0;
  7375. bool global = bnx2x_reset_is_global(bp);
  7376. u32 load_code;
  7377. /* if not going to reset MCP - load "fake" driver to reset HW while
  7378. * driver is owner of the HW
  7379. */
  7380. if (!global && !BP_NOMCP(bp)) {
  7381. load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
  7382. DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
  7383. if (!load_code) {
  7384. BNX2X_ERR("MCP response failure, aborting\n");
  7385. rc = -EAGAIN;
  7386. goto exit_leader_reset;
  7387. }
  7388. if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
  7389. (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
  7390. BNX2X_ERR("MCP unexpected resp, aborting\n");
  7391. rc = -EAGAIN;
  7392. goto exit_leader_reset2;
  7393. }
  7394. load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
  7395. if (!load_code) {
  7396. BNX2X_ERR("MCP response failure, aborting\n");
  7397. rc = -EAGAIN;
  7398. goto exit_leader_reset2;
  7399. }
  7400. }
  7401. /* Try to recover after the failure */
  7402. if (bnx2x_process_kill(bp, global)) {
  7403. BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
  7404. BP_PATH(bp));
  7405. rc = -EAGAIN;
  7406. goto exit_leader_reset2;
  7407. }
  7408. /*
  7409. * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
  7410. * state.
  7411. */
  7412. bnx2x_set_reset_done(bp);
  7413. if (global)
  7414. bnx2x_clear_reset_global(bp);
  7415. exit_leader_reset2:
  7416. /* unload "fake driver" if it was loaded */
  7417. if (!global && !BP_NOMCP(bp)) {
  7418. bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
  7419. bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
  7420. }
  7421. exit_leader_reset:
  7422. bp->is_leader = 0;
  7423. bnx2x_release_leader_lock(bp);
  7424. smp_mb();
  7425. return rc;
  7426. }
  7427. static void bnx2x_recovery_failed(struct bnx2x *bp)
  7428. {
  7429. netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
  7430. /* Disconnect this device */
  7431. netif_device_detach(bp->dev);
  7432. /*
  7433. * Block ifup for all function on this engine until "process kill"
  7434. * or power cycle.
  7435. */
  7436. bnx2x_set_reset_in_progress(bp);
  7437. /* Shut down the power */
  7438. bnx2x_set_power_state(bp, PCI_D3hot);
  7439. bp->recovery_state = BNX2X_RECOVERY_FAILED;
  7440. smp_mb();
  7441. }
  7442. /*
  7443. * Assumption: runs under rtnl lock. This together with the fact
  7444. * that it's called only from bnx2x_sp_rtnl() ensure that it
  7445. * will never be called when netif_running(bp->dev) is false.
  7446. */
  7447. static void bnx2x_parity_recover(struct bnx2x *bp)
  7448. {
  7449. bool global = false;
  7450. u32 error_recovered, error_unrecovered;
  7451. bool is_parity;
  7452. DP(NETIF_MSG_HW, "Handling parity\n");
  7453. while (1) {
  7454. switch (bp->recovery_state) {
  7455. case BNX2X_RECOVERY_INIT:
  7456. DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
  7457. is_parity = bnx2x_chk_parity_attn(bp, &global, false);
  7458. WARN_ON(!is_parity);
  7459. /* Try to get a LEADER_LOCK HW lock */
  7460. if (bnx2x_trylock_leader_lock(bp)) {
  7461. bnx2x_set_reset_in_progress(bp);
  7462. /*
  7463. * Check if there is a global attention and if
  7464. * there was a global attention, set the global
  7465. * reset bit.
  7466. */
  7467. if (global)
  7468. bnx2x_set_reset_global(bp);
  7469. bp->is_leader = 1;
  7470. }
  7471. /* Stop the driver */
  7472. /* If interface has been removed - break */
  7473. if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
  7474. return;
  7475. bp->recovery_state = BNX2X_RECOVERY_WAIT;
  7476. /* Ensure "is_leader", MCP command sequence and
  7477. * "recovery_state" update values are seen on other
  7478. * CPUs.
  7479. */
  7480. smp_mb();
  7481. break;
  7482. case BNX2X_RECOVERY_WAIT:
  7483. DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
  7484. if (bp->is_leader) {
  7485. int other_engine = BP_PATH(bp) ? 0 : 1;
  7486. bool other_load_status =
  7487. bnx2x_get_load_status(bp, other_engine);
  7488. bool load_status =
  7489. bnx2x_get_load_status(bp, BP_PATH(bp));
  7490. global = bnx2x_reset_is_global(bp);
  7491. /*
  7492. * In case of a parity in a global block, let
  7493. * the first leader that performs a
  7494. * leader_reset() reset the global blocks in
  7495. * order to clear global attentions. Otherwise
  7496. * the the gates will remain closed for that
  7497. * engine.
  7498. */
  7499. if (load_status ||
  7500. (global && other_load_status)) {
  7501. /* Wait until all other functions get
  7502. * down.
  7503. */
  7504. schedule_delayed_work(&bp->sp_rtnl_task,
  7505. HZ/10);
  7506. return;
  7507. } else {
  7508. /* If all other functions got down -
  7509. * try to bring the chip back to
  7510. * normal. In any case it's an exit
  7511. * point for a leader.
  7512. */
  7513. if (bnx2x_leader_reset(bp)) {
  7514. bnx2x_recovery_failed(bp);
  7515. return;
  7516. }
  7517. /* If we are here, means that the
  7518. * leader has succeeded and doesn't
  7519. * want to be a leader any more. Try
  7520. * to continue as a none-leader.
  7521. */
  7522. break;
  7523. }
  7524. } else { /* non-leader */
  7525. if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
  7526. /* Try to get a LEADER_LOCK HW lock as
  7527. * long as a former leader may have
  7528. * been unloaded by the user or
  7529. * released a leadership by another
  7530. * reason.
  7531. */
  7532. if (bnx2x_trylock_leader_lock(bp)) {
  7533. /* I'm a leader now! Restart a
  7534. * switch case.
  7535. */
  7536. bp->is_leader = 1;
  7537. break;
  7538. }
  7539. schedule_delayed_work(&bp->sp_rtnl_task,
  7540. HZ/10);
  7541. return;
  7542. } else {
  7543. /*
  7544. * If there was a global attention, wait
  7545. * for it to be cleared.
  7546. */
  7547. if (bnx2x_reset_is_global(bp)) {
  7548. schedule_delayed_work(
  7549. &bp->sp_rtnl_task,
  7550. HZ/10);
  7551. return;
  7552. }
  7553. error_recovered =
  7554. bp->eth_stats.recoverable_error;
  7555. error_unrecovered =
  7556. bp->eth_stats.unrecoverable_error;
  7557. bp->recovery_state =
  7558. BNX2X_RECOVERY_NIC_LOADING;
  7559. if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
  7560. error_unrecovered++;
  7561. netdev_err(bp->dev,
  7562. "Recovery failed. Power cycle needed\n");
  7563. /* Disconnect this device */
  7564. netif_device_detach(bp->dev);
  7565. /* Shut down the power */
  7566. bnx2x_set_power_state(
  7567. bp, PCI_D3hot);
  7568. smp_mb();
  7569. } else {
  7570. bp->recovery_state =
  7571. BNX2X_RECOVERY_DONE;
  7572. error_recovered++;
  7573. smp_mb();
  7574. }
  7575. bp->eth_stats.recoverable_error =
  7576. error_recovered;
  7577. bp->eth_stats.unrecoverable_error =
  7578. error_unrecovered;
  7579. return;
  7580. }
  7581. }
  7582. default:
  7583. return;
  7584. }
  7585. }
  7586. }
  7587. static int bnx2x_close(struct net_device *dev);
  7588. /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
  7589. * scheduled on a general queue in order to prevent a dead lock.
  7590. */
  7591. static void bnx2x_sp_rtnl_task(struct work_struct *work)
  7592. {
  7593. struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
  7594. rtnl_lock();
  7595. if (!netif_running(bp->dev))
  7596. goto sp_rtnl_exit;
  7597. /* if stop on error is defined no recovery flows should be executed */
  7598. #ifdef BNX2X_STOP_ON_ERROR
  7599. BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
  7600. "you will need to reboot when done\n");
  7601. goto sp_rtnl_not_reset;
  7602. #endif
  7603. if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
  7604. /*
  7605. * Clear all pending SP commands as we are going to reset the
  7606. * function anyway.
  7607. */
  7608. bp->sp_rtnl_state = 0;
  7609. smp_mb();
  7610. bnx2x_parity_recover(bp);
  7611. goto sp_rtnl_exit;
  7612. }
  7613. if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
  7614. /*
  7615. * Clear all pending SP commands as we are going to reset the
  7616. * function anyway.
  7617. */
  7618. bp->sp_rtnl_state = 0;
  7619. smp_mb();
  7620. bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
  7621. bnx2x_nic_load(bp, LOAD_NORMAL);
  7622. goto sp_rtnl_exit;
  7623. }
  7624. #ifdef BNX2X_STOP_ON_ERROR
  7625. sp_rtnl_not_reset:
  7626. #endif
  7627. if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
  7628. bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
  7629. if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
  7630. bnx2x_after_function_update(bp);
  7631. /*
  7632. * in case of fan failure we need to reset id if the "stop on error"
  7633. * debug flag is set, since we trying to prevent permanent overheating
  7634. * damage
  7635. */
  7636. if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
  7637. DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
  7638. netif_device_detach(bp->dev);
  7639. bnx2x_close(bp->dev);
  7640. }
  7641. sp_rtnl_exit:
  7642. rtnl_unlock();
  7643. }
  7644. /* end of nic load/unload */
  7645. static void bnx2x_period_task(struct work_struct *work)
  7646. {
  7647. struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
  7648. if (!netif_running(bp->dev))
  7649. goto period_task_exit;
  7650. if (CHIP_REV_IS_SLOW(bp)) {
  7651. BNX2X_ERR("period task called on emulation, ignoring\n");
  7652. goto period_task_exit;
  7653. }
  7654. bnx2x_acquire_phy_lock(bp);
  7655. /*
  7656. * The barrier is needed to ensure the ordering between the writing to
  7657. * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
  7658. * the reading here.
  7659. */
  7660. smp_mb();
  7661. if (bp->port.pmf) {
  7662. bnx2x_period_func(&bp->link_params, &bp->link_vars);
  7663. /* Re-queue task in 1 sec */
  7664. queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
  7665. }
  7666. bnx2x_release_phy_lock(bp);
  7667. period_task_exit:
  7668. return;
  7669. }
  7670. /*
  7671. * Init service functions
  7672. */
  7673. static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
  7674. {
  7675. u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
  7676. u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
  7677. return base + (BP_ABS_FUNC(bp)) * stride;
  7678. }
  7679. static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
  7680. {
  7681. u32 reg = bnx2x_get_pretend_reg(bp);
  7682. /* Flush all outstanding writes */
  7683. mmiowb();
  7684. /* Pretend to be function 0 */
  7685. REG_WR(bp, reg, 0);
  7686. REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
  7687. /* From now we are in the "like-E1" mode */
  7688. bnx2x_int_disable(bp);
  7689. /* Flush all outstanding writes */
  7690. mmiowb();
  7691. /* Restore the original function */
  7692. REG_WR(bp, reg, BP_ABS_FUNC(bp));
  7693. REG_RD(bp, reg);
  7694. }
  7695. static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
  7696. {
  7697. if (CHIP_IS_E1(bp))
  7698. bnx2x_int_disable(bp);
  7699. else
  7700. bnx2x_undi_int_disable_e1h(bp);
  7701. }
  7702. static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
  7703. {
  7704. u32 val, base_addr, offset, mask, reset_reg;
  7705. bool mac_stopped = false;
  7706. u8 port = BP_PORT(bp);
  7707. reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
  7708. if (!CHIP_IS_E3(bp)) {
  7709. val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
  7710. mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
  7711. if ((mask & reset_reg) && val) {
  7712. u32 wb_data[2];
  7713. BNX2X_DEV_INFO("Disable bmac Rx\n");
  7714. base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
  7715. : NIG_REG_INGRESS_BMAC0_MEM;
  7716. offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
  7717. : BIGMAC_REGISTER_BMAC_CONTROL;
  7718. /*
  7719. * use rd/wr since we cannot use dmae. This is safe
  7720. * since MCP won't access the bus due to the request
  7721. * to unload, and no function on the path can be
  7722. * loaded at this time.
  7723. */
  7724. wb_data[0] = REG_RD(bp, base_addr + offset);
  7725. wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
  7726. wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
  7727. REG_WR(bp, base_addr + offset, wb_data[0]);
  7728. REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
  7729. }
  7730. BNX2X_DEV_INFO("Disable emac Rx\n");
  7731. REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
  7732. mac_stopped = true;
  7733. } else {
  7734. if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
  7735. BNX2X_DEV_INFO("Disable xmac Rx\n");
  7736. base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
  7737. val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
  7738. REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
  7739. val & ~(1 << 1));
  7740. REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
  7741. val | (1 << 1));
  7742. REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
  7743. mac_stopped = true;
  7744. }
  7745. mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
  7746. if (mask & reset_reg) {
  7747. BNX2X_DEV_INFO("Disable umac Rx\n");
  7748. base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
  7749. REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
  7750. mac_stopped = true;
  7751. }
  7752. }
  7753. if (mac_stopped)
  7754. msleep(20);
  7755. }
  7756. #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
  7757. #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
  7758. #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
  7759. #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
  7760. static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
  7761. u8 inc)
  7762. {
  7763. u16 rcq, bd;
  7764. u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
  7765. rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
  7766. bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
  7767. tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
  7768. REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
  7769. BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
  7770. port, bd, rcq);
  7771. }
  7772. static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
  7773. {
  7774. u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
  7775. DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
  7776. if (!rc) {
  7777. BNX2X_ERR("MCP response failure, aborting\n");
  7778. return -EBUSY;
  7779. }
  7780. return 0;
  7781. }
  7782. static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
  7783. {
  7784. struct bnx2x_prev_path_list *tmp_list;
  7785. int rc = false;
  7786. if (down_trylock(&bnx2x_prev_sem))
  7787. return false;
  7788. list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
  7789. if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
  7790. bp->pdev->bus->number == tmp_list->bus &&
  7791. BP_PATH(bp) == tmp_list->path) {
  7792. rc = true;
  7793. BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
  7794. BP_PATH(bp));
  7795. break;
  7796. }
  7797. }
  7798. up(&bnx2x_prev_sem);
  7799. return rc;
  7800. }
  7801. static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
  7802. {
  7803. struct bnx2x_prev_path_list *tmp_list;
  7804. int rc;
  7805. tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
  7806. if (!tmp_list) {
  7807. BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
  7808. return -ENOMEM;
  7809. }
  7810. tmp_list->bus = bp->pdev->bus->number;
  7811. tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
  7812. tmp_list->path = BP_PATH(bp);
  7813. rc = down_interruptible(&bnx2x_prev_sem);
  7814. if (rc) {
  7815. BNX2X_ERR("Received %d when tried to take lock\n", rc);
  7816. kfree(tmp_list);
  7817. } else {
  7818. BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
  7819. BP_PATH(bp));
  7820. list_add(&tmp_list->list, &bnx2x_prev_list);
  7821. up(&bnx2x_prev_sem);
  7822. }
  7823. return rc;
  7824. }
  7825. static int __devinit bnx2x_do_flr(struct bnx2x *bp)
  7826. {
  7827. int i;
  7828. u16 status;
  7829. struct pci_dev *dev = bp->pdev;
  7830. if (CHIP_IS_E1x(bp)) {
  7831. BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
  7832. return -EINVAL;
  7833. }
  7834. /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
  7835. if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
  7836. BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
  7837. bp->common.bc_ver);
  7838. return -EINVAL;
  7839. }
  7840. /* Wait for Transaction Pending bit clean */
  7841. for (i = 0; i < 4; i++) {
  7842. if (i)
  7843. msleep((1 << (i - 1)) * 100);
  7844. pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
  7845. if (!(status & PCI_EXP_DEVSTA_TRPND))
  7846. goto clear;
  7847. }
  7848. dev_err(&dev->dev,
  7849. "transaction is not cleared; proceeding with reset anyway\n");
  7850. clear:
  7851. BNX2X_DEV_INFO("Initiating FLR\n");
  7852. bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
  7853. return 0;
  7854. }
  7855. static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
  7856. {
  7857. int rc;
  7858. BNX2X_DEV_INFO("Uncommon unload Flow\n");
  7859. /* Test if previous unload process was already finished for this path */
  7860. if (bnx2x_prev_is_path_marked(bp))
  7861. return bnx2x_prev_mcp_done(bp);
  7862. /* If function has FLR capabilities, and existing FW version matches
  7863. * the one required, then FLR will be sufficient to clean any residue
  7864. * left by previous driver
  7865. */
  7866. rc = bnx2x_test_firmware_version(bp, false);
  7867. if (!rc) {
  7868. /* fw version is good */
  7869. BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
  7870. rc = bnx2x_do_flr(bp);
  7871. }
  7872. if (!rc) {
  7873. /* FLR was performed */
  7874. BNX2X_DEV_INFO("FLR successful\n");
  7875. return 0;
  7876. }
  7877. BNX2X_DEV_INFO("Could not FLR\n");
  7878. /* Close the MCP request, return failure*/
  7879. rc = bnx2x_prev_mcp_done(bp);
  7880. if (!rc)
  7881. rc = BNX2X_PREV_WAIT_NEEDED;
  7882. return rc;
  7883. }
  7884. static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
  7885. {
  7886. u32 reset_reg, tmp_reg = 0, rc;
  7887. /* It is possible a previous function received 'common' answer,
  7888. * but hasn't loaded yet, therefore creating a scenario of
  7889. * multiple functions receiving 'common' on the same path.
  7890. */
  7891. BNX2X_DEV_INFO("Common unload Flow\n");
  7892. if (bnx2x_prev_is_path_marked(bp))
  7893. return bnx2x_prev_mcp_done(bp);
  7894. reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
  7895. /* Reset should be performed after BRB is emptied */
  7896. if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
  7897. u32 timer_count = 1000;
  7898. bool prev_undi = false;
  7899. /* Close the MAC Rx to prevent BRB from filling up */
  7900. bnx2x_prev_unload_close_mac(bp);
  7901. /* Check if the UNDI driver was previously loaded
  7902. * UNDI driver initializes CID offset for normal bell to 0x7
  7903. */
  7904. reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
  7905. if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
  7906. tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
  7907. if (tmp_reg == 0x7) {
  7908. BNX2X_DEV_INFO("UNDI previously loaded\n");
  7909. prev_undi = true;
  7910. /* clear the UNDI indication */
  7911. REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
  7912. }
  7913. }
  7914. /* wait until BRB is empty */
  7915. tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
  7916. while (timer_count) {
  7917. u32 prev_brb = tmp_reg;
  7918. tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
  7919. if (!tmp_reg)
  7920. break;
  7921. BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
  7922. /* reset timer as long as BRB actually gets emptied */
  7923. if (prev_brb > tmp_reg)
  7924. timer_count = 1000;
  7925. else
  7926. timer_count--;
  7927. /* If UNDI resides in memory, manually increment it */
  7928. if (prev_undi)
  7929. bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
  7930. udelay(10);
  7931. }
  7932. if (!timer_count)
  7933. BNX2X_ERR("Failed to empty BRB, hope for the best\n");
  7934. }
  7935. /* No packets are in the pipeline, path is ready for reset */
  7936. bnx2x_reset_common(bp);
  7937. rc = bnx2x_prev_mark_path(bp);
  7938. if (rc) {
  7939. bnx2x_prev_mcp_done(bp);
  7940. return rc;
  7941. }
  7942. return bnx2x_prev_mcp_done(bp);
  7943. }
  7944. /* previous driver DMAE transaction may have occurred when pre-boot stage ended
  7945. * and boot began, or when kdump kernel was loaded. Either case would invalidate
  7946. * the addresses of the transaction, resulting in was-error bit set in the pci
  7947. * causing all hw-to-host pcie transactions to timeout. If this happened we want
  7948. * to clear the interrupt which detected this from the pglueb and the was done
  7949. * bit
  7950. */
  7951. static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
  7952. {
  7953. if (!CHIP_IS_E1x(bp)) {
  7954. u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
  7955. if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
  7956. BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
  7957. REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
  7958. 1 << BP_FUNC(bp));
  7959. }
  7960. }
  7961. }
  7962. static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
  7963. {
  7964. int time_counter = 10;
  7965. u32 rc, fw, hw_lock_reg, hw_lock_val;
  7966. BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
  7967. /* clear hw from errors which may have resulted from an interrupted
  7968. * dmae transaction.
  7969. */
  7970. bnx2x_prev_interrupted_dmae(bp);
  7971. /* Release previously held locks */
  7972. hw_lock_reg = (BP_FUNC(bp) <= 5) ?
  7973. (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
  7974. (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
  7975. hw_lock_val = (REG_RD(bp, hw_lock_reg));
  7976. if (hw_lock_val) {
  7977. if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
  7978. BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
  7979. REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
  7980. (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
  7981. }
  7982. BNX2X_DEV_INFO("Release Previously held hw lock\n");
  7983. REG_WR(bp, hw_lock_reg, 0xffffffff);
  7984. } else
  7985. BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
  7986. if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
  7987. BNX2X_DEV_INFO("Release previously held alr\n");
  7988. REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
  7989. }
  7990. do {
  7991. /* Lock MCP using an unload request */
  7992. fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
  7993. if (!fw) {
  7994. BNX2X_ERR("MCP response failure, aborting\n");
  7995. rc = -EBUSY;
  7996. break;
  7997. }
  7998. if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
  7999. rc = bnx2x_prev_unload_common(bp);
  8000. break;
  8001. }
  8002. /* non-common reply from MCP night require looping */
  8003. rc = bnx2x_prev_unload_uncommon(bp);
  8004. if (rc != BNX2X_PREV_WAIT_NEEDED)
  8005. break;
  8006. msleep(20);
  8007. } while (--time_counter);
  8008. if (!time_counter || rc) {
  8009. BNX2X_ERR("Failed unloading previous driver, aborting\n");
  8010. rc = -EBUSY;
  8011. }
  8012. BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
  8013. return rc;
  8014. }
  8015. static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
  8016. {
  8017. u32 val, val2, val3, val4, id, boot_mode;
  8018. u16 pmc;
  8019. /* Get the chip revision id and number. */
  8020. /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
  8021. val = REG_RD(bp, MISC_REG_CHIP_NUM);
  8022. id = ((val & 0xffff) << 16);
  8023. val = REG_RD(bp, MISC_REG_CHIP_REV);
  8024. id |= ((val & 0xf) << 12);
  8025. val = REG_RD(bp, MISC_REG_CHIP_METAL);
  8026. id |= ((val & 0xff) << 4);
  8027. val = REG_RD(bp, MISC_REG_BOND_ID);
  8028. id |= (val & 0xf);
  8029. bp->common.chip_id = id;
  8030. /* force 57811 according to MISC register */
  8031. if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
  8032. if (CHIP_IS_57810(bp))
  8033. bp->common.chip_id = (CHIP_NUM_57811 << 16) |
  8034. (bp->common.chip_id & 0x0000FFFF);
  8035. else if (CHIP_IS_57810_MF(bp))
  8036. bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
  8037. (bp->common.chip_id & 0x0000FFFF);
  8038. bp->common.chip_id |= 0x1;
  8039. }
  8040. /* Set doorbell size */
  8041. bp->db_size = (1 << BNX2X_DB_SHIFT);
  8042. if (!CHIP_IS_E1x(bp)) {
  8043. val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
  8044. if ((val & 1) == 0)
  8045. val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
  8046. else
  8047. val = (val >> 1) & 1;
  8048. BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
  8049. "2_PORT_MODE");
  8050. bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
  8051. CHIP_2_PORT_MODE;
  8052. if (CHIP_MODE_IS_4_PORT(bp))
  8053. bp->pfid = (bp->pf_num >> 1); /* 0..3 */
  8054. else
  8055. bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
  8056. } else {
  8057. bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
  8058. bp->pfid = bp->pf_num; /* 0..7 */
  8059. }
  8060. BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
  8061. bp->link_params.chip_id = bp->common.chip_id;
  8062. BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
  8063. val = (REG_RD(bp, 0x2874) & 0x55);
  8064. if ((bp->common.chip_id & 0x1) ||
  8065. (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
  8066. bp->flags |= ONE_PORT_FLAG;
  8067. BNX2X_DEV_INFO("single port device\n");
  8068. }
  8069. val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
  8070. bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
  8071. (val & MCPR_NVM_CFG4_FLASH_SIZE));
  8072. BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
  8073. bp->common.flash_size, bp->common.flash_size);
  8074. bnx2x_init_shmem(bp);
  8075. bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
  8076. MISC_REG_GENERIC_CR_1 :
  8077. MISC_REG_GENERIC_CR_0));
  8078. bp->link_params.shmem_base = bp->common.shmem_base;
  8079. bp->link_params.shmem2_base = bp->common.shmem2_base;
  8080. BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
  8081. bp->common.shmem_base, bp->common.shmem2_base);
  8082. if (!bp->common.shmem_base) {
  8083. BNX2X_DEV_INFO("MCP not active\n");
  8084. bp->flags |= NO_MCP_FLAG;
  8085. return;
  8086. }
  8087. bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
  8088. BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
  8089. bp->link_params.hw_led_mode = ((bp->common.hw_config &
  8090. SHARED_HW_CFG_LED_MODE_MASK) >>
  8091. SHARED_HW_CFG_LED_MODE_SHIFT);
  8092. bp->link_params.feature_config_flags = 0;
  8093. val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
  8094. if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
  8095. bp->link_params.feature_config_flags |=
  8096. FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
  8097. else
  8098. bp->link_params.feature_config_flags &=
  8099. ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
  8100. val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
  8101. bp->common.bc_ver = val;
  8102. BNX2X_DEV_INFO("bc_ver %X\n", val);
  8103. if (val < BNX2X_BC_VER) {
  8104. /* for now only warn
  8105. * later we might need to enforce this */
  8106. BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
  8107. BNX2X_BC_VER, val);
  8108. }
  8109. bp->link_params.feature_config_flags |=
  8110. (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
  8111. FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
  8112. bp->link_params.feature_config_flags |=
  8113. (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
  8114. FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
  8115. bp->link_params.feature_config_flags |=
  8116. (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
  8117. FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
  8118. bp->link_params.feature_config_flags |=
  8119. (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
  8120. FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
  8121. bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
  8122. BC_SUPPORTS_PFC_STATS : 0;
  8123. bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
  8124. BC_SUPPORTS_FCOE_FEATURES : 0;
  8125. bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
  8126. BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
  8127. boot_mode = SHMEM_RD(bp,
  8128. dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
  8129. PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
  8130. switch (boot_mode) {
  8131. case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
  8132. bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
  8133. break;
  8134. case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
  8135. bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
  8136. break;
  8137. case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
  8138. bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
  8139. break;
  8140. case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
  8141. bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
  8142. break;
  8143. }
  8144. pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
  8145. bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
  8146. BNX2X_DEV_INFO("%sWoL capable\n",
  8147. (bp->flags & NO_WOL_FLAG) ? "not " : "");
  8148. val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
  8149. val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
  8150. val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
  8151. val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
  8152. dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
  8153. val, val2, val3, val4);
  8154. }
  8155. #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
  8156. #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
  8157. static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
  8158. {
  8159. int pfid = BP_FUNC(bp);
  8160. int igu_sb_id;
  8161. u32 val;
  8162. u8 fid, igu_sb_cnt = 0;
  8163. bp->igu_base_sb = 0xff;
  8164. if (CHIP_INT_MODE_IS_BC(bp)) {
  8165. int vn = BP_VN(bp);
  8166. igu_sb_cnt = bp->igu_sb_cnt;
  8167. bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
  8168. FP_SB_MAX_E1x;
  8169. bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
  8170. (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
  8171. return;
  8172. }
  8173. /* IGU in normal mode - read CAM */
  8174. for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
  8175. igu_sb_id++) {
  8176. val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
  8177. if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
  8178. continue;
  8179. fid = IGU_FID(val);
  8180. if ((fid & IGU_FID_ENCODE_IS_PF)) {
  8181. if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
  8182. continue;
  8183. if (IGU_VEC(val) == 0)
  8184. /* default status block */
  8185. bp->igu_dsb_id = igu_sb_id;
  8186. else {
  8187. if (bp->igu_base_sb == 0xff)
  8188. bp->igu_base_sb = igu_sb_id;
  8189. igu_sb_cnt++;
  8190. }
  8191. }
  8192. }
  8193. #ifdef CONFIG_PCI_MSI
  8194. /* Due to new PF resource allocation by MFW T7.4 and above, it's
  8195. * optional that number of CAM entries will not be equal to the value
  8196. * advertised in PCI.
  8197. * Driver should use the minimal value of both as the actual status
  8198. * block count
  8199. */
  8200. bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
  8201. #endif
  8202. if (igu_sb_cnt == 0)
  8203. BNX2X_ERR("CAM configuration error\n");
  8204. }
  8205. static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
  8206. u32 switch_cfg)
  8207. {
  8208. int cfg_size = 0, idx, port = BP_PORT(bp);
  8209. /* Aggregation of supported attributes of all external phys */
  8210. bp->port.supported[0] = 0;
  8211. bp->port.supported[1] = 0;
  8212. switch (bp->link_params.num_phys) {
  8213. case 1:
  8214. bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
  8215. cfg_size = 1;
  8216. break;
  8217. case 2:
  8218. bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
  8219. cfg_size = 1;
  8220. break;
  8221. case 3:
  8222. if (bp->link_params.multi_phy_config &
  8223. PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
  8224. bp->port.supported[1] =
  8225. bp->link_params.phy[EXT_PHY1].supported;
  8226. bp->port.supported[0] =
  8227. bp->link_params.phy[EXT_PHY2].supported;
  8228. } else {
  8229. bp->port.supported[0] =
  8230. bp->link_params.phy[EXT_PHY1].supported;
  8231. bp->port.supported[1] =
  8232. bp->link_params.phy[EXT_PHY2].supported;
  8233. }
  8234. cfg_size = 2;
  8235. break;
  8236. }
  8237. if (!(bp->port.supported[0] || bp->port.supported[1])) {
  8238. BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
  8239. SHMEM_RD(bp,
  8240. dev_info.port_hw_config[port].external_phy_config),
  8241. SHMEM_RD(bp,
  8242. dev_info.port_hw_config[port].external_phy_config2));
  8243. return;
  8244. }
  8245. if (CHIP_IS_E3(bp))
  8246. bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
  8247. else {
  8248. switch (switch_cfg) {
  8249. case SWITCH_CFG_1G:
  8250. bp->port.phy_addr = REG_RD(
  8251. bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
  8252. break;
  8253. case SWITCH_CFG_10G:
  8254. bp->port.phy_addr = REG_RD(
  8255. bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
  8256. break;
  8257. default:
  8258. BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
  8259. bp->port.link_config[0]);
  8260. return;
  8261. }
  8262. }
  8263. BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
  8264. /* mask what we support according to speed_cap_mask per configuration */
  8265. for (idx = 0; idx < cfg_size; idx++) {
  8266. if (!(bp->link_params.speed_cap_mask[idx] &
  8267. PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
  8268. bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
  8269. if (!(bp->link_params.speed_cap_mask[idx] &
  8270. PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
  8271. bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
  8272. if (!(bp->link_params.speed_cap_mask[idx] &
  8273. PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
  8274. bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
  8275. if (!(bp->link_params.speed_cap_mask[idx] &
  8276. PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
  8277. bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
  8278. if (!(bp->link_params.speed_cap_mask[idx] &
  8279. PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
  8280. bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
  8281. SUPPORTED_1000baseT_Full);
  8282. if (!(bp->link_params.speed_cap_mask[idx] &
  8283. PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
  8284. bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
  8285. if (!(bp->link_params.speed_cap_mask[idx] &
  8286. PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
  8287. bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
  8288. }
  8289. BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
  8290. bp->port.supported[1]);
  8291. }
  8292. static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
  8293. {
  8294. u32 link_config, idx, cfg_size = 0;
  8295. bp->port.advertising[0] = 0;
  8296. bp->port.advertising[1] = 0;
  8297. switch (bp->link_params.num_phys) {
  8298. case 1:
  8299. case 2:
  8300. cfg_size = 1;
  8301. break;
  8302. case 3:
  8303. cfg_size = 2;
  8304. break;
  8305. }
  8306. for (idx = 0; idx < cfg_size; idx++) {
  8307. bp->link_params.req_duplex[idx] = DUPLEX_FULL;
  8308. link_config = bp->port.link_config[idx];
  8309. switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
  8310. case PORT_FEATURE_LINK_SPEED_AUTO:
  8311. if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
  8312. bp->link_params.req_line_speed[idx] =
  8313. SPEED_AUTO_NEG;
  8314. bp->port.advertising[idx] |=
  8315. bp->port.supported[idx];
  8316. if (bp->link_params.phy[EXT_PHY1].type ==
  8317. PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
  8318. bp->port.advertising[idx] |=
  8319. (SUPPORTED_100baseT_Half |
  8320. SUPPORTED_100baseT_Full);
  8321. } else {
  8322. /* force 10G, no AN */
  8323. bp->link_params.req_line_speed[idx] =
  8324. SPEED_10000;
  8325. bp->port.advertising[idx] |=
  8326. (ADVERTISED_10000baseT_Full |
  8327. ADVERTISED_FIBRE);
  8328. continue;
  8329. }
  8330. break;
  8331. case PORT_FEATURE_LINK_SPEED_10M_FULL:
  8332. if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
  8333. bp->link_params.req_line_speed[idx] =
  8334. SPEED_10;
  8335. bp->port.advertising[idx] |=
  8336. (ADVERTISED_10baseT_Full |
  8337. ADVERTISED_TP);
  8338. } else {
  8339. BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
  8340. link_config,
  8341. bp->link_params.speed_cap_mask[idx]);
  8342. return;
  8343. }
  8344. break;
  8345. case PORT_FEATURE_LINK_SPEED_10M_HALF:
  8346. if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
  8347. bp->link_params.req_line_speed[idx] =
  8348. SPEED_10;
  8349. bp->link_params.req_duplex[idx] =
  8350. DUPLEX_HALF;
  8351. bp->port.advertising[idx] |=
  8352. (ADVERTISED_10baseT_Half |
  8353. ADVERTISED_TP);
  8354. } else {
  8355. BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
  8356. link_config,
  8357. bp->link_params.speed_cap_mask[idx]);
  8358. return;
  8359. }
  8360. break;
  8361. case PORT_FEATURE_LINK_SPEED_100M_FULL:
  8362. if (bp->port.supported[idx] &
  8363. SUPPORTED_100baseT_Full) {
  8364. bp->link_params.req_line_speed[idx] =
  8365. SPEED_100;
  8366. bp->port.advertising[idx] |=
  8367. (ADVERTISED_100baseT_Full |
  8368. ADVERTISED_TP);
  8369. } else {
  8370. BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
  8371. link_config,
  8372. bp->link_params.speed_cap_mask[idx]);
  8373. return;
  8374. }
  8375. break;
  8376. case PORT_FEATURE_LINK_SPEED_100M_HALF:
  8377. if (bp->port.supported[idx] &
  8378. SUPPORTED_100baseT_Half) {
  8379. bp->link_params.req_line_speed[idx] =
  8380. SPEED_100;
  8381. bp->link_params.req_duplex[idx] =
  8382. DUPLEX_HALF;
  8383. bp->port.advertising[idx] |=
  8384. (ADVERTISED_100baseT_Half |
  8385. ADVERTISED_TP);
  8386. } else {
  8387. BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
  8388. link_config,
  8389. bp->link_params.speed_cap_mask[idx]);
  8390. return;
  8391. }
  8392. break;
  8393. case PORT_FEATURE_LINK_SPEED_1G:
  8394. if (bp->port.supported[idx] &
  8395. SUPPORTED_1000baseT_Full) {
  8396. bp->link_params.req_line_speed[idx] =
  8397. SPEED_1000;
  8398. bp->port.advertising[idx] |=
  8399. (ADVERTISED_1000baseT_Full |
  8400. ADVERTISED_TP);
  8401. } else {
  8402. BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
  8403. link_config,
  8404. bp->link_params.speed_cap_mask[idx]);
  8405. return;
  8406. }
  8407. break;
  8408. case PORT_FEATURE_LINK_SPEED_2_5G:
  8409. if (bp->port.supported[idx] &
  8410. SUPPORTED_2500baseX_Full) {
  8411. bp->link_params.req_line_speed[idx] =
  8412. SPEED_2500;
  8413. bp->port.advertising[idx] |=
  8414. (ADVERTISED_2500baseX_Full |
  8415. ADVERTISED_TP);
  8416. } else {
  8417. BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
  8418. link_config,
  8419. bp->link_params.speed_cap_mask[idx]);
  8420. return;
  8421. }
  8422. break;
  8423. case PORT_FEATURE_LINK_SPEED_10G_CX4:
  8424. if (bp->port.supported[idx] &
  8425. SUPPORTED_10000baseT_Full) {
  8426. bp->link_params.req_line_speed[idx] =
  8427. SPEED_10000;
  8428. bp->port.advertising[idx] |=
  8429. (ADVERTISED_10000baseT_Full |
  8430. ADVERTISED_FIBRE);
  8431. } else {
  8432. BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
  8433. link_config,
  8434. bp->link_params.speed_cap_mask[idx]);
  8435. return;
  8436. }
  8437. break;
  8438. case PORT_FEATURE_LINK_SPEED_20G:
  8439. bp->link_params.req_line_speed[idx] = SPEED_20000;
  8440. break;
  8441. default:
  8442. BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
  8443. link_config);
  8444. bp->link_params.req_line_speed[idx] =
  8445. SPEED_AUTO_NEG;
  8446. bp->port.advertising[idx] =
  8447. bp->port.supported[idx];
  8448. break;
  8449. }
  8450. bp->link_params.req_flow_ctrl[idx] = (link_config &
  8451. PORT_FEATURE_FLOW_CONTROL_MASK);
  8452. if ((bp->link_params.req_flow_ctrl[idx] ==
  8453. BNX2X_FLOW_CTRL_AUTO) &&
  8454. !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
  8455. bp->link_params.req_flow_ctrl[idx] =
  8456. BNX2X_FLOW_CTRL_NONE;
  8457. }
  8458. BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
  8459. bp->link_params.req_line_speed[idx],
  8460. bp->link_params.req_duplex[idx],
  8461. bp->link_params.req_flow_ctrl[idx],
  8462. bp->port.advertising[idx]);
  8463. }
  8464. }
  8465. static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
  8466. {
  8467. mac_hi = cpu_to_be16(mac_hi);
  8468. mac_lo = cpu_to_be32(mac_lo);
  8469. memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
  8470. memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
  8471. }
  8472. static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
  8473. {
  8474. int port = BP_PORT(bp);
  8475. u32 config;
  8476. u32 ext_phy_type, ext_phy_config, eee_mode;
  8477. bp->link_params.bp = bp;
  8478. bp->link_params.port = port;
  8479. bp->link_params.lane_config =
  8480. SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
  8481. bp->link_params.speed_cap_mask[0] =
  8482. SHMEM_RD(bp,
  8483. dev_info.port_hw_config[port].speed_capability_mask);
  8484. bp->link_params.speed_cap_mask[1] =
  8485. SHMEM_RD(bp,
  8486. dev_info.port_hw_config[port].speed_capability_mask2);
  8487. bp->port.link_config[0] =
  8488. SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
  8489. bp->port.link_config[1] =
  8490. SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
  8491. bp->link_params.multi_phy_config =
  8492. SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
  8493. /* If the device is capable of WoL, set the default state according
  8494. * to the HW
  8495. */
  8496. config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
  8497. bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
  8498. (config & PORT_FEATURE_WOL_ENABLED));
  8499. BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
  8500. bp->link_params.lane_config,
  8501. bp->link_params.speed_cap_mask[0],
  8502. bp->port.link_config[0]);
  8503. bp->link_params.switch_cfg = (bp->port.link_config[0] &
  8504. PORT_FEATURE_CONNECTED_SWITCH_MASK);
  8505. bnx2x_phy_probe(&bp->link_params);
  8506. bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
  8507. bnx2x_link_settings_requested(bp);
  8508. /*
  8509. * If connected directly, work with the internal PHY, otherwise, work
  8510. * with the external PHY
  8511. */
  8512. ext_phy_config =
  8513. SHMEM_RD(bp,
  8514. dev_info.port_hw_config[port].external_phy_config);
  8515. ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
  8516. if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
  8517. bp->mdio.prtad = bp->port.phy_addr;
  8518. else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
  8519. (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
  8520. bp->mdio.prtad =
  8521. XGXS_EXT_PHY_ADDR(ext_phy_config);
  8522. /*
  8523. * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
  8524. * In MF mode, it is set to cover self test cases
  8525. */
  8526. if (IS_MF(bp))
  8527. bp->port.need_hw_lock = 1;
  8528. else
  8529. bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
  8530. bp->common.shmem_base,
  8531. bp->common.shmem2_base);
  8532. /* Configure link feature according to nvram value */
  8533. eee_mode = (((SHMEM_RD(bp, dev_info.
  8534. port_feature_config[port].eee_power_mode)) &
  8535. PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
  8536. PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
  8537. if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
  8538. bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
  8539. EEE_MODE_ENABLE_LPI |
  8540. EEE_MODE_OUTPUT_TIME;
  8541. } else {
  8542. bp->link_params.eee_mode = 0;
  8543. }
  8544. }
  8545. void bnx2x_get_iscsi_info(struct bnx2x *bp)
  8546. {
  8547. u32 no_flags = NO_ISCSI_FLAG;
  8548. #ifdef BCM_CNIC
  8549. int port = BP_PORT(bp);
  8550. u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
  8551. drv_lic_key[port].max_iscsi_conn);
  8552. /* Get the number of maximum allowed iSCSI connections */
  8553. bp->cnic_eth_dev.max_iscsi_conn =
  8554. (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
  8555. BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
  8556. BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
  8557. bp->cnic_eth_dev.max_iscsi_conn);
  8558. /*
  8559. * If maximum allowed number of connections is zero -
  8560. * disable the feature.
  8561. */
  8562. if (!bp->cnic_eth_dev.max_iscsi_conn)
  8563. bp->flags |= no_flags;
  8564. #else
  8565. bp->flags |= no_flags;
  8566. #endif
  8567. }
  8568. #ifdef BCM_CNIC
  8569. static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
  8570. {
  8571. /* Port info */
  8572. bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
  8573. MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
  8574. bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
  8575. MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
  8576. /* Node info */
  8577. bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
  8578. MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
  8579. bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
  8580. MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
  8581. }
  8582. #endif
  8583. static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
  8584. {
  8585. #ifdef BCM_CNIC
  8586. int port = BP_PORT(bp);
  8587. int func = BP_ABS_FUNC(bp);
  8588. u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
  8589. drv_lic_key[port].max_fcoe_conn);
  8590. /* Get the number of maximum allowed FCoE connections */
  8591. bp->cnic_eth_dev.max_fcoe_conn =
  8592. (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
  8593. BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
  8594. /* Read the WWN: */
  8595. if (!IS_MF(bp)) {
  8596. /* Port info */
  8597. bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
  8598. SHMEM_RD(bp,
  8599. dev_info.port_hw_config[port].
  8600. fcoe_wwn_port_name_upper);
  8601. bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
  8602. SHMEM_RD(bp,
  8603. dev_info.port_hw_config[port].
  8604. fcoe_wwn_port_name_lower);
  8605. /* Node info */
  8606. bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
  8607. SHMEM_RD(bp,
  8608. dev_info.port_hw_config[port].
  8609. fcoe_wwn_node_name_upper);
  8610. bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
  8611. SHMEM_RD(bp,
  8612. dev_info.port_hw_config[port].
  8613. fcoe_wwn_node_name_lower);
  8614. } else if (!IS_MF_SD(bp)) {
  8615. /*
  8616. * Read the WWN info only if the FCoE feature is enabled for
  8617. * this function.
  8618. */
  8619. if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
  8620. bnx2x_get_ext_wwn_info(bp, func);
  8621. } else if (IS_MF_FCOE_SD(bp))
  8622. bnx2x_get_ext_wwn_info(bp, func);
  8623. BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
  8624. /*
  8625. * If maximum allowed number of connections is zero -
  8626. * disable the feature.
  8627. */
  8628. if (!bp->cnic_eth_dev.max_fcoe_conn)
  8629. bp->flags |= NO_FCOE_FLAG;
  8630. #else
  8631. bp->flags |= NO_FCOE_FLAG;
  8632. #endif
  8633. }
  8634. static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
  8635. {
  8636. /*
  8637. * iSCSI may be dynamically disabled but reading
  8638. * info here we will decrease memory usage by driver
  8639. * if the feature is disabled for good
  8640. */
  8641. bnx2x_get_iscsi_info(bp);
  8642. bnx2x_get_fcoe_info(bp);
  8643. }
  8644. static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
  8645. {
  8646. u32 val, val2;
  8647. int func = BP_ABS_FUNC(bp);
  8648. int port = BP_PORT(bp);
  8649. #ifdef BCM_CNIC
  8650. u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
  8651. u8 *fip_mac = bp->fip_mac;
  8652. #endif
  8653. /* Zero primary MAC configuration */
  8654. memset(bp->dev->dev_addr, 0, ETH_ALEN);
  8655. if (BP_NOMCP(bp)) {
  8656. BNX2X_ERROR("warning: random MAC workaround active\n");
  8657. eth_hw_addr_random(bp->dev);
  8658. } else if (IS_MF(bp)) {
  8659. val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
  8660. val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
  8661. if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
  8662. (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
  8663. bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
  8664. #ifdef BCM_CNIC
  8665. /*
  8666. * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
  8667. * FCoE MAC then the appropriate feature should be disabled.
  8668. *
  8669. * In non SD mode features configuration comes from
  8670. * struct func_ext_config.
  8671. */
  8672. if (!IS_MF_SD(bp)) {
  8673. u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
  8674. if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
  8675. val2 = MF_CFG_RD(bp, func_ext_config[func].
  8676. iscsi_mac_addr_upper);
  8677. val = MF_CFG_RD(bp, func_ext_config[func].
  8678. iscsi_mac_addr_lower);
  8679. bnx2x_set_mac_buf(iscsi_mac, val, val2);
  8680. BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
  8681. iscsi_mac);
  8682. } else
  8683. bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
  8684. if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
  8685. val2 = MF_CFG_RD(bp, func_ext_config[func].
  8686. fcoe_mac_addr_upper);
  8687. val = MF_CFG_RD(bp, func_ext_config[func].
  8688. fcoe_mac_addr_lower);
  8689. bnx2x_set_mac_buf(fip_mac, val, val2);
  8690. BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
  8691. fip_mac);
  8692. } else
  8693. bp->flags |= NO_FCOE_FLAG;
  8694. bp->mf_ext_config = cfg;
  8695. } else { /* SD MODE */
  8696. if (IS_MF_STORAGE_SD(bp)) {
  8697. if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
  8698. /* use primary mac as iscsi mac */
  8699. memcpy(iscsi_mac, bp->dev->dev_addr,
  8700. ETH_ALEN);
  8701. BNX2X_DEV_INFO("SD ISCSI MODE\n");
  8702. BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
  8703. iscsi_mac);
  8704. } else { /* FCoE */
  8705. memcpy(fip_mac, bp->dev->dev_addr,
  8706. ETH_ALEN);
  8707. BNX2X_DEV_INFO("SD FCoE MODE\n");
  8708. BNX2X_DEV_INFO("Read FIP MAC: %pM\n",
  8709. fip_mac);
  8710. }
  8711. /* Zero primary MAC configuration */
  8712. memset(bp->dev->dev_addr, 0, ETH_ALEN);
  8713. }
  8714. }
  8715. if (IS_MF_FCOE_AFEX(bp))
  8716. /* use FIP MAC as primary MAC */
  8717. memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
  8718. #endif
  8719. } else {
  8720. /* in SF read MACs from port configuration */
  8721. val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
  8722. val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
  8723. bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
  8724. #ifdef BCM_CNIC
  8725. val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
  8726. iscsi_mac_upper);
  8727. val = SHMEM_RD(bp, dev_info.port_hw_config[port].
  8728. iscsi_mac_lower);
  8729. bnx2x_set_mac_buf(iscsi_mac, val, val2);
  8730. val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
  8731. fcoe_fip_mac_upper);
  8732. val = SHMEM_RD(bp, dev_info.port_hw_config[port].
  8733. fcoe_fip_mac_lower);
  8734. bnx2x_set_mac_buf(fip_mac, val, val2);
  8735. #endif
  8736. }
  8737. memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
  8738. memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
  8739. #ifdef BCM_CNIC
  8740. /* Disable iSCSI if MAC configuration is
  8741. * invalid.
  8742. */
  8743. if (!is_valid_ether_addr(iscsi_mac)) {
  8744. bp->flags |= NO_ISCSI_FLAG;
  8745. memset(iscsi_mac, 0, ETH_ALEN);
  8746. }
  8747. /* Disable FCoE if MAC configuration is
  8748. * invalid.
  8749. */
  8750. if (!is_valid_ether_addr(fip_mac)) {
  8751. bp->flags |= NO_FCOE_FLAG;
  8752. memset(bp->fip_mac, 0, ETH_ALEN);
  8753. }
  8754. #endif
  8755. if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
  8756. dev_err(&bp->pdev->dev,
  8757. "bad Ethernet MAC address configuration: %pM\n"
  8758. "change it manually before bringing up the appropriate network interface\n",
  8759. bp->dev->dev_addr);
  8760. }
  8761. static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
  8762. {
  8763. int /*abs*/func = BP_ABS_FUNC(bp);
  8764. int vn;
  8765. u32 val = 0;
  8766. int rc = 0;
  8767. bnx2x_get_common_hwinfo(bp);
  8768. /*
  8769. * initialize IGU parameters
  8770. */
  8771. if (CHIP_IS_E1x(bp)) {
  8772. bp->common.int_block = INT_BLOCK_HC;
  8773. bp->igu_dsb_id = DEF_SB_IGU_ID;
  8774. bp->igu_base_sb = 0;
  8775. } else {
  8776. bp->common.int_block = INT_BLOCK_IGU;
  8777. /* do not allow device reset during IGU info preocessing */
  8778. bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
  8779. val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
  8780. if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
  8781. int tout = 5000;
  8782. BNX2X_DEV_INFO("FORCING Normal Mode\n");
  8783. val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
  8784. REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
  8785. REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
  8786. while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
  8787. tout--;
  8788. usleep_range(1000, 1000);
  8789. }
  8790. if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
  8791. dev_err(&bp->pdev->dev,
  8792. "FORCING Normal Mode failed!!!\n");
  8793. return -EPERM;
  8794. }
  8795. }
  8796. if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
  8797. BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
  8798. bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
  8799. } else
  8800. BNX2X_DEV_INFO("IGU Normal Mode\n");
  8801. bnx2x_get_igu_cam_info(bp);
  8802. bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
  8803. }
  8804. /*
  8805. * set base FW non-default (fast path) status block id, this value is
  8806. * used to initialize the fw_sb_id saved on the fp/queue structure to
  8807. * determine the id used by the FW.
  8808. */
  8809. if (CHIP_IS_E1x(bp))
  8810. bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
  8811. else /*
  8812. * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
  8813. * the same queue are indicated on the same IGU SB). So we prefer
  8814. * FW and IGU SBs to be the same value.
  8815. */
  8816. bp->base_fw_ndsb = bp->igu_base_sb;
  8817. BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
  8818. "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
  8819. bp->igu_sb_cnt, bp->base_fw_ndsb);
  8820. /*
  8821. * Initialize MF configuration
  8822. */
  8823. bp->mf_ov = 0;
  8824. bp->mf_mode = 0;
  8825. vn = BP_VN(bp);
  8826. if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
  8827. BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
  8828. bp->common.shmem2_base, SHMEM2_RD(bp, size),
  8829. (u32)offsetof(struct shmem2_region, mf_cfg_addr));
  8830. if (SHMEM2_HAS(bp, mf_cfg_addr))
  8831. bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
  8832. else
  8833. bp->common.mf_cfg_base = bp->common.shmem_base +
  8834. offsetof(struct shmem_region, func_mb) +
  8835. E1H_FUNC_MAX * sizeof(struct drv_func_mb);
  8836. /*
  8837. * get mf configuration:
  8838. * 1. existence of MF configuration
  8839. * 2. MAC address must be legal (check only upper bytes)
  8840. * for Switch-Independent mode;
  8841. * OVLAN must be legal for Switch-Dependent mode
  8842. * 3. SF_MODE configures specific MF mode
  8843. */
  8844. if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
  8845. /* get mf configuration */
  8846. val = SHMEM_RD(bp,
  8847. dev_info.shared_feature_config.config);
  8848. val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
  8849. switch (val) {
  8850. case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
  8851. val = MF_CFG_RD(bp, func_mf_config[func].
  8852. mac_upper);
  8853. /* check for legal mac (upper bytes)*/
  8854. if (val != 0xffff) {
  8855. bp->mf_mode = MULTI_FUNCTION_SI;
  8856. bp->mf_config[vn] = MF_CFG_RD(bp,
  8857. func_mf_config[func].config);
  8858. } else
  8859. BNX2X_DEV_INFO("illegal MAC address for SI\n");
  8860. break;
  8861. case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
  8862. if ((!CHIP_IS_E1x(bp)) &&
  8863. (MF_CFG_RD(bp, func_mf_config[func].
  8864. mac_upper) != 0xffff) &&
  8865. (SHMEM2_HAS(bp,
  8866. afex_driver_support))) {
  8867. bp->mf_mode = MULTI_FUNCTION_AFEX;
  8868. bp->mf_config[vn] = MF_CFG_RD(bp,
  8869. func_mf_config[func].config);
  8870. } else {
  8871. BNX2X_DEV_INFO("can not configure afex mode\n");
  8872. }
  8873. break;
  8874. case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
  8875. /* get OV configuration */
  8876. val = MF_CFG_RD(bp,
  8877. func_mf_config[FUNC_0].e1hov_tag);
  8878. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  8879. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  8880. bp->mf_mode = MULTI_FUNCTION_SD;
  8881. bp->mf_config[vn] = MF_CFG_RD(bp,
  8882. func_mf_config[func].config);
  8883. } else
  8884. BNX2X_DEV_INFO("illegal OV for SD\n");
  8885. break;
  8886. default:
  8887. /* Unknown configuration: reset mf_config */
  8888. bp->mf_config[vn] = 0;
  8889. BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
  8890. }
  8891. }
  8892. BNX2X_DEV_INFO("%s function mode\n",
  8893. IS_MF(bp) ? "multi" : "single");
  8894. switch (bp->mf_mode) {
  8895. case MULTI_FUNCTION_SD:
  8896. val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
  8897. FUNC_MF_CFG_E1HOV_TAG_MASK;
  8898. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  8899. bp->mf_ov = val;
  8900. bp->path_has_ovlan = true;
  8901. BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
  8902. func, bp->mf_ov, bp->mf_ov);
  8903. } else {
  8904. dev_err(&bp->pdev->dev,
  8905. "No valid MF OV for func %d, aborting\n",
  8906. func);
  8907. return -EPERM;
  8908. }
  8909. break;
  8910. case MULTI_FUNCTION_AFEX:
  8911. BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
  8912. break;
  8913. case MULTI_FUNCTION_SI:
  8914. BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
  8915. func);
  8916. break;
  8917. default:
  8918. if (vn) {
  8919. dev_err(&bp->pdev->dev,
  8920. "VN %d is in a single function mode, aborting\n",
  8921. vn);
  8922. return -EPERM;
  8923. }
  8924. break;
  8925. }
  8926. /* check if other port on the path needs ovlan:
  8927. * Since MF configuration is shared between ports
  8928. * Possible mixed modes are only
  8929. * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
  8930. */
  8931. if (CHIP_MODE_IS_4_PORT(bp) &&
  8932. !bp->path_has_ovlan &&
  8933. !IS_MF(bp) &&
  8934. bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
  8935. u8 other_port = !BP_PORT(bp);
  8936. u8 other_func = BP_PATH(bp) + 2*other_port;
  8937. val = MF_CFG_RD(bp,
  8938. func_mf_config[other_func].e1hov_tag);
  8939. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
  8940. bp->path_has_ovlan = true;
  8941. }
  8942. }
  8943. /* adjust igu_sb_cnt to MF for E1x */
  8944. if (CHIP_IS_E1x(bp) && IS_MF(bp))
  8945. bp->igu_sb_cnt /= E1HVN_MAX;
  8946. /* port info */
  8947. bnx2x_get_port_hwinfo(bp);
  8948. /* Get MAC addresses */
  8949. bnx2x_get_mac_hwinfo(bp);
  8950. bnx2x_get_cnic_info(bp);
  8951. return rc;
  8952. }
  8953. static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
  8954. {
  8955. int cnt, i, block_end, rodi;
  8956. char vpd_start[BNX2X_VPD_LEN+1];
  8957. char str_id_reg[VENDOR_ID_LEN+1];
  8958. char str_id_cap[VENDOR_ID_LEN+1];
  8959. char *vpd_data;
  8960. char *vpd_extended_data = NULL;
  8961. u8 len;
  8962. cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
  8963. memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
  8964. if (cnt < BNX2X_VPD_LEN)
  8965. goto out_not_found;
  8966. /* VPD RO tag should be first tag after identifier string, hence
  8967. * we should be able to find it in first BNX2X_VPD_LEN chars
  8968. */
  8969. i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
  8970. PCI_VPD_LRDT_RO_DATA);
  8971. if (i < 0)
  8972. goto out_not_found;
  8973. block_end = i + PCI_VPD_LRDT_TAG_SIZE +
  8974. pci_vpd_lrdt_size(&vpd_start[i]);
  8975. i += PCI_VPD_LRDT_TAG_SIZE;
  8976. if (block_end > BNX2X_VPD_LEN) {
  8977. vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
  8978. if (vpd_extended_data == NULL)
  8979. goto out_not_found;
  8980. /* read rest of vpd image into vpd_extended_data */
  8981. memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
  8982. cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
  8983. block_end - BNX2X_VPD_LEN,
  8984. vpd_extended_data + BNX2X_VPD_LEN);
  8985. if (cnt < (block_end - BNX2X_VPD_LEN))
  8986. goto out_not_found;
  8987. vpd_data = vpd_extended_data;
  8988. } else
  8989. vpd_data = vpd_start;
  8990. /* now vpd_data holds full vpd content in both cases */
  8991. rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
  8992. PCI_VPD_RO_KEYWORD_MFR_ID);
  8993. if (rodi < 0)
  8994. goto out_not_found;
  8995. len = pci_vpd_info_field_size(&vpd_data[rodi]);
  8996. if (len != VENDOR_ID_LEN)
  8997. goto out_not_found;
  8998. rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
  8999. /* vendor specific info */
  9000. snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
  9001. snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
  9002. if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
  9003. !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
  9004. rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
  9005. PCI_VPD_RO_KEYWORD_VENDOR0);
  9006. if (rodi >= 0) {
  9007. len = pci_vpd_info_field_size(&vpd_data[rodi]);
  9008. rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
  9009. if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
  9010. memcpy(bp->fw_ver, &vpd_data[rodi], len);
  9011. bp->fw_ver[len] = ' ';
  9012. }
  9013. }
  9014. kfree(vpd_extended_data);
  9015. return;
  9016. }
  9017. out_not_found:
  9018. kfree(vpd_extended_data);
  9019. return;
  9020. }
  9021. static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
  9022. {
  9023. u32 flags = 0;
  9024. if (CHIP_REV_IS_FPGA(bp))
  9025. SET_FLAGS(flags, MODE_FPGA);
  9026. else if (CHIP_REV_IS_EMUL(bp))
  9027. SET_FLAGS(flags, MODE_EMUL);
  9028. else
  9029. SET_FLAGS(flags, MODE_ASIC);
  9030. if (CHIP_MODE_IS_4_PORT(bp))
  9031. SET_FLAGS(flags, MODE_PORT4);
  9032. else
  9033. SET_FLAGS(flags, MODE_PORT2);
  9034. if (CHIP_IS_E2(bp))
  9035. SET_FLAGS(flags, MODE_E2);
  9036. else if (CHIP_IS_E3(bp)) {
  9037. SET_FLAGS(flags, MODE_E3);
  9038. if (CHIP_REV(bp) == CHIP_REV_Ax)
  9039. SET_FLAGS(flags, MODE_E3_A0);
  9040. else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
  9041. SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
  9042. }
  9043. if (IS_MF(bp)) {
  9044. SET_FLAGS(flags, MODE_MF);
  9045. switch (bp->mf_mode) {
  9046. case MULTI_FUNCTION_SD:
  9047. SET_FLAGS(flags, MODE_MF_SD);
  9048. break;
  9049. case MULTI_FUNCTION_SI:
  9050. SET_FLAGS(flags, MODE_MF_SI);
  9051. break;
  9052. case MULTI_FUNCTION_AFEX:
  9053. SET_FLAGS(flags, MODE_MF_AFEX);
  9054. break;
  9055. }
  9056. } else
  9057. SET_FLAGS(flags, MODE_SF);
  9058. #if defined(__LITTLE_ENDIAN)
  9059. SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
  9060. #else /*(__BIG_ENDIAN)*/
  9061. SET_FLAGS(flags, MODE_BIG_ENDIAN);
  9062. #endif
  9063. INIT_MODE_FLAGS(bp) = flags;
  9064. }
  9065. static int __devinit bnx2x_init_bp(struct bnx2x *bp)
  9066. {
  9067. int func;
  9068. int rc;
  9069. mutex_init(&bp->port.phy_mutex);
  9070. mutex_init(&bp->fw_mb_mutex);
  9071. spin_lock_init(&bp->stats_lock);
  9072. #ifdef BCM_CNIC
  9073. mutex_init(&bp->cnic_mutex);
  9074. #endif
  9075. INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
  9076. INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
  9077. INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
  9078. rc = bnx2x_get_hwinfo(bp);
  9079. if (rc)
  9080. return rc;
  9081. bnx2x_set_modes_bitmap(bp);
  9082. rc = bnx2x_alloc_mem_bp(bp);
  9083. if (rc)
  9084. return rc;
  9085. bnx2x_read_fwinfo(bp);
  9086. func = BP_FUNC(bp);
  9087. /* need to reset chip if undi was active */
  9088. if (!BP_NOMCP(bp)) {
  9089. /* init fw_seq */
  9090. bp->fw_seq =
  9091. SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
  9092. DRV_MSG_SEQ_NUMBER_MASK;
  9093. BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
  9094. bnx2x_prev_unload(bp);
  9095. }
  9096. if (CHIP_REV_IS_FPGA(bp))
  9097. dev_err(&bp->pdev->dev, "FPGA detected\n");
  9098. if (BP_NOMCP(bp) && (func == 0))
  9099. dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
  9100. bp->disable_tpa = disable_tpa;
  9101. #ifdef BCM_CNIC
  9102. bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
  9103. #endif
  9104. /* Set TPA flags */
  9105. if (bp->disable_tpa) {
  9106. bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
  9107. bp->dev->features &= ~NETIF_F_LRO;
  9108. } else {
  9109. bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
  9110. bp->dev->features |= NETIF_F_LRO;
  9111. }
  9112. if (CHIP_IS_E1(bp))
  9113. bp->dropless_fc = 0;
  9114. else
  9115. bp->dropless_fc = dropless_fc;
  9116. bp->mrrs = mrrs;
  9117. bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
  9118. /* make sure that the numbers are in the right granularity */
  9119. bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
  9120. bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
  9121. bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
  9122. init_timer(&bp->timer);
  9123. bp->timer.expires = jiffies + bp->current_interval;
  9124. bp->timer.data = (unsigned long) bp;
  9125. bp->timer.function = bnx2x_timer;
  9126. bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
  9127. bnx2x_dcbx_init_params(bp);
  9128. #ifdef BCM_CNIC
  9129. if (CHIP_IS_E1x(bp))
  9130. bp->cnic_base_cl_id = FP_SB_MAX_E1x;
  9131. else
  9132. bp->cnic_base_cl_id = FP_SB_MAX_E2;
  9133. #endif
  9134. /* multiple tx priority */
  9135. if (CHIP_IS_E1x(bp))
  9136. bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
  9137. if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
  9138. bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
  9139. if (CHIP_IS_E3B0(bp))
  9140. bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
  9141. return rc;
  9142. }
  9143. /****************************************************************************
  9144. * General service functions
  9145. ****************************************************************************/
  9146. /*
  9147. * net_device service functions
  9148. */
  9149. /* called with rtnl_lock */
  9150. static int bnx2x_open(struct net_device *dev)
  9151. {
  9152. struct bnx2x *bp = netdev_priv(dev);
  9153. bool global = false;
  9154. int other_engine = BP_PATH(bp) ? 0 : 1;
  9155. bool other_load_status, load_status;
  9156. bp->stats_init = true;
  9157. netif_carrier_off(dev);
  9158. bnx2x_set_power_state(bp, PCI_D0);
  9159. other_load_status = bnx2x_get_load_status(bp, other_engine);
  9160. load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
  9161. /*
  9162. * If parity had happen during the unload, then attentions
  9163. * and/or RECOVERY_IN_PROGRES may still be set. In this case we
  9164. * want the first function loaded on the current engine to
  9165. * complete the recovery.
  9166. */
  9167. if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
  9168. bnx2x_chk_parity_attn(bp, &global, true))
  9169. do {
  9170. /*
  9171. * If there are attentions and they are in a global
  9172. * blocks, set the GLOBAL_RESET bit regardless whether
  9173. * it will be this function that will complete the
  9174. * recovery or not.
  9175. */
  9176. if (global)
  9177. bnx2x_set_reset_global(bp);
  9178. /*
  9179. * Only the first function on the current engine should
  9180. * try to recover in open. In case of attentions in
  9181. * global blocks only the first in the chip should try
  9182. * to recover.
  9183. */
  9184. if ((!load_status &&
  9185. (!global || !other_load_status)) &&
  9186. bnx2x_trylock_leader_lock(bp) &&
  9187. !bnx2x_leader_reset(bp)) {
  9188. netdev_info(bp->dev, "Recovered in open\n");
  9189. break;
  9190. }
  9191. /* recovery has failed... */
  9192. bnx2x_set_power_state(bp, PCI_D3hot);
  9193. bp->recovery_state = BNX2X_RECOVERY_FAILED;
  9194. BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
  9195. "If you still see this message after a few retries then power cycle is required.\n");
  9196. return -EAGAIN;
  9197. } while (0);
  9198. bp->recovery_state = BNX2X_RECOVERY_DONE;
  9199. return bnx2x_nic_load(bp, LOAD_OPEN);
  9200. }
  9201. /* called with rtnl_lock */
  9202. static int bnx2x_close(struct net_device *dev)
  9203. {
  9204. struct bnx2x *bp = netdev_priv(dev);
  9205. /* Unload the driver, release IRQs */
  9206. bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
  9207. /* Power off */
  9208. bnx2x_set_power_state(bp, PCI_D3hot);
  9209. return 0;
  9210. }
  9211. static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
  9212. struct bnx2x_mcast_ramrod_params *p)
  9213. {
  9214. int mc_count = netdev_mc_count(bp->dev);
  9215. struct bnx2x_mcast_list_elem *mc_mac =
  9216. kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
  9217. struct netdev_hw_addr *ha;
  9218. if (!mc_mac)
  9219. return -ENOMEM;
  9220. INIT_LIST_HEAD(&p->mcast_list);
  9221. netdev_for_each_mc_addr(ha, bp->dev) {
  9222. mc_mac->mac = bnx2x_mc_addr(ha);
  9223. list_add_tail(&mc_mac->link, &p->mcast_list);
  9224. mc_mac++;
  9225. }
  9226. p->mcast_list_len = mc_count;
  9227. return 0;
  9228. }
  9229. static void bnx2x_free_mcast_macs_list(
  9230. struct bnx2x_mcast_ramrod_params *p)
  9231. {
  9232. struct bnx2x_mcast_list_elem *mc_mac =
  9233. list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
  9234. link);
  9235. WARN_ON(!mc_mac);
  9236. kfree(mc_mac);
  9237. }
  9238. /**
  9239. * bnx2x_set_uc_list - configure a new unicast MACs list.
  9240. *
  9241. * @bp: driver handle
  9242. *
  9243. * We will use zero (0) as a MAC type for these MACs.
  9244. */
  9245. static int bnx2x_set_uc_list(struct bnx2x *bp)
  9246. {
  9247. int rc;
  9248. struct net_device *dev = bp->dev;
  9249. struct netdev_hw_addr *ha;
  9250. struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
  9251. unsigned long ramrod_flags = 0;
  9252. /* First schedule a cleanup up of old configuration */
  9253. rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
  9254. if (rc < 0) {
  9255. BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
  9256. return rc;
  9257. }
  9258. netdev_for_each_uc_addr(ha, dev) {
  9259. rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
  9260. BNX2X_UC_LIST_MAC, &ramrod_flags);
  9261. if (rc == -EEXIST) {
  9262. DP(BNX2X_MSG_SP,
  9263. "Failed to schedule ADD operations: %d\n", rc);
  9264. /* do not treat adding same MAC as error */
  9265. rc = 0;
  9266. } else if (rc < 0) {
  9267. BNX2X_ERR("Failed to schedule ADD operations: %d\n",
  9268. rc);
  9269. return rc;
  9270. }
  9271. }
  9272. /* Execute the pending commands */
  9273. __set_bit(RAMROD_CONT, &ramrod_flags);
  9274. return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
  9275. BNX2X_UC_LIST_MAC, &ramrod_flags);
  9276. }
  9277. static int bnx2x_set_mc_list(struct bnx2x *bp)
  9278. {
  9279. struct net_device *dev = bp->dev;
  9280. struct bnx2x_mcast_ramrod_params rparam = {NULL};
  9281. int rc = 0;
  9282. rparam.mcast_obj = &bp->mcast_obj;
  9283. /* first, clear all configured multicast MACs */
  9284. rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
  9285. if (rc < 0) {
  9286. BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
  9287. return rc;
  9288. }
  9289. /* then, configure a new MACs list */
  9290. if (netdev_mc_count(dev)) {
  9291. rc = bnx2x_init_mcast_macs_list(bp, &rparam);
  9292. if (rc) {
  9293. BNX2X_ERR("Failed to create multicast MACs list: %d\n",
  9294. rc);
  9295. return rc;
  9296. }
  9297. /* Now add the new MACs */
  9298. rc = bnx2x_config_mcast(bp, &rparam,
  9299. BNX2X_MCAST_CMD_ADD);
  9300. if (rc < 0)
  9301. BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
  9302. rc);
  9303. bnx2x_free_mcast_macs_list(&rparam);
  9304. }
  9305. return rc;
  9306. }
  9307. /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
  9308. void bnx2x_set_rx_mode(struct net_device *dev)
  9309. {
  9310. struct bnx2x *bp = netdev_priv(dev);
  9311. u32 rx_mode = BNX2X_RX_MODE_NORMAL;
  9312. if (bp->state != BNX2X_STATE_OPEN) {
  9313. DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
  9314. return;
  9315. }
  9316. DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
  9317. if (dev->flags & IFF_PROMISC)
  9318. rx_mode = BNX2X_RX_MODE_PROMISC;
  9319. else if ((dev->flags & IFF_ALLMULTI) ||
  9320. ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
  9321. CHIP_IS_E1(bp)))
  9322. rx_mode = BNX2X_RX_MODE_ALLMULTI;
  9323. else {
  9324. /* some multicasts */
  9325. if (bnx2x_set_mc_list(bp) < 0)
  9326. rx_mode = BNX2X_RX_MODE_ALLMULTI;
  9327. if (bnx2x_set_uc_list(bp) < 0)
  9328. rx_mode = BNX2X_RX_MODE_PROMISC;
  9329. }
  9330. bp->rx_mode = rx_mode;
  9331. #ifdef BCM_CNIC
  9332. /* handle ISCSI SD mode */
  9333. if (IS_MF_ISCSI_SD(bp))
  9334. bp->rx_mode = BNX2X_RX_MODE_NONE;
  9335. #endif
  9336. /* Schedule the rx_mode command */
  9337. if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
  9338. set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
  9339. return;
  9340. }
  9341. bnx2x_set_storm_rx_mode(bp);
  9342. }
  9343. /* called with rtnl_lock */
  9344. static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
  9345. int devad, u16 addr)
  9346. {
  9347. struct bnx2x *bp = netdev_priv(netdev);
  9348. u16 value;
  9349. int rc;
  9350. DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
  9351. prtad, devad, addr);
  9352. /* The HW expects different devad if CL22 is used */
  9353. devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
  9354. bnx2x_acquire_phy_lock(bp);
  9355. rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
  9356. bnx2x_release_phy_lock(bp);
  9357. DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
  9358. if (!rc)
  9359. rc = value;
  9360. return rc;
  9361. }
  9362. /* called with rtnl_lock */
  9363. static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
  9364. u16 addr, u16 value)
  9365. {
  9366. struct bnx2x *bp = netdev_priv(netdev);
  9367. int rc;
  9368. DP(NETIF_MSG_LINK,
  9369. "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
  9370. prtad, devad, addr, value);
  9371. /* The HW expects different devad if CL22 is used */
  9372. devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
  9373. bnx2x_acquire_phy_lock(bp);
  9374. rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
  9375. bnx2x_release_phy_lock(bp);
  9376. return rc;
  9377. }
  9378. /* called with rtnl_lock */
  9379. static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  9380. {
  9381. struct bnx2x *bp = netdev_priv(dev);
  9382. struct mii_ioctl_data *mdio = if_mii(ifr);
  9383. DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
  9384. mdio->phy_id, mdio->reg_num, mdio->val_in);
  9385. if (!netif_running(dev))
  9386. return -EAGAIN;
  9387. return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
  9388. }
  9389. #ifdef CONFIG_NET_POLL_CONTROLLER
  9390. static void poll_bnx2x(struct net_device *dev)
  9391. {
  9392. struct bnx2x *bp = netdev_priv(dev);
  9393. int i;
  9394. for_each_eth_queue(bp, i) {
  9395. struct bnx2x_fastpath *fp = &bp->fp[i];
  9396. napi_schedule(&bnx2x_fp(bp, fp->index, napi));
  9397. }
  9398. }
  9399. #endif
  9400. static int bnx2x_validate_addr(struct net_device *dev)
  9401. {
  9402. struct bnx2x *bp = netdev_priv(dev);
  9403. if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
  9404. BNX2X_ERR("Non-valid Ethernet address\n");
  9405. return -EADDRNOTAVAIL;
  9406. }
  9407. return 0;
  9408. }
  9409. static const struct net_device_ops bnx2x_netdev_ops = {
  9410. .ndo_open = bnx2x_open,
  9411. .ndo_stop = bnx2x_close,
  9412. .ndo_start_xmit = bnx2x_start_xmit,
  9413. .ndo_select_queue = bnx2x_select_queue,
  9414. .ndo_set_rx_mode = bnx2x_set_rx_mode,
  9415. .ndo_set_mac_address = bnx2x_change_mac_addr,
  9416. .ndo_validate_addr = bnx2x_validate_addr,
  9417. .ndo_do_ioctl = bnx2x_ioctl,
  9418. .ndo_change_mtu = bnx2x_change_mtu,
  9419. .ndo_fix_features = bnx2x_fix_features,
  9420. .ndo_set_features = bnx2x_set_features,
  9421. .ndo_tx_timeout = bnx2x_tx_timeout,
  9422. #ifdef CONFIG_NET_POLL_CONTROLLER
  9423. .ndo_poll_controller = poll_bnx2x,
  9424. #endif
  9425. .ndo_setup_tc = bnx2x_setup_tc,
  9426. #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
  9427. .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
  9428. #endif
  9429. };
  9430. static int bnx2x_set_coherency_mask(struct bnx2x *bp)
  9431. {
  9432. struct device *dev = &bp->pdev->dev;
  9433. if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
  9434. bp->flags |= USING_DAC_FLAG;
  9435. if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
  9436. dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
  9437. return -EIO;
  9438. }
  9439. } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
  9440. dev_err(dev, "System does not support DMA, aborting\n");
  9441. return -EIO;
  9442. }
  9443. return 0;
  9444. }
  9445. static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
  9446. struct net_device *dev,
  9447. unsigned long board_type)
  9448. {
  9449. struct bnx2x *bp;
  9450. int rc;
  9451. u32 pci_cfg_dword;
  9452. bool chip_is_e1x = (board_type == BCM57710 ||
  9453. board_type == BCM57711 ||
  9454. board_type == BCM57711E);
  9455. SET_NETDEV_DEV(dev, &pdev->dev);
  9456. bp = netdev_priv(dev);
  9457. bp->dev = dev;
  9458. bp->pdev = pdev;
  9459. bp->flags = 0;
  9460. rc = pci_enable_device(pdev);
  9461. if (rc) {
  9462. dev_err(&bp->pdev->dev,
  9463. "Cannot enable PCI device, aborting\n");
  9464. goto err_out;
  9465. }
  9466. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  9467. dev_err(&bp->pdev->dev,
  9468. "Cannot find PCI device base address, aborting\n");
  9469. rc = -ENODEV;
  9470. goto err_out_disable;
  9471. }
  9472. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  9473. dev_err(&bp->pdev->dev, "Cannot find second PCI device"
  9474. " base address, aborting\n");
  9475. rc = -ENODEV;
  9476. goto err_out_disable;
  9477. }
  9478. if (atomic_read(&pdev->enable_cnt) == 1) {
  9479. rc = pci_request_regions(pdev, DRV_MODULE_NAME);
  9480. if (rc) {
  9481. dev_err(&bp->pdev->dev,
  9482. "Cannot obtain PCI resources, aborting\n");
  9483. goto err_out_disable;
  9484. }
  9485. pci_set_master(pdev);
  9486. pci_save_state(pdev);
  9487. }
  9488. bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  9489. if (bp->pm_cap == 0) {
  9490. dev_err(&bp->pdev->dev,
  9491. "Cannot find power management capability, aborting\n");
  9492. rc = -EIO;
  9493. goto err_out_release;
  9494. }
  9495. if (!pci_is_pcie(pdev)) {
  9496. dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
  9497. rc = -EIO;
  9498. goto err_out_release;
  9499. }
  9500. rc = bnx2x_set_coherency_mask(bp);
  9501. if (rc)
  9502. goto err_out_release;
  9503. dev->mem_start = pci_resource_start(pdev, 0);
  9504. dev->base_addr = dev->mem_start;
  9505. dev->mem_end = pci_resource_end(pdev, 0);
  9506. dev->irq = pdev->irq;
  9507. bp->regview = pci_ioremap_bar(pdev, 0);
  9508. if (!bp->regview) {
  9509. dev_err(&bp->pdev->dev,
  9510. "Cannot map register space, aborting\n");
  9511. rc = -ENOMEM;
  9512. goto err_out_release;
  9513. }
  9514. /* In E1/E1H use pci device function given by kernel.
  9515. * In E2/E3 read physical function from ME register since these chips
  9516. * support Physical Device Assignment where kernel BDF maybe arbitrary
  9517. * (depending on hypervisor).
  9518. */
  9519. if (chip_is_e1x)
  9520. bp->pf_num = PCI_FUNC(pdev->devfn);
  9521. else {/* chip is E2/3*/
  9522. pci_read_config_dword(bp->pdev,
  9523. PCICFG_ME_REGISTER, &pci_cfg_dword);
  9524. bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
  9525. ME_REG_ABS_PF_NUM_SHIFT);
  9526. }
  9527. BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
  9528. bnx2x_set_power_state(bp, PCI_D0);
  9529. /* clean indirect addresses */
  9530. pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
  9531. PCICFG_VENDOR_ID_OFFSET);
  9532. /*
  9533. * Clean the following indirect addresses for all functions since it
  9534. * is not used by the driver.
  9535. */
  9536. REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
  9537. REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
  9538. REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
  9539. REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
  9540. if (chip_is_e1x) {
  9541. REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
  9542. REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
  9543. REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
  9544. REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
  9545. }
  9546. /*
  9547. * Enable internal target-read (in case we are probed after PF FLR).
  9548. * Must be done prior to any BAR read access. Only for 57712 and up
  9549. */
  9550. if (!chip_is_e1x)
  9551. REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
  9552. dev->watchdog_timeo = TX_TIMEOUT;
  9553. dev->netdev_ops = &bnx2x_netdev_ops;
  9554. bnx2x_set_ethtool_ops(dev);
  9555. dev->priv_flags |= IFF_UNICAST_FLT;
  9556. dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  9557. NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
  9558. NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
  9559. NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
  9560. dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  9561. NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
  9562. dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
  9563. if (bp->flags & USING_DAC_FLAG)
  9564. dev->features |= NETIF_F_HIGHDMA;
  9565. /* Add Loopback capability to the device */
  9566. dev->hw_features |= NETIF_F_LOOPBACK;
  9567. #ifdef BCM_DCBNL
  9568. dev->dcbnl_ops = &bnx2x_dcbnl_ops;
  9569. #endif
  9570. /* get_port_hwinfo() will set prtad and mmds properly */
  9571. bp->mdio.prtad = MDIO_PRTAD_NONE;
  9572. bp->mdio.mmds = 0;
  9573. bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
  9574. bp->mdio.dev = dev;
  9575. bp->mdio.mdio_read = bnx2x_mdio_read;
  9576. bp->mdio.mdio_write = bnx2x_mdio_write;
  9577. return 0;
  9578. err_out_release:
  9579. if (atomic_read(&pdev->enable_cnt) == 1)
  9580. pci_release_regions(pdev);
  9581. err_out_disable:
  9582. pci_disable_device(pdev);
  9583. pci_set_drvdata(pdev, NULL);
  9584. err_out:
  9585. return rc;
  9586. }
  9587. static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
  9588. int *width, int *speed)
  9589. {
  9590. u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
  9591. *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
  9592. /* return value of 1=2.5GHz 2=5GHz */
  9593. *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
  9594. }
  9595. static int bnx2x_check_firmware(struct bnx2x *bp)
  9596. {
  9597. const struct firmware *firmware = bp->firmware;
  9598. struct bnx2x_fw_file_hdr *fw_hdr;
  9599. struct bnx2x_fw_file_section *sections;
  9600. u32 offset, len, num_ops;
  9601. u16 *ops_offsets;
  9602. int i;
  9603. const u8 *fw_ver;
  9604. if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
  9605. BNX2X_ERR("Wrong FW size\n");
  9606. return -EINVAL;
  9607. }
  9608. fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
  9609. sections = (struct bnx2x_fw_file_section *)fw_hdr;
  9610. /* Make sure none of the offsets and sizes make us read beyond
  9611. * the end of the firmware data */
  9612. for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
  9613. offset = be32_to_cpu(sections[i].offset);
  9614. len = be32_to_cpu(sections[i].len);
  9615. if (offset + len > firmware->size) {
  9616. BNX2X_ERR("Section %d length is out of bounds\n", i);
  9617. return -EINVAL;
  9618. }
  9619. }
  9620. /* Likewise for the init_ops offsets */
  9621. offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
  9622. ops_offsets = (u16 *)(firmware->data + offset);
  9623. num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
  9624. for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
  9625. if (be16_to_cpu(ops_offsets[i]) > num_ops) {
  9626. BNX2X_ERR("Section offset %d is out of bounds\n", i);
  9627. return -EINVAL;
  9628. }
  9629. }
  9630. /* Check FW version */
  9631. offset = be32_to_cpu(fw_hdr->fw_version.offset);
  9632. fw_ver = firmware->data + offset;
  9633. if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
  9634. (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
  9635. (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
  9636. (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
  9637. BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
  9638. fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
  9639. BCM_5710_FW_MAJOR_VERSION,
  9640. BCM_5710_FW_MINOR_VERSION,
  9641. BCM_5710_FW_REVISION_VERSION,
  9642. BCM_5710_FW_ENGINEERING_VERSION);
  9643. return -EINVAL;
  9644. }
  9645. return 0;
  9646. }
  9647. static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
  9648. {
  9649. const __be32 *source = (const __be32 *)_source;
  9650. u32 *target = (u32 *)_target;
  9651. u32 i;
  9652. for (i = 0; i < n/4; i++)
  9653. target[i] = be32_to_cpu(source[i]);
  9654. }
  9655. /*
  9656. Ops array is stored in the following format:
  9657. {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
  9658. */
  9659. static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
  9660. {
  9661. const __be32 *source = (const __be32 *)_source;
  9662. struct raw_op *target = (struct raw_op *)_target;
  9663. u32 i, j, tmp;
  9664. for (i = 0, j = 0; i < n/8; i++, j += 2) {
  9665. tmp = be32_to_cpu(source[j]);
  9666. target[i].op = (tmp >> 24) & 0xff;
  9667. target[i].offset = tmp & 0xffffff;
  9668. target[i].raw_data = be32_to_cpu(source[j + 1]);
  9669. }
  9670. }
  9671. /* IRO array is stored in the following format:
  9672. * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
  9673. */
  9674. static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
  9675. {
  9676. const __be32 *source = (const __be32 *)_source;
  9677. struct iro *target = (struct iro *)_target;
  9678. u32 i, j, tmp;
  9679. for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
  9680. target[i].base = be32_to_cpu(source[j]);
  9681. j++;
  9682. tmp = be32_to_cpu(source[j]);
  9683. target[i].m1 = (tmp >> 16) & 0xffff;
  9684. target[i].m2 = tmp & 0xffff;
  9685. j++;
  9686. tmp = be32_to_cpu(source[j]);
  9687. target[i].m3 = (tmp >> 16) & 0xffff;
  9688. target[i].size = tmp & 0xffff;
  9689. j++;
  9690. }
  9691. }
  9692. static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
  9693. {
  9694. const __be16 *source = (const __be16 *)_source;
  9695. u16 *target = (u16 *)_target;
  9696. u32 i;
  9697. for (i = 0; i < n/2; i++)
  9698. target[i] = be16_to_cpu(source[i]);
  9699. }
  9700. #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
  9701. do { \
  9702. u32 len = be32_to_cpu(fw_hdr->arr.len); \
  9703. bp->arr = kmalloc(len, GFP_KERNEL); \
  9704. if (!bp->arr) \
  9705. goto lbl; \
  9706. func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
  9707. (u8 *)bp->arr, len); \
  9708. } while (0)
  9709. static int bnx2x_init_firmware(struct bnx2x *bp)
  9710. {
  9711. const char *fw_file_name;
  9712. struct bnx2x_fw_file_hdr *fw_hdr;
  9713. int rc;
  9714. if (bp->firmware)
  9715. return 0;
  9716. if (CHIP_IS_E1(bp))
  9717. fw_file_name = FW_FILE_NAME_E1;
  9718. else if (CHIP_IS_E1H(bp))
  9719. fw_file_name = FW_FILE_NAME_E1H;
  9720. else if (!CHIP_IS_E1x(bp))
  9721. fw_file_name = FW_FILE_NAME_E2;
  9722. else {
  9723. BNX2X_ERR("Unsupported chip revision\n");
  9724. return -EINVAL;
  9725. }
  9726. BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
  9727. rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
  9728. if (rc) {
  9729. BNX2X_ERR("Can't load firmware file %s\n",
  9730. fw_file_name);
  9731. goto request_firmware_exit;
  9732. }
  9733. rc = bnx2x_check_firmware(bp);
  9734. if (rc) {
  9735. BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
  9736. goto request_firmware_exit;
  9737. }
  9738. fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
  9739. /* Initialize the pointers to the init arrays */
  9740. /* Blob */
  9741. BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
  9742. /* Opcodes */
  9743. BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
  9744. /* Offsets */
  9745. BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
  9746. be16_to_cpu_n);
  9747. /* STORMs firmware */
  9748. INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
  9749. be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
  9750. INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
  9751. be32_to_cpu(fw_hdr->tsem_pram_data.offset);
  9752. INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
  9753. be32_to_cpu(fw_hdr->usem_int_table_data.offset);
  9754. INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
  9755. be32_to_cpu(fw_hdr->usem_pram_data.offset);
  9756. INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
  9757. be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
  9758. INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
  9759. be32_to_cpu(fw_hdr->xsem_pram_data.offset);
  9760. INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
  9761. be32_to_cpu(fw_hdr->csem_int_table_data.offset);
  9762. INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
  9763. be32_to_cpu(fw_hdr->csem_pram_data.offset);
  9764. /* IRO */
  9765. BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
  9766. return 0;
  9767. iro_alloc_err:
  9768. kfree(bp->init_ops_offsets);
  9769. init_offsets_alloc_err:
  9770. kfree(bp->init_ops);
  9771. init_ops_alloc_err:
  9772. kfree(bp->init_data);
  9773. request_firmware_exit:
  9774. release_firmware(bp->firmware);
  9775. bp->firmware = NULL;
  9776. return rc;
  9777. }
  9778. static void bnx2x_release_firmware(struct bnx2x *bp)
  9779. {
  9780. kfree(bp->init_ops_offsets);
  9781. kfree(bp->init_ops);
  9782. kfree(bp->init_data);
  9783. release_firmware(bp->firmware);
  9784. bp->firmware = NULL;
  9785. }
  9786. static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
  9787. .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
  9788. .init_hw_cmn = bnx2x_init_hw_common,
  9789. .init_hw_port = bnx2x_init_hw_port,
  9790. .init_hw_func = bnx2x_init_hw_func,
  9791. .reset_hw_cmn = bnx2x_reset_common,
  9792. .reset_hw_port = bnx2x_reset_port,
  9793. .reset_hw_func = bnx2x_reset_func,
  9794. .gunzip_init = bnx2x_gunzip_init,
  9795. .gunzip_end = bnx2x_gunzip_end,
  9796. .init_fw = bnx2x_init_firmware,
  9797. .release_fw = bnx2x_release_firmware,
  9798. };
  9799. void bnx2x__init_func_obj(struct bnx2x *bp)
  9800. {
  9801. /* Prepare DMAE related driver resources */
  9802. bnx2x_setup_dmae(bp);
  9803. bnx2x_init_func_obj(bp, &bp->func_obj,
  9804. bnx2x_sp(bp, func_rdata),
  9805. bnx2x_sp_mapping(bp, func_rdata),
  9806. bnx2x_sp(bp, func_afex_rdata),
  9807. bnx2x_sp_mapping(bp, func_afex_rdata),
  9808. &bnx2x_func_sp_drv);
  9809. }
  9810. /* must be called after sriov-enable */
  9811. static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
  9812. {
  9813. int cid_count = BNX2X_L2_MAX_CID(bp);
  9814. #ifdef BCM_CNIC
  9815. cid_count += CNIC_CID_MAX;
  9816. #endif
  9817. return roundup(cid_count, QM_CID_ROUND);
  9818. }
  9819. /**
  9820. * bnx2x_get_num_none_def_sbs - return the number of none default SBs
  9821. *
  9822. * @dev: pci device
  9823. *
  9824. */
  9825. static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
  9826. {
  9827. int pos;
  9828. u16 control;
  9829. pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
  9830. /*
  9831. * If MSI-X is not supported - return number of SBs needed to support
  9832. * one fast path queue: one FP queue + SB for CNIC
  9833. */
  9834. if (!pos)
  9835. return 1 + CNIC_PRESENT;
  9836. /*
  9837. * The value in the PCI configuration space is the index of the last
  9838. * entry, namely one less than the actual size of the table, which is
  9839. * exactly what we want to return from this function: number of all SBs
  9840. * without the default SB.
  9841. */
  9842. pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
  9843. return control & PCI_MSIX_FLAGS_QSIZE;
  9844. }
  9845. static int __devinit bnx2x_init_one(struct pci_dev *pdev,
  9846. const struct pci_device_id *ent)
  9847. {
  9848. struct net_device *dev = NULL;
  9849. struct bnx2x *bp;
  9850. int pcie_width, pcie_speed;
  9851. int rc, max_non_def_sbs;
  9852. int rx_count, tx_count, rss_count, doorbell_size;
  9853. /*
  9854. * An estimated maximum supported CoS number according to the chip
  9855. * version.
  9856. * We will try to roughly estimate the maximum number of CoSes this chip
  9857. * may support in order to minimize the memory allocated for Tx
  9858. * netdev_queue's. This number will be accurately calculated during the
  9859. * initialization of bp->max_cos based on the chip versions AND chip
  9860. * revision in the bnx2x_init_bp().
  9861. */
  9862. u8 max_cos_est = 0;
  9863. switch (ent->driver_data) {
  9864. case BCM57710:
  9865. case BCM57711:
  9866. case BCM57711E:
  9867. max_cos_est = BNX2X_MULTI_TX_COS_E1X;
  9868. break;
  9869. case BCM57712:
  9870. case BCM57712_MF:
  9871. max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
  9872. break;
  9873. case BCM57800:
  9874. case BCM57800_MF:
  9875. case BCM57810:
  9876. case BCM57810_MF:
  9877. case BCM57840_O:
  9878. case BCM57840_4_10:
  9879. case BCM57840_2_20:
  9880. case BCM57840_MFO:
  9881. case BCM57840_MF:
  9882. case BCM57811:
  9883. case BCM57811_MF:
  9884. max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
  9885. break;
  9886. default:
  9887. pr_err("Unknown board_type (%ld), aborting\n",
  9888. ent->driver_data);
  9889. return -ENODEV;
  9890. }
  9891. max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
  9892. WARN_ON(!max_non_def_sbs);
  9893. /* Maximum number of RSS queues: one IGU SB goes to CNIC */
  9894. rss_count = max_non_def_sbs - CNIC_PRESENT;
  9895. /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
  9896. rx_count = rss_count + FCOE_PRESENT;
  9897. /*
  9898. * Maximum number of netdev Tx queues:
  9899. * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
  9900. */
  9901. tx_count = rss_count * max_cos_est + FCOE_PRESENT;
  9902. /* dev zeroed in init_etherdev */
  9903. dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
  9904. if (!dev)
  9905. return -ENOMEM;
  9906. bp = netdev_priv(dev);
  9907. bp->igu_sb_cnt = max_non_def_sbs;
  9908. bp->msg_enable = debug;
  9909. pci_set_drvdata(pdev, dev);
  9910. rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
  9911. if (rc < 0) {
  9912. free_netdev(dev);
  9913. return rc;
  9914. }
  9915. BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
  9916. BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
  9917. tx_count, rx_count);
  9918. rc = bnx2x_init_bp(bp);
  9919. if (rc)
  9920. goto init_one_exit;
  9921. /*
  9922. * Map doorbels here as we need the real value of bp->max_cos which
  9923. * is initialized in bnx2x_init_bp().
  9924. */
  9925. doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
  9926. if (doorbell_size > pci_resource_len(pdev, 2)) {
  9927. dev_err(&bp->pdev->dev,
  9928. "Cannot map doorbells, bar size too small, aborting\n");
  9929. rc = -ENOMEM;
  9930. goto init_one_exit;
  9931. }
  9932. bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
  9933. doorbell_size);
  9934. if (!bp->doorbells) {
  9935. dev_err(&bp->pdev->dev,
  9936. "Cannot map doorbell space, aborting\n");
  9937. rc = -ENOMEM;
  9938. goto init_one_exit;
  9939. }
  9940. /* calc qm_cid_count */
  9941. bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
  9942. #ifdef BCM_CNIC
  9943. /* disable FCOE L2 queue for E1x */
  9944. if (CHIP_IS_E1x(bp))
  9945. bp->flags |= NO_FCOE_FLAG;
  9946. /* disable FCOE for 57840 device, until FW supports it */
  9947. switch (ent->driver_data) {
  9948. case BCM57840_O:
  9949. case BCM57840_4_10:
  9950. case BCM57840_2_20:
  9951. case BCM57840_MFO:
  9952. case BCM57840_MF:
  9953. bp->flags |= NO_FCOE_FLAG;
  9954. }
  9955. #endif
  9956. /* Set bp->num_queues for MSI-X mode*/
  9957. bnx2x_set_num_queues(bp);
  9958. /* Configure interrupt mode: try to enable MSI-X/MSI if
  9959. * needed.
  9960. */
  9961. bnx2x_set_int_mode(bp);
  9962. rc = register_netdev(dev);
  9963. if (rc) {
  9964. dev_err(&pdev->dev, "Cannot register net device\n");
  9965. goto init_one_exit;
  9966. }
  9967. #ifdef BCM_CNIC
  9968. if (!NO_FCOE(bp)) {
  9969. /* Add storage MAC address */
  9970. rtnl_lock();
  9971. dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
  9972. rtnl_unlock();
  9973. }
  9974. #endif
  9975. bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
  9976. BNX2X_DEV_INFO(
  9977. "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
  9978. board_info[ent->driver_data].name,
  9979. (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
  9980. pcie_width,
  9981. ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
  9982. (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
  9983. "5GHz (Gen2)" : "2.5GHz",
  9984. dev->base_addr, bp->pdev->irq, dev->dev_addr);
  9985. return 0;
  9986. init_one_exit:
  9987. if (bp->regview)
  9988. iounmap(bp->regview);
  9989. if (bp->doorbells)
  9990. iounmap(bp->doorbells);
  9991. free_netdev(dev);
  9992. if (atomic_read(&pdev->enable_cnt) == 1)
  9993. pci_release_regions(pdev);
  9994. pci_disable_device(pdev);
  9995. pci_set_drvdata(pdev, NULL);
  9996. return rc;
  9997. }
  9998. static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
  9999. {
  10000. struct net_device *dev = pci_get_drvdata(pdev);
  10001. struct bnx2x *bp;
  10002. if (!dev) {
  10003. dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
  10004. return;
  10005. }
  10006. bp = netdev_priv(dev);
  10007. #ifdef BCM_CNIC
  10008. /* Delete storage MAC address */
  10009. if (!NO_FCOE(bp)) {
  10010. rtnl_lock();
  10011. dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
  10012. rtnl_unlock();
  10013. }
  10014. #endif
  10015. #ifdef BCM_DCBNL
  10016. /* Delete app tlvs from dcbnl */
  10017. bnx2x_dcbnl_update_applist(bp, true);
  10018. #endif
  10019. unregister_netdev(dev);
  10020. /* Power on: we can't let PCI layer write to us while we are in D3 */
  10021. bnx2x_set_power_state(bp, PCI_D0);
  10022. /* Disable MSI/MSI-X */
  10023. bnx2x_disable_msi(bp);
  10024. /* Power off */
  10025. bnx2x_set_power_state(bp, PCI_D3hot);
  10026. /* Make sure RESET task is not scheduled before continuing */
  10027. cancel_delayed_work_sync(&bp->sp_rtnl_task);
  10028. if (bp->regview)
  10029. iounmap(bp->regview);
  10030. if (bp->doorbells)
  10031. iounmap(bp->doorbells);
  10032. bnx2x_release_firmware(bp);
  10033. bnx2x_free_mem_bp(bp);
  10034. free_netdev(dev);
  10035. if (atomic_read(&pdev->enable_cnt) == 1)
  10036. pci_release_regions(pdev);
  10037. pci_disable_device(pdev);
  10038. pci_set_drvdata(pdev, NULL);
  10039. }
  10040. static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
  10041. {
  10042. int i;
  10043. bp->state = BNX2X_STATE_ERROR;
  10044. bp->rx_mode = BNX2X_RX_MODE_NONE;
  10045. #ifdef BCM_CNIC
  10046. bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
  10047. #endif
  10048. /* Stop Tx */
  10049. bnx2x_tx_disable(bp);
  10050. bnx2x_netif_stop(bp, 0);
  10051. /* Delete all NAPI objects */
  10052. bnx2x_del_all_napi(bp);
  10053. del_timer_sync(&bp->timer);
  10054. bnx2x_stats_handle(bp, STATS_EVENT_STOP);
  10055. /* Release IRQs */
  10056. bnx2x_free_irq(bp);
  10057. /* Free SKBs, SGEs, TPA pool and driver internals */
  10058. bnx2x_free_skbs(bp);
  10059. for_each_rx_queue(bp, i)
  10060. bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
  10061. bnx2x_free_mem(bp);
  10062. bp->state = BNX2X_STATE_CLOSED;
  10063. netif_carrier_off(bp->dev);
  10064. return 0;
  10065. }
  10066. static void bnx2x_eeh_recover(struct bnx2x *bp)
  10067. {
  10068. u32 val;
  10069. mutex_init(&bp->port.phy_mutex);
  10070. val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
  10071. if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
  10072. != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
  10073. BNX2X_ERR("BAD MCP validity signature\n");
  10074. }
  10075. /**
  10076. * bnx2x_io_error_detected - called when PCI error is detected
  10077. * @pdev: Pointer to PCI device
  10078. * @state: The current pci connection state
  10079. *
  10080. * This function is called after a PCI bus error affecting
  10081. * this device has been detected.
  10082. */
  10083. static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
  10084. pci_channel_state_t state)
  10085. {
  10086. struct net_device *dev = pci_get_drvdata(pdev);
  10087. struct bnx2x *bp = netdev_priv(dev);
  10088. rtnl_lock();
  10089. netif_device_detach(dev);
  10090. if (state == pci_channel_io_perm_failure) {
  10091. rtnl_unlock();
  10092. return PCI_ERS_RESULT_DISCONNECT;
  10093. }
  10094. if (netif_running(dev))
  10095. bnx2x_eeh_nic_unload(bp);
  10096. pci_disable_device(pdev);
  10097. rtnl_unlock();
  10098. /* Request a slot reset */
  10099. return PCI_ERS_RESULT_NEED_RESET;
  10100. }
  10101. /**
  10102. * bnx2x_io_slot_reset - called after the PCI bus has been reset
  10103. * @pdev: Pointer to PCI device
  10104. *
  10105. * Restart the card from scratch, as if from a cold-boot.
  10106. */
  10107. static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
  10108. {
  10109. struct net_device *dev = pci_get_drvdata(pdev);
  10110. struct bnx2x *bp = netdev_priv(dev);
  10111. rtnl_lock();
  10112. if (pci_enable_device(pdev)) {
  10113. dev_err(&pdev->dev,
  10114. "Cannot re-enable PCI device after reset\n");
  10115. rtnl_unlock();
  10116. return PCI_ERS_RESULT_DISCONNECT;
  10117. }
  10118. pci_set_master(pdev);
  10119. pci_restore_state(pdev);
  10120. if (netif_running(dev))
  10121. bnx2x_set_power_state(bp, PCI_D0);
  10122. rtnl_unlock();
  10123. return PCI_ERS_RESULT_RECOVERED;
  10124. }
  10125. /**
  10126. * bnx2x_io_resume - called when traffic can start flowing again
  10127. * @pdev: Pointer to PCI device
  10128. *
  10129. * This callback is called when the error recovery driver tells us that
  10130. * its OK to resume normal operation.
  10131. */
  10132. static void bnx2x_io_resume(struct pci_dev *pdev)
  10133. {
  10134. struct net_device *dev = pci_get_drvdata(pdev);
  10135. struct bnx2x *bp = netdev_priv(dev);
  10136. if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
  10137. netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
  10138. return;
  10139. }
  10140. rtnl_lock();
  10141. bnx2x_eeh_recover(bp);
  10142. if (netif_running(dev))
  10143. bnx2x_nic_load(bp, LOAD_NORMAL);
  10144. netif_device_attach(dev);
  10145. rtnl_unlock();
  10146. }
  10147. static const struct pci_error_handlers bnx2x_err_handler = {
  10148. .error_detected = bnx2x_io_error_detected,
  10149. .slot_reset = bnx2x_io_slot_reset,
  10150. .resume = bnx2x_io_resume,
  10151. };
  10152. static struct pci_driver bnx2x_pci_driver = {
  10153. .name = DRV_MODULE_NAME,
  10154. .id_table = bnx2x_pci_tbl,
  10155. .probe = bnx2x_init_one,
  10156. .remove = __devexit_p(bnx2x_remove_one),
  10157. .suspend = bnx2x_suspend,
  10158. .resume = bnx2x_resume,
  10159. .err_handler = &bnx2x_err_handler,
  10160. };
  10161. static int __init bnx2x_init(void)
  10162. {
  10163. int ret;
  10164. pr_info("%s", version);
  10165. bnx2x_wq = create_singlethread_workqueue("bnx2x");
  10166. if (bnx2x_wq == NULL) {
  10167. pr_err("Cannot create workqueue\n");
  10168. return -ENOMEM;
  10169. }
  10170. ret = pci_register_driver(&bnx2x_pci_driver);
  10171. if (ret) {
  10172. pr_err("Cannot register driver\n");
  10173. destroy_workqueue(bnx2x_wq);
  10174. }
  10175. return ret;
  10176. }
  10177. static void __exit bnx2x_cleanup(void)
  10178. {
  10179. struct list_head *pos, *q;
  10180. pci_unregister_driver(&bnx2x_pci_driver);
  10181. destroy_workqueue(bnx2x_wq);
  10182. /* Free globablly allocated resources */
  10183. list_for_each_safe(pos, q, &bnx2x_prev_list) {
  10184. struct bnx2x_prev_path_list *tmp =
  10185. list_entry(pos, struct bnx2x_prev_path_list, list);
  10186. list_del(pos);
  10187. kfree(tmp);
  10188. }
  10189. }
  10190. void bnx2x_notify_link_changed(struct bnx2x *bp)
  10191. {
  10192. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
  10193. }
  10194. module_init(bnx2x_init);
  10195. module_exit(bnx2x_cleanup);
  10196. #ifdef BCM_CNIC
  10197. /**
  10198. * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
  10199. *
  10200. * @bp: driver handle
  10201. * @set: set or clear the CAM entry
  10202. *
  10203. * This function will wait until the ramdord completion returns.
  10204. * Return 0 if success, -ENODEV if ramrod doesn't return.
  10205. */
  10206. static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
  10207. {
  10208. unsigned long ramrod_flags = 0;
  10209. __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
  10210. return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
  10211. &bp->iscsi_l2_mac_obj, true,
  10212. BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
  10213. }
  10214. /* count denotes the number of new completions we have seen */
  10215. static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
  10216. {
  10217. struct eth_spe *spe;
  10218. int cxt_index, cxt_offset;
  10219. #ifdef BNX2X_STOP_ON_ERROR
  10220. if (unlikely(bp->panic))
  10221. return;
  10222. #endif
  10223. spin_lock_bh(&bp->spq_lock);
  10224. BUG_ON(bp->cnic_spq_pending < count);
  10225. bp->cnic_spq_pending -= count;
  10226. for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
  10227. u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
  10228. & SPE_HDR_CONN_TYPE) >>
  10229. SPE_HDR_CONN_TYPE_SHIFT;
  10230. u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
  10231. >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
  10232. /* Set validation for iSCSI L2 client before sending SETUP
  10233. * ramrod
  10234. */
  10235. if (type == ETH_CONNECTION_TYPE) {
  10236. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
  10237. cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
  10238. ILT_PAGE_CIDS;
  10239. cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
  10240. (cxt_index * ILT_PAGE_CIDS);
  10241. bnx2x_set_ctx_validation(bp,
  10242. &bp->context[cxt_index].
  10243. vcxt[cxt_offset].eth,
  10244. BNX2X_ISCSI_ETH_CID(bp));
  10245. }
  10246. }
  10247. /*
  10248. * There may be not more than 8 L2, not more than 8 L5 SPEs
  10249. * and in the air. We also check that number of outstanding
  10250. * COMMON ramrods is not more than the EQ and SPQ can
  10251. * accommodate.
  10252. */
  10253. if (type == ETH_CONNECTION_TYPE) {
  10254. if (!atomic_read(&bp->cq_spq_left))
  10255. break;
  10256. else
  10257. atomic_dec(&bp->cq_spq_left);
  10258. } else if (type == NONE_CONNECTION_TYPE) {
  10259. if (!atomic_read(&bp->eq_spq_left))
  10260. break;
  10261. else
  10262. atomic_dec(&bp->eq_spq_left);
  10263. } else if ((type == ISCSI_CONNECTION_TYPE) ||
  10264. (type == FCOE_CONNECTION_TYPE)) {
  10265. if (bp->cnic_spq_pending >=
  10266. bp->cnic_eth_dev.max_kwqe_pending)
  10267. break;
  10268. else
  10269. bp->cnic_spq_pending++;
  10270. } else {
  10271. BNX2X_ERR("Unknown SPE type: %d\n", type);
  10272. bnx2x_panic();
  10273. break;
  10274. }
  10275. spe = bnx2x_sp_get_next(bp);
  10276. *spe = *bp->cnic_kwq_cons;
  10277. DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
  10278. bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
  10279. if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
  10280. bp->cnic_kwq_cons = bp->cnic_kwq;
  10281. else
  10282. bp->cnic_kwq_cons++;
  10283. }
  10284. bnx2x_sp_prod_update(bp);
  10285. spin_unlock_bh(&bp->spq_lock);
  10286. }
  10287. static int bnx2x_cnic_sp_queue(struct net_device *dev,
  10288. struct kwqe_16 *kwqes[], u32 count)
  10289. {
  10290. struct bnx2x *bp = netdev_priv(dev);
  10291. int i;
  10292. #ifdef BNX2X_STOP_ON_ERROR
  10293. if (unlikely(bp->panic)) {
  10294. BNX2X_ERR("Can't post to SP queue while panic\n");
  10295. return -EIO;
  10296. }
  10297. #endif
  10298. if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
  10299. (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
  10300. BNX2X_ERR("Handling parity error recovery. Try again later\n");
  10301. return -EAGAIN;
  10302. }
  10303. spin_lock_bh(&bp->spq_lock);
  10304. for (i = 0; i < count; i++) {
  10305. struct eth_spe *spe = (struct eth_spe *)kwqes[i];
  10306. if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
  10307. break;
  10308. *bp->cnic_kwq_prod = *spe;
  10309. bp->cnic_kwq_pending++;
  10310. DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
  10311. spe->hdr.conn_and_cmd_data, spe->hdr.type,
  10312. spe->data.update_data_addr.hi,
  10313. spe->data.update_data_addr.lo,
  10314. bp->cnic_kwq_pending);
  10315. if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
  10316. bp->cnic_kwq_prod = bp->cnic_kwq;
  10317. else
  10318. bp->cnic_kwq_prod++;
  10319. }
  10320. spin_unlock_bh(&bp->spq_lock);
  10321. if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
  10322. bnx2x_cnic_sp_post(bp, 0);
  10323. return i;
  10324. }
  10325. static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
  10326. {
  10327. struct cnic_ops *c_ops;
  10328. int rc = 0;
  10329. mutex_lock(&bp->cnic_mutex);
  10330. c_ops = rcu_dereference_protected(bp->cnic_ops,
  10331. lockdep_is_held(&bp->cnic_mutex));
  10332. if (c_ops)
  10333. rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
  10334. mutex_unlock(&bp->cnic_mutex);
  10335. return rc;
  10336. }
  10337. static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
  10338. {
  10339. struct cnic_ops *c_ops;
  10340. int rc = 0;
  10341. rcu_read_lock();
  10342. c_ops = rcu_dereference(bp->cnic_ops);
  10343. if (c_ops)
  10344. rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
  10345. rcu_read_unlock();
  10346. return rc;
  10347. }
  10348. /*
  10349. * for commands that have no data
  10350. */
  10351. int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
  10352. {
  10353. struct cnic_ctl_info ctl = {0};
  10354. ctl.cmd = cmd;
  10355. return bnx2x_cnic_ctl_send(bp, &ctl);
  10356. }
  10357. static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
  10358. {
  10359. struct cnic_ctl_info ctl = {0};
  10360. /* first we tell CNIC and only then we count this as a completion */
  10361. ctl.cmd = CNIC_CTL_COMPLETION_CMD;
  10362. ctl.data.comp.cid = cid;
  10363. ctl.data.comp.error = err;
  10364. bnx2x_cnic_ctl_send_bh(bp, &ctl);
  10365. bnx2x_cnic_sp_post(bp, 0);
  10366. }
  10367. /* Called with netif_addr_lock_bh() taken.
  10368. * Sets an rx_mode config for an iSCSI ETH client.
  10369. * Doesn't block.
  10370. * Completion should be checked outside.
  10371. */
  10372. static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
  10373. {
  10374. unsigned long accept_flags = 0, ramrod_flags = 0;
  10375. u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
  10376. int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
  10377. if (start) {
  10378. /* Start accepting on iSCSI L2 ring. Accept all multicasts
  10379. * because it's the only way for UIO Queue to accept
  10380. * multicasts (in non-promiscuous mode only one Queue per
  10381. * function will receive multicast packets (leading in our
  10382. * case).
  10383. */
  10384. __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
  10385. __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
  10386. __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
  10387. __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
  10388. /* Clear STOP_PENDING bit if START is requested */
  10389. clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
  10390. sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
  10391. } else
  10392. /* Clear START_PENDING bit if STOP is requested */
  10393. clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
  10394. if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
  10395. set_bit(sched_state, &bp->sp_state);
  10396. else {
  10397. __set_bit(RAMROD_RX, &ramrod_flags);
  10398. bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
  10399. ramrod_flags);
  10400. }
  10401. }
  10402. static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
  10403. {
  10404. struct bnx2x *bp = netdev_priv(dev);
  10405. int rc = 0;
  10406. switch (ctl->cmd) {
  10407. case DRV_CTL_CTXTBL_WR_CMD: {
  10408. u32 index = ctl->data.io.offset;
  10409. dma_addr_t addr = ctl->data.io.dma_addr;
  10410. bnx2x_ilt_wr(bp, index, addr);
  10411. break;
  10412. }
  10413. case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
  10414. int count = ctl->data.credit.credit_count;
  10415. bnx2x_cnic_sp_post(bp, count);
  10416. break;
  10417. }
  10418. /* rtnl_lock is held. */
  10419. case DRV_CTL_START_L2_CMD: {
  10420. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  10421. unsigned long sp_bits = 0;
  10422. /* Configure the iSCSI classification object */
  10423. bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
  10424. cp->iscsi_l2_client_id,
  10425. cp->iscsi_l2_cid, BP_FUNC(bp),
  10426. bnx2x_sp(bp, mac_rdata),
  10427. bnx2x_sp_mapping(bp, mac_rdata),
  10428. BNX2X_FILTER_MAC_PENDING,
  10429. &bp->sp_state, BNX2X_OBJ_TYPE_RX,
  10430. &bp->macs_pool);
  10431. /* Set iSCSI MAC address */
  10432. rc = bnx2x_set_iscsi_eth_mac_addr(bp);
  10433. if (rc)
  10434. break;
  10435. mmiowb();
  10436. barrier();
  10437. /* Start accepting on iSCSI L2 ring */
  10438. netif_addr_lock_bh(dev);
  10439. bnx2x_set_iscsi_eth_rx_mode(bp, true);
  10440. netif_addr_unlock_bh(dev);
  10441. /* bits to wait on */
  10442. __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
  10443. __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
  10444. if (!bnx2x_wait_sp_comp(bp, sp_bits))
  10445. BNX2X_ERR("rx_mode completion timed out!\n");
  10446. break;
  10447. }
  10448. /* rtnl_lock is held. */
  10449. case DRV_CTL_STOP_L2_CMD: {
  10450. unsigned long sp_bits = 0;
  10451. /* Stop accepting on iSCSI L2 ring */
  10452. netif_addr_lock_bh(dev);
  10453. bnx2x_set_iscsi_eth_rx_mode(bp, false);
  10454. netif_addr_unlock_bh(dev);
  10455. /* bits to wait on */
  10456. __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
  10457. __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
  10458. if (!bnx2x_wait_sp_comp(bp, sp_bits))
  10459. BNX2X_ERR("rx_mode completion timed out!\n");
  10460. mmiowb();
  10461. barrier();
  10462. /* Unset iSCSI L2 MAC */
  10463. rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
  10464. BNX2X_ISCSI_ETH_MAC, true);
  10465. break;
  10466. }
  10467. case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
  10468. int count = ctl->data.credit.credit_count;
  10469. smp_mb__before_atomic_inc();
  10470. atomic_add(count, &bp->cq_spq_left);
  10471. smp_mb__after_atomic_inc();
  10472. break;
  10473. }
  10474. case DRV_CTL_ULP_REGISTER_CMD: {
  10475. int ulp_type = ctl->data.register_data.ulp_type;
  10476. if (CHIP_IS_E3(bp)) {
  10477. int idx = BP_FW_MB_IDX(bp);
  10478. u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
  10479. int path = BP_PATH(bp);
  10480. int port = BP_PORT(bp);
  10481. int i;
  10482. u32 scratch_offset;
  10483. u32 *host_addr;
  10484. /* first write capability to shmem2 */
  10485. if (ulp_type == CNIC_ULP_ISCSI)
  10486. cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
  10487. else if (ulp_type == CNIC_ULP_FCOE)
  10488. cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
  10489. SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
  10490. if ((ulp_type != CNIC_ULP_FCOE) ||
  10491. (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
  10492. (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
  10493. break;
  10494. /* if reached here - should write fcoe capabilities */
  10495. scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
  10496. if (!scratch_offset)
  10497. break;
  10498. scratch_offset += offsetof(struct glob_ncsi_oem_data,
  10499. fcoe_features[path][port]);
  10500. host_addr = (u32 *) &(ctl->data.register_data.
  10501. fcoe_features);
  10502. for (i = 0; i < sizeof(struct fcoe_capabilities);
  10503. i += 4)
  10504. REG_WR(bp, scratch_offset + i,
  10505. *(host_addr + i/4));
  10506. }
  10507. break;
  10508. }
  10509. case DRV_CTL_ULP_UNREGISTER_CMD: {
  10510. int ulp_type = ctl->data.ulp_type;
  10511. if (CHIP_IS_E3(bp)) {
  10512. int idx = BP_FW_MB_IDX(bp);
  10513. u32 cap;
  10514. cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
  10515. if (ulp_type == CNIC_ULP_ISCSI)
  10516. cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
  10517. else if (ulp_type == CNIC_ULP_FCOE)
  10518. cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
  10519. SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
  10520. }
  10521. break;
  10522. }
  10523. default:
  10524. BNX2X_ERR("unknown command %x\n", ctl->cmd);
  10525. rc = -EINVAL;
  10526. }
  10527. return rc;
  10528. }
  10529. void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
  10530. {
  10531. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  10532. if (bp->flags & USING_MSIX_FLAG) {
  10533. cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
  10534. cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
  10535. cp->irq_arr[0].vector = bp->msix_table[1].vector;
  10536. } else {
  10537. cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
  10538. cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
  10539. }
  10540. if (!CHIP_IS_E1x(bp))
  10541. cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
  10542. else
  10543. cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
  10544. cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
  10545. cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
  10546. cp->irq_arr[1].status_blk = bp->def_status_blk;
  10547. cp->irq_arr[1].status_blk_num = DEF_SB_ID;
  10548. cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
  10549. cp->num_irq = 2;
  10550. }
  10551. void bnx2x_setup_cnic_info(struct bnx2x *bp)
  10552. {
  10553. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  10554. cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
  10555. bnx2x_cid_ilt_lines(bp);
  10556. cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
  10557. cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
  10558. cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
  10559. if (NO_ISCSI_OOO(bp))
  10560. cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
  10561. }
  10562. static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
  10563. void *data)
  10564. {
  10565. struct bnx2x *bp = netdev_priv(dev);
  10566. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  10567. if (ops == NULL) {
  10568. BNX2X_ERR("NULL ops received\n");
  10569. return -EINVAL;
  10570. }
  10571. bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
  10572. if (!bp->cnic_kwq)
  10573. return -ENOMEM;
  10574. bp->cnic_kwq_cons = bp->cnic_kwq;
  10575. bp->cnic_kwq_prod = bp->cnic_kwq;
  10576. bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
  10577. bp->cnic_spq_pending = 0;
  10578. bp->cnic_kwq_pending = 0;
  10579. bp->cnic_data = data;
  10580. cp->num_irq = 0;
  10581. cp->drv_state |= CNIC_DRV_STATE_REGD;
  10582. cp->iro_arr = bp->iro_arr;
  10583. bnx2x_setup_cnic_irq_info(bp);
  10584. rcu_assign_pointer(bp->cnic_ops, ops);
  10585. return 0;
  10586. }
  10587. static int bnx2x_unregister_cnic(struct net_device *dev)
  10588. {
  10589. struct bnx2x *bp = netdev_priv(dev);
  10590. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  10591. mutex_lock(&bp->cnic_mutex);
  10592. cp->drv_state = 0;
  10593. RCU_INIT_POINTER(bp->cnic_ops, NULL);
  10594. mutex_unlock(&bp->cnic_mutex);
  10595. synchronize_rcu();
  10596. kfree(bp->cnic_kwq);
  10597. bp->cnic_kwq = NULL;
  10598. return 0;
  10599. }
  10600. struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
  10601. {
  10602. struct bnx2x *bp = netdev_priv(dev);
  10603. struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
  10604. /* If both iSCSI and FCoE are disabled - return NULL in
  10605. * order to indicate CNIC that it should not try to work
  10606. * with this device.
  10607. */
  10608. if (NO_ISCSI(bp) && NO_FCOE(bp))
  10609. return NULL;
  10610. cp->drv_owner = THIS_MODULE;
  10611. cp->chip_id = CHIP_ID(bp);
  10612. cp->pdev = bp->pdev;
  10613. cp->io_base = bp->regview;
  10614. cp->io_base2 = bp->doorbells;
  10615. cp->max_kwqe_pending = 8;
  10616. cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
  10617. cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
  10618. bnx2x_cid_ilt_lines(bp);
  10619. cp->ctx_tbl_len = CNIC_ILT_LINES;
  10620. cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
  10621. cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
  10622. cp->drv_ctl = bnx2x_drv_ctl;
  10623. cp->drv_register_cnic = bnx2x_register_cnic;
  10624. cp->drv_unregister_cnic = bnx2x_unregister_cnic;
  10625. cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
  10626. cp->iscsi_l2_client_id =
  10627. bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
  10628. cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
  10629. if (NO_ISCSI_OOO(bp))
  10630. cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
  10631. if (NO_ISCSI(bp))
  10632. cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
  10633. if (NO_FCOE(bp))
  10634. cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
  10635. BNX2X_DEV_INFO(
  10636. "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
  10637. cp->ctx_blk_size,
  10638. cp->ctx_tbl_offset,
  10639. cp->ctx_tbl_len,
  10640. cp->starting_cid);
  10641. return cp;
  10642. }
  10643. EXPORT_SYMBOL(bnx2x_cnic_probe);
  10644. #endif /* BCM_CNIC */