sh_mobile_meram.c 18 KB

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  1. /*
  2. * SuperH Mobile MERAM Driver for SuperH Mobile LCDC Driver
  3. *
  4. * Copyright (c) 2011 Damian Hobson-Garcia <dhobsong@igel.co.jp>
  5. * Takanari Hayama <taki@igel.co.jp>
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/device.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/io.h>
  16. #include <linux/slab.h>
  17. #include <linux/platform_device.h>
  18. #include <video/sh_mobile_meram.h>
  19. /* meram registers */
  20. #define MEVCR1 0x4
  21. #define MEVCR1_RST (1 << 31)
  22. #define MEVCR1_WD (1 << 30)
  23. #define MEVCR1_AMD1 (1 << 29)
  24. #define MEVCR1_AMD0 (1 << 28)
  25. #define MEQSEL1 0x40
  26. #define MEQSEL2 0x44
  27. #define MExxCTL 0x400
  28. #define MExxCTL_BV (1 << 31)
  29. #define MExxCTL_BSZ_SHIFT 28
  30. #define MExxCTL_MSAR_MASK (0x7ff << MExxCTL_MSAR_SHIFT)
  31. #define MExxCTL_MSAR_SHIFT 16
  32. #define MExxCTL_NXT_MASK (0x1f << MExxCTL_NXT_SHIFT)
  33. #define MExxCTL_NXT_SHIFT 11
  34. #define MExxCTL_WD1 (1 << 10)
  35. #define MExxCTL_WD0 (1 << 9)
  36. #define MExxCTL_WS (1 << 8)
  37. #define MExxCTL_CB (1 << 7)
  38. #define MExxCTL_WBF (1 << 6)
  39. #define MExxCTL_WF (1 << 5)
  40. #define MExxCTL_RF (1 << 4)
  41. #define MExxCTL_CM (1 << 3)
  42. #define MExxCTL_MD_READ (1 << 0)
  43. #define MExxCTL_MD_WRITE (2 << 0)
  44. #define MExxCTL_MD_ICB_WB (3 << 0)
  45. #define MExxCTL_MD_ICB (4 << 0)
  46. #define MExxCTL_MD_FB (7 << 0)
  47. #define MExxCTL_MD_MASK (7 << 0)
  48. #define MExxBSIZE 0x404
  49. #define MExxBSIZE_RCNT_SHIFT 28
  50. #define MExxBSIZE_YSZM1_SHIFT 16
  51. #define MExxBSIZE_XSZM1_SHIFT 0
  52. #define MExxMNCF 0x408
  53. #define MExxMNCF_KWBNM_SHIFT 28
  54. #define MExxMNCF_KRBNM_SHIFT 24
  55. #define MExxMNCF_BNM_SHIFT 16
  56. #define MExxMNCF_XBV (1 << 15)
  57. #define MExxMNCF_CPL_YCBCR444 (1 << 12)
  58. #define MExxMNCF_CPL_YCBCR420 (2 << 12)
  59. #define MExxMNCF_CPL_YCBCR422 (3 << 12)
  60. #define MExxMNCF_CPL_MSK (3 << 12)
  61. #define MExxMNCF_BL (1 << 2)
  62. #define MExxMNCF_LNM_SHIFT 0
  63. #define MExxSARA 0x410
  64. #define MExxSARB 0x414
  65. #define MExxSBSIZE 0x418
  66. #define MExxSBSIZE_HDV (1 << 31)
  67. #define MExxSBSIZE_HSZ16 (0 << 28)
  68. #define MExxSBSIZE_HSZ32 (1 << 28)
  69. #define MExxSBSIZE_HSZ64 (2 << 28)
  70. #define MExxSBSIZE_HSZ128 (3 << 28)
  71. #define MExxSBSIZE_SBSIZZ_SHIFT 0
  72. #define MERAM_MExxCTL_VAL(next, addr) \
  73. ((((next) << MExxCTL_NXT_SHIFT) & MExxCTL_NXT_MASK) | \
  74. (((addr) << MExxCTL_MSAR_SHIFT) & MExxCTL_MSAR_MASK))
  75. #define MERAM_MExxBSIZE_VAL(rcnt, yszm1, xszm1) \
  76. (((rcnt) << MExxBSIZE_RCNT_SHIFT) | \
  77. ((yszm1) << MExxBSIZE_YSZM1_SHIFT) | \
  78. ((xszm1) << MExxBSIZE_XSZM1_SHIFT))
  79. #define SH_MOBILE_MERAM_ICB_NUM 32
  80. static unsigned long common_regs[] = {
  81. MEVCR1,
  82. MEQSEL1,
  83. MEQSEL2,
  84. };
  85. #define CMN_REGS_SIZE ARRAY_SIZE(common_regs)
  86. static unsigned long icb_regs[] = {
  87. MExxCTL,
  88. MExxBSIZE,
  89. MExxMNCF,
  90. MExxSARA,
  91. MExxSARB,
  92. MExxSBSIZE,
  93. };
  94. #define ICB_REGS_SIZE ARRAY_SIZE(icb_regs)
  95. struct sh_mobile_meram_priv {
  96. void __iomem *base;
  97. struct mutex lock;
  98. unsigned long used_icb;
  99. unsigned int used_meram_cache_regions;
  100. unsigned long used_meram_cache[SH_MOBILE_MERAM_ICB_NUM];
  101. unsigned long cmn_saved_regs[CMN_REGS_SIZE];
  102. unsigned long icb_saved_regs[ICB_REGS_SIZE * SH_MOBILE_MERAM_ICB_NUM];
  103. };
  104. /* settings */
  105. #define MERAM_SEC_LINE 15
  106. #define MERAM_LINE_WIDTH 2048
  107. /*
  108. * MERAM/ICB access functions
  109. */
  110. #define MERAM_ICB_OFFSET(base, idx, off) ((base) + (off) + (idx) * 0x20)
  111. static inline void meram_write_icb(void __iomem *base, unsigned int idx,
  112. unsigned int off, unsigned long val)
  113. {
  114. iowrite32(val, MERAM_ICB_OFFSET(base, idx, off));
  115. }
  116. static inline unsigned long meram_read_icb(void __iomem *base, unsigned int idx,
  117. unsigned int off)
  118. {
  119. return ioread32(MERAM_ICB_OFFSET(base, idx, off));
  120. }
  121. static inline void meram_write_reg(void __iomem *base, unsigned int off,
  122. unsigned long val)
  123. {
  124. iowrite32(val, base + off);
  125. }
  126. static inline unsigned long meram_read_reg(void __iomem *base, unsigned int off)
  127. {
  128. return ioread32(base + off);
  129. }
  130. /*
  131. * register ICB
  132. */
  133. #define MERAM_CACHE_START(p) ((p) >> 16)
  134. #define MERAM_CACHE_END(p) ((p) & 0xffff)
  135. #define MERAM_CACHE_SET(o, s) ((((o) & 0xffff) << 16) | \
  136. (((o) + (s) - 1) & 0xffff))
  137. /*
  138. * check if there's no overlaps in MERAM allocation.
  139. */
  140. static inline int meram_check_overlap(struct sh_mobile_meram_priv *priv,
  141. struct sh_mobile_meram_icb_cfg *new)
  142. {
  143. unsigned int used_start, used_end, meram_start, meram_end;
  144. unsigned int i;
  145. /* valid ICB? */
  146. if (new->marker_icb & ~0x1f || new->cache_icb & ~0x1f)
  147. return 1;
  148. if (test_bit(new->marker_icb, &priv->used_icb) ||
  149. test_bit(new->cache_icb, &priv->used_icb))
  150. return 1;
  151. for (i = 0; i < priv->used_meram_cache_regions; i++) {
  152. used_start = MERAM_CACHE_START(priv->used_meram_cache[i]);
  153. used_end = MERAM_CACHE_END(priv->used_meram_cache[i]);
  154. meram_start = new->meram_offset;
  155. meram_end = new->meram_offset + new->meram_size;
  156. if ((meram_start >= used_start && meram_start < used_end) ||
  157. (meram_end > used_start && meram_end < used_end))
  158. return 1;
  159. }
  160. return 0;
  161. }
  162. /*
  163. * mark the specified ICB as used
  164. */
  165. static inline void meram_mark(struct sh_mobile_meram_priv *priv,
  166. struct sh_mobile_meram_icb_cfg *new)
  167. {
  168. unsigned int n;
  169. if (new->marker_icb < 0 || new->cache_icb < 0)
  170. return;
  171. __set_bit(new->marker_icb, &priv->used_icb);
  172. __set_bit(new->cache_icb, &priv->used_icb);
  173. n = priv->used_meram_cache_regions;
  174. priv->used_meram_cache[n] = MERAM_CACHE_SET(new->meram_offset,
  175. new->meram_size);
  176. priv->used_meram_cache_regions++;
  177. }
  178. /*
  179. * unmark the specified ICB as used
  180. */
  181. static inline void meram_unmark(struct sh_mobile_meram_priv *priv,
  182. struct sh_mobile_meram_icb_cfg *icb)
  183. {
  184. unsigned long pattern;
  185. unsigned int i;
  186. if (icb->marker_icb < 0 || icb->cache_icb < 0)
  187. return;
  188. __clear_bit(icb->marker_icb, &priv->used_icb);
  189. __clear_bit(icb->cache_icb, &priv->used_icb);
  190. pattern = MERAM_CACHE_SET(icb->meram_offset, icb->meram_size);
  191. for (i = 0; i < priv->used_meram_cache_regions; i++) {
  192. if (priv->used_meram_cache[i] == pattern) {
  193. while (i < priv->used_meram_cache_regions - 1) {
  194. priv->used_meram_cache[i] =
  195. priv->used_meram_cache[i + 1] ;
  196. i++;
  197. }
  198. priv->used_meram_cache[i] = 0;
  199. priv->used_meram_cache_regions--;
  200. break;
  201. }
  202. }
  203. }
  204. /*
  205. * is this a YCbCr(NV12, NV16 or NV24) colorspace
  206. */
  207. static inline int is_nvcolor(int cspace)
  208. {
  209. if (cspace == SH_MOBILE_MERAM_PF_NV ||
  210. cspace == SH_MOBILE_MERAM_PF_NV24)
  211. return 1;
  212. return 0;
  213. }
  214. /*
  215. * set the next address to fetch
  216. */
  217. static inline void meram_set_next_addr(struct sh_mobile_meram_priv *priv,
  218. struct sh_mobile_meram_cfg *cfg,
  219. unsigned long base_addr_y,
  220. unsigned long base_addr_c)
  221. {
  222. unsigned long target;
  223. cfg->current_reg ^= 1;
  224. target = cfg->current_reg ? MExxSARB : MExxSARA;
  225. /* set the next address to fetch */
  226. meram_write_icb(priv->base, cfg->icb[0].cache_icb, target,
  227. base_addr_y);
  228. meram_write_icb(priv->base, cfg->icb[0].marker_icb, target,
  229. base_addr_y + cfg->icb[0].cache_unit);
  230. if (is_nvcolor(cfg->pixelformat)) {
  231. meram_write_icb(priv->base, cfg->icb[1].cache_icb, target,
  232. base_addr_c);
  233. meram_write_icb(priv->base, cfg->icb[1].marker_icb, target,
  234. base_addr_c + cfg->icb[1].cache_unit);
  235. }
  236. }
  237. /*
  238. * get the next ICB address
  239. */
  240. static inline void meram_get_next_icb_addr(struct sh_mobile_meram_info *pdata,
  241. struct sh_mobile_meram_cfg *cfg,
  242. unsigned long *icb_addr_y,
  243. unsigned long *icb_addr_c)
  244. {
  245. unsigned long icb_offset;
  246. if (pdata->addr_mode == SH_MOBILE_MERAM_MODE0)
  247. icb_offset = 0x80000000 | (cfg->current_reg << 29);
  248. else
  249. icb_offset = 0xc0000000 | (cfg->current_reg << 23);
  250. *icb_addr_y = icb_offset | (cfg->icb[0].marker_icb << 24);
  251. if (is_nvcolor(cfg->pixelformat))
  252. *icb_addr_c = icb_offset | (cfg->icb[1].marker_icb << 24);
  253. }
  254. #define MERAM_CALC_BYTECOUNT(x, y) \
  255. (((x) * (y) + (MERAM_LINE_WIDTH - 1)) & ~(MERAM_LINE_WIDTH - 1))
  256. /*
  257. * initialize MERAM
  258. */
  259. static int meram_init(struct sh_mobile_meram_priv *priv,
  260. struct sh_mobile_meram_icb_cfg *icb,
  261. unsigned int xres, unsigned int yres,
  262. unsigned int *out_pitch)
  263. {
  264. unsigned long total_byte_count = MERAM_CALC_BYTECOUNT(xres, yres);
  265. unsigned long bnm;
  266. unsigned int lcdc_pitch;
  267. unsigned int xpitch;
  268. unsigned int line_cnt;
  269. unsigned int save_lines;
  270. /* adjust pitch to 1024, 2048, 4096 or 8192 */
  271. lcdc_pitch = (xres - 1) | 1023;
  272. lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 1);
  273. lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 2);
  274. lcdc_pitch += 1;
  275. /* derive settings */
  276. if (lcdc_pitch == 8192 && yres >= 1024) {
  277. lcdc_pitch = xpitch = MERAM_LINE_WIDTH;
  278. line_cnt = total_byte_count >> 11;
  279. *out_pitch = xres;
  280. save_lines = (icb->meram_size / 16 / MERAM_SEC_LINE);
  281. save_lines *= MERAM_SEC_LINE;
  282. } else {
  283. xpitch = xres;
  284. line_cnt = yres;
  285. *out_pitch = lcdc_pitch;
  286. save_lines = icb->meram_size / (lcdc_pitch >> 10) / 2;
  287. save_lines &= 0xff;
  288. }
  289. bnm = (save_lines - 1) << 16;
  290. /* TODO: we better to check if we have enough MERAM buffer size */
  291. /* set up ICB */
  292. meram_write_icb(priv->base, icb->cache_icb, MExxBSIZE,
  293. MERAM_MExxBSIZE_VAL(0x0, line_cnt - 1, xpitch - 1));
  294. meram_write_icb(priv->base, icb->marker_icb, MExxBSIZE,
  295. MERAM_MExxBSIZE_VAL(0xf, line_cnt - 1, xpitch - 1));
  296. meram_write_icb(priv->base, icb->cache_icb, MExxMNCF, bnm);
  297. meram_write_icb(priv->base, icb->marker_icb, MExxMNCF, bnm);
  298. meram_write_icb(priv->base, icb->cache_icb, MExxSBSIZE, xpitch);
  299. meram_write_icb(priv->base, icb->marker_icb, MExxSBSIZE, xpitch);
  300. /* save a cache unit size */
  301. icb->cache_unit = xres * save_lines;
  302. /*
  303. * Set MERAM for framebuffer
  304. *
  305. * we also chain the cache_icb and the marker_icb.
  306. * we also split the allocated MERAM buffer between two ICBs.
  307. */
  308. meram_write_icb(priv->base, icb->cache_icb, MExxCTL,
  309. MERAM_MExxCTL_VAL(icb->marker_icb, icb->meram_offset) |
  310. MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
  311. MExxCTL_MD_FB);
  312. meram_write_icb(priv->base, icb->marker_icb, MExxCTL,
  313. MERAM_MExxCTL_VAL(icb->cache_icb, icb->meram_offset +
  314. icb->meram_size / 2) |
  315. MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM |
  316. MExxCTL_MD_FB);
  317. return 0;
  318. }
  319. static void meram_deinit(struct sh_mobile_meram_priv *priv,
  320. struct sh_mobile_meram_icb_cfg *icb)
  321. {
  322. /* disable ICB */
  323. meram_write_icb(priv->base, icb->cache_icb, MExxCTL,
  324. MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF);
  325. meram_write_icb(priv->base, icb->marker_icb, MExxCTL,
  326. MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF);
  327. icb->cache_unit = 0;
  328. }
  329. /*
  330. * register the ICB
  331. */
  332. static int sh_mobile_meram_register(struct sh_mobile_meram_info *pdata,
  333. struct sh_mobile_meram_cfg *cfg,
  334. unsigned int xres, unsigned int yres,
  335. unsigned int pixelformat,
  336. unsigned long base_addr_y,
  337. unsigned long base_addr_c,
  338. unsigned long *icb_addr_y,
  339. unsigned long *icb_addr_c,
  340. unsigned int *pitch)
  341. {
  342. struct platform_device *pdev;
  343. struct sh_mobile_meram_priv *priv;
  344. unsigned int out_pitch;
  345. unsigned int n;
  346. int error = 0;
  347. if (!pdata || !pdata->priv || !pdata->pdev || !cfg)
  348. return -EINVAL;
  349. if (pixelformat != SH_MOBILE_MERAM_PF_NV &&
  350. pixelformat != SH_MOBILE_MERAM_PF_NV24 &&
  351. pixelformat != SH_MOBILE_MERAM_PF_RGB)
  352. return -EINVAL;
  353. priv = pdata->priv;
  354. pdev = pdata->pdev;
  355. dev_dbg(&pdev->dev, "registering %dx%d (%s) (y=%08lx, c=%08lx)",
  356. xres, yres, (!pixelformat) ? "yuv" : "rgb",
  357. base_addr_y, base_addr_c);
  358. /* we can't handle wider than 8192px */
  359. if (xres > 8192) {
  360. dev_err(&pdev->dev, "width exceeding the limit (> 8192).");
  361. return -EINVAL;
  362. }
  363. /* do we have at least one ICB config? */
  364. if (cfg->icb[0].marker_icb < 0 || cfg->icb[0].cache_icb < 0) {
  365. dev_err(&pdev->dev, "at least one ICB is required.");
  366. return -EINVAL;
  367. }
  368. mutex_lock(&priv->lock);
  369. if (priv->used_meram_cache_regions + 2 > SH_MOBILE_MERAM_ICB_NUM) {
  370. dev_err(&pdev->dev, "no more ICB available.");
  371. error = -EINVAL;
  372. goto err;
  373. }
  374. /* make sure that there's no overlaps */
  375. if (meram_check_overlap(priv, &cfg->icb[0])) {
  376. dev_err(&pdev->dev, "conflicting config detected.");
  377. error = -EINVAL;
  378. goto err;
  379. }
  380. n = 1;
  381. /* do the same if we have the second ICB set */
  382. if (cfg->icb[1].marker_icb >= 0 && cfg->icb[1].cache_icb >= 0) {
  383. if (meram_check_overlap(priv, &cfg->icb[1])) {
  384. dev_err(&pdev->dev, "conflicting config detected.");
  385. error = -EINVAL;
  386. goto err;
  387. }
  388. n = 2;
  389. }
  390. if (is_nvcolor(pixelformat) && n != 2) {
  391. dev_err(&pdev->dev, "requires two ICB sets for planar Y/C.");
  392. error = -EINVAL;
  393. goto err;
  394. }
  395. /* we now register the ICB */
  396. cfg->pixelformat = pixelformat;
  397. meram_mark(priv, &cfg->icb[0]);
  398. if (is_nvcolor(pixelformat))
  399. meram_mark(priv, &cfg->icb[1]);
  400. /* initialize MERAM */
  401. meram_init(priv, &cfg->icb[0], xres, yres, &out_pitch);
  402. *pitch = out_pitch;
  403. if (pixelformat == SH_MOBILE_MERAM_PF_NV)
  404. meram_init(priv, &cfg->icb[1], xres, (yres + 1) / 2,
  405. &out_pitch);
  406. else if (pixelformat == SH_MOBILE_MERAM_PF_NV24)
  407. meram_init(priv, &cfg->icb[1], 2 * xres, (yres + 1) / 2,
  408. &out_pitch);
  409. cfg->current_reg = 1;
  410. meram_set_next_addr(priv, cfg, base_addr_y, base_addr_c);
  411. meram_get_next_icb_addr(pdata, cfg, icb_addr_y, icb_addr_c);
  412. dev_dbg(&pdev->dev, "registered - can access via y=%08lx, c=%08lx",
  413. *icb_addr_y, *icb_addr_c);
  414. err:
  415. mutex_unlock(&priv->lock);
  416. return error;
  417. }
  418. static int sh_mobile_meram_unregister(struct sh_mobile_meram_info *pdata,
  419. struct sh_mobile_meram_cfg *cfg)
  420. {
  421. struct sh_mobile_meram_priv *priv;
  422. if (!pdata || !pdata->priv || !cfg)
  423. return -EINVAL;
  424. priv = pdata->priv;
  425. mutex_lock(&priv->lock);
  426. /* deinit & unmark */
  427. if (is_nvcolor(cfg->pixelformat)) {
  428. meram_deinit(priv, &cfg->icb[1]);
  429. meram_unmark(priv, &cfg->icb[1]);
  430. }
  431. meram_deinit(priv, &cfg->icb[0]);
  432. meram_unmark(priv, &cfg->icb[0]);
  433. mutex_unlock(&priv->lock);
  434. return 0;
  435. }
  436. static int sh_mobile_meram_update(struct sh_mobile_meram_info *pdata,
  437. struct sh_mobile_meram_cfg *cfg,
  438. unsigned long base_addr_y,
  439. unsigned long base_addr_c,
  440. unsigned long *icb_addr_y,
  441. unsigned long *icb_addr_c)
  442. {
  443. struct sh_mobile_meram_priv *priv;
  444. if (!pdata || !pdata->priv || !cfg)
  445. return -EINVAL;
  446. priv = pdata->priv;
  447. mutex_lock(&priv->lock);
  448. meram_set_next_addr(priv, cfg, base_addr_y, base_addr_c);
  449. meram_get_next_icb_addr(pdata, cfg, icb_addr_y, icb_addr_c);
  450. mutex_unlock(&priv->lock);
  451. return 0;
  452. }
  453. static int sh_mobile_meram_runtime_suspend(struct device *dev)
  454. {
  455. struct platform_device *pdev = to_platform_device(dev);
  456. struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
  457. unsigned int i, j;
  458. for (i = 0; i < CMN_REGS_SIZE; i++)
  459. priv->cmn_saved_regs[i] = meram_read_reg(priv->base,
  460. common_regs[i]);
  461. for (i = 0; i < 32; i++) {
  462. if (!test_bit(i, &priv->used_icb))
  463. continue;
  464. for (j = 0; j < ICB_REGS_SIZE; j++) {
  465. priv->icb_saved_regs[i * ICB_REGS_SIZE + j] =
  466. meram_read_icb(priv->base, i, icb_regs[j]);
  467. /* Reset ICB on resume */
  468. if (icb_regs[j] == MExxCTL)
  469. priv->icb_saved_regs[i * ICB_REGS_SIZE + j] |=
  470. MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF;
  471. }
  472. }
  473. return 0;
  474. }
  475. static int sh_mobile_meram_runtime_resume(struct device *dev)
  476. {
  477. struct platform_device *pdev = to_platform_device(dev);
  478. struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
  479. unsigned int i, j;
  480. for (i = 0; i < 32; i++) {
  481. if (!test_bit(i, &priv->used_icb))
  482. continue;
  483. for (j = 0; j < ICB_REGS_SIZE; j++) {
  484. meram_write_icb(priv->base, i, icb_regs[j],
  485. priv->icb_saved_regs[i * ICB_REGS_SIZE + j]);
  486. }
  487. }
  488. for (i = 0; i < CMN_REGS_SIZE; i++)
  489. meram_write_reg(priv->base, common_regs[i],
  490. priv->cmn_saved_regs[i]);
  491. return 0;
  492. }
  493. static const struct dev_pm_ops sh_mobile_meram_dev_pm_ops = {
  494. .runtime_suspend = sh_mobile_meram_runtime_suspend,
  495. .runtime_resume = sh_mobile_meram_runtime_resume,
  496. };
  497. static struct sh_mobile_meram_ops sh_mobile_meram_ops = {
  498. .module = THIS_MODULE,
  499. .meram_register = sh_mobile_meram_register,
  500. .meram_unregister = sh_mobile_meram_unregister,
  501. .meram_update = sh_mobile_meram_update,
  502. };
  503. /*
  504. * initialize MERAM
  505. */
  506. static int __devinit sh_mobile_meram_probe(struct platform_device *pdev)
  507. {
  508. struct sh_mobile_meram_priv *priv;
  509. struct sh_mobile_meram_info *pdata = pdev->dev.platform_data;
  510. struct resource *regs;
  511. struct resource *meram;
  512. int error;
  513. if (!pdata) {
  514. dev_err(&pdev->dev, "no platform data defined\n");
  515. return -EINVAL;
  516. }
  517. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  518. meram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  519. if (regs == NULL || meram == NULL) {
  520. dev_err(&pdev->dev, "cannot get platform resources\n");
  521. return -ENOENT;
  522. }
  523. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  524. if (!priv) {
  525. dev_err(&pdev->dev, "cannot allocate device data\n");
  526. return -ENOMEM;
  527. }
  528. /* initialize private data */
  529. mutex_init(&priv->lock);
  530. pdata->ops = &sh_mobile_meram_ops;
  531. pdata->priv = priv;
  532. pdata->pdev = pdev;
  533. if (!request_mem_region(regs->start, resource_size(regs), pdev->name)) {
  534. dev_err(&pdev->dev, "MERAM registers region already claimed\n");
  535. error = -EBUSY;
  536. goto err_req_regs;
  537. }
  538. if (!request_mem_region(meram->start, resource_size(meram),
  539. pdev->name)) {
  540. dev_err(&pdev->dev, "MERAM memory region already claimed\n");
  541. error = -EBUSY;
  542. goto err_req_meram;
  543. }
  544. priv->base = ioremap_nocache(regs->start, resource_size(regs));
  545. if (!priv->base) {
  546. dev_err(&pdev->dev, "ioremap failed\n");
  547. error = -EFAULT;
  548. goto err_ioremap;
  549. }
  550. /* initialize ICB addressing mode */
  551. if (pdata->addr_mode == SH_MOBILE_MERAM_MODE1)
  552. meram_write_reg(priv->base, MEVCR1, MEVCR1_AMD1);
  553. platform_set_drvdata(pdev, priv);
  554. pm_runtime_enable(&pdev->dev);
  555. dev_info(&pdev->dev, "sh_mobile_meram initialized.");
  556. return 0;
  557. err_ioremap:
  558. release_mem_region(meram->start, resource_size(meram));
  559. err_req_meram:
  560. release_mem_region(regs->start, resource_size(regs));
  561. err_req_regs:
  562. mutex_destroy(&priv->lock);
  563. kfree(priv);
  564. return error;
  565. }
  566. static int sh_mobile_meram_remove(struct platform_device *pdev)
  567. {
  568. struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
  569. struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  570. struct resource *meram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  571. pm_runtime_disable(&pdev->dev);
  572. iounmap(priv->base);
  573. release_mem_region(meram->start, resource_size(meram));
  574. release_mem_region(regs->start, resource_size(regs));
  575. mutex_destroy(&priv->lock);
  576. kfree(priv);
  577. return 0;
  578. }
  579. static struct platform_driver sh_mobile_meram_driver = {
  580. .driver = {
  581. .name = "sh_mobile_meram",
  582. .owner = THIS_MODULE,
  583. .pm = &sh_mobile_meram_dev_pm_ops,
  584. },
  585. .probe = sh_mobile_meram_probe,
  586. .remove = sh_mobile_meram_remove,
  587. };
  588. module_platform_driver(sh_mobile_meram_driver);
  589. MODULE_DESCRIPTION("SuperH Mobile MERAM driver");
  590. MODULE_AUTHOR("Damian Hobson-Garcia / Takanari Hayama");
  591. MODULE_LICENSE("GPL v2");