qeth_core_main.c 153 KB

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  1. /*
  2. * Copyright IBM Corp. 2007, 2009
  3. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  4. * Frank Pavlic <fpavlic@de.ibm.com>,
  5. * Thomas Spatzier <tspat@de.ibm.com>,
  6. * Frank Blaschka <frank.blaschka@de.ibm.com>
  7. */
  8. #define KMSG_COMPONENT "qeth"
  9. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/tcp.h>
  17. #include <linux/mii.h>
  18. #include <linux/kthread.h>
  19. #include <linux/slab.h>
  20. #include <net/iucv/af_iucv.h>
  21. #include <asm/ebcdic.h>
  22. #include <asm/io.h>
  23. #include <asm/sysinfo.h>
  24. #include <asm/compat.h>
  25. #include "qeth_core.h"
  26. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  27. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  28. /* N P A M L V H */
  29. [QETH_DBF_SETUP] = {"qeth_setup",
  30. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_MSG] = {"qeth_msg",
  32. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  33. [QETH_DBF_CTRL] = {"qeth_control",
  34. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  35. };
  36. EXPORT_SYMBOL_GPL(qeth_dbf);
  37. struct qeth_card_list_struct qeth_core_card_list;
  38. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  39. struct kmem_cache *qeth_core_header_cache;
  40. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  41. static struct kmem_cache *qeth_qdio_outbuf_cache;
  42. static struct device *qeth_core_root_dev;
  43. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  44. static struct lock_class_key qdio_out_skb_queue_key;
  45. static struct mutex qeth_mod_mutex;
  46. static void qeth_send_control_data_cb(struct qeth_channel *,
  47. struct qeth_cmd_buffer *);
  48. static int qeth_issue_next_read(struct qeth_card *);
  49. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  50. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  51. static void qeth_free_buffer_pool(struct qeth_card *);
  52. static int qeth_qdio_establish(struct qeth_card *);
  53. static void qeth_free_qdio_buffers(struct qeth_card *);
  54. static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
  55. struct qeth_qdio_out_buffer *buf,
  56. enum iucv_tx_notify notification);
  57. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf);
  58. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  59. struct qeth_qdio_out_buffer *buf,
  60. enum qeth_qdio_buffer_states newbufstate);
  61. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *, int);
  62. static inline const char *qeth_get_cardname(struct qeth_card *card)
  63. {
  64. if (card->info.guestlan) {
  65. switch (card->info.type) {
  66. case QETH_CARD_TYPE_OSD:
  67. return " Virtual NIC QDIO";
  68. case QETH_CARD_TYPE_IQD:
  69. return " Virtual NIC Hiper";
  70. case QETH_CARD_TYPE_OSM:
  71. return " Virtual NIC QDIO - OSM";
  72. case QETH_CARD_TYPE_OSX:
  73. return " Virtual NIC QDIO - OSX";
  74. default:
  75. return " unknown";
  76. }
  77. } else {
  78. switch (card->info.type) {
  79. case QETH_CARD_TYPE_OSD:
  80. return " OSD Express";
  81. case QETH_CARD_TYPE_IQD:
  82. return " HiperSockets";
  83. case QETH_CARD_TYPE_OSN:
  84. return " OSN QDIO";
  85. case QETH_CARD_TYPE_OSM:
  86. return " OSM QDIO";
  87. case QETH_CARD_TYPE_OSX:
  88. return " OSX QDIO";
  89. default:
  90. return " unknown";
  91. }
  92. }
  93. return " n/a";
  94. }
  95. /* max length to be returned: 14 */
  96. const char *qeth_get_cardname_short(struct qeth_card *card)
  97. {
  98. if (card->info.guestlan) {
  99. switch (card->info.type) {
  100. case QETH_CARD_TYPE_OSD:
  101. return "Virt.NIC QDIO";
  102. case QETH_CARD_TYPE_IQD:
  103. return "Virt.NIC Hiper";
  104. case QETH_CARD_TYPE_OSM:
  105. return "Virt.NIC OSM";
  106. case QETH_CARD_TYPE_OSX:
  107. return "Virt.NIC OSX";
  108. default:
  109. return "unknown";
  110. }
  111. } else {
  112. switch (card->info.type) {
  113. case QETH_CARD_TYPE_OSD:
  114. switch (card->info.link_type) {
  115. case QETH_LINK_TYPE_FAST_ETH:
  116. return "OSD_100";
  117. case QETH_LINK_TYPE_HSTR:
  118. return "HSTR";
  119. case QETH_LINK_TYPE_GBIT_ETH:
  120. return "OSD_1000";
  121. case QETH_LINK_TYPE_10GBIT_ETH:
  122. return "OSD_10GIG";
  123. case QETH_LINK_TYPE_LANE_ETH100:
  124. return "OSD_FE_LANE";
  125. case QETH_LINK_TYPE_LANE_TR:
  126. return "OSD_TR_LANE";
  127. case QETH_LINK_TYPE_LANE_ETH1000:
  128. return "OSD_GbE_LANE";
  129. case QETH_LINK_TYPE_LANE:
  130. return "OSD_ATM_LANE";
  131. default:
  132. return "OSD_Express";
  133. }
  134. case QETH_CARD_TYPE_IQD:
  135. return "HiperSockets";
  136. case QETH_CARD_TYPE_OSN:
  137. return "OSN";
  138. case QETH_CARD_TYPE_OSM:
  139. return "OSM_1000";
  140. case QETH_CARD_TYPE_OSX:
  141. return "OSX_10GIG";
  142. default:
  143. return "unknown";
  144. }
  145. }
  146. return "n/a";
  147. }
  148. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  149. int clear_start_mask)
  150. {
  151. unsigned long flags;
  152. spin_lock_irqsave(&card->thread_mask_lock, flags);
  153. card->thread_allowed_mask = threads;
  154. if (clear_start_mask)
  155. card->thread_start_mask &= threads;
  156. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  157. wake_up(&card->wait_q);
  158. }
  159. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  160. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  161. {
  162. unsigned long flags;
  163. int rc = 0;
  164. spin_lock_irqsave(&card->thread_mask_lock, flags);
  165. rc = (card->thread_running_mask & threads);
  166. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  167. return rc;
  168. }
  169. EXPORT_SYMBOL_GPL(qeth_threads_running);
  170. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  171. {
  172. return wait_event_interruptible(card->wait_q,
  173. qeth_threads_running(card, threads) == 0);
  174. }
  175. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  176. void qeth_clear_working_pool_list(struct qeth_card *card)
  177. {
  178. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  179. QETH_CARD_TEXT(card, 5, "clwrklst");
  180. list_for_each_entry_safe(pool_entry, tmp,
  181. &card->qdio.in_buf_pool.entry_list, list){
  182. list_del(&pool_entry->list);
  183. }
  184. }
  185. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  186. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  187. {
  188. struct qeth_buffer_pool_entry *pool_entry;
  189. void *ptr;
  190. int i, j;
  191. QETH_CARD_TEXT(card, 5, "alocpool");
  192. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  193. pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);
  194. if (!pool_entry) {
  195. qeth_free_buffer_pool(card);
  196. return -ENOMEM;
  197. }
  198. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  199. ptr = (void *) __get_free_page(GFP_KERNEL);
  200. if (!ptr) {
  201. while (j > 0)
  202. free_page((unsigned long)
  203. pool_entry->elements[--j]);
  204. kfree(pool_entry);
  205. qeth_free_buffer_pool(card);
  206. return -ENOMEM;
  207. }
  208. pool_entry->elements[j] = ptr;
  209. }
  210. list_add(&pool_entry->init_list,
  211. &card->qdio.init_pool.entry_list);
  212. }
  213. return 0;
  214. }
  215. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  216. {
  217. QETH_CARD_TEXT(card, 2, "realcbp");
  218. if ((card->state != CARD_STATE_DOWN) &&
  219. (card->state != CARD_STATE_RECOVER))
  220. return -EPERM;
  221. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  222. qeth_clear_working_pool_list(card);
  223. qeth_free_buffer_pool(card);
  224. card->qdio.in_buf_pool.buf_count = bufcnt;
  225. card->qdio.init_pool.buf_count = bufcnt;
  226. return qeth_alloc_buffer_pool(card);
  227. }
  228. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  229. static inline int qeth_cq_init(struct qeth_card *card)
  230. {
  231. int rc;
  232. if (card->options.cq == QETH_CQ_ENABLED) {
  233. QETH_DBF_TEXT(SETUP, 2, "cqinit");
  234. memset(card->qdio.c_q->qdio_bufs, 0,
  235. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  236. card->qdio.c_q->next_buf_to_init = 127;
  237. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT,
  238. card->qdio.no_in_queues - 1, 0,
  239. 127);
  240. if (rc) {
  241. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  242. goto out;
  243. }
  244. }
  245. rc = 0;
  246. out:
  247. return rc;
  248. }
  249. static inline int qeth_alloc_cq(struct qeth_card *card)
  250. {
  251. int rc;
  252. if (card->options.cq == QETH_CQ_ENABLED) {
  253. int i;
  254. struct qdio_outbuf_state *outbuf_states;
  255. QETH_DBF_TEXT(SETUP, 2, "cqon");
  256. card->qdio.c_q = kzalloc(sizeof(struct qeth_qdio_q),
  257. GFP_KERNEL);
  258. if (!card->qdio.c_q) {
  259. rc = -1;
  260. goto kmsg_out;
  261. }
  262. QETH_DBF_HEX(SETUP, 2, &card->qdio.c_q, sizeof(void *));
  263. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  264. card->qdio.c_q->bufs[i].buffer =
  265. &card->qdio.c_q->qdio_bufs[i];
  266. }
  267. card->qdio.no_in_queues = 2;
  268. card->qdio.out_bufstates = (struct qdio_outbuf_state *)
  269. kzalloc(card->qdio.no_out_queues *
  270. QDIO_MAX_BUFFERS_PER_Q *
  271. sizeof(struct qdio_outbuf_state), GFP_KERNEL);
  272. outbuf_states = card->qdio.out_bufstates;
  273. if (outbuf_states == NULL) {
  274. rc = -1;
  275. goto free_cq_out;
  276. }
  277. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  278. card->qdio.out_qs[i]->bufstates = outbuf_states;
  279. outbuf_states += QDIO_MAX_BUFFERS_PER_Q;
  280. }
  281. } else {
  282. QETH_DBF_TEXT(SETUP, 2, "nocq");
  283. card->qdio.c_q = NULL;
  284. card->qdio.no_in_queues = 1;
  285. }
  286. QETH_DBF_TEXT_(SETUP, 2, "iqc%d", card->qdio.no_in_queues);
  287. rc = 0;
  288. out:
  289. return rc;
  290. free_cq_out:
  291. kfree(card->qdio.c_q);
  292. card->qdio.c_q = NULL;
  293. kmsg_out:
  294. dev_err(&card->gdev->dev, "Failed to create completion queue\n");
  295. goto out;
  296. }
  297. static inline void qeth_free_cq(struct qeth_card *card)
  298. {
  299. if (card->qdio.c_q) {
  300. --card->qdio.no_in_queues;
  301. kfree(card->qdio.c_q);
  302. card->qdio.c_q = NULL;
  303. }
  304. kfree(card->qdio.out_bufstates);
  305. card->qdio.out_bufstates = NULL;
  306. }
  307. static inline enum iucv_tx_notify qeth_compute_cq_notification(int sbalf15,
  308. int delayed) {
  309. enum iucv_tx_notify n;
  310. switch (sbalf15) {
  311. case 0:
  312. n = delayed ? TX_NOTIFY_DELAYED_OK : TX_NOTIFY_OK;
  313. break;
  314. case 4:
  315. case 16:
  316. case 17:
  317. case 18:
  318. n = delayed ? TX_NOTIFY_DELAYED_UNREACHABLE :
  319. TX_NOTIFY_UNREACHABLE;
  320. break;
  321. default:
  322. n = delayed ? TX_NOTIFY_DELAYED_GENERALERROR :
  323. TX_NOTIFY_GENERALERROR;
  324. break;
  325. }
  326. return n;
  327. }
  328. static inline void qeth_cleanup_handled_pending(struct qeth_qdio_out_q *q,
  329. int bidx, int forced_cleanup)
  330. {
  331. if (q->card->options.cq != QETH_CQ_ENABLED)
  332. return;
  333. if (q->bufs[bidx]->next_pending != NULL) {
  334. struct qeth_qdio_out_buffer *head = q->bufs[bidx];
  335. struct qeth_qdio_out_buffer *c = q->bufs[bidx]->next_pending;
  336. while (c) {
  337. if (forced_cleanup ||
  338. atomic_read(&c->state) ==
  339. QETH_QDIO_BUF_HANDLED_DELAYED) {
  340. struct qeth_qdio_out_buffer *f = c;
  341. QETH_CARD_TEXT(f->q->card, 5, "fp");
  342. QETH_CARD_TEXT_(f->q->card, 5, "%lx", (long) f);
  343. /* release here to avoid interleaving between
  344. outbound tasklet and inbound tasklet
  345. regarding notifications and lifecycle */
  346. qeth_release_skbs(c);
  347. c = f->next_pending;
  348. WARN_ON_ONCE(head->next_pending != f);
  349. head->next_pending = c;
  350. kmem_cache_free(qeth_qdio_outbuf_cache, f);
  351. } else {
  352. head = c;
  353. c = c->next_pending;
  354. }
  355. }
  356. }
  357. if (forced_cleanup && (atomic_read(&(q->bufs[bidx]->state)) ==
  358. QETH_QDIO_BUF_HANDLED_DELAYED)) {
  359. /* for recovery situations */
  360. q->bufs[bidx]->aob = q->bufstates[bidx].aob;
  361. qeth_init_qdio_out_buf(q, bidx);
  362. QETH_CARD_TEXT(q->card, 2, "clprecov");
  363. }
  364. }
  365. static inline void qeth_qdio_handle_aob(struct qeth_card *card,
  366. unsigned long phys_aob_addr) {
  367. struct qaob *aob;
  368. struct qeth_qdio_out_buffer *buffer;
  369. enum iucv_tx_notify notification;
  370. aob = (struct qaob *) phys_to_virt(phys_aob_addr);
  371. QETH_CARD_TEXT(card, 5, "haob");
  372. QETH_CARD_TEXT_(card, 5, "%lx", phys_aob_addr);
  373. buffer = (struct qeth_qdio_out_buffer *) aob->user1;
  374. QETH_CARD_TEXT_(card, 5, "%lx", aob->user1);
  375. if (atomic_cmpxchg(&buffer->state, QETH_QDIO_BUF_PRIMED,
  376. QETH_QDIO_BUF_IN_CQ) == QETH_QDIO_BUF_PRIMED) {
  377. notification = TX_NOTIFY_OK;
  378. } else {
  379. WARN_ON_ONCE(atomic_read(&buffer->state) !=
  380. QETH_QDIO_BUF_PENDING);
  381. atomic_set(&buffer->state, QETH_QDIO_BUF_IN_CQ);
  382. notification = TX_NOTIFY_DELAYED_OK;
  383. }
  384. if (aob->aorc != 0) {
  385. QETH_CARD_TEXT_(card, 2, "aorc%02X", aob->aorc);
  386. notification = qeth_compute_cq_notification(aob->aorc, 1);
  387. }
  388. qeth_notify_skbs(buffer->q, buffer, notification);
  389. buffer->aob = NULL;
  390. qeth_clear_output_buffer(buffer->q, buffer,
  391. QETH_QDIO_BUF_HANDLED_DELAYED);
  392. /* from here on: do not touch buffer anymore */
  393. qdio_release_aob(aob);
  394. }
  395. static inline int qeth_is_cq(struct qeth_card *card, unsigned int queue)
  396. {
  397. return card->options.cq == QETH_CQ_ENABLED &&
  398. card->qdio.c_q != NULL &&
  399. queue != 0 &&
  400. queue == card->qdio.no_in_queues - 1;
  401. }
  402. static int qeth_issue_next_read(struct qeth_card *card)
  403. {
  404. int rc;
  405. struct qeth_cmd_buffer *iob;
  406. QETH_CARD_TEXT(card, 5, "issnxrd");
  407. if (card->read.state != CH_STATE_UP)
  408. return -EIO;
  409. iob = qeth_get_buffer(&card->read);
  410. if (!iob) {
  411. dev_warn(&card->gdev->dev, "The qeth device driver "
  412. "failed to recover an error on the device\n");
  413. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  414. "available\n", dev_name(&card->gdev->dev));
  415. return -ENOMEM;
  416. }
  417. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  418. QETH_CARD_TEXT(card, 6, "noirqpnd");
  419. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  420. (addr_t) iob, 0, 0);
  421. if (rc) {
  422. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  423. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  424. atomic_set(&card->read.irq_pending, 0);
  425. card->read_or_write_problem = 1;
  426. qeth_schedule_recovery(card);
  427. wake_up(&card->wait_q);
  428. }
  429. return rc;
  430. }
  431. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  432. {
  433. struct qeth_reply *reply;
  434. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  435. if (reply) {
  436. atomic_set(&reply->refcnt, 1);
  437. atomic_set(&reply->received, 0);
  438. reply->card = card;
  439. }
  440. return reply;
  441. }
  442. static void qeth_get_reply(struct qeth_reply *reply)
  443. {
  444. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  445. atomic_inc(&reply->refcnt);
  446. }
  447. static void qeth_put_reply(struct qeth_reply *reply)
  448. {
  449. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  450. if (atomic_dec_and_test(&reply->refcnt))
  451. kfree(reply);
  452. }
  453. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  454. struct qeth_card *card)
  455. {
  456. char *ipa_name;
  457. int com = cmd->hdr.command;
  458. ipa_name = qeth_get_ipa_cmd_name(com);
  459. if (rc)
  460. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  461. "x%X \"%s\"\n",
  462. ipa_name, com, dev_name(&card->gdev->dev),
  463. QETH_CARD_IFNAME(card), rc,
  464. qeth_get_ipa_msg(rc));
  465. else
  466. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  467. ipa_name, com, dev_name(&card->gdev->dev),
  468. QETH_CARD_IFNAME(card));
  469. }
  470. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  471. struct qeth_cmd_buffer *iob)
  472. {
  473. struct qeth_ipa_cmd *cmd = NULL;
  474. QETH_CARD_TEXT(card, 5, "chkipad");
  475. if (IS_IPA(iob->data)) {
  476. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  477. if (IS_IPA_REPLY(cmd)) {
  478. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  479. cmd->hdr.command != IPA_CMD_DELCCID &&
  480. cmd->hdr.command != IPA_CMD_MODCCID &&
  481. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  482. qeth_issue_ipa_msg(cmd,
  483. cmd->hdr.return_code, card);
  484. return cmd;
  485. } else {
  486. switch (cmd->hdr.command) {
  487. case IPA_CMD_STOPLAN:
  488. dev_warn(&card->gdev->dev,
  489. "The link for interface %s on CHPID"
  490. " 0x%X failed\n",
  491. QETH_CARD_IFNAME(card),
  492. card->info.chpid);
  493. card->lan_online = 0;
  494. if (card->dev && netif_carrier_ok(card->dev))
  495. netif_carrier_off(card->dev);
  496. return NULL;
  497. case IPA_CMD_STARTLAN:
  498. dev_info(&card->gdev->dev,
  499. "The link for %s on CHPID 0x%X has"
  500. " been restored\n",
  501. QETH_CARD_IFNAME(card),
  502. card->info.chpid);
  503. netif_carrier_on(card->dev);
  504. card->lan_online = 1;
  505. if (card->info.hwtrap)
  506. card->info.hwtrap = 2;
  507. qeth_schedule_recovery(card);
  508. return NULL;
  509. case IPA_CMD_MODCCID:
  510. return cmd;
  511. case IPA_CMD_REGISTER_LOCAL_ADDR:
  512. QETH_CARD_TEXT(card, 3, "irla");
  513. break;
  514. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  515. QETH_CARD_TEXT(card, 3, "urla");
  516. break;
  517. default:
  518. QETH_DBF_MESSAGE(2, "Received data is IPA "
  519. "but not a reply!\n");
  520. break;
  521. }
  522. }
  523. }
  524. return cmd;
  525. }
  526. void qeth_clear_ipacmd_list(struct qeth_card *card)
  527. {
  528. struct qeth_reply *reply, *r;
  529. unsigned long flags;
  530. QETH_CARD_TEXT(card, 4, "clipalst");
  531. spin_lock_irqsave(&card->lock, flags);
  532. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  533. qeth_get_reply(reply);
  534. reply->rc = -EIO;
  535. atomic_inc(&reply->received);
  536. list_del_init(&reply->list);
  537. wake_up(&reply->wait_q);
  538. qeth_put_reply(reply);
  539. }
  540. spin_unlock_irqrestore(&card->lock, flags);
  541. atomic_set(&card->write.irq_pending, 0);
  542. }
  543. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  544. static int qeth_check_idx_response(struct qeth_card *card,
  545. unsigned char *buffer)
  546. {
  547. if (!buffer)
  548. return 0;
  549. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  550. if ((buffer[2] & 0xc0) == 0xc0) {
  551. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  552. "with cause code 0x%02x%s\n",
  553. buffer[4],
  554. ((buffer[4] == 0x22) ?
  555. " -- try another portname" : ""));
  556. QETH_CARD_TEXT(card, 2, "ckidxres");
  557. QETH_CARD_TEXT(card, 2, " idxterm");
  558. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  559. if (buffer[4] == 0xf6) {
  560. dev_err(&card->gdev->dev,
  561. "The qeth device is not configured "
  562. "for the OSI layer required by z/VM\n");
  563. return -EPERM;
  564. }
  565. return -EIO;
  566. }
  567. return 0;
  568. }
  569. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  570. __u32 len)
  571. {
  572. struct qeth_card *card;
  573. card = CARD_FROM_CDEV(channel->ccwdev);
  574. QETH_CARD_TEXT(card, 4, "setupccw");
  575. if (channel == &card->read)
  576. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  577. else
  578. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  579. channel->ccw.count = len;
  580. channel->ccw.cda = (__u32) __pa(iob);
  581. }
  582. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  583. {
  584. __u8 index;
  585. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  586. index = channel->io_buf_no;
  587. do {
  588. if (channel->iob[index].state == BUF_STATE_FREE) {
  589. channel->iob[index].state = BUF_STATE_LOCKED;
  590. channel->io_buf_no = (channel->io_buf_no + 1) %
  591. QETH_CMD_BUFFER_NO;
  592. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  593. return channel->iob + index;
  594. }
  595. index = (index + 1) % QETH_CMD_BUFFER_NO;
  596. } while (index != channel->io_buf_no);
  597. return NULL;
  598. }
  599. void qeth_release_buffer(struct qeth_channel *channel,
  600. struct qeth_cmd_buffer *iob)
  601. {
  602. unsigned long flags;
  603. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  604. spin_lock_irqsave(&channel->iob_lock, flags);
  605. memset(iob->data, 0, QETH_BUFSIZE);
  606. iob->state = BUF_STATE_FREE;
  607. iob->callback = qeth_send_control_data_cb;
  608. iob->rc = 0;
  609. spin_unlock_irqrestore(&channel->iob_lock, flags);
  610. wake_up(&channel->wait_q);
  611. }
  612. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  613. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  614. {
  615. struct qeth_cmd_buffer *buffer = NULL;
  616. unsigned long flags;
  617. spin_lock_irqsave(&channel->iob_lock, flags);
  618. buffer = __qeth_get_buffer(channel);
  619. spin_unlock_irqrestore(&channel->iob_lock, flags);
  620. return buffer;
  621. }
  622. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  623. {
  624. struct qeth_cmd_buffer *buffer;
  625. wait_event(channel->wait_q,
  626. ((buffer = qeth_get_buffer(channel)) != NULL));
  627. return buffer;
  628. }
  629. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  630. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  631. {
  632. int cnt;
  633. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  634. qeth_release_buffer(channel, &channel->iob[cnt]);
  635. channel->buf_no = 0;
  636. channel->io_buf_no = 0;
  637. }
  638. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  639. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  640. struct qeth_cmd_buffer *iob)
  641. {
  642. struct qeth_card *card;
  643. struct qeth_reply *reply, *r;
  644. struct qeth_ipa_cmd *cmd;
  645. unsigned long flags;
  646. int keep_reply;
  647. int rc = 0;
  648. card = CARD_FROM_CDEV(channel->ccwdev);
  649. QETH_CARD_TEXT(card, 4, "sndctlcb");
  650. rc = qeth_check_idx_response(card, iob->data);
  651. switch (rc) {
  652. case 0:
  653. break;
  654. case -EIO:
  655. qeth_clear_ipacmd_list(card);
  656. qeth_schedule_recovery(card);
  657. /* fall through */
  658. default:
  659. goto out;
  660. }
  661. cmd = qeth_check_ipa_data(card, iob);
  662. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  663. goto out;
  664. /*in case of OSN : check if cmd is set */
  665. if (card->info.type == QETH_CARD_TYPE_OSN &&
  666. cmd &&
  667. cmd->hdr.command != IPA_CMD_STARTLAN &&
  668. card->osn_info.assist_cb != NULL) {
  669. card->osn_info.assist_cb(card->dev, cmd);
  670. goto out;
  671. }
  672. spin_lock_irqsave(&card->lock, flags);
  673. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  674. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  675. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  676. qeth_get_reply(reply);
  677. list_del_init(&reply->list);
  678. spin_unlock_irqrestore(&card->lock, flags);
  679. keep_reply = 0;
  680. if (reply->callback != NULL) {
  681. if (cmd) {
  682. reply->offset = (__u16)((char *)cmd -
  683. (char *)iob->data);
  684. keep_reply = reply->callback(card,
  685. reply,
  686. (unsigned long)cmd);
  687. } else
  688. keep_reply = reply->callback(card,
  689. reply,
  690. (unsigned long)iob);
  691. }
  692. if (cmd)
  693. reply->rc = (u16) cmd->hdr.return_code;
  694. else if (iob->rc)
  695. reply->rc = iob->rc;
  696. if (keep_reply) {
  697. spin_lock_irqsave(&card->lock, flags);
  698. list_add_tail(&reply->list,
  699. &card->cmd_waiter_list);
  700. spin_unlock_irqrestore(&card->lock, flags);
  701. } else {
  702. atomic_inc(&reply->received);
  703. wake_up(&reply->wait_q);
  704. }
  705. qeth_put_reply(reply);
  706. goto out;
  707. }
  708. }
  709. spin_unlock_irqrestore(&card->lock, flags);
  710. out:
  711. memcpy(&card->seqno.pdu_hdr_ack,
  712. QETH_PDU_HEADER_SEQ_NO(iob->data),
  713. QETH_SEQ_NO_LENGTH);
  714. qeth_release_buffer(channel, iob);
  715. }
  716. static int qeth_setup_channel(struct qeth_channel *channel)
  717. {
  718. int cnt;
  719. QETH_DBF_TEXT(SETUP, 2, "setupch");
  720. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  721. channel->iob[cnt].data =
  722. kzalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  723. if (channel->iob[cnt].data == NULL)
  724. break;
  725. channel->iob[cnt].state = BUF_STATE_FREE;
  726. channel->iob[cnt].channel = channel;
  727. channel->iob[cnt].callback = qeth_send_control_data_cb;
  728. channel->iob[cnt].rc = 0;
  729. }
  730. if (cnt < QETH_CMD_BUFFER_NO) {
  731. while (cnt-- > 0)
  732. kfree(channel->iob[cnt].data);
  733. return -ENOMEM;
  734. }
  735. channel->buf_no = 0;
  736. channel->io_buf_no = 0;
  737. atomic_set(&channel->irq_pending, 0);
  738. spin_lock_init(&channel->iob_lock);
  739. init_waitqueue_head(&channel->wait_q);
  740. return 0;
  741. }
  742. static int qeth_set_thread_start_bit(struct qeth_card *card,
  743. unsigned long thread)
  744. {
  745. unsigned long flags;
  746. spin_lock_irqsave(&card->thread_mask_lock, flags);
  747. if (!(card->thread_allowed_mask & thread) ||
  748. (card->thread_start_mask & thread)) {
  749. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  750. return -EPERM;
  751. }
  752. card->thread_start_mask |= thread;
  753. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  754. return 0;
  755. }
  756. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  757. {
  758. unsigned long flags;
  759. spin_lock_irqsave(&card->thread_mask_lock, flags);
  760. card->thread_start_mask &= ~thread;
  761. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  762. wake_up(&card->wait_q);
  763. }
  764. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  765. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  766. {
  767. unsigned long flags;
  768. spin_lock_irqsave(&card->thread_mask_lock, flags);
  769. card->thread_running_mask &= ~thread;
  770. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  771. wake_up(&card->wait_q);
  772. }
  773. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  774. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  775. {
  776. unsigned long flags;
  777. int rc = 0;
  778. spin_lock_irqsave(&card->thread_mask_lock, flags);
  779. if (card->thread_start_mask & thread) {
  780. if ((card->thread_allowed_mask & thread) &&
  781. !(card->thread_running_mask & thread)) {
  782. rc = 1;
  783. card->thread_start_mask &= ~thread;
  784. card->thread_running_mask |= thread;
  785. } else
  786. rc = -EPERM;
  787. }
  788. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  789. return rc;
  790. }
  791. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  792. {
  793. int rc = 0;
  794. wait_event(card->wait_q,
  795. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  796. return rc;
  797. }
  798. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  799. void qeth_schedule_recovery(struct qeth_card *card)
  800. {
  801. QETH_CARD_TEXT(card, 2, "startrec");
  802. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  803. schedule_work(&card->kernel_thread_starter);
  804. }
  805. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  806. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  807. {
  808. int dstat, cstat;
  809. char *sense;
  810. struct qeth_card *card;
  811. sense = (char *) irb->ecw;
  812. cstat = irb->scsw.cmd.cstat;
  813. dstat = irb->scsw.cmd.dstat;
  814. card = CARD_FROM_CDEV(cdev);
  815. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  816. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  817. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  818. QETH_CARD_TEXT(card, 2, "CGENCHK");
  819. dev_warn(&cdev->dev, "The qeth device driver "
  820. "failed to recover an error on the device\n");
  821. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  822. dev_name(&cdev->dev), dstat, cstat);
  823. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  824. 16, 1, irb, 64, 1);
  825. return 1;
  826. }
  827. if (dstat & DEV_STAT_UNIT_CHECK) {
  828. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  829. SENSE_RESETTING_EVENT_FLAG) {
  830. QETH_CARD_TEXT(card, 2, "REVIND");
  831. return 1;
  832. }
  833. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  834. SENSE_COMMAND_REJECT_FLAG) {
  835. QETH_CARD_TEXT(card, 2, "CMDREJi");
  836. return 1;
  837. }
  838. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  839. QETH_CARD_TEXT(card, 2, "AFFE");
  840. return 1;
  841. }
  842. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  843. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  844. return 0;
  845. }
  846. QETH_CARD_TEXT(card, 2, "DGENCHK");
  847. return 1;
  848. }
  849. return 0;
  850. }
  851. static long __qeth_check_irb_error(struct ccw_device *cdev,
  852. unsigned long intparm, struct irb *irb)
  853. {
  854. struct qeth_card *card;
  855. card = CARD_FROM_CDEV(cdev);
  856. if (!IS_ERR(irb))
  857. return 0;
  858. switch (PTR_ERR(irb)) {
  859. case -EIO:
  860. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  861. dev_name(&cdev->dev));
  862. QETH_CARD_TEXT(card, 2, "ckirberr");
  863. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  864. break;
  865. case -ETIMEDOUT:
  866. dev_warn(&cdev->dev, "A hardware operation timed out"
  867. " on the device\n");
  868. QETH_CARD_TEXT(card, 2, "ckirberr");
  869. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  870. if (intparm == QETH_RCD_PARM) {
  871. if (card && (card->data.ccwdev == cdev)) {
  872. card->data.state = CH_STATE_DOWN;
  873. wake_up(&card->wait_q);
  874. }
  875. }
  876. break;
  877. default:
  878. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  879. dev_name(&cdev->dev), PTR_ERR(irb));
  880. QETH_CARD_TEXT(card, 2, "ckirberr");
  881. QETH_CARD_TEXT(card, 2, " rc???");
  882. }
  883. return PTR_ERR(irb);
  884. }
  885. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  886. struct irb *irb)
  887. {
  888. int rc;
  889. int cstat, dstat;
  890. struct qeth_cmd_buffer *buffer;
  891. struct qeth_channel *channel;
  892. struct qeth_card *card;
  893. struct qeth_cmd_buffer *iob;
  894. __u8 index;
  895. if (__qeth_check_irb_error(cdev, intparm, irb))
  896. return;
  897. cstat = irb->scsw.cmd.cstat;
  898. dstat = irb->scsw.cmd.dstat;
  899. card = CARD_FROM_CDEV(cdev);
  900. if (!card)
  901. return;
  902. QETH_CARD_TEXT(card, 5, "irq");
  903. if (card->read.ccwdev == cdev) {
  904. channel = &card->read;
  905. QETH_CARD_TEXT(card, 5, "read");
  906. } else if (card->write.ccwdev == cdev) {
  907. channel = &card->write;
  908. QETH_CARD_TEXT(card, 5, "write");
  909. } else {
  910. channel = &card->data;
  911. QETH_CARD_TEXT(card, 5, "data");
  912. }
  913. atomic_set(&channel->irq_pending, 0);
  914. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  915. channel->state = CH_STATE_STOPPED;
  916. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  917. channel->state = CH_STATE_HALTED;
  918. /*let's wake up immediately on data channel*/
  919. if ((channel == &card->data) && (intparm != 0) &&
  920. (intparm != QETH_RCD_PARM))
  921. goto out;
  922. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  923. QETH_CARD_TEXT(card, 6, "clrchpar");
  924. /* we don't have to handle this further */
  925. intparm = 0;
  926. }
  927. if (intparm == QETH_HALT_CHANNEL_PARM) {
  928. QETH_CARD_TEXT(card, 6, "hltchpar");
  929. /* we don't have to handle this further */
  930. intparm = 0;
  931. }
  932. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  933. (dstat & DEV_STAT_UNIT_CHECK) ||
  934. (cstat)) {
  935. if (irb->esw.esw0.erw.cons) {
  936. dev_warn(&channel->ccwdev->dev,
  937. "The qeth device driver failed to recover "
  938. "an error on the device\n");
  939. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  940. "0x%X dstat 0x%X\n",
  941. dev_name(&channel->ccwdev->dev), cstat, dstat);
  942. print_hex_dump(KERN_WARNING, "qeth: irb ",
  943. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  944. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  945. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  946. }
  947. if (intparm == QETH_RCD_PARM) {
  948. channel->state = CH_STATE_DOWN;
  949. goto out;
  950. }
  951. rc = qeth_get_problem(cdev, irb);
  952. if (rc) {
  953. qeth_clear_ipacmd_list(card);
  954. qeth_schedule_recovery(card);
  955. goto out;
  956. }
  957. }
  958. if (intparm == QETH_RCD_PARM) {
  959. channel->state = CH_STATE_RCD_DONE;
  960. goto out;
  961. }
  962. if (intparm) {
  963. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  964. buffer->state = BUF_STATE_PROCESSED;
  965. }
  966. if (channel == &card->data)
  967. return;
  968. if (channel == &card->read &&
  969. channel->state == CH_STATE_UP)
  970. qeth_issue_next_read(card);
  971. iob = channel->iob;
  972. index = channel->buf_no;
  973. while (iob[index].state == BUF_STATE_PROCESSED) {
  974. if (iob[index].callback != NULL)
  975. iob[index].callback(channel, iob + index);
  976. index = (index + 1) % QETH_CMD_BUFFER_NO;
  977. }
  978. channel->buf_no = index;
  979. out:
  980. wake_up(&card->wait_q);
  981. return;
  982. }
  983. static void qeth_notify_skbs(struct qeth_qdio_out_q *q,
  984. struct qeth_qdio_out_buffer *buf,
  985. enum iucv_tx_notify notification)
  986. {
  987. struct sk_buff *skb;
  988. if (skb_queue_empty(&buf->skb_list))
  989. goto out;
  990. skb = skb_peek(&buf->skb_list);
  991. while (skb) {
  992. QETH_CARD_TEXT_(q->card, 5, "skbn%d", notification);
  993. QETH_CARD_TEXT_(q->card, 5, "%lx", (long) skb);
  994. if (skb->protocol == ETH_P_AF_IUCV) {
  995. if (skb->sk) {
  996. struct iucv_sock *iucv = iucv_sk(skb->sk);
  997. iucv->sk_txnotify(skb, notification);
  998. }
  999. }
  1000. if (skb_queue_is_last(&buf->skb_list, skb))
  1001. skb = NULL;
  1002. else
  1003. skb = skb_queue_next(&buf->skb_list, skb);
  1004. }
  1005. out:
  1006. return;
  1007. }
  1008. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf)
  1009. {
  1010. struct sk_buff *skb;
  1011. struct iucv_sock *iucv;
  1012. int notify_general_error = 0;
  1013. if (atomic_read(&buf->state) == QETH_QDIO_BUF_PENDING)
  1014. notify_general_error = 1;
  1015. /* release may never happen from within CQ tasklet scope */
  1016. WARN_ON_ONCE(atomic_read(&buf->state) == QETH_QDIO_BUF_IN_CQ);
  1017. skb = skb_dequeue(&buf->skb_list);
  1018. while (skb) {
  1019. QETH_CARD_TEXT(buf->q->card, 5, "skbr");
  1020. QETH_CARD_TEXT_(buf->q->card, 5, "%lx", (long) skb);
  1021. if (notify_general_error && skb->protocol == ETH_P_AF_IUCV) {
  1022. if (skb->sk) {
  1023. iucv = iucv_sk(skb->sk);
  1024. iucv->sk_txnotify(skb, TX_NOTIFY_GENERALERROR);
  1025. }
  1026. }
  1027. atomic_dec(&skb->users);
  1028. dev_kfree_skb_any(skb);
  1029. skb = skb_dequeue(&buf->skb_list);
  1030. }
  1031. }
  1032. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  1033. struct qeth_qdio_out_buffer *buf,
  1034. enum qeth_qdio_buffer_states newbufstate)
  1035. {
  1036. int i;
  1037. /* is PCI flag set on buffer? */
  1038. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  1039. atomic_dec(&queue->set_pci_flags_count);
  1040. if (newbufstate == QETH_QDIO_BUF_EMPTY) {
  1041. qeth_release_skbs(buf);
  1042. }
  1043. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  1044. if (buf->buffer->element[i].addr && buf->is_header[i])
  1045. kmem_cache_free(qeth_core_header_cache,
  1046. buf->buffer->element[i].addr);
  1047. buf->is_header[i] = 0;
  1048. buf->buffer->element[i].length = 0;
  1049. buf->buffer->element[i].addr = NULL;
  1050. buf->buffer->element[i].eflags = 0;
  1051. buf->buffer->element[i].sflags = 0;
  1052. }
  1053. buf->buffer->element[15].eflags = 0;
  1054. buf->buffer->element[15].sflags = 0;
  1055. buf->next_element_to_fill = 0;
  1056. atomic_set(&buf->state, newbufstate);
  1057. }
  1058. static void qeth_clear_outq_buffers(struct qeth_qdio_out_q *q, int free)
  1059. {
  1060. int j;
  1061. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1062. if (!q->bufs[j])
  1063. continue;
  1064. qeth_cleanup_handled_pending(q, j, 1);
  1065. qeth_clear_output_buffer(q, q->bufs[j], QETH_QDIO_BUF_EMPTY);
  1066. if (free) {
  1067. kmem_cache_free(qeth_qdio_outbuf_cache, q->bufs[j]);
  1068. q->bufs[j] = NULL;
  1069. }
  1070. }
  1071. }
  1072. void qeth_clear_qdio_buffers(struct qeth_card *card)
  1073. {
  1074. int i;
  1075. QETH_CARD_TEXT(card, 2, "clearqdbf");
  1076. /* clear outbound buffers to free skbs */
  1077. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1078. if (card->qdio.out_qs[i]) {
  1079. qeth_clear_outq_buffers(card->qdio.out_qs[i], 0);
  1080. }
  1081. }
  1082. }
  1083. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  1084. static void qeth_free_buffer_pool(struct qeth_card *card)
  1085. {
  1086. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  1087. int i = 0;
  1088. list_for_each_entry_safe(pool_entry, tmp,
  1089. &card->qdio.init_pool.entry_list, init_list){
  1090. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  1091. free_page((unsigned long)pool_entry->elements[i]);
  1092. list_del(&pool_entry->init_list);
  1093. kfree(pool_entry);
  1094. }
  1095. }
  1096. static void qeth_free_qdio_buffers(struct qeth_card *card)
  1097. {
  1098. int i, j;
  1099. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  1100. QETH_QDIO_UNINITIALIZED)
  1101. return;
  1102. qeth_free_cq(card);
  1103. cancel_delayed_work_sync(&card->buffer_reclaim_work);
  1104. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  1105. dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);
  1106. kfree(card->qdio.in_q);
  1107. card->qdio.in_q = NULL;
  1108. /* inbound buffer pool */
  1109. qeth_free_buffer_pool(card);
  1110. /* free outbound qdio_qs */
  1111. if (card->qdio.out_qs) {
  1112. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1113. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  1114. kfree(card->qdio.out_qs[i]);
  1115. }
  1116. kfree(card->qdio.out_qs);
  1117. card->qdio.out_qs = NULL;
  1118. }
  1119. }
  1120. static void qeth_clean_channel(struct qeth_channel *channel)
  1121. {
  1122. int cnt;
  1123. QETH_DBF_TEXT(SETUP, 2, "freech");
  1124. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  1125. kfree(channel->iob[cnt].data);
  1126. }
  1127. static void qeth_set_single_write_queues(struct qeth_card *card)
  1128. {
  1129. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1130. (card->qdio.no_out_queues == 4))
  1131. qeth_free_qdio_buffers(card);
  1132. card->qdio.no_out_queues = 1;
  1133. if (card->qdio.default_out_queue != 0)
  1134. dev_info(&card->gdev->dev, "Priority Queueing not supported\n");
  1135. card->qdio.default_out_queue = 0;
  1136. }
  1137. static void qeth_set_multiple_write_queues(struct qeth_card *card)
  1138. {
  1139. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1140. (card->qdio.no_out_queues == 1)) {
  1141. qeth_free_qdio_buffers(card);
  1142. card->qdio.default_out_queue = 2;
  1143. }
  1144. card->qdio.no_out_queues = 4;
  1145. }
  1146. static void qeth_update_from_chp_desc(struct qeth_card *card)
  1147. {
  1148. struct ccw_device *ccwdev;
  1149. struct channelPath_dsc {
  1150. u8 flags;
  1151. u8 lsn;
  1152. u8 desc;
  1153. u8 chpid;
  1154. u8 swla;
  1155. u8 zeroes;
  1156. u8 chla;
  1157. u8 chpp;
  1158. } *chp_dsc;
  1159. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  1160. ccwdev = card->data.ccwdev;
  1161. chp_dsc = ccw_device_get_chp_desc(ccwdev, 0);
  1162. if (!chp_dsc)
  1163. goto out;
  1164. card->info.func_level = 0x4100 + chp_dsc->desc;
  1165. if (card->info.type == QETH_CARD_TYPE_IQD)
  1166. goto out;
  1167. /* CHPP field bit 6 == 1 -> single queue */
  1168. if ((chp_dsc->chpp & 0x02) == 0x02)
  1169. qeth_set_single_write_queues(card);
  1170. else
  1171. qeth_set_multiple_write_queues(card);
  1172. out:
  1173. kfree(chp_dsc);
  1174. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  1175. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  1176. }
  1177. static void qeth_init_qdio_info(struct qeth_card *card)
  1178. {
  1179. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  1180. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1181. /* inbound */
  1182. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1183. if (card->info.type == QETH_CARD_TYPE_IQD)
  1184. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  1185. else
  1186. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  1187. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  1188. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  1189. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  1190. }
  1191. static void qeth_set_intial_options(struct qeth_card *card)
  1192. {
  1193. card->options.route4.type = NO_ROUTER;
  1194. card->options.route6.type = NO_ROUTER;
  1195. card->options.fake_broadcast = 0;
  1196. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  1197. card->options.performance_stats = 0;
  1198. card->options.rx_sg_cb = QETH_RX_SG_CB;
  1199. card->options.isolation = ISOLATION_MODE_NONE;
  1200. card->options.cq = QETH_CQ_DISABLED;
  1201. }
  1202. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  1203. {
  1204. unsigned long flags;
  1205. int rc = 0;
  1206. spin_lock_irqsave(&card->thread_mask_lock, flags);
  1207. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  1208. (u8) card->thread_start_mask,
  1209. (u8) card->thread_allowed_mask,
  1210. (u8) card->thread_running_mask);
  1211. rc = (card->thread_start_mask & thread);
  1212. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  1213. return rc;
  1214. }
  1215. static void qeth_start_kernel_thread(struct work_struct *work)
  1216. {
  1217. struct task_struct *ts;
  1218. struct qeth_card *card = container_of(work, struct qeth_card,
  1219. kernel_thread_starter);
  1220. QETH_CARD_TEXT(card , 2, "strthrd");
  1221. if (card->read.state != CH_STATE_UP &&
  1222. card->write.state != CH_STATE_UP)
  1223. return;
  1224. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD)) {
  1225. ts = kthread_run(card->discipline->recover, (void *)card,
  1226. "qeth_recover");
  1227. if (IS_ERR(ts)) {
  1228. qeth_clear_thread_start_bit(card, QETH_RECOVER_THREAD);
  1229. qeth_clear_thread_running_bit(card,
  1230. QETH_RECOVER_THREAD);
  1231. }
  1232. }
  1233. }
  1234. static int qeth_setup_card(struct qeth_card *card)
  1235. {
  1236. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1237. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1238. card->read.state = CH_STATE_DOWN;
  1239. card->write.state = CH_STATE_DOWN;
  1240. card->data.state = CH_STATE_DOWN;
  1241. card->state = CARD_STATE_DOWN;
  1242. card->lan_online = 0;
  1243. card->read_or_write_problem = 0;
  1244. card->dev = NULL;
  1245. spin_lock_init(&card->vlanlock);
  1246. spin_lock_init(&card->mclock);
  1247. spin_lock_init(&card->lock);
  1248. spin_lock_init(&card->ip_lock);
  1249. spin_lock_init(&card->thread_mask_lock);
  1250. mutex_init(&card->conf_mutex);
  1251. mutex_init(&card->discipline_mutex);
  1252. card->thread_start_mask = 0;
  1253. card->thread_allowed_mask = 0;
  1254. card->thread_running_mask = 0;
  1255. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1256. INIT_LIST_HEAD(&card->ip_list);
  1257. INIT_LIST_HEAD(card->ip_tbd_list);
  1258. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1259. init_waitqueue_head(&card->wait_q);
  1260. /* initial options */
  1261. qeth_set_intial_options(card);
  1262. /* IP address takeover */
  1263. INIT_LIST_HEAD(&card->ipato.entries);
  1264. card->ipato.enabled = 0;
  1265. card->ipato.invert4 = 0;
  1266. card->ipato.invert6 = 0;
  1267. /* init QDIO stuff */
  1268. qeth_init_qdio_info(card);
  1269. INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
  1270. return 0;
  1271. }
  1272. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1273. {
  1274. struct qeth_card *card = container_of(slr, struct qeth_card,
  1275. qeth_service_level);
  1276. if (card->info.mcl_level[0])
  1277. seq_printf(m, "qeth: %s firmware level %s\n",
  1278. CARD_BUS_ID(card), card->info.mcl_level);
  1279. }
  1280. static struct qeth_card *qeth_alloc_card(void)
  1281. {
  1282. struct qeth_card *card;
  1283. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1284. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1285. if (!card)
  1286. goto out;
  1287. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1288. card->ip_tbd_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
  1289. if (!card->ip_tbd_list) {
  1290. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1291. goto out_card;
  1292. }
  1293. if (qeth_setup_channel(&card->read))
  1294. goto out_ip;
  1295. if (qeth_setup_channel(&card->write))
  1296. goto out_channel;
  1297. card->options.layer2 = -1;
  1298. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1299. register_service_level(&card->qeth_service_level);
  1300. return card;
  1301. out_channel:
  1302. qeth_clean_channel(&card->read);
  1303. out_ip:
  1304. kfree(card->ip_tbd_list);
  1305. out_card:
  1306. kfree(card);
  1307. out:
  1308. return NULL;
  1309. }
  1310. static int qeth_determine_card_type(struct qeth_card *card)
  1311. {
  1312. int i = 0;
  1313. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1314. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1315. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1316. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1317. if ((CARD_RDEV(card)->id.dev_type ==
  1318. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1319. (CARD_RDEV(card)->id.dev_model ==
  1320. known_devices[i][QETH_DEV_MODEL_IND])) {
  1321. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1322. card->qdio.no_out_queues =
  1323. known_devices[i][QETH_QUEUE_NO_IND];
  1324. card->qdio.no_in_queues = 1;
  1325. card->info.is_multicast_different =
  1326. known_devices[i][QETH_MULTICAST_IND];
  1327. qeth_update_from_chp_desc(card);
  1328. return 0;
  1329. }
  1330. i++;
  1331. }
  1332. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1333. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1334. "unknown type\n");
  1335. return -ENOENT;
  1336. }
  1337. static int qeth_clear_channel(struct qeth_channel *channel)
  1338. {
  1339. unsigned long flags;
  1340. struct qeth_card *card;
  1341. int rc;
  1342. card = CARD_FROM_CDEV(channel->ccwdev);
  1343. QETH_CARD_TEXT(card, 3, "clearch");
  1344. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1345. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1346. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1347. if (rc)
  1348. return rc;
  1349. rc = wait_event_interruptible_timeout(card->wait_q,
  1350. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1351. if (rc == -ERESTARTSYS)
  1352. return rc;
  1353. if (channel->state != CH_STATE_STOPPED)
  1354. return -ETIME;
  1355. channel->state = CH_STATE_DOWN;
  1356. return 0;
  1357. }
  1358. static int qeth_halt_channel(struct qeth_channel *channel)
  1359. {
  1360. unsigned long flags;
  1361. struct qeth_card *card;
  1362. int rc;
  1363. card = CARD_FROM_CDEV(channel->ccwdev);
  1364. QETH_CARD_TEXT(card, 3, "haltch");
  1365. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1366. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1367. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1368. if (rc)
  1369. return rc;
  1370. rc = wait_event_interruptible_timeout(card->wait_q,
  1371. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1372. if (rc == -ERESTARTSYS)
  1373. return rc;
  1374. if (channel->state != CH_STATE_HALTED)
  1375. return -ETIME;
  1376. return 0;
  1377. }
  1378. static int qeth_halt_channels(struct qeth_card *card)
  1379. {
  1380. int rc1 = 0, rc2 = 0, rc3 = 0;
  1381. QETH_CARD_TEXT(card, 3, "haltchs");
  1382. rc1 = qeth_halt_channel(&card->read);
  1383. rc2 = qeth_halt_channel(&card->write);
  1384. rc3 = qeth_halt_channel(&card->data);
  1385. if (rc1)
  1386. return rc1;
  1387. if (rc2)
  1388. return rc2;
  1389. return rc3;
  1390. }
  1391. static int qeth_clear_channels(struct qeth_card *card)
  1392. {
  1393. int rc1 = 0, rc2 = 0, rc3 = 0;
  1394. QETH_CARD_TEXT(card, 3, "clearchs");
  1395. rc1 = qeth_clear_channel(&card->read);
  1396. rc2 = qeth_clear_channel(&card->write);
  1397. rc3 = qeth_clear_channel(&card->data);
  1398. if (rc1)
  1399. return rc1;
  1400. if (rc2)
  1401. return rc2;
  1402. return rc3;
  1403. }
  1404. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1405. {
  1406. int rc = 0;
  1407. QETH_CARD_TEXT(card, 3, "clhacrd");
  1408. if (halt)
  1409. rc = qeth_halt_channels(card);
  1410. if (rc)
  1411. return rc;
  1412. return qeth_clear_channels(card);
  1413. }
  1414. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1415. {
  1416. int rc = 0;
  1417. QETH_CARD_TEXT(card, 3, "qdioclr");
  1418. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1419. QETH_QDIO_CLEANING)) {
  1420. case QETH_QDIO_ESTABLISHED:
  1421. if (card->info.type == QETH_CARD_TYPE_IQD)
  1422. rc = qdio_shutdown(CARD_DDEV(card),
  1423. QDIO_FLAG_CLEANUP_USING_HALT);
  1424. else
  1425. rc = qdio_shutdown(CARD_DDEV(card),
  1426. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1427. if (rc)
  1428. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1429. qdio_free(CARD_DDEV(card));
  1430. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1431. break;
  1432. case QETH_QDIO_CLEANING:
  1433. return rc;
  1434. default:
  1435. break;
  1436. }
  1437. rc = qeth_clear_halt_card(card, use_halt);
  1438. if (rc)
  1439. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1440. card->state = CARD_STATE_DOWN;
  1441. return rc;
  1442. }
  1443. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1444. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1445. int *length)
  1446. {
  1447. struct ciw *ciw;
  1448. char *rcd_buf;
  1449. int ret;
  1450. struct qeth_channel *channel = &card->data;
  1451. unsigned long flags;
  1452. /*
  1453. * scan for RCD command in extended SenseID data
  1454. */
  1455. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1456. if (!ciw || ciw->cmd == 0)
  1457. return -EOPNOTSUPP;
  1458. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1459. if (!rcd_buf)
  1460. return -ENOMEM;
  1461. channel->ccw.cmd_code = ciw->cmd;
  1462. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1463. channel->ccw.count = ciw->count;
  1464. channel->ccw.flags = CCW_FLAG_SLI;
  1465. channel->state = CH_STATE_RCD;
  1466. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1467. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1468. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1469. QETH_RCD_TIMEOUT);
  1470. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1471. if (!ret)
  1472. wait_event(card->wait_q,
  1473. (channel->state == CH_STATE_RCD_DONE ||
  1474. channel->state == CH_STATE_DOWN));
  1475. if (channel->state == CH_STATE_DOWN)
  1476. ret = -EIO;
  1477. else
  1478. channel->state = CH_STATE_DOWN;
  1479. if (ret) {
  1480. kfree(rcd_buf);
  1481. *buffer = NULL;
  1482. *length = 0;
  1483. } else {
  1484. *length = ciw->count;
  1485. *buffer = rcd_buf;
  1486. }
  1487. return ret;
  1488. }
  1489. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1490. {
  1491. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1492. card->info.chpid = prcd[30];
  1493. card->info.unit_addr2 = prcd[31];
  1494. card->info.cula = prcd[63];
  1495. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1496. (prcd[0x11] == _ascebc['M']));
  1497. }
  1498. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1499. {
  1500. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1501. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 &&
  1502. (prcd[76] == 0xF5 || prcd[76] == 0xF6)) {
  1503. card->info.blkt.time_total = 250;
  1504. card->info.blkt.inter_packet = 5;
  1505. card->info.blkt.inter_packet_jumbo = 15;
  1506. } else {
  1507. card->info.blkt.time_total = 0;
  1508. card->info.blkt.inter_packet = 0;
  1509. card->info.blkt.inter_packet_jumbo = 0;
  1510. }
  1511. }
  1512. static void qeth_init_tokens(struct qeth_card *card)
  1513. {
  1514. card->token.issuer_rm_w = 0x00010103UL;
  1515. card->token.cm_filter_w = 0x00010108UL;
  1516. card->token.cm_connection_w = 0x0001010aUL;
  1517. card->token.ulp_filter_w = 0x0001010bUL;
  1518. card->token.ulp_connection_w = 0x0001010dUL;
  1519. }
  1520. static void qeth_init_func_level(struct qeth_card *card)
  1521. {
  1522. switch (card->info.type) {
  1523. case QETH_CARD_TYPE_IQD:
  1524. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1525. break;
  1526. case QETH_CARD_TYPE_OSD:
  1527. case QETH_CARD_TYPE_OSN:
  1528. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1529. break;
  1530. default:
  1531. break;
  1532. }
  1533. }
  1534. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1535. void (*idx_reply_cb)(struct qeth_channel *,
  1536. struct qeth_cmd_buffer *))
  1537. {
  1538. struct qeth_cmd_buffer *iob;
  1539. unsigned long flags;
  1540. int rc;
  1541. struct qeth_card *card;
  1542. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1543. card = CARD_FROM_CDEV(channel->ccwdev);
  1544. iob = qeth_get_buffer(channel);
  1545. iob->callback = idx_reply_cb;
  1546. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1547. channel->ccw.count = QETH_BUFSIZE;
  1548. channel->ccw.cda = (__u32) __pa(iob->data);
  1549. wait_event(card->wait_q,
  1550. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1551. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1552. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1553. rc = ccw_device_start(channel->ccwdev,
  1554. &channel->ccw, (addr_t) iob, 0, 0);
  1555. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1556. if (rc) {
  1557. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1558. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1559. atomic_set(&channel->irq_pending, 0);
  1560. wake_up(&card->wait_q);
  1561. return rc;
  1562. }
  1563. rc = wait_event_interruptible_timeout(card->wait_q,
  1564. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1565. if (rc == -ERESTARTSYS)
  1566. return rc;
  1567. if (channel->state != CH_STATE_UP) {
  1568. rc = -ETIME;
  1569. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1570. qeth_clear_cmd_buffers(channel);
  1571. } else
  1572. rc = 0;
  1573. return rc;
  1574. }
  1575. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1576. void (*idx_reply_cb)(struct qeth_channel *,
  1577. struct qeth_cmd_buffer *))
  1578. {
  1579. struct qeth_card *card;
  1580. struct qeth_cmd_buffer *iob;
  1581. unsigned long flags;
  1582. __u16 temp;
  1583. __u8 tmp;
  1584. int rc;
  1585. struct ccw_dev_id temp_devid;
  1586. card = CARD_FROM_CDEV(channel->ccwdev);
  1587. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1588. iob = qeth_get_buffer(channel);
  1589. iob->callback = idx_reply_cb;
  1590. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1591. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1592. channel->ccw.cda = (__u32) __pa(iob->data);
  1593. if (channel == &card->write) {
  1594. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1595. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1596. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1597. card->seqno.trans_hdr++;
  1598. } else {
  1599. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1600. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1601. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1602. }
  1603. tmp = ((__u8)card->info.portno) | 0x80;
  1604. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1605. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1606. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1607. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1608. &card->info.func_level, sizeof(__u16));
  1609. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1610. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1611. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1612. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1613. wait_event(card->wait_q,
  1614. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1615. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1616. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1617. rc = ccw_device_start(channel->ccwdev,
  1618. &channel->ccw, (addr_t) iob, 0, 0);
  1619. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1620. if (rc) {
  1621. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1622. rc);
  1623. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1624. atomic_set(&channel->irq_pending, 0);
  1625. wake_up(&card->wait_q);
  1626. return rc;
  1627. }
  1628. rc = wait_event_interruptible_timeout(card->wait_q,
  1629. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1630. if (rc == -ERESTARTSYS)
  1631. return rc;
  1632. if (channel->state != CH_STATE_ACTIVATING) {
  1633. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1634. " failed to recover an error on the device\n");
  1635. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1636. dev_name(&channel->ccwdev->dev));
  1637. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1638. qeth_clear_cmd_buffers(channel);
  1639. return -ETIME;
  1640. }
  1641. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1642. }
  1643. static int qeth_peer_func_level(int level)
  1644. {
  1645. if ((level & 0xff) == 8)
  1646. return (level & 0xff) + 0x400;
  1647. if (((level >> 8) & 3) == 1)
  1648. return (level & 0xff) + 0x200;
  1649. return level;
  1650. }
  1651. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1652. struct qeth_cmd_buffer *iob)
  1653. {
  1654. struct qeth_card *card;
  1655. __u16 temp;
  1656. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1657. if (channel->state == CH_STATE_DOWN) {
  1658. channel->state = CH_STATE_ACTIVATING;
  1659. goto out;
  1660. }
  1661. card = CARD_FROM_CDEV(channel->ccwdev);
  1662. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1663. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1664. dev_err(&card->write.ccwdev->dev,
  1665. "The adapter is used exclusively by another "
  1666. "host\n");
  1667. else
  1668. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1669. " negative reply\n",
  1670. dev_name(&card->write.ccwdev->dev));
  1671. goto out;
  1672. }
  1673. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1674. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1675. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1676. "function level mismatch (sent: 0x%x, received: "
  1677. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1678. card->info.func_level, temp);
  1679. goto out;
  1680. }
  1681. channel->state = CH_STATE_UP;
  1682. out:
  1683. qeth_release_buffer(channel, iob);
  1684. }
  1685. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1686. struct qeth_cmd_buffer *iob)
  1687. {
  1688. struct qeth_card *card;
  1689. __u16 temp;
  1690. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1691. if (channel->state == CH_STATE_DOWN) {
  1692. channel->state = CH_STATE_ACTIVATING;
  1693. goto out;
  1694. }
  1695. card = CARD_FROM_CDEV(channel->ccwdev);
  1696. if (qeth_check_idx_response(card, iob->data))
  1697. goto out;
  1698. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1699. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1700. case QETH_IDX_ACT_ERR_EXCL:
  1701. dev_err(&card->write.ccwdev->dev,
  1702. "The adapter is used exclusively by another "
  1703. "host\n");
  1704. break;
  1705. case QETH_IDX_ACT_ERR_AUTH:
  1706. case QETH_IDX_ACT_ERR_AUTH_USER:
  1707. dev_err(&card->read.ccwdev->dev,
  1708. "Setting the device online failed because of "
  1709. "insufficient authorization\n");
  1710. break;
  1711. default:
  1712. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1713. " negative reply\n",
  1714. dev_name(&card->read.ccwdev->dev));
  1715. }
  1716. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1717. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1718. goto out;
  1719. }
  1720. /**
  1721. * * temporary fix for microcode bug
  1722. * * to revert it,replace OR by AND
  1723. * */
  1724. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1725. (card->info.type == QETH_CARD_TYPE_OSD))
  1726. card->info.portname_required = 1;
  1727. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1728. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1729. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1730. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1731. dev_name(&card->read.ccwdev->dev),
  1732. card->info.func_level, temp);
  1733. goto out;
  1734. }
  1735. memcpy(&card->token.issuer_rm_r,
  1736. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1737. QETH_MPC_TOKEN_LENGTH);
  1738. memcpy(&card->info.mcl_level[0],
  1739. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1740. channel->state = CH_STATE_UP;
  1741. out:
  1742. qeth_release_buffer(channel, iob);
  1743. }
  1744. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1745. struct qeth_cmd_buffer *iob)
  1746. {
  1747. qeth_setup_ccw(&card->write, iob->data, len);
  1748. iob->callback = qeth_release_buffer;
  1749. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1750. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1751. card->seqno.trans_hdr++;
  1752. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1753. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1754. card->seqno.pdu_hdr++;
  1755. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1756. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1757. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1758. }
  1759. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1760. int qeth_send_control_data(struct qeth_card *card, int len,
  1761. struct qeth_cmd_buffer *iob,
  1762. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1763. unsigned long),
  1764. void *reply_param)
  1765. {
  1766. int rc;
  1767. unsigned long flags;
  1768. struct qeth_reply *reply = NULL;
  1769. unsigned long timeout, event_timeout;
  1770. struct qeth_ipa_cmd *cmd;
  1771. QETH_CARD_TEXT(card, 2, "sendctl");
  1772. if (card->read_or_write_problem) {
  1773. qeth_release_buffer(iob->channel, iob);
  1774. return -EIO;
  1775. }
  1776. reply = qeth_alloc_reply(card);
  1777. if (!reply) {
  1778. return -ENOMEM;
  1779. }
  1780. reply->callback = reply_cb;
  1781. reply->param = reply_param;
  1782. if (card->state == CARD_STATE_DOWN)
  1783. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1784. else
  1785. reply->seqno = card->seqno.ipa++;
  1786. init_waitqueue_head(&reply->wait_q);
  1787. spin_lock_irqsave(&card->lock, flags);
  1788. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1789. spin_unlock_irqrestore(&card->lock, flags);
  1790. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1791. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1792. qeth_prepare_control_data(card, len, iob);
  1793. if (IS_IPA(iob->data))
  1794. event_timeout = QETH_IPA_TIMEOUT;
  1795. else
  1796. event_timeout = QETH_TIMEOUT;
  1797. timeout = jiffies + event_timeout;
  1798. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1799. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1800. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1801. (addr_t) iob, 0, 0);
  1802. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1803. if (rc) {
  1804. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1805. "ccw_device_start rc = %i\n",
  1806. dev_name(&card->write.ccwdev->dev), rc);
  1807. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1808. spin_lock_irqsave(&card->lock, flags);
  1809. list_del_init(&reply->list);
  1810. qeth_put_reply(reply);
  1811. spin_unlock_irqrestore(&card->lock, flags);
  1812. qeth_release_buffer(iob->channel, iob);
  1813. atomic_set(&card->write.irq_pending, 0);
  1814. wake_up(&card->wait_q);
  1815. return rc;
  1816. }
  1817. /* we have only one long running ipassist, since we can ensure
  1818. process context of this command we can sleep */
  1819. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1820. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1821. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1822. if (!wait_event_timeout(reply->wait_q,
  1823. atomic_read(&reply->received), event_timeout))
  1824. goto time_err;
  1825. } else {
  1826. while (!atomic_read(&reply->received)) {
  1827. if (time_after(jiffies, timeout))
  1828. goto time_err;
  1829. cpu_relax();
  1830. }
  1831. }
  1832. if (reply->rc == -EIO)
  1833. goto error;
  1834. rc = reply->rc;
  1835. qeth_put_reply(reply);
  1836. return rc;
  1837. time_err:
  1838. reply->rc = -ETIME;
  1839. spin_lock_irqsave(&reply->card->lock, flags);
  1840. list_del_init(&reply->list);
  1841. spin_unlock_irqrestore(&reply->card->lock, flags);
  1842. atomic_inc(&reply->received);
  1843. error:
  1844. atomic_set(&card->write.irq_pending, 0);
  1845. qeth_release_buffer(iob->channel, iob);
  1846. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1847. rc = reply->rc;
  1848. qeth_put_reply(reply);
  1849. return rc;
  1850. }
  1851. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1852. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1853. unsigned long data)
  1854. {
  1855. struct qeth_cmd_buffer *iob;
  1856. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1857. iob = (struct qeth_cmd_buffer *) data;
  1858. memcpy(&card->token.cm_filter_r,
  1859. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1860. QETH_MPC_TOKEN_LENGTH);
  1861. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1862. return 0;
  1863. }
  1864. static int qeth_cm_enable(struct qeth_card *card)
  1865. {
  1866. int rc;
  1867. struct qeth_cmd_buffer *iob;
  1868. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1869. iob = qeth_wait_for_buffer(&card->write);
  1870. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1871. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1872. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1873. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1874. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1875. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1876. qeth_cm_enable_cb, NULL);
  1877. return rc;
  1878. }
  1879. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1880. unsigned long data)
  1881. {
  1882. struct qeth_cmd_buffer *iob;
  1883. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1884. iob = (struct qeth_cmd_buffer *) data;
  1885. memcpy(&card->token.cm_connection_r,
  1886. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1887. QETH_MPC_TOKEN_LENGTH);
  1888. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1889. return 0;
  1890. }
  1891. static int qeth_cm_setup(struct qeth_card *card)
  1892. {
  1893. int rc;
  1894. struct qeth_cmd_buffer *iob;
  1895. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1896. iob = qeth_wait_for_buffer(&card->write);
  1897. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1898. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1899. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1900. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1901. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1902. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1903. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1904. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1905. qeth_cm_setup_cb, NULL);
  1906. return rc;
  1907. }
  1908. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1909. {
  1910. switch (card->info.type) {
  1911. case QETH_CARD_TYPE_UNKNOWN:
  1912. return 1500;
  1913. case QETH_CARD_TYPE_IQD:
  1914. return card->info.max_mtu;
  1915. case QETH_CARD_TYPE_OSD:
  1916. switch (card->info.link_type) {
  1917. case QETH_LINK_TYPE_HSTR:
  1918. case QETH_LINK_TYPE_LANE_TR:
  1919. return 2000;
  1920. default:
  1921. return 1492;
  1922. }
  1923. case QETH_CARD_TYPE_OSM:
  1924. case QETH_CARD_TYPE_OSX:
  1925. return 1492;
  1926. default:
  1927. return 1500;
  1928. }
  1929. }
  1930. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1931. {
  1932. switch (framesize) {
  1933. case 0x4000:
  1934. return 8192;
  1935. case 0x6000:
  1936. return 16384;
  1937. case 0xa000:
  1938. return 32768;
  1939. case 0xffff:
  1940. return 57344;
  1941. default:
  1942. return 0;
  1943. }
  1944. }
  1945. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1946. {
  1947. switch (card->info.type) {
  1948. case QETH_CARD_TYPE_OSD:
  1949. case QETH_CARD_TYPE_OSM:
  1950. case QETH_CARD_TYPE_OSX:
  1951. case QETH_CARD_TYPE_IQD:
  1952. return ((mtu >= 576) &&
  1953. (mtu <= card->info.max_mtu));
  1954. case QETH_CARD_TYPE_OSN:
  1955. case QETH_CARD_TYPE_UNKNOWN:
  1956. default:
  1957. return 1;
  1958. }
  1959. }
  1960. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1961. unsigned long data)
  1962. {
  1963. __u16 mtu, framesize;
  1964. __u16 len;
  1965. __u8 link_type;
  1966. struct qeth_cmd_buffer *iob;
  1967. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1968. iob = (struct qeth_cmd_buffer *) data;
  1969. memcpy(&card->token.ulp_filter_r,
  1970. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1971. QETH_MPC_TOKEN_LENGTH);
  1972. if (card->info.type == QETH_CARD_TYPE_IQD) {
  1973. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1974. mtu = qeth_get_mtu_outof_framesize(framesize);
  1975. if (!mtu) {
  1976. iob->rc = -EINVAL;
  1977. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1978. return 0;
  1979. }
  1980. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  1981. /* frame size has changed */
  1982. if (card->dev &&
  1983. ((card->dev->mtu == card->info.initial_mtu) ||
  1984. (card->dev->mtu > mtu)))
  1985. card->dev->mtu = mtu;
  1986. qeth_free_qdio_buffers(card);
  1987. }
  1988. card->info.initial_mtu = mtu;
  1989. card->info.max_mtu = mtu;
  1990. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1991. } else {
  1992. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1993. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  1994. iob->data);
  1995. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1996. }
  1997. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1998. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1999. memcpy(&link_type,
  2000. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  2001. card->info.link_type = link_type;
  2002. } else
  2003. card->info.link_type = 0;
  2004. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  2005. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2006. return 0;
  2007. }
  2008. static int qeth_ulp_enable(struct qeth_card *card)
  2009. {
  2010. int rc;
  2011. char prot_type;
  2012. struct qeth_cmd_buffer *iob;
  2013. /*FIXME: trace view callbacks*/
  2014. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  2015. iob = qeth_wait_for_buffer(&card->write);
  2016. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  2017. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  2018. (__u8) card->info.portno;
  2019. if (card->options.layer2)
  2020. if (card->info.type == QETH_CARD_TYPE_OSN)
  2021. prot_type = QETH_PROT_OSN2;
  2022. else
  2023. prot_type = QETH_PROT_LAYER2;
  2024. else
  2025. prot_type = QETH_PROT_TCPIP;
  2026. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  2027. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  2028. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2029. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  2030. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  2031. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  2032. card->info.portname, 9);
  2033. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  2034. qeth_ulp_enable_cb, NULL);
  2035. return rc;
  2036. }
  2037. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  2038. unsigned long data)
  2039. {
  2040. struct qeth_cmd_buffer *iob;
  2041. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  2042. iob = (struct qeth_cmd_buffer *) data;
  2043. memcpy(&card->token.ulp_connection_r,
  2044. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2045. QETH_MPC_TOKEN_LENGTH);
  2046. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2047. 3)) {
  2048. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  2049. dev_err(&card->gdev->dev, "A connection could not be "
  2050. "established because of an OLM limit\n");
  2051. iob->rc = -EMLINK;
  2052. }
  2053. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2054. return 0;
  2055. }
  2056. static int qeth_ulp_setup(struct qeth_card *card)
  2057. {
  2058. int rc;
  2059. __u16 temp;
  2060. struct qeth_cmd_buffer *iob;
  2061. struct ccw_dev_id dev_id;
  2062. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  2063. iob = qeth_wait_for_buffer(&card->write);
  2064. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  2065. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  2066. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2067. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  2068. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  2069. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  2070. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  2071. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  2072. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  2073. temp = (card->info.cula << 8) + card->info.unit_addr2;
  2074. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  2075. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  2076. qeth_ulp_setup_cb, NULL);
  2077. return rc;
  2078. }
  2079. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *q, int bidx)
  2080. {
  2081. int rc;
  2082. struct qeth_qdio_out_buffer *newbuf;
  2083. rc = 0;
  2084. newbuf = kmem_cache_zalloc(qeth_qdio_outbuf_cache, GFP_ATOMIC);
  2085. if (!newbuf) {
  2086. rc = -ENOMEM;
  2087. goto out;
  2088. }
  2089. newbuf->buffer = &q->qdio_bufs[bidx];
  2090. skb_queue_head_init(&newbuf->skb_list);
  2091. lockdep_set_class(&newbuf->skb_list.lock, &qdio_out_skb_queue_key);
  2092. newbuf->q = q;
  2093. newbuf->aob = NULL;
  2094. newbuf->next_pending = q->bufs[bidx];
  2095. atomic_set(&newbuf->state, QETH_QDIO_BUF_EMPTY);
  2096. q->bufs[bidx] = newbuf;
  2097. if (q->bufstates) {
  2098. q->bufstates[bidx].user = newbuf;
  2099. QETH_CARD_TEXT_(q->card, 2, "nbs%d", bidx);
  2100. QETH_CARD_TEXT_(q->card, 2, "%lx", (long) newbuf);
  2101. QETH_CARD_TEXT_(q->card, 2, "%lx",
  2102. (long) newbuf->next_pending);
  2103. }
  2104. out:
  2105. return rc;
  2106. }
  2107. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  2108. {
  2109. int i, j;
  2110. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  2111. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  2112. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  2113. return 0;
  2114. card->qdio.in_q = kzalloc(sizeof(struct qeth_qdio_q),
  2115. GFP_KERNEL);
  2116. if (!card->qdio.in_q)
  2117. goto out_nomem;
  2118. QETH_DBF_TEXT(SETUP, 2, "inq");
  2119. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  2120. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  2121. /* give inbound qeth_qdio_buffers their qdio_buffers */
  2122. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  2123. card->qdio.in_q->bufs[i].buffer =
  2124. &card->qdio.in_q->qdio_bufs[i];
  2125. card->qdio.in_q->bufs[i].rx_skb = NULL;
  2126. }
  2127. /* inbound buffer pool */
  2128. if (qeth_alloc_buffer_pool(card))
  2129. goto out_freeinq;
  2130. /* outbound */
  2131. card->qdio.out_qs =
  2132. kzalloc(card->qdio.no_out_queues *
  2133. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  2134. if (!card->qdio.out_qs)
  2135. goto out_freepool;
  2136. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2137. card->qdio.out_qs[i] = kzalloc(sizeof(struct qeth_qdio_out_q),
  2138. GFP_KERNEL);
  2139. if (!card->qdio.out_qs[i])
  2140. goto out_freeoutq;
  2141. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  2142. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  2143. card->qdio.out_qs[i]->queue_no = i;
  2144. /* give outbound qeth_qdio_buffers their qdio_buffers */
  2145. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2146. WARN_ON(card->qdio.out_qs[i]->bufs[j] != NULL);
  2147. if (qeth_init_qdio_out_buf(card->qdio.out_qs[i], j))
  2148. goto out_freeoutqbufs;
  2149. }
  2150. }
  2151. /* completion */
  2152. if (qeth_alloc_cq(card))
  2153. goto out_freeoutq;
  2154. return 0;
  2155. out_freeoutqbufs:
  2156. while (j > 0) {
  2157. --j;
  2158. kmem_cache_free(qeth_qdio_outbuf_cache,
  2159. card->qdio.out_qs[i]->bufs[j]);
  2160. card->qdio.out_qs[i]->bufs[j] = NULL;
  2161. }
  2162. out_freeoutq:
  2163. while (i > 0) {
  2164. kfree(card->qdio.out_qs[--i]);
  2165. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2166. }
  2167. kfree(card->qdio.out_qs);
  2168. card->qdio.out_qs = NULL;
  2169. out_freepool:
  2170. qeth_free_buffer_pool(card);
  2171. out_freeinq:
  2172. kfree(card->qdio.in_q);
  2173. card->qdio.in_q = NULL;
  2174. out_nomem:
  2175. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  2176. return -ENOMEM;
  2177. }
  2178. static void qeth_create_qib_param_field(struct qeth_card *card,
  2179. char *param_field)
  2180. {
  2181. param_field[0] = _ascebc['P'];
  2182. param_field[1] = _ascebc['C'];
  2183. param_field[2] = _ascebc['I'];
  2184. param_field[3] = _ascebc['T'];
  2185. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  2186. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  2187. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  2188. }
  2189. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  2190. char *param_field)
  2191. {
  2192. param_field[16] = _ascebc['B'];
  2193. param_field[17] = _ascebc['L'];
  2194. param_field[18] = _ascebc['K'];
  2195. param_field[19] = _ascebc['T'];
  2196. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  2197. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  2198. *((unsigned int *) (&param_field[28])) =
  2199. card->info.blkt.inter_packet_jumbo;
  2200. }
  2201. static int qeth_qdio_activate(struct qeth_card *card)
  2202. {
  2203. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  2204. return qdio_activate(CARD_DDEV(card));
  2205. }
  2206. static int qeth_dm_act(struct qeth_card *card)
  2207. {
  2208. int rc;
  2209. struct qeth_cmd_buffer *iob;
  2210. QETH_DBF_TEXT(SETUP, 2, "dmact");
  2211. iob = qeth_wait_for_buffer(&card->write);
  2212. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  2213. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  2214. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2215. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  2216. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2217. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  2218. return rc;
  2219. }
  2220. static int qeth_mpc_initialize(struct qeth_card *card)
  2221. {
  2222. int rc;
  2223. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  2224. rc = qeth_issue_next_read(card);
  2225. if (rc) {
  2226. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2227. return rc;
  2228. }
  2229. rc = qeth_cm_enable(card);
  2230. if (rc) {
  2231. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2232. goto out_qdio;
  2233. }
  2234. rc = qeth_cm_setup(card);
  2235. if (rc) {
  2236. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  2237. goto out_qdio;
  2238. }
  2239. rc = qeth_ulp_enable(card);
  2240. if (rc) {
  2241. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  2242. goto out_qdio;
  2243. }
  2244. rc = qeth_ulp_setup(card);
  2245. if (rc) {
  2246. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2247. goto out_qdio;
  2248. }
  2249. rc = qeth_alloc_qdio_buffers(card);
  2250. if (rc) {
  2251. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2252. goto out_qdio;
  2253. }
  2254. rc = qeth_qdio_establish(card);
  2255. if (rc) {
  2256. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  2257. qeth_free_qdio_buffers(card);
  2258. goto out_qdio;
  2259. }
  2260. rc = qeth_qdio_activate(card);
  2261. if (rc) {
  2262. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2263. goto out_qdio;
  2264. }
  2265. rc = qeth_dm_act(card);
  2266. if (rc) {
  2267. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2268. goto out_qdio;
  2269. }
  2270. return 0;
  2271. out_qdio:
  2272. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2273. return rc;
  2274. }
  2275. static void qeth_print_status_with_portname(struct qeth_card *card)
  2276. {
  2277. char dbf_text[15];
  2278. int i;
  2279. sprintf(dbf_text, "%s", card->info.portname + 1);
  2280. for (i = 0; i < 8; i++)
  2281. dbf_text[i] =
  2282. (char) _ebcasc[(__u8) dbf_text[i]];
  2283. dbf_text[8] = 0;
  2284. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2285. "with link type %s (portname: %s)\n",
  2286. qeth_get_cardname(card),
  2287. (card->info.mcl_level[0]) ? " (level: " : "",
  2288. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2289. (card->info.mcl_level[0]) ? ")" : "",
  2290. qeth_get_cardname_short(card),
  2291. dbf_text);
  2292. }
  2293. static void qeth_print_status_no_portname(struct qeth_card *card)
  2294. {
  2295. if (card->info.portname[0])
  2296. dev_info(&card->gdev->dev, "Device is a%s "
  2297. "card%s%s%s\nwith link type %s "
  2298. "(no portname needed by interface).\n",
  2299. qeth_get_cardname(card),
  2300. (card->info.mcl_level[0]) ? " (level: " : "",
  2301. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2302. (card->info.mcl_level[0]) ? ")" : "",
  2303. qeth_get_cardname_short(card));
  2304. else
  2305. dev_info(&card->gdev->dev, "Device is a%s "
  2306. "card%s%s%s\nwith link type %s.\n",
  2307. qeth_get_cardname(card),
  2308. (card->info.mcl_level[0]) ? " (level: " : "",
  2309. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2310. (card->info.mcl_level[0]) ? ")" : "",
  2311. qeth_get_cardname_short(card));
  2312. }
  2313. void qeth_print_status_message(struct qeth_card *card)
  2314. {
  2315. switch (card->info.type) {
  2316. case QETH_CARD_TYPE_OSD:
  2317. case QETH_CARD_TYPE_OSM:
  2318. case QETH_CARD_TYPE_OSX:
  2319. /* VM will use a non-zero first character
  2320. * to indicate a HiperSockets like reporting
  2321. * of the level OSA sets the first character to zero
  2322. * */
  2323. if (!card->info.mcl_level[0]) {
  2324. sprintf(card->info.mcl_level, "%02x%02x",
  2325. card->info.mcl_level[2],
  2326. card->info.mcl_level[3]);
  2327. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2328. break;
  2329. }
  2330. /* fallthrough */
  2331. case QETH_CARD_TYPE_IQD:
  2332. if ((card->info.guestlan) ||
  2333. (card->info.mcl_level[0] & 0x80)) {
  2334. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2335. card->info.mcl_level[0]];
  2336. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2337. card->info.mcl_level[1]];
  2338. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2339. card->info.mcl_level[2]];
  2340. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2341. card->info.mcl_level[3]];
  2342. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2343. }
  2344. break;
  2345. default:
  2346. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2347. }
  2348. if (card->info.portname_required)
  2349. qeth_print_status_with_portname(card);
  2350. else
  2351. qeth_print_status_no_portname(card);
  2352. }
  2353. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2354. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2355. {
  2356. struct qeth_buffer_pool_entry *entry;
  2357. QETH_CARD_TEXT(card, 5, "inwrklst");
  2358. list_for_each_entry(entry,
  2359. &card->qdio.init_pool.entry_list, init_list) {
  2360. qeth_put_buffer_pool_entry(card, entry);
  2361. }
  2362. }
  2363. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2364. struct qeth_card *card)
  2365. {
  2366. struct list_head *plh;
  2367. struct qeth_buffer_pool_entry *entry;
  2368. int i, free;
  2369. struct page *page;
  2370. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2371. return NULL;
  2372. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2373. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2374. free = 1;
  2375. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2376. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2377. free = 0;
  2378. break;
  2379. }
  2380. }
  2381. if (free) {
  2382. list_del_init(&entry->list);
  2383. return entry;
  2384. }
  2385. }
  2386. /* no free buffer in pool so take first one and swap pages */
  2387. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2388. struct qeth_buffer_pool_entry, list);
  2389. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2390. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2391. page = alloc_page(GFP_ATOMIC);
  2392. if (!page) {
  2393. return NULL;
  2394. } else {
  2395. free_page((unsigned long)entry->elements[i]);
  2396. entry->elements[i] = page_address(page);
  2397. if (card->options.performance_stats)
  2398. card->perf_stats.sg_alloc_page_rx++;
  2399. }
  2400. }
  2401. }
  2402. list_del_init(&entry->list);
  2403. return entry;
  2404. }
  2405. static int qeth_init_input_buffer(struct qeth_card *card,
  2406. struct qeth_qdio_buffer *buf)
  2407. {
  2408. struct qeth_buffer_pool_entry *pool_entry;
  2409. int i;
  2410. if ((card->options.cq == QETH_CQ_ENABLED) && (!buf->rx_skb)) {
  2411. buf->rx_skb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  2412. if (!buf->rx_skb)
  2413. return 1;
  2414. }
  2415. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2416. if (!pool_entry)
  2417. return 1;
  2418. /*
  2419. * since the buffer is accessed only from the input_tasklet
  2420. * there shouldn't be a need to synchronize; also, since we use
  2421. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2422. * buffers
  2423. */
  2424. buf->pool_entry = pool_entry;
  2425. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2426. buf->buffer->element[i].length = PAGE_SIZE;
  2427. buf->buffer->element[i].addr = pool_entry->elements[i];
  2428. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2429. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2430. else
  2431. buf->buffer->element[i].eflags = 0;
  2432. buf->buffer->element[i].sflags = 0;
  2433. }
  2434. return 0;
  2435. }
  2436. int qeth_init_qdio_queues(struct qeth_card *card)
  2437. {
  2438. int i, j;
  2439. int rc;
  2440. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2441. /* inbound queue */
  2442. memset(card->qdio.in_q->qdio_bufs, 0,
  2443. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2444. qeth_initialize_working_pool_list(card);
  2445. /*give only as many buffers to hardware as we have buffer pool entries*/
  2446. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2447. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2448. card->qdio.in_q->next_buf_to_init =
  2449. card->qdio.in_buf_pool.buf_count - 1;
  2450. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2451. card->qdio.in_buf_pool.buf_count - 1);
  2452. if (rc) {
  2453. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2454. return rc;
  2455. }
  2456. /* completion */
  2457. rc = qeth_cq_init(card);
  2458. if (rc) {
  2459. return rc;
  2460. }
  2461. /* outbound queue */
  2462. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2463. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2464. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2465. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2466. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2467. card->qdio.out_qs[i]->bufs[j],
  2468. QETH_QDIO_BUF_EMPTY);
  2469. }
  2470. card->qdio.out_qs[i]->card = card;
  2471. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2472. card->qdio.out_qs[i]->do_pack = 0;
  2473. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2474. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2475. atomic_set(&card->qdio.out_qs[i]->state,
  2476. QETH_OUT_Q_UNLOCKED);
  2477. }
  2478. return 0;
  2479. }
  2480. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2481. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2482. {
  2483. switch (link_type) {
  2484. case QETH_LINK_TYPE_HSTR:
  2485. return 2;
  2486. default:
  2487. return 1;
  2488. }
  2489. }
  2490. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2491. struct qeth_ipa_cmd *cmd, __u8 command,
  2492. enum qeth_prot_versions prot)
  2493. {
  2494. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2495. cmd->hdr.command = command;
  2496. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2497. cmd->hdr.seqno = card->seqno.ipa;
  2498. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2499. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2500. if (card->options.layer2)
  2501. cmd->hdr.prim_version_no = 2;
  2502. else
  2503. cmd->hdr.prim_version_no = 1;
  2504. cmd->hdr.param_count = 1;
  2505. cmd->hdr.prot_version = prot;
  2506. cmd->hdr.ipa_supported = 0;
  2507. cmd->hdr.ipa_enabled = 0;
  2508. }
  2509. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2510. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2511. {
  2512. struct qeth_cmd_buffer *iob;
  2513. struct qeth_ipa_cmd *cmd;
  2514. iob = qeth_wait_for_buffer(&card->write);
  2515. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2516. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2517. return iob;
  2518. }
  2519. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2520. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2521. char prot_type)
  2522. {
  2523. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2524. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2525. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2526. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2527. }
  2528. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2529. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2530. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2531. unsigned long),
  2532. void *reply_param)
  2533. {
  2534. int rc;
  2535. char prot_type;
  2536. QETH_CARD_TEXT(card, 4, "sendipa");
  2537. if (card->options.layer2)
  2538. if (card->info.type == QETH_CARD_TYPE_OSN)
  2539. prot_type = QETH_PROT_OSN2;
  2540. else
  2541. prot_type = QETH_PROT_LAYER2;
  2542. else
  2543. prot_type = QETH_PROT_TCPIP;
  2544. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2545. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2546. iob, reply_cb, reply_param);
  2547. if (rc == -ETIME) {
  2548. qeth_clear_ipacmd_list(card);
  2549. qeth_schedule_recovery(card);
  2550. }
  2551. return rc;
  2552. }
  2553. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2554. int qeth_send_startlan(struct qeth_card *card)
  2555. {
  2556. int rc;
  2557. struct qeth_cmd_buffer *iob;
  2558. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2559. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2560. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2561. return rc;
  2562. }
  2563. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2564. static int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2565. struct qeth_reply *reply, unsigned long data)
  2566. {
  2567. struct qeth_ipa_cmd *cmd;
  2568. QETH_CARD_TEXT(card, 4, "defadpcb");
  2569. cmd = (struct qeth_ipa_cmd *) data;
  2570. if (cmd->hdr.return_code == 0)
  2571. cmd->hdr.return_code =
  2572. cmd->data.setadapterparms.hdr.return_code;
  2573. return 0;
  2574. }
  2575. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2576. struct qeth_reply *reply, unsigned long data)
  2577. {
  2578. struct qeth_ipa_cmd *cmd;
  2579. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2580. cmd = (struct qeth_ipa_cmd *) data;
  2581. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2582. card->info.link_type =
  2583. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2584. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2585. }
  2586. card->options.adp.supported_funcs =
  2587. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2588. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2589. }
  2590. static struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2591. __u32 command, __u32 cmdlen)
  2592. {
  2593. struct qeth_cmd_buffer *iob;
  2594. struct qeth_ipa_cmd *cmd;
  2595. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2596. QETH_PROT_IPV4);
  2597. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2598. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2599. cmd->data.setadapterparms.hdr.command_code = command;
  2600. cmd->data.setadapterparms.hdr.used_total = 1;
  2601. cmd->data.setadapterparms.hdr.seq_no = 1;
  2602. return iob;
  2603. }
  2604. int qeth_query_setadapterparms(struct qeth_card *card)
  2605. {
  2606. int rc;
  2607. struct qeth_cmd_buffer *iob;
  2608. QETH_CARD_TEXT(card, 3, "queryadp");
  2609. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2610. sizeof(struct qeth_ipacmd_setadpparms));
  2611. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2612. return rc;
  2613. }
  2614. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2615. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2616. struct qeth_reply *reply, unsigned long data)
  2617. {
  2618. struct qeth_ipa_cmd *cmd;
  2619. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2620. cmd = (struct qeth_ipa_cmd *) data;
  2621. switch (cmd->hdr.return_code) {
  2622. case IPA_RC_NOTSUPP:
  2623. case IPA_RC_L2_UNSUPPORTED_CMD:
  2624. QETH_DBF_TEXT(SETUP, 2, "ipaunsup");
  2625. card->options.ipa4.supported_funcs |= IPA_SETADAPTERPARMS;
  2626. card->options.ipa6.supported_funcs |= IPA_SETADAPTERPARMS;
  2627. return -0;
  2628. default:
  2629. if (cmd->hdr.return_code) {
  2630. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Unhandled "
  2631. "rc=%d\n",
  2632. dev_name(&card->gdev->dev),
  2633. cmd->hdr.return_code);
  2634. return 0;
  2635. }
  2636. }
  2637. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2638. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2639. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2640. } else if (cmd->hdr.prot_version == QETH_PROT_IPV6) {
  2641. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2642. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2643. } else
  2644. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Flawed LIC detected"
  2645. "\n", dev_name(&card->gdev->dev));
  2646. return 0;
  2647. }
  2648. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2649. {
  2650. int rc;
  2651. struct qeth_cmd_buffer *iob;
  2652. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2653. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2654. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2655. return rc;
  2656. }
  2657. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2658. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2659. struct qeth_reply *reply, unsigned long data)
  2660. {
  2661. struct qeth_ipa_cmd *cmd;
  2662. __u16 rc;
  2663. cmd = (struct qeth_ipa_cmd *)data;
  2664. rc = cmd->hdr.return_code;
  2665. if (rc)
  2666. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2667. else
  2668. card->info.diagass_support = cmd->data.diagass.ext;
  2669. return 0;
  2670. }
  2671. static int qeth_query_setdiagass(struct qeth_card *card)
  2672. {
  2673. struct qeth_cmd_buffer *iob;
  2674. struct qeth_ipa_cmd *cmd;
  2675. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2676. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2677. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2678. cmd->data.diagass.subcmd_len = 16;
  2679. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2680. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2681. }
  2682. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2683. {
  2684. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2685. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2686. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2687. struct ccw_dev_id ccwid;
  2688. int level;
  2689. tid->chpid = card->info.chpid;
  2690. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2691. tid->ssid = ccwid.ssid;
  2692. tid->devno = ccwid.devno;
  2693. if (!info)
  2694. return;
  2695. level = stsi(NULL, 0, 0, 0);
  2696. if ((level >= 2) && (stsi(info222, 2, 2, 2) == 0))
  2697. tid->lparnr = info222->lpar_number;
  2698. if ((level >= 3) && (stsi(info322, 3, 2, 2) == 0)) {
  2699. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2700. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2701. }
  2702. free_page(info);
  2703. return;
  2704. }
  2705. static int qeth_hw_trap_cb(struct qeth_card *card,
  2706. struct qeth_reply *reply, unsigned long data)
  2707. {
  2708. struct qeth_ipa_cmd *cmd;
  2709. __u16 rc;
  2710. cmd = (struct qeth_ipa_cmd *)data;
  2711. rc = cmd->hdr.return_code;
  2712. if (rc)
  2713. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2714. return 0;
  2715. }
  2716. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2717. {
  2718. struct qeth_cmd_buffer *iob;
  2719. struct qeth_ipa_cmd *cmd;
  2720. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2721. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2722. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2723. cmd->data.diagass.subcmd_len = 80;
  2724. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2725. cmd->data.diagass.type = 1;
  2726. cmd->data.diagass.action = action;
  2727. switch (action) {
  2728. case QETH_DIAGS_TRAP_ARM:
  2729. cmd->data.diagass.options = 0x0003;
  2730. cmd->data.diagass.ext = 0x00010000 +
  2731. sizeof(struct qeth_trap_id);
  2732. qeth_get_trap_id(card,
  2733. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2734. break;
  2735. case QETH_DIAGS_TRAP_DISARM:
  2736. cmd->data.diagass.options = 0x0001;
  2737. break;
  2738. case QETH_DIAGS_TRAP_CAPTURE:
  2739. break;
  2740. }
  2741. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2742. }
  2743. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2744. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2745. unsigned int qdio_error, const char *dbftext)
  2746. {
  2747. if (qdio_error) {
  2748. QETH_CARD_TEXT(card, 2, dbftext);
  2749. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2750. buf->element[15].sflags);
  2751. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2752. buf->element[14].sflags);
  2753. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2754. if ((buf->element[15].sflags) == 0x12) {
  2755. card->stats.rx_dropped++;
  2756. return 0;
  2757. } else
  2758. return 1;
  2759. }
  2760. return 0;
  2761. }
  2762. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2763. void qeth_buffer_reclaim_work(struct work_struct *work)
  2764. {
  2765. struct qeth_card *card = container_of(work, struct qeth_card,
  2766. buffer_reclaim_work.work);
  2767. QETH_CARD_TEXT_(card, 2, "brw:%x", card->reclaim_index);
  2768. qeth_queue_input_buffer(card, card->reclaim_index);
  2769. }
  2770. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2771. {
  2772. struct qeth_qdio_q *queue = card->qdio.in_q;
  2773. struct list_head *lh;
  2774. int count;
  2775. int i;
  2776. int rc;
  2777. int newcount = 0;
  2778. count = (index < queue->next_buf_to_init)?
  2779. card->qdio.in_buf_pool.buf_count -
  2780. (queue->next_buf_to_init - index) :
  2781. card->qdio.in_buf_pool.buf_count -
  2782. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2783. /* only requeue at a certain threshold to avoid SIGAs */
  2784. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2785. for (i = queue->next_buf_to_init;
  2786. i < queue->next_buf_to_init + count; ++i) {
  2787. if (qeth_init_input_buffer(card,
  2788. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2789. break;
  2790. } else {
  2791. newcount++;
  2792. }
  2793. }
  2794. if (newcount < count) {
  2795. /* we are in memory shortage so we switch back to
  2796. traditional skb allocation and drop packages */
  2797. atomic_set(&card->force_alloc_skb, 3);
  2798. count = newcount;
  2799. } else {
  2800. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2801. }
  2802. if (!count) {
  2803. i = 0;
  2804. list_for_each(lh, &card->qdio.in_buf_pool.entry_list)
  2805. i++;
  2806. if (i == card->qdio.in_buf_pool.buf_count) {
  2807. QETH_CARD_TEXT(card, 2, "qsarbw");
  2808. card->reclaim_index = index;
  2809. schedule_delayed_work(
  2810. &card->buffer_reclaim_work,
  2811. QETH_RECLAIM_WORK_TIME);
  2812. }
  2813. return;
  2814. }
  2815. /*
  2816. * according to old code it should be avoided to requeue all
  2817. * 128 buffers in order to benefit from PCI avoidance.
  2818. * this function keeps at least one buffer (the buffer at
  2819. * 'index') un-requeued -> this buffer is the first buffer that
  2820. * will be requeued the next time
  2821. */
  2822. if (card->options.performance_stats) {
  2823. card->perf_stats.inbound_do_qdio_cnt++;
  2824. card->perf_stats.inbound_do_qdio_start_time =
  2825. qeth_get_micros();
  2826. }
  2827. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2828. queue->next_buf_to_init, count);
  2829. if (card->options.performance_stats)
  2830. card->perf_stats.inbound_do_qdio_time +=
  2831. qeth_get_micros() -
  2832. card->perf_stats.inbound_do_qdio_start_time;
  2833. if (rc) {
  2834. QETH_CARD_TEXT(card, 2, "qinberr");
  2835. }
  2836. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2837. QDIO_MAX_BUFFERS_PER_Q;
  2838. }
  2839. }
  2840. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2841. static int qeth_handle_send_error(struct qeth_card *card,
  2842. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2843. {
  2844. int sbalf15 = buffer->buffer->element[15].sflags;
  2845. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2846. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2847. if (sbalf15 == 0) {
  2848. qdio_err = 0;
  2849. } else {
  2850. qdio_err = 1;
  2851. }
  2852. }
  2853. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2854. if (!qdio_err)
  2855. return QETH_SEND_ERROR_NONE;
  2856. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2857. return QETH_SEND_ERROR_RETRY;
  2858. QETH_CARD_TEXT(card, 1, "lnkfail");
  2859. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2860. (u16)qdio_err, (u8)sbalf15);
  2861. return QETH_SEND_ERROR_LINK_FAILURE;
  2862. }
  2863. /*
  2864. * Switched to packing state if the number of used buffers on a queue
  2865. * reaches a certain limit.
  2866. */
  2867. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2868. {
  2869. if (!queue->do_pack) {
  2870. if (atomic_read(&queue->used_buffers)
  2871. >= QETH_HIGH_WATERMARK_PACK){
  2872. /* switch non-PACKING -> PACKING */
  2873. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2874. if (queue->card->options.performance_stats)
  2875. queue->card->perf_stats.sc_dp_p++;
  2876. queue->do_pack = 1;
  2877. }
  2878. }
  2879. }
  2880. /*
  2881. * Switches from packing to non-packing mode. If there is a packing
  2882. * buffer on the queue this buffer will be prepared to be flushed.
  2883. * In that case 1 is returned to inform the caller. If no buffer
  2884. * has to be flushed, zero is returned.
  2885. */
  2886. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2887. {
  2888. struct qeth_qdio_out_buffer *buffer;
  2889. int flush_count = 0;
  2890. if (queue->do_pack) {
  2891. if (atomic_read(&queue->used_buffers)
  2892. <= QETH_LOW_WATERMARK_PACK) {
  2893. /* switch PACKING -> non-PACKING */
  2894. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2895. if (queue->card->options.performance_stats)
  2896. queue->card->perf_stats.sc_p_dp++;
  2897. queue->do_pack = 0;
  2898. /* flush packing buffers */
  2899. buffer = queue->bufs[queue->next_buf_to_fill];
  2900. if ((atomic_read(&buffer->state) ==
  2901. QETH_QDIO_BUF_EMPTY) &&
  2902. (buffer->next_element_to_fill > 0)) {
  2903. atomic_set(&buffer->state,
  2904. QETH_QDIO_BUF_PRIMED);
  2905. flush_count++;
  2906. queue->next_buf_to_fill =
  2907. (queue->next_buf_to_fill + 1) %
  2908. QDIO_MAX_BUFFERS_PER_Q;
  2909. }
  2910. }
  2911. }
  2912. return flush_count;
  2913. }
  2914. /*
  2915. * Called to flush a packing buffer if no more pci flags are on the queue.
  2916. * Checks if there is a packing buffer and prepares it to be flushed.
  2917. * In that case returns 1, otherwise zero.
  2918. */
  2919. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2920. {
  2921. struct qeth_qdio_out_buffer *buffer;
  2922. buffer = queue->bufs[queue->next_buf_to_fill];
  2923. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2924. (buffer->next_element_to_fill > 0)) {
  2925. /* it's a packing buffer */
  2926. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2927. queue->next_buf_to_fill =
  2928. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2929. return 1;
  2930. }
  2931. return 0;
  2932. }
  2933. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2934. int count)
  2935. {
  2936. struct qeth_qdio_out_buffer *buf;
  2937. int rc;
  2938. int i;
  2939. unsigned int qdio_flags;
  2940. for (i = index; i < index + count; ++i) {
  2941. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  2942. buf = queue->bufs[bidx];
  2943. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  2944. SBAL_EFLAGS_LAST_ENTRY;
  2945. if (queue->bufstates)
  2946. queue->bufstates[bidx].user = buf;
  2947. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2948. continue;
  2949. if (!queue->do_pack) {
  2950. if ((atomic_read(&queue->used_buffers) >=
  2951. (QETH_HIGH_WATERMARK_PACK -
  2952. QETH_WATERMARK_PACK_FUZZ)) &&
  2953. !atomic_read(&queue->set_pci_flags_count)) {
  2954. /* it's likely that we'll go to packing
  2955. * mode soon */
  2956. atomic_inc(&queue->set_pci_flags_count);
  2957. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2958. }
  2959. } else {
  2960. if (!atomic_read(&queue->set_pci_flags_count)) {
  2961. /*
  2962. * there's no outstanding PCI any more, so we
  2963. * have to request a PCI to be sure the the PCI
  2964. * will wake at some time in the future then we
  2965. * can flush packed buffers that might still be
  2966. * hanging around, which can happen if no
  2967. * further send was requested by the stack
  2968. */
  2969. atomic_inc(&queue->set_pci_flags_count);
  2970. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2971. }
  2972. }
  2973. }
  2974. queue->card->dev->trans_start = jiffies;
  2975. if (queue->card->options.performance_stats) {
  2976. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2977. queue->card->perf_stats.outbound_do_qdio_start_time =
  2978. qeth_get_micros();
  2979. }
  2980. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2981. if (atomic_read(&queue->set_pci_flags_count))
  2982. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2983. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2984. queue->queue_no, index, count);
  2985. if (queue->card->options.performance_stats)
  2986. queue->card->perf_stats.outbound_do_qdio_time +=
  2987. qeth_get_micros() -
  2988. queue->card->perf_stats.outbound_do_qdio_start_time;
  2989. atomic_add(count, &queue->used_buffers);
  2990. if (rc) {
  2991. queue->card->stats.tx_errors += count;
  2992. /* ignore temporary SIGA errors without busy condition */
  2993. if (rc == -ENOBUFS)
  2994. return;
  2995. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2996. QETH_CARD_TEXT_(queue->card, 2, " q%d", queue->queue_no);
  2997. QETH_CARD_TEXT_(queue->card, 2, " idx%d", index);
  2998. QETH_CARD_TEXT_(queue->card, 2, " c%d", count);
  2999. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  3000. /* this must not happen under normal circumstances. if it
  3001. * happens something is really wrong -> recover */
  3002. qeth_schedule_recovery(queue->card);
  3003. return;
  3004. }
  3005. if (queue->card->options.performance_stats)
  3006. queue->card->perf_stats.bufs_sent += count;
  3007. }
  3008. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  3009. {
  3010. int index;
  3011. int flush_cnt = 0;
  3012. int q_was_packing = 0;
  3013. /*
  3014. * check if weed have to switch to non-packing mode or if
  3015. * we have to get a pci flag out on the queue
  3016. */
  3017. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  3018. !atomic_read(&queue->set_pci_flags_count)) {
  3019. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  3020. QETH_OUT_Q_UNLOCKED) {
  3021. /*
  3022. * If we get in here, there was no action in
  3023. * do_send_packet. So, we check if there is a
  3024. * packing buffer to be flushed here.
  3025. */
  3026. netif_stop_queue(queue->card->dev);
  3027. index = queue->next_buf_to_fill;
  3028. q_was_packing = queue->do_pack;
  3029. /* queue->do_pack may change */
  3030. barrier();
  3031. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  3032. if (!flush_cnt &&
  3033. !atomic_read(&queue->set_pci_flags_count))
  3034. flush_cnt +=
  3035. qeth_flush_buffers_on_no_pci(queue);
  3036. if (queue->card->options.performance_stats &&
  3037. q_was_packing)
  3038. queue->card->perf_stats.bufs_sent_pack +=
  3039. flush_cnt;
  3040. if (flush_cnt)
  3041. qeth_flush_buffers(queue, index, flush_cnt);
  3042. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3043. }
  3044. }
  3045. }
  3046. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  3047. unsigned long card_ptr)
  3048. {
  3049. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3050. if (card->dev && (card->dev->flags & IFF_UP))
  3051. napi_schedule(&card->napi);
  3052. }
  3053. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  3054. int qeth_configure_cq(struct qeth_card *card, enum qeth_cq cq)
  3055. {
  3056. int rc;
  3057. if (card->options.cq == QETH_CQ_NOTAVAILABLE) {
  3058. rc = -1;
  3059. goto out;
  3060. } else {
  3061. if (card->options.cq == cq) {
  3062. rc = 0;
  3063. goto out;
  3064. }
  3065. if (card->state != CARD_STATE_DOWN &&
  3066. card->state != CARD_STATE_RECOVER) {
  3067. rc = -1;
  3068. goto out;
  3069. }
  3070. qeth_free_qdio_buffers(card);
  3071. card->options.cq = cq;
  3072. rc = 0;
  3073. }
  3074. out:
  3075. return rc;
  3076. }
  3077. EXPORT_SYMBOL_GPL(qeth_configure_cq);
  3078. static void qeth_qdio_cq_handler(struct qeth_card *card,
  3079. unsigned int qdio_err,
  3080. unsigned int queue, int first_element, int count) {
  3081. struct qeth_qdio_q *cq = card->qdio.c_q;
  3082. int i;
  3083. int rc;
  3084. if (!qeth_is_cq(card, queue))
  3085. goto out;
  3086. QETH_CARD_TEXT_(card, 5, "qcqhe%d", first_element);
  3087. QETH_CARD_TEXT_(card, 5, "qcqhc%d", count);
  3088. QETH_CARD_TEXT_(card, 5, "qcqherr%d", qdio_err);
  3089. if (qdio_err) {
  3090. netif_stop_queue(card->dev);
  3091. qeth_schedule_recovery(card);
  3092. goto out;
  3093. }
  3094. if (card->options.performance_stats) {
  3095. card->perf_stats.cq_cnt++;
  3096. card->perf_stats.cq_start_time = qeth_get_micros();
  3097. }
  3098. for (i = first_element; i < first_element + count; ++i) {
  3099. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3100. struct qdio_buffer *buffer = &cq->qdio_bufs[bidx];
  3101. int e;
  3102. e = 0;
  3103. while (buffer->element[e].addr) {
  3104. unsigned long phys_aob_addr;
  3105. phys_aob_addr = (unsigned long) buffer->element[e].addr;
  3106. qeth_qdio_handle_aob(card, phys_aob_addr);
  3107. buffer->element[e].addr = NULL;
  3108. buffer->element[e].eflags = 0;
  3109. buffer->element[e].sflags = 0;
  3110. buffer->element[e].length = 0;
  3111. ++e;
  3112. }
  3113. buffer->element[15].eflags = 0;
  3114. buffer->element[15].sflags = 0;
  3115. }
  3116. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue,
  3117. card->qdio.c_q->next_buf_to_init,
  3118. count);
  3119. if (rc) {
  3120. dev_warn(&card->gdev->dev,
  3121. "QDIO reported an error, rc=%i\n", rc);
  3122. QETH_CARD_TEXT(card, 2, "qcqherr");
  3123. }
  3124. card->qdio.c_q->next_buf_to_init = (card->qdio.c_q->next_buf_to_init
  3125. + count) % QDIO_MAX_BUFFERS_PER_Q;
  3126. netif_wake_queue(card->dev);
  3127. if (card->options.performance_stats) {
  3128. int delta_t = qeth_get_micros();
  3129. delta_t -= card->perf_stats.cq_start_time;
  3130. card->perf_stats.cq_time += delta_t;
  3131. }
  3132. out:
  3133. return;
  3134. }
  3135. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  3136. unsigned int queue, int first_elem, int count,
  3137. unsigned long card_ptr)
  3138. {
  3139. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3140. QETH_CARD_TEXT_(card, 2, "qihq%d", queue);
  3141. QETH_CARD_TEXT_(card, 2, "qiec%d", qdio_err);
  3142. if (qeth_is_cq(card, queue))
  3143. qeth_qdio_cq_handler(card, qdio_err, queue, first_elem, count);
  3144. else if (qdio_err)
  3145. qeth_schedule_recovery(card);
  3146. }
  3147. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  3148. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  3149. unsigned int qdio_error, int __queue, int first_element,
  3150. int count, unsigned long card_ptr)
  3151. {
  3152. struct qeth_card *card = (struct qeth_card *) card_ptr;
  3153. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  3154. struct qeth_qdio_out_buffer *buffer;
  3155. int i;
  3156. QETH_CARD_TEXT(card, 6, "qdouhdl");
  3157. if (qdio_error & QDIO_ERROR_FATAL) {
  3158. QETH_CARD_TEXT(card, 2, "achkcond");
  3159. netif_stop_queue(card->dev);
  3160. qeth_schedule_recovery(card);
  3161. return;
  3162. }
  3163. if (card->options.performance_stats) {
  3164. card->perf_stats.outbound_handler_cnt++;
  3165. card->perf_stats.outbound_handler_start_time =
  3166. qeth_get_micros();
  3167. }
  3168. for (i = first_element; i < (first_element + count); ++i) {
  3169. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3170. buffer = queue->bufs[bidx];
  3171. qeth_handle_send_error(card, buffer, qdio_error);
  3172. if (queue->bufstates &&
  3173. (queue->bufstates[bidx].flags &
  3174. QDIO_OUTBUF_STATE_FLAG_PENDING) != 0) {
  3175. WARN_ON_ONCE(card->options.cq != QETH_CQ_ENABLED);
  3176. if (atomic_cmpxchg(&buffer->state,
  3177. QETH_QDIO_BUF_PRIMED,
  3178. QETH_QDIO_BUF_PENDING) ==
  3179. QETH_QDIO_BUF_PRIMED) {
  3180. qeth_notify_skbs(queue, buffer,
  3181. TX_NOTIFY_PENDING);
  3182. }
  3183. buffer->aob = queue->bufstates[bidx].aob;
  3184. QETH_CARD_TEXT_(queue->card, 5, "pel%d", bidx);
  3185. QETH_CARD_TEXT(queue->card, 5, "aob");
  3186. QETH_CARD_TEXT_(queue->card, 5, "%lx",
  3187. virt_to_phys(buffer->aob));
  3188. if (qeth_init_qdio_out_buf(queue, bidx)) {
  3189. QETH_CARD_TEXT(card, 2, "outofbuf");
  3190. qeth_schedule_recovery(card);
  3191. }
  3192. } else {
  3193. if (card->options.cq == QETH_CQ_ENABLED) {
  3194. enum iucv_tx_notify n;
  3195. n = qeth_compute_cq_notification(
  3196. buffer->buffer->element[15].sflags, 0);
  3197. qeth_notify_skbs(queue, buffer, n);
  3198. }
  3199. qeth_clear_output_buffer(queue, buffer,
  3200. QETH_QDIO_BUF_EMPTY);
  3201. }
  3202. qeth_cleanup_handled_pending(queue, bidx, 0);
  3203. }
  3204. atomic_sub(count, &queue->used_buffers);
  3205. /* check if we need to do something on this outbound queue */
  3206. if (card->info.type != QETH_CARD_TYPE_IQD)
  3207. qeth_check_outbound_queue(queue);
  3208. netif_wake_queue(queue->card->dev);
  3209. if (card->options.performance_stats)
  3210. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  3211. card->perf_stats.outbound_handler_start_time;
  3212. }
  3213. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  3214. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  3215. int ipv, int cast_type)
  3216. {
  3217. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  3218. card->info.type == QETH_CARD_TYPE_OSX))
  3219. return card->qdio.default_out_queue;
  3220. switch (card->qdio.no_out_queues) {
  3221. case 4:
  3222. if (cast_type && card->info.is_multicast_different)
  3223. return card->info.is_multicast_different &
  3224. (card->qdio.no_out_queues - 1);
  3225. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  3226. const u8 tos = ip_hdr(skb)->tos;
  3227. if (card->qdio.do_prio_queueing ==
  3228. QETH_PRIO_Q_ING_TOS) {
  3229. if (tos & IP_TOS_NOTIMPORTANT)
  3230. return 3;
  3231. if (tos & IP_TOS_HIGHRELIABILITY)
  3232. return 2;
  3233. if (tos & IP_TOS_HIGHTHROUGHPUT)
  3234. return 1;
  3235. if (tos & IP_TOS_LOWDELAY)
  3236. return 0;
  3237. }
  3238. if (card->qdio.do_prio_queueing ==
  3239. QETH_PRIO_Q_ING_PREC)
  3240. return 3 - (tos >> 6);
  3241. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  3242. /* TODO: IPv6!!! */
  3243. }
  3244. return card->qdio.default_out_queue;
  3245. case 1: /* fallthrough for single-out-queue 1920-device */
  3246. default:
  3247. return card->qdio.default_out_queue;
  3248. }
  3249. }
  3250. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  3251. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  3252. struct sk_buff *skb, int elems)
  3253. {
  3254. int dlen = skb->len - skb->data_len;
  3255. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  3256. PFN_DOWN((unsigned long)skb->data);
  3257. elements_needed += skb_shinfo(skb)->nr_frags;
  3258. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  3259. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  3260. "(Number=%d / Length=%d). Discarded.\n",
  3261. (elements_needed+elems), skb->len);
  3262. return 0;
  3263. }
  3264. return elements_needed;
  3265. }
  3266. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  3267. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  3268. {
  3269. int hroom, inpage, rest;
  3270. if (((unsigned long)skb->data & PAGE_MASK) !=
  3271. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  3272. hroom = skb_headroom(skb);
  3273. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  3274. rest = len - inpage;
  3275. if (rest > hroom)
  3276. return 1;
  3277. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  3278. skb->data -= rest;
  3279. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  3280. }
  3281. return 0;
  3282. }
  3283. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  3284. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  3285. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  3286. int offset)
  3287. {
  3288. int length = skb->len - skb->data_len;
  3289. int length_here;
  3290. int element;
  3291. char *data;
  3292. int first_lap, cnt;
  3293. struct skb_frag_struct *frag;
  3294. element = *next_element_to_fill;
  3295. data = skb->data;
  3296. first_lap = (is_tso == 0 ? 1 : 0);
  3297. if (offset >= 0) {
  3298. data = skb->data + offset;
  3299. length -= offset;
  3300. first_lap = 0;
  3301. }
  3302. while (length > 0) {
  3303. /* length_here is the remaining amount of data in this page */
  3304. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  3305. if (length < length_here)
  3306. length_here = length;
  3307. buffer->element[element].addr = data;
  3308. buffer->element[element].length = length_here;
  3309. length -= length_here;
  3310. if (!length) {
  3311. if (first_lap)
  3312. if (skb_shinfo(skb)->nr_frags)
  3313. buffer->element[element].eflags =
  3314. SBAL_EFLAGS_FIRST_FRAG;
  3315. else
  3316. buffer->element[element].eflags = 0;
  3317. else
  3318. buffer->element[element].eflags =
  3319. SBAL_EFLAGS_MIDDLE_FRAG;
  3320. } else {
  3321. if (first_lap)
  3322. buffer->element[element].eflags =
  3323. SBAL_EFLAGS_FIRST_FRAG;
  3324. else
  3325. buffer->element[element].eflags =
  3326. SBAL_EFLAGS_MIDDLE_FRAG;
  3327. }
  3328. data += length_here;
  3329. element++;
  3330. first_lap = 0;
  3331. }
  3332. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3333. frag = &skb_shinfo(skb)->frags[cnt];
  3334. buffer->element[element].addr = (char *)
  3335. page_to_phys(skb_frag_page(frag))
  3336. + frag->page_offset;
  3337. buffer->element[element].length = frag->size;
  3338. buffer->element[element].eflags = SBAL_EFLAGS_MIDDLE_FRAG;
  3339. element++;
  3340. }
  3341. if (buffer->element[element - 1].eflags)
  3342. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  3343. *next_element_to_fill = element;
  3344. }
  3345. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  3346. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  3347. struct qeth_hdr *hdr, int offset, int hd_len)
  3348. {
  3349. struct qdio_buffer *buffer;
  3350. int flush_cnt = 0, hdr_len, large_send = 0;
  3351. buffer = buf->buffer;
  3352. atomic_inc(&skb->users);
  3353. skb_queue_tail(&buf->skb_list, skb);
  3354. /*check first on TSO ....*/
  3355. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  3356. int element = buf->next_element_to_fill;
  3357. hdr_len = sizeof(struct qeth_hdr_tso) +
  3358. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  3359. /*fill first buffer entry only with header information */
  3360. buffer->element[element].addr = skb->data;
  3361. buffer->element[element].length = hdr_len;
  3362. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3363. buf->next_element_to_fill++;
  3364. skb->data += hdr_len;
  3365. skb->len -= hdr_len;
  3366. large_send = 1;
  3367. }
  3368. if (offset >= 0) {
  3369. int element = buf->next_element_to_fill;
  3370. buffer->element[element].addr = hdr;
  3371. buffer->element[element].length = sizeof(struct qeth_hdr) +
  3372. hd_len;
  3373. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3374. buf->is_header[element] = 1;
  3375. buf->next_element_to_fill++;
  3376. }
  3377. __qeth_fill_buffer(skb, buffer, large_send,
  3378. (int *)&buf->next_element_to_fill, offset);
  3379. if (!queue->do_pack) {
  3380. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  3381. /* set state to PRIMED -> will be flushed */
  3382. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3383. flush_cnt = 1;
  3384. } else {
  3385. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  3386. if (queue->card->options.performance_stats)
  3387. queue->card->perf_stats.skbs_sent_pack++;
  3388. if (buf->next_element_to_fill >=
  3389. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  3390. /*
  3391. * packed buffer if full -> set state PRIMED
  3392. * -> will be flushed
  3393. */
  3394. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3395. flush_cnt = 1;
  3396. }
  3397. }
  3398. return flush_cnt;
  3399. }
  3400. int qeth_do_send_packet_fast(struct qeth_card *card,
  3401. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  3402. struct qeth_hdr *hdr, int elements_needed,
  3403. int offset, int hd_len)
  3404. {
  3405. struct qeth_qdio_out_buffer *buffer;
  3406. int index;
  3407. /* spin until we get the queue ... */
  3408. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3409. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3410. /* ... now we've got the queue */
  3411. index = queue->next_buf_to_fill;
  3412. buffer = queue->bufs[queue->next_buf_to_fill];
  3413. /*
  3414. * check if buffer is empty to make sure that we do not 'overtake'
  3415. * ourselves and try to fill a buffer that is already primed
  3416. */
  3417. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  3418. goto out;
  3419. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  3420. QDIO_MAX_BUFFERS_PER_Q;
  3421. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3422. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  3423. qeth_flush_buffers(queue, index, 1);
  3424. return 0;
  3425. out:
  3426. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3427. return -EBUSY;
  3428. }
  3429. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  3430. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  3431. struct sk_buff *skb, struct qeth_hdr *hdr,
  3432. int elements_needed)
  3433. {
  3434. struct qeth_qdio_out_buffer *buffer;
  3435. int start_index;
  3436. int flush_count = 0;
  3437. int do_pack = 0;
  3438. int tmp;
  3439. int rc = 0;
  3440. /* spin until we get the queue ... */
  3441. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3442. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3443. start_index = queue->next_buf_to_fill;
  3444. buffer = queue->bufs[queue->next_buf_to_fill];
  3445. /*
  3446. * check if buffer is empty to make sure that we do not 'overtake'
  3447. * ourselves and try to fill a buffer that is already primed
  3448. */
  3449. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  3450. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3451. return -EBUSY;
  3452. }
  3453. /* check if we need to switch packing state of this queue */
  3454. qeth_switch_to_packing_if_needed(queue);
  3455. if (queue->do_pack) {
  3456. do_pack = 1;
  3457. /* does packet fit in current buffer? */
  3458. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3459. buffer->next_element_to_fill) < elements_needed) {
  3460. /* ... no -> set state PRIMED */
  3461. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3462. flush_count++;
  3463. queue->next_buf_to_fill =
  3464. (queue->next_buf_to_fill + 1) %
  3465. QDIO_MAX_BUFFERS_PER_Q;
  3466. buffer = queue->bufs[queue->next_buf_to_fill];
  3467. /* we did a step forward, so check buffer state
  3468. * again */
  3469. if (atomic_read(&buffer->state) !=
  3470. QETH_QDIO_BUF_EMPTY) {
  3471. qeth_flush_buffers(queue, start_index,
  3472. flush_count);
  3473. atomic_set(&queue->state,
  3474. QETH_OUT_Q_UNLOCKED);
  3475. return -EBUSY;
  3476. }
  3477. }
  3478. }
  3479. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3480. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3481. QDIO_MAX_BUFFERS_PER_Q;
  3482. flush_count += tmp;
  3483. if (flush_count)
  3484. qeth_flush_buffers(queue, start_index, flush_count);
  3485. else if (!atomic_read(&queue->set_pci_flags_count))
  3486. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3487. /*
  3488. * queue->state will go from LOCKED -> UNLOCKED or from
  3489. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3490. * (switch packing state or flush buffer to get another pci flag out).
  3491. * In that case we will enter this loop
  3492. */
  3493. while (atomic_dec_return(&queue->state)) {
  3494. flush_count = 0;
  3495. start_index = queue->next_buf_to_fill;
  3496. /* check if we can go back to non-packing state */
  3497. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3498. /*
  3499. * check if we need to flush a packing buffer to get a pci
  3500. * flag out on the queue
  3501. */
  3502. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3503. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3504. if (flush_count)
  3505. qeth_flush_buffers(queue, start_index, flush_count);
  3506. }
  3507. /* at this point the queue is UNLOCKED again */
  3508. if (queue->card->options.performance_stats && do_pack)
  3509. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3510. return rc;
  3511. }
  3512. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3513. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3514. struct qeth_reply *reply, unsigned long data)
  3515. {
  3516. struct qeth_ipa_cmd *cmd;
  3517. struct qeth_ipacmd_setadpparms *setparms;
  3518. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3519. cmd = (struct qeth_ipa_cmd *) data;
  3520. setparms = &(cmd->data.setadapterparms);
  3521. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3522. if (cmd->hdr.return_code) {
  3523. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3524. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3525. }
  3526. card->info.promisc_mode = setparms->data.mode;
  3527. return 0;
  3528. }
  3529. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3530. {
  3531. enum qeth_ipa_promisc_modes mode;
  3532. struct net_device *dev = card->dev;
  3533. struct qeth_cmd_buffer *iob;
  3534. struct qeth_ipa_cmd *cmd;
  3535. QETH_CARD_TEXT(card, 4, "setprom");
  3536. if (((dev->flags & IFF_PROMISC) &&
  3537. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3538. (!(dev->flags & IFF_PROMISC) &&
  3539. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3540. return;
  3541. mode = SET_PROMISC_MODE_OFF;
  3542. if (dev->flags & IFF_PROMISC)
  3543. mode = SET_PROMISC_MODE_ON;
  3544. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3545. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3546. sizeof(struct qeth_ipacmd_setadpparms));
  3547. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3548. cmd->data.setadapterparms.data.mode = mode;
  3549. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3550. }
  3551. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3552. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3553. {
  3554. struct qeth_card *card;
  3555. char dbf_text[15];
  3556. card = dev->ml_priv;
  3557. QETH_CARD_TEXT(card, 4, "chgmtu");
  3558. sprintf(dbf_text, "%8x", new_mtu);
  3559. QETH_CARD_TEXT(card, 4, dbf_text);
  3560. if (new_mtu < 64)
  3561. return -EINVAL;
  3562. if (new_mtu > 65535)
  3563. return -EINVAL;
  3564. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3565. (!qeth_mtu_is_valid(card, new_mtu)))
  3566. return -EINVAL;
  3567. dev->mtu = new_mtu;
  3568. return 0;
  3569. }
  3570. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3571. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3572. {
  3573. struct qeth_card *card;
  3574. card = dev->ml_priv;
  3575. QETH_CARD_TEXT(card, 5, "getstat");
  3576. return &card->stats;
  3577. }
  3578. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3579. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3580. struct qeth_reply *reply, unsigned long data)
  3581. {
  3582. struct qeth_ipa_cmd *cmd;
  3583. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3584. cmd = (struct qeth_ipa_cmd *) data;
  3585. if (!card->options.layer2 ||
  3586. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3587. memcpy(card->dev->dev_addr,
  3588. &cmd->data.setadapterparms.data.change_addr.addr,
  3589. OSA_ADDR_LEN);
  3590. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3591. }
  3592. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3593. return 0;
  3594. }
  3595. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3596. {
  3597. int rc;
  3598. struct qeth_cmd_buffer *iob;
  3599. struct qeth_ipa_cmd *cmd;
  3600. QETH_CARD_TEXT(card, 4, "chgmac");
  3601. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3602. sizeof(struct qeth_ipacmd_setadpparms));
  3603. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3604. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3605. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3606. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3607. card->dev->dev_addr, OSA_ADDR_LEN);
  3608. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3609. NULL);
  3610. return rc;
  3611. }
  3612. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3613. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3614. struct qeth_reply *reply, unsigned long data)
  3615. {
  3616. struct qeth_ipa_cmd *cmd;
  3617. struct qeth_set_access_ctrl *access_ctrl_req;
  3618. QETH_CARD_TEXT(card, 4, "setaccb");
  3619. cmd = (struct qeth_ipa_cmd *) data;
  3620. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3621. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3622. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3623. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3624. cmd->data.setadapterparms.hdr.return_code);
  3625. switch (cmd->data.setadapterparms.hdr.return_code) {
  3626. case SET_ACCESS_CTRL_RC_SUCCESS:
  3627. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3628. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3629. {
  3630. card->options.isolation = access_ctrl_req->subcmd_code;
  3631. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3632. dev_info(&card->gdev->dev,
  3633. "QDIO data connection isolation is deactivated\n");
  3634. } else {
  3635. dev_info(&card->gdev->dev,
  3636. "QDIO data connection isolation is activated\n");
  3637. }
  3638. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3639. card->gdev->dev.kobj.name,
  3640. access_ctrl_req->subcmd_code,
  3641. cmd->data.setadapterparms.hdr.return_code);
  3642. break;
  3643. }
  3644. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3645. {
  3646. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3647. card->gdev->dev.kobj.name,
  3648. access_ctrl_req->subcmd_code,
  3649. cmd->data.setadapterparms.hdr.return_code);
  3650. dev_err(&card->gdev->dev, "Adapter does not "
  3651. "support QDIO data connection isolation\n");
  3652. /* ensure isolation mode is "none" */
  3653. card->options.isolation = ISOLATION_MODE_NONE;
  3654. break;
  3655. }
  3656. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3657. {
  3658. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3659. card->gdev->dev.kobj.name,
  3660. access_ctrl_req->subcmd_code,
  3661. cmd->data.setadapterparms.hdr.return_code);
  3662. dev_err(&card->gdev->dev,
  3663. "Adapter is dedicated. "
  3664. "QDIO data connection isolation not supported\n");
  3665. /* ensure isolation mode is "none" */
  3666. card->options.isolation = ISOLATION_MODE_NONE;
  3667. break;
  3668. }
  3669. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3670. {
  3671. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3672. card->gdev->dev.kobj.name,
  3673. access_ctrl_req->subcmd_code,
  3674. cmd->data.setadapterparms.hdr.return_code);
  3675. dev_err(&card->gdev->dev,
  3676. "TSO does not permit QDIO data connection isolation\n");
  3677. /* ensure isolation mode is "none" */
  3678. card->options.isolation = ISOLATION_MODE_NONE;
  3679. break;
  3680. }
  3681. default:
  3682. {
  3683. /* this should never happen */
  3684. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3685. "==UNKNOWN\n",
  3686. card->gdev->dev.kobj.name,
  3687. access_ctrl_req->subcmd_code,
  3688. cmd->data.setadapterparms.hdr.return_code);
  3689. /* ensure isolation mode is "none" */
  3690. card->options.isolation = ISOLATION_MODE_NONE;
  3691. break;
  3692. }
  3693. }
  3694. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3695. return 0;
  3696. }
  3697. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3698. enum qeth_ipa_isolation_modes isolation)
  3699. {
  3700. int rc;
  3701. struct qeth_cmd_buffer *iob;
  3702. struct qeth_ipa_cmd *cmd;
  3703. struct qeth_set_access_ctrl *access_ctrl_req;
  3704. QETH_CARD_TEXT(card, 4, "setacctl");
  3705. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3706. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3707. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3708. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3709. sizeof(struct qeth_set_access_ctrl));
  3710. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3711. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3712. access_ctrl_req->subcmd_code = isolation;
  3713. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3714. NULL);
  3715. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3716. return rc;
  3717. }
  3718. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3719. {
  3720. int rc = 0;
  3721. QETH_CARD_TEXT(card, 4, "setactlo");
  3722. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3723. card->info.type == QETH_CARD_TYPE_OSX) &&
  3724. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3725. rc = qeth_setadpparms_set_access_ctrl(card,
  3726. card->options.isolation);
  3727. if (rc) {
  3728. QETH_DBF_MESSAGE(3,
  3729. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3730. card->gdev->dev.kobj.name,
  3731. rc);
  3732. }
  3733. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3734. card->options.isolation = ISOLATION_MODE_NONE;
  3735. dev_err(&card->gdev->dev, "Adapter does not "
  3736. "support QDIO data connection isolation\n");
  3737. rc = -EOPNOTSUPP;
  3738. }
  3739. return rc;
  3740. }
  3741. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3742. void qeth_tx_timeout(struct net_device *dev)
  3743. {
  3744. struct qeth_card *card;
  3745. card = dev->ml_priv;
  3746. QETH_CARD_TEXT(card, 4, "txtimeo");
  3747. card->stats.tx_errors++;
  3748. qeth_schedule_recovery(card);
  3749. }
  3750. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3751. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3752. {
  3753. struct qeth_card *card = dev->ml_priv;
  3754. int rc = 0;
  3755. switch (regnum) {
  3756. case MII_BMCR: /* Basic mode control register */
  3757. rc = BMCR_FULLDPLX;
  3758. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3759. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3760. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3761. rc |= BMCR_SPEED100;
  3762. break;
  3763. case MII_BMSR: /* Basic mode status register */
  3764. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3765. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3766. BMSR_100BASE4;
  3767. break;
  3768. case MII_PHYSID1: /* PHYS ID 1 */
  3769. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3770. dev->dev_addr[2];
  3771. rc = (rc >> 5) & 0xFFFF;
  3772. break;
  3773. case MII_PHYSID2: /* PHYS ID 2 */
  3774. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3775. break;
  3776. case MII_ADVERTISE: /* Advertisement control reg */
  3777. rc = ADVERTISE_ALL;
  3778. break;
  3779. case MII_LPA: /* Link partner ability reg */
  3780. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3781. LPA_100BASE4 | LPA_LPACK;
  3782. break;
  3783. case MII_EXPANSION: /* Expansion register */
  3784. break;
  3785. case MII_DCOUNTER: /* disconnect counter */
  3786. break;
  3787. case MII_FCSCOUNTER: /* false carrier counter */
  3788. break;
  3789. case MII_NWAYTEST: /* N-way auto-neg test register */
  3790. break;
  3791. case MII_RERRCOUNTER: /* rx error counter */
  3792. rc = card->stats.rx_errors;
  3793. break;
  3794. case MII_SREVISION: /* silicon revision */
  3795. break;
  3796. case MII_RESV1: /* reserved 1 */
  3797. break;
  3798. case MII_LBRERROR: /* loopback, rx, bypass error */
  3799. break;
  3800. case MII_PHYADDR: /* physical address */
  3801. break;
  3802. case MII_RESV2: /* reserved 2 */
  3803. break;
  3804. case MII_TPISTATUS: /* TPI status for 10mbps */
  3805. break;
  3806. case MII_NCONFIG: /* network interface config */
  3807. break;
  3808. default:
  3809. break;
  3810. }
  3811. return rc;
  3812. }
  3813. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3814. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3815. struct qeth_cmd_buffer *iob, int len,
  3816. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3817. unsigned long),
  3818. void *reply_param)
  3819. {
  3820. u16 s1, s2;
  3821. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3822. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3823. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3824. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3825. /* adjust PDU length fields in IPA_PDU_HEADER */
  3826. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3827. s2 = (u32) len;
  3828. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3829. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3830. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3831. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3832. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3833. reply_cb, reply_param);
  3834. }
  3835. static int qeth_snmp_command_cb(struct qeth_card *card,
  3836. struct qeth_reply *reply, unsigned long sdata)
  3837. {
  3838. struct qeth_ipa_cmd *cmd;
  3839. struct qeth_arp_query_info *qinfo;
  3840. struct qeth_snmp_cmd *snmp;
  3841. unsigned char *data;
  3842. __u16 data_len;
  3843. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3844. cmd = (struct qeth_ipa_cmd *) sdata;
  3845. data = (unsigned char *)((char *)cmd - reply->offset);
  3846. qinfo = (struct qeth_arp_query_info *) reply->param;
  3847. snmp = &cmd->data.setadapterparms.data.snmp;
  3848. if (cmd->hdr.return_code) {
  3849. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3850. return 0;
  3851. }
  3852. if (cmd->data.setadapterparms.hdr.return_code) {
  3853. cmd->hdr.return_code =
  3854. cmd->data.setadapterparms.hdr.return_code;
  3855. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3856. return 0;
  3857. }
  3858. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3859. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3860. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3861. else
  3862. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3863. /* check if there is enough room in userspace */
  3864. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3865. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3866. cmd->hdr.return_code = IPA_RC_ENOMEM;
  3867. return 0;
  3868. }
  3869. QETH_CARD_TEXT_(card, 4, "snore%i",
  3870. cmd->data.setadapterparms.hdr.used_total);
  3871. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3872. cmd->data.setadapterparms.hdr.seq_no);
  3873. /*copy entries to user buffer*/
  3874. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3875. memcpy(qinfo->udata + qinfo->udata_offset,
  3876. (char *)snmp,
  3877. data_len + offsetof(struct qeth_snmp_cmd, data));
  3878. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3879. } else {
  3880. memcpy(qinfo->udata + qinfo->udata_offset,
  3881. (char *)&snmp->request, data_len);
  3882. }
  3883. qinfo->udata_offset += data_len;
  3884. /* check if all replies received ... */
  3885. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3886. cmd->data.setadapterparms.hdr.used_total);
  3887. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3888. cmd->data.setadapterparms.hdr.seq_no);
  3889. if (cmd->data.setadapterparms.hdr.seq_no <
  3890. cmd->data.setadapterparms.hdr.used_total)
  3891. return 1;
  3892. return 0;
  3893. }
  3894. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3895. {
  3896. struct qeth_cmd_buffer *iob;
  3897. struct qeth_ipa_cmd *cmd;
  3898. struct qeth_snmp_ureq *ureq;
  3899. int req_len;
  3900. struct qeth_arp_query_info qinfo = {0, };
  3901. int rc = 0;
  3902. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3903. if (card->info.guestlan)
  3904. return -EOPNOTSUPP;
  3905. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3906. (!card->options.layer2)) {
  3907. return -EOPNOTSUPP;
  3908. }
  3909. /* skip 4 bytes (data_len struct member) to get req_len */
  3910. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3911. return -EFAULT;
  3912. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3913. if (IS_ERR(ureq)) {
  3914. QETH_CARD_TEXT(card, 2, "snmpnome");
  3915. return PTR_ERR(ureq);
  3916. }
  3917. qinfo.udata_len = ureq->hdr.data_len;
  3918. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3919. if (!qinfo.udata) {
  3920. kfree(ureq);
  3921. return -ENOMEM;
  3922. }
  3923. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3924. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3925. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3926. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3927. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3928. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3929. qeth_snmp_command_cb, (void *)&qinfo);
  3930. if (rc)
  3931. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3932. QETH_CARD_IFNAME(card), rc);
  3933. else {
  3934. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3935. rc = -EFAULT;
  3936. }
  3937. kfree(ureq);
  3938. kfree(qinfo.udata);
  3939. return rc;
  3940. }
  3941. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3942. static int qeth_setadpparms_query_oat_cb(struct qeth_card *card,
  3943. struct qeth_reply *reply, unsigned long data)
  3944. {
  3945. struct qeth_ipa_cmd *cmd;
  3946. struct qeth_qoat_priv *priv;
  3947. char *resdata;
  3948. int resdatalen;
  3949. QETH_CARD_TEXT(card, 3, "qoatcb");
  3950. cmd = (struct qeth_ipa_cmd *)data;
  3951. priv = (struct qeth_qoat_priv *)reply->param;
  3952. resdatalen = cmd->data.setadapterparms.hdr.cmdlength;
  3953. resdata = (char *)data + 28;
  3954. if (resdatalen > (priv->buffer_len - priv->response_len)) {
  3955. cmd->hdr.return_code = IPA_RC_FFFF;
  3956. return 0;
  3957. }
  3958. memcpy((priv->buffer + priv->response_len), resdata,
  3959. resdatalen);
  3960. priv->response_len += resdatalen;
  3961. if (cmd->data.setadapterparms.hdr.seq_no <
  3962. cmd->data.setadapterparms.hdr.used_total)
  3963. return 1;
  3964. return 0;
  3965. }
  3966. int qeth_query_oat_command(struct qeth_card *card, char __user *udata)
  3967. {
  3968. int rc = 0;
  3969. struct qeth_cmd_buffer *iob;
  3970. struct qeth_ipa_cmd *cmd;
  3971. struct qeth_query_oat *oat_req;
  3972. struct qeth_query_oat_data oat_data;
  3973. struct qeth_qoat_priv priv;
  3974. void __user *tmp;
  3975. QETH_CARD_TEXT(card, 3, "qoatcmd");
  3976. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_OAT)) {
  3977. rc = -EOPNOTSUPP;
  3978. goto out;
  3979. }
  3980. if (copy_from_user(&oat_data, udata,
  3981. sizeof(struct qeth_query_oat_data))) {
  3982. rc = -EFAULT;
  3983. goto out;
  3984. }
  3985. priv.buffer_len = oat_data.buffer_len;
  3986. priv.response_len = 0;
  3987. priv.buffer = kzalloc(oat_data.buffer_len, GFP_KERNEL);
  3988. if (!priv.buffer) {
  3989. rc = -ENOMEM;
  3990. goto out;
  3991. }
  3992. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_OAT,
  3993. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3994. sizeof(struct qeth_query_oat));
  3995. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3996. oat_req = &cmd->data.setadapterparms.data.query_oat;
  3997. oat_req->subcmd_code = oat_data.command;
  3998. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_query_oat_cb,
  3999. &priv);
  4000. if (!rc) {
  4001. if (is_compat_task())
  4002. tmp = compat_ptr(oat_data.ptr);
  4003. else
  4004. tmp = (void __user *)(unsigned long)oat_data.ptr;
  4005. if (copy_to_user(tmp, priv.buffer,
  4006. priv.response_len)) {
  4007. rc = -EFAULT;
  4008. goto out_free;
  4009. }
  4010. oat_data.response_len = priv.response_len;
  4011. if (copy_to_user(udata, &oat_data,
  4012. sizeof(struct qeth_query_oat_data)))
  4013. rc = -EFAULT;
  4014. } else
  4015. if (rc == IPA_RC_FFFF)
  4016. rc = -EFAULT;
  4017. out_free:
  4018. kfree(priv.buffer);
  4019. out:
  4020. return rc;
  4021. }
  4022. EXPORT_SYMBOL_GPL(qeth_query_oat_command);
  4023. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  4024. {
  4025. switch (card->info.type) {
  4026. case QETH_CARD_TYPE_IQD:
  4027. return 2;
  4028. default:
  4029. return 0;
  4030. }
  4031. }
  4032. static void qeth_determine_capabilities(struct qeth_card *card)
  4033. {
  4034. int rc;
  4035. int length;
  4036. char *prcd;
  4037. struct ccw_device *ddev;
  4038. int ddev_offline = 0;
  4039. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  4040. ddev = CARD_DDEV(card);
  4041. if (!ddev->online) {
  4042. ddev_offline = 1;
  4043. rc = ccw_device_set_online(ddev);
  4044. if (rc) {
  4045. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4046. goto out;
  4047. }
  4048. }
  4049. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  4050. if (rc) {
  4051. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  4052. dev_name(&card->gdev->dev), rc);
  4053. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4054. goto out_offline;
  4055. }
  4056. qeth_configure_unitaddr(card, prcd);
  4057. if (ddev_offline)
  4058. qeth_configure_blkt_default(card, prcd);
  4059. kfree(prcd);
  4060. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  4061. if (rc)
  4062. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  4063. QETH_DBF_TEXT_(SETUP, 2, "qfmt%d", card->ssqd.qfmt);
  4064. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac1);
  4065. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac3);
  4066. QETH_DBF_TEXT_(SETUP, 2, "icnt%d", card->ssqd.icnt);
  4067. if (!((card->ssqd.qfmt != QDIO_IQDIO_QFMT) ||
  4068. ((card->ssqd.qdioac1 & CHSC_AC1_INITIATE_INPUTQ) == 0) ||
  4069. ((card->ssqd.qdioac3 & CHSC_AC3_FORMAT2_CQ_AVAILABLE) == 0))) {
  4070. dev_info(&card->gdev->dev,
  4071. "Completion Queueing supported\n");
  4072. } else {
  4073. card->options.cq = QETH_CQ_NOTAVAILABLE;
  4074. }
  4075. out_offline:
  4076. if (ddev_offline == 1)
  4077. ccw_device_set_offline(ddev);
  4078. out:
  4079. return;
  4080. }
  4081. static inline void qeth_qdio_establish_cq(struct qeth_card *card,
  4082. struct qdio_buffer **in_sbal_ptrs,
  4083. void (**queue_start_poll) (struct ccw_device *, int, unsigned long)) {
  4084. int i;
  4085. if (card->options.cq == QETH_CQ_ENABLED) {
  4086. int offset = QDIO_MAX_BUFFERS_PER_Q *
  4087. (card->qdio.no_in_queues - 1);
  4088. i = QDIO_MAX_BUFFERS_PER_Q * (card->qdio.no_in_queues - 1);
  4089. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4090. in_sbal_ptrs[offset + i] = (struct qdio_buffer *)
  4091. virt_to_phys(card->qdio.c_q->bufs[i].buffer);
  4092. }
  4093. queue_start_poll[card->qdio.no_in_queues - 1] = NULL;
  4094. }
  4095. }
  4096. static int qeth_qdio_establish(struct qeth_card *card)
  4097. {
  4098. struct qdio_initialize init_data;
  4099. char *qib_param_field;
  4100. struct qdio_buffer **in_sbal_ptrs;
  4101. void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
  4102. struct qdio_buffer **out_sbal_ptrs;
  4103. int i, j, k;
  4104. int rc = 0;
  4105. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  4106. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  4107. GFP_KERNEL);
  4108. if (!qib_param_field) {
  4109. rc = -ENOMEM;
  4110. goto out_free_nothing;
  4111. }
  4112. qeth_create_qib_param_field(card, qib_param_field);
  4113. qeth_create_qib_param_field_blkt(card, qib_param_field);
  4114. in_sbal_ptrs = kzalloc(card->qdio.no_in_queues *
  4115. QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  4116. GFP_KERNEL);
  4117. if (!in_sbal_ptrs) {
  4118. rc = -ENOMEM;
  4119. goto out_free_qib_param;
  4120. }
  4121. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4122. in_sbal_ptrs[i] = (struct qdio_buffer *)
  4123. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  4124. }
  4125. queue_start_poll = kzalloc(sizeof(void *) * card->qdio.no_in_queues,
  4126. GFP_KERNEL);
  4127. if (!queue_start_poll) {
  4128. rc = -ENOMEM;
  4129. goto out_free_in_sbals;
  4130. }
  4131. for (i = 0; i < card->qdio.no_in_queues; ++i)
  4132. queue_start_poll[i] = card->discipline->start_poll;
  4133. qeth_qdio_establish_cq(card, in_sbal_ptrs, queue_start_poll);
  4134. out_sbal_ptrs =
  4135. kzalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  4136. sizeof(void *), GFP_KERNEL);
  4137. if (!out_sbal_ptrs) {
  4138. rc = -ENOMEM;
  4139. goto out_free_queue_start_poll;
  4140. }
  4141. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  4142. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  4143. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  4144. card->qdio.out_qs[i]->bufs[j]->buffer);
  4145. }
  4146. memset(&init_data, 0, sizeof(struct qdio_initialize));
  4147. init_data.cdev = CARD_DDEV(card);
  4148. init_data.q_format = qeth_get_qdio_q_format(card);
  4149. init_data.qib_param_field_format = 0;
  4150. init_data.qib_param_field = qib_param_field;
  4151. init_data.no_input_qs = card->qdio.no_in_queues;
  4152. init_data.no_output_qs = card->qdio.no_out_queues;
  4153. init_data.input_handler = card->discipline->input_handler;
  4154. init_data.output_handler = card->discipline->output_handler;
  4155. init_data.queue_start_poll_array = queue_start_poll;
  4156. init_data.int_parm = (unsigned long) card;
  4157. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  4158. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  4159. init_data.output_sbal_state_array = card->qdio.out_bufstates;
  4160. init_data.scan_threshold =
  4161. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  4162. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  4163. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  4164. rc = qdio_allocate(&init_data);
  4165. if (rc) {
  4166. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4167. goto out;
  4168. }
  4169. rc = qdio_establish(&init_data);
  4170. if (rc) {
  4171. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4172. qdio_free(CARD_DDEV(card));
  4173. }
  4174. }
  4175. switch (card->options.cq) {
  4176. case QETH_CQ_ENABLED:
  4177. dev_info(&card->gdev->dev, "Completion Queue support enabled");
  4178. break;
  4179. case QETH_CQ_DISABLED:
  4180. dev_info(&card->gdev->dev, "Completion Queue support disabled");
  4181. break;
  4182. default:
  4183. break;
  4184. }
  4185. out:
  4186. kfree(out_sbal_ptrs);
  4187. out_free_queue_start_poll:
  4188. kfree(queue_start_poll);
  4189. out_free_in_sbals:
  4190. kfree(in_sbal_ptrs);
  4191. out_free_qib_param:
  4192. kfree(qib_param_field);
  4193. out_free_nothing:
  4194. return rc;
  4195. }
  4196. static void qeth_core_free_card(struct qeth_card *card)
  4197. {
  4198. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  4199. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  4200. qeth_clean_channel(&card->read);
  4201. qeth_clean_channel(&card->write);
  4202. if (card->dev)
  4203. free_netdev(card->dev);
  4204. kfree(card->ip_tbd_list);
  4205. qeth_free_qdio_buffers(card);
  4206. unregister_service_level(&card->qeth_service_level);
  4207. kfree(card);
  4208. }
  4209. void qeth_trace_features(struct qeth_card *card)
  4210. {
  4211. QETH_CARD_TEXT(card, 2, "features");
  4212. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.supported_funcs);
  4213. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.enabled_funcs);
  4214. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.supported_funcs);
  4215. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.enabled_funcs);
  4216. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.supported_funcs);
  4217. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.enabled_funcs);
  4218. QETH_CARD_TEXT_(card, 2, "%x", card->info.diagass_support);
  4219. }
  4220. EXPORT_SYMBOL_GPL(qeth_trace_features);
  4221. static struct ccw_device_id qeth_ids[] = {
  4222. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  4223. .driver_info = QETH_CARD_TYPE_OSD},
  4224. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  4225. .driver_info = QETH_CARD_TYPE_IQD},
  4226. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  4227. .driver_info = QETH_CARD_TYPE_OSN},
  4228. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  4229. .driver_info = QETH_CARD_TYPE_OSM},
  4230. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  4231. .driver_info = QETH_CARD_TYPE_OSX},
  4232. {},
  4233. };
  4234. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  4235. static struct ccw_driver qeth_ccw_driver = {
  4236. .driver = {
  4237. .owner = THIS_MODULE,
  4238. .name = "qeth",
  4239. },
  4240. .ids = qeth_ids,
  4241. .probe = ccwgroup_probe_ccwdev,
  4242. .remove = ccwgroup_remove_ccwdev,
  4243. };
  4244. int qeth_core_hardsetup_card(struct qeth_card *card)
  4245. {
  4246. int retries = 3;
  4247. int rc;
  4248. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  4249. atomic_set(&card->force_alloc_skb, 0);
  4250. qeth_update_from_chp_desc(card);
  4251. retry:
  4252. if (retries < 3)
  4253. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  4254. dev_name(&card->gdev->dev));
  4255. ccw_device_set_offline(CARD_DDEV(card));
  4256. ccw_device_set_offline(CARD_WDEV(card));
  4257. ccw_device_set_offline(CARD_RDEV(card));
  4258. rc = ccw_device_set_online(CARD_RDEV(card));
  4259. if (rc)
  4260. goto retriable;
  4261. rc = ccw_device_set_online(CARD_WDEV(card));
  4262. if (rc)
  4263. goto retriable;
  4264. rc = ccw_device_set_online(CARD_DDEV(card));
  4265. if (rc)
  4266. goto retriable;
  4267. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  4268. retriable:
  4269. if (rc == -ERESTARTSYS) {
  4270. QETH_DBF_TEXT(SETUP, 2, "break1");
  4271. return rc;
  4272. } else if (rc) {
  4273. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  4274. if (--retries < 0)
  4275. goto out;
  4276. else
  4277. goto retry;
  4278. }
  4279. qeth_determine_capabilities(card);
  4280. qeth_init_tokens(card);
  4281. qeth_init_func_level(card);
  4282. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  4283. if (rc == -ERESTARTSYS) {
  4284. QETH_DBF_TEXT(SETUP, 2, "break2");
  4285. return rc;
  4286. } else if (rc) {
  4287. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4288. if (--retries < 0)
  4289. goto out;
  4290. else
  4291. goto retry;
  4292. }
  4293. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  4294. if (rc == -ERESTARTSYS) {
  4295. QETH_DBF_TEXT(SETUP, 2, "break3");
  4296. return rc;
  4297. } else if (rc) {
  4298. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  4299. if (--retries < 0)
  4300. goto out;
  4301. else
  4302. goto retry;
  4303. }
  4304. card->read_or_write_problem = 0;
  4305. rc = qeth_mpc_initialize(card);
  4306. if (rc) {
  4307. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4308. goto out;
  4309. }
  4310. card->options.ipa4.supported_funcs = 0;
  4311. card->options.adp.supported_funcs = 0;
  4312. card->info.diagass_support = 0;
  4313. qeth_query_ipassists(card, QETH_PROT_IPV4);
  4314. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  4315. qeth_query_setadapterparms(card);
  4316. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  4317. qeth_query_setdiagass(card);
  4318. return 0;
  4319. out:
  4320. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  4321. "an error on the device\n");
  4322. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  4323. dev_name(&card->gdev->dev), rc);
  4324. return rc;
  4325. }
  4326. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  4327. static inline int qeth_create_skb_frag(struct qeth_qdio_buffer *qethbuffer,
  4328. struct qdio_buffer_element *element,
  4329. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  4330. {
  4331. struct page *page = virt_to_page(element->addr);
  4332. if (*pskb == NULL) {
  4333. if (qethbuffer->rx_skb) {
  4334. /* only if qeth_card.options.cq == QETH_CQ_ENABLED */
  4335. *pskb = qethbuffer->rx_skb;
  4336. qethbuffer->rx_skb = NULL;
  4337. } else {
  4338. *pskb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  4339. if (!(*pskb))
  4340. return -ENOMEM;
  4341. }
  4342. skb_reserve(*pskb, ETH_HLEN);
  4343. if (data_len <= QETH_RX_PULL_LEN) {
  4344. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  4345. data_len);
  4346. } else {
  4347. get_page(page);
  4348. memcpy(skb_put(*pskb, QETH_RX_PULL_LEN),
  4349. element->addr + offset, QETH_RX_PULL_LEN);
  4350. skb_fill_page_desc(*pskb, *pfrag, page,
  4351. offset + QETH_RX_PULL_LEN,
  4352. data_len - QETH_RX_PULL_LEN);
  4353. (*pskb)->data_len += data_len - QETH_RX_PULL_LEN;
  4354. (*pskb)->len += data_len - QETH_RX_PULL_LEN;
  4355. (*pskb)->truesize += data_len - QETH_RX_PULL_LEN;
  4356. (*pfrag)++;
  4357. }
  4358. } else {
  4359. get_page(page);
  4360. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  4361. (*pskb)->data_len += data_len;
  4362. (*pskb)->len += data_len;
  4363. (*pskb)->truesize += data_len;
  4364. (*pfrag)++;
  4365. }
  4366. return 0;
  4367. }
  4368. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  4369. struct qeth_qdio_buffer *qethbuffer,
  4370. struct qdio_buffer_element **__element, int *__offset,
  4371. struct qeth_hdr **hdr)
  4372. {
  4373. struct qdio_buffer_element *element = *__element;
  4374. struct qdio_buffer *buffer = qethbuffer->buffer;
  4375. int offset = *__offset;
  4376. struct sk_buff *skb = NULL;
  4377. int skb_len = 0;
  4378. void *data_ptr;
  4379. int data_len;
  4380. int headroom = 0;
  4381. int use_rx_sg = 0;
  4382. int frag = 0;
  4383. /* qeth_hdr must not cross element boundaries */
  4384. if (element->length < offset + sizeof(struct qeth_hdr)) {
  4385. if (qeth_is_last_sbale(element))
  4386. return NULL;
  4387. element++;
  4388. offset = 0;
  4389. if (element->length < sizeof(struct qeth_hdr))
  4390. return NULL;
  4391. }
  4392. *hdr = element->addr + offset;
  4393. offset += sizeof(struct qeth_hdr);
  4394. switch ((*hdr)->hdr.l2.id) {
  4395. case QETH_HEADER_TYPE_LAYER2:
  4396. skb_len = (*hdr)->hdr.l2.pkt_length;
  4397. break;
  4398. case QETH_HEADER_TYPE_LAYER3:
  4399. skb_len = (*hdr)->hdr.l3.length;
  4400. headroom = ETH_HLEN;
  4401. break;
  4402. case QETH_HEADER_TYPE_OSN:
  4403. skb_len = (*hdr)->hdr.osn.pdu_length;
  4404. headroom = sizeof(struct qeth_hdr);
  4405. break;
  4406. default:
  4407. break;
  4408. }
  4409. if (!skb_len)
  4410. return NULL;
  4411. if (((skb_len >= card->options.rx_sg_cb) &&
  4412. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  4413. (!atomic_read(&card->force_alloc_skb))) ||
  4414. (card->options.cq == QETH_CQ_ENABLED)) {
  4415. use_rx_sg = 1;
  4416. } else {
  4417. skb = dev_alloc_skb(skb_len + headroom);
  4418. if (!skb)
  4419. goto no_mem;
  4420. if (headroom)
  4421. skb_reserve(skb, headroom);
  4422. }
  4423. data_ptr = element->addr + offset;
  4424. while (skb_len) {
  4425. data_len = min(skb_len, (int)(element->length - offset));
  4426. if (data_len) {
  4427. if (use_rx_sg) {
  4428. if (qeth_create_skb_frag(qethbuffer, element,
  4429. &skb, offset, &frag, data_len))
  4430. goto no_mem;
  4431. } else {
  4432. memcpy(skb_put(skb, data_len), data_ptr,
  4433. data_len);
  4434. }
  4435. }
  4436. skb_len -= data_len;
  4437. if (skb_len) {
  4438. if (qeth_is_last_sbale(element)) {
  4439. QETH_CARD_TEXT(card, 4, "unexeob");
  4440. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  4441. dev_kfree_skb_any(skb);
  4442. card->stats.rx_errors++;
  4443. return NULL;
  4444. }
  4445. element++;
  4446. offset = 0;
  4447. data_ptr = element->addr;
  4448. } else {
  4449. offset += data_len;
  4450. }
  4451. }
  4452. *__element = element;
  4453. *__offset = offset;
  4454. if (use_rx_sg && card->options.performance_stats) {
  4455. card->perf_stats.sg_skbs_rx++;
  4456. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  4457. }
  4458. return skb;
  4459. no_mem:
  4460. if (net_ratelimit()) {
  4461. QETH_CARD_TEXT(card, 2, "noskbmem");
  4462. }
  4463. card->stats.rx_dropped++;
  4464. return NULL;
  4465. }
  4466. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  4467. static void qeth_unregister_dbf_views(void)
  4468. {
  4469. int x;
  4470. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4471. debug_unregister(qeth_dbf[x].id);
  4472. qeth_dbf[x].id = NULL;
  4473. }
  4474. }
  4475. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  4476. {
  4477. char dbf_txt_buf[32];
  4478. va_list args;
  4479. if (level > id->level)
  4480. return;
  4481. va_start(args, fmt);
  4482. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  4483. va_end(args);
  4484. debug_text_event(id, level, dbf_txt_buf);
  4485. }
  4486. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  4487. static int qeth_register_dbf_views(void)
  4488. {
  4489. int ret;
  4490. int x;
  4491. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4492. /* register the areas */
  4493. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  4494. qeth_dbf[x].pages,
  4495. qeth_dbf[x].areas,
  4496. qeth_dbf[x].len);
  4497. if (qeth_dbf[x].id == NULL) {
  4498. qeth_unregister_dbf_views();
  4499. return -ENOMEM;
  4500. }
  4501. /* register a view */
  4502. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  4503. if (ret) {
  4504. qeth_unregister_dbf_views();
  4505. return ret;
  4506. }
  4507. /* set a passing level */
  4508. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  4509. }
  4510. return 0;
  4511. }
  4512. int qeth_core_load_discipline(struct qeth_card *card,
  4513. enum qeth_discipline_id discipline)
  4514. {
  4515. int rc = 0;
  4516. mutex_lock(&qeth_mod_mutex);
  4517. switch (discipline) {
  4518. case QETH_DISCIPLINE_LAYER3:
  4519. card->discipline = try_then_request_module(
  4520. symbol_get(qeth_l3_discipline), "qeth_l3");
  4521. break;
  4522. case QETH_DISCIPLINE_LAYER2:
  4523. card->discipline = try_then_request_module(
  4524. symbol_get(qeth_l2_discipline), "qeth_l2");
  4525. break;
  4526. }
  4527. if (!card->discipline) {
  4528. dev_err(&card->gdev->dev, "There is no kernel module to "
  4529. "support discipline %d\n", discipline);
  4530. rc = -EINVAL;
  4531. }
  4532. mutex_unlock(&qeth_mod_mutex);
  4533. return rc;
  4534. }
  4535. void qeth_core_free_discipline(struct qeth_card *card)
  4536. {
  4537. if (card->options.layer2)
  4538. symbol_put(qeth_l2_discipline);
  4539. else
  4540. symbol_put(qeth_l3_discipline);
  4541. card->discipline = NULL;
  4542. }
  4543. static const struct device_type qeth_generic_devtype = {
  4544. .name = "qeth_generic",
  4545. .groups = qeth_generic_attr_groups,
  4546. };
  4547. static const struct device_type qeth_osn_devtype = {
  4548. .name = "qeth_osn",
  4549. .groups = qeth_osn_attr_groups,
  4550. };
  4551. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  4552. {
  4553. struct qeth_card *card;
  4554. struct device *dev;
  4555. int rc;
  4556. unsigned long flags;
  4557. char dbf_name[20];
  4558. QETH_DBF_TEXT(SETUP, 2, "probedev");
  4559. dev = &gdev->dev;
  4560. if (!get_device(dev))
  4561. return -ENODEV;
  4562. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  4563. card = qeth_alloc_card();
  4564. if (!card) {
  4565. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  4566. rc = -ENOMEM;
  4567. goto err_dev;
  4568. }
  4569. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  4570. dev_name(&gdev->dev));
  4571. card->debug = debug_register(dbf_name, 2, 1, 8);
  4572. if (!card->debug) {
  4573. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  4574. rc = -ENOMEM;
  4575. goto err_card;
  4576. }
  4577. debug_register_view(card->debug, &debug_hex_ascii_view);
  4578. card->read.ccwdev = gdev->cdev[0];
  4579. card->write.ccwdev = gdev->cdev[1];
  4580. card->data.ccwdev = gdev->cdev[2];
  4581. dev_set_drvdata(&gdev->dev, card);
  4582. card->gdev = gdev;
  4583. gdev->cdev[0]->handler = qeth_irq;
  4584. gdev->cdev[1]->handler = qeth_irq;
  4585. gdev->cdev[2]->handler = qeth_irq;
  4586. rc = qeth_determine_card_type(card);
  4587. if (rc) {
  4588. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4589. goto err_dbf;
  4590. }
  4591. rc = qeth_setup_card(card);
  4592. if (rc) {
  4593. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  4594. goto err_dbf;
  4595. }
  4596. if (card->info.type == QETH_CARD_TYPE_OSN)
  4597. gdev->dev.type = &qeth_osn_devtype;
  4598. else
  4599. gdev->dev.type = &qeth_generic_devtype;
  4600. switch (card->info.type) {
  4601. case QETH_CARD_TYPE_OSN:
  4602. case QETH_CARD_TYPE_OSM:
  4603. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  4604. if (rc)
  4605. goto err_dbf;
  4606. rc = card->discipline->setup(card->gdev);
  4607. if (rc)
  4608. goto err_disc;
  4609. case QETH_CARD_TYPE_OSD:
  4610. case QETH_CARD_TYPE_OSX:
  4611. default:
  4612. break;
  4613. }
  4614. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4615. list_add_tail(&card->list, &qeth_core_card_list.list);
  4616. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4617. qeth_determine_capabilities(card);
  4618. return 0;
  4619. err_disc:
  4620. qeth_core_free_discipline(card);
  4621. err_dbf:
  4622. debug_unregister(card->debug);
  4623. err_card:
  4624. qeth_core_free_card(card);
  4625. err_dev:
  4626. put_device(dev);
  4627. return rc;
  4628. }
  4629. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4630. {
  4631. unsigned long flags;
  4632. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4633. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4634. if (card->discipline) {
  4635. card->discipline->remove(gdev);
  4636. qeth_core_free_discipline(card);
  4637. }
  4638. debug_unregister(card->debug);
  4639. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4640. list_del(&card->list);
  4641. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4642. qeth_core_free_card(card);
  4643. dev_set_drvdata(&gdev->dev, NULL);
  4644. put_device(&gdev->dev);
  4645. return;
  4646. }
  4647. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4648. {
  4649. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4650. int rc = 0;
  4651. int def_discipline;
  4652. if (!card->discipline) {
  4653. if (card->info.type == QETH_CARD_TYPE_IQD)
  4654. def_discipline = QETH_DISCIPLINE_LAYER3;
  4655. else
  4656. def_discipline = QETH_DISCIPLINE_LAYER2;
  4657. rc = qeth_core_load_discipline(card, def_discipline);
  4658. if (rc)
  4659. goto err;
  4660. rc = card->discipline->setup(card->gdev);
  4661. if (rc)
  4662. goto err;
  4663. }
  4664. rc = card->discipline->set_online(gdev);
  4665. err:
  4666. return rc;
  4667. }
  4668. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4669. {
  4670. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4671. return card->discipline->set_offline(gdev);
  4672. }
  4673. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4674. {
  4675. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4676. if (card->discipline && card->discipline->shutdown)
  4677. card->discipline->shutdown(gdev);
  4678. }
  4679. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4680. {
  4681. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4682. if (card->discipline && card->discipline->prepare)
  4683. return card->discipline->prepare(gdev);
  4684. return 0;
  4685. }
  4686. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4687. {
  4688. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4689. if (card->discipline && card->discipline->complete)
  4690. card->discipline->complete(gdev);
  4691. }
  4692. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4693. {
  4694. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4695. if (card->discipline && card->discipline->freeze)
  4696. return card->discipline->freeze(gdev);
  4697. return 0;
  4698. }
  4699. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4700. {
  4701. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4702. if (card->discipline && card->discipline->thaw)
  4703. return card->discipline->thaw(gdev);
  4704. return 0;
  4705. }
  4706. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4707. {
  4708. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4709. if (card->discipline && card->discipline->restore)
  4710. return card->discipline->restore(gdev);
  4711. return 0;
  4712. }
  4713. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4714. .driver = {
  4715. .owner = THIS_MODULE,
  4716. .name = "qeth",
  4717. },
  4718. .setup = qeth_core_probe_device,
  4719. .remove = qeth_core_remove_device,
  4720. .set_online = qeth_core_set_online,
  4721. .set_offline = qeth_core_set_offline,
  4722. .shutdown = qeth_core_shutdown,
  4723. .prepare = qeth_core_prepare,
  4724. .complete = qeth_core_complete,
  4725. .freeze = qeth_core_freeze,
  4726. .thaw = qeth_core_thaw,
  4727. .restore = qeth_core_restore,
  4728. };
  4729. static ssize_t qeth_core_driver_group_store(struct device_driver *ddrv,
  4730. const char *buf, size_t count)
  4731. {
  4732. int err;
  4733. err = ccwgroup_create_dev(qeth_core_root_dev,
  4734. &qeth_core_ccwgroup_driver, 3, buf);
  4735. return err ? err : count;
  4736. }
  4737. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4738. static struct attribute *qeth_drv_attrs[] = {
  4739. &driver_attr_group.attr,
  4740. NULL,
  4741. };
  4742. static struct attribute_group qeth_drv_attr_group = {
  4743. .attrs = qeth_drv_attrs,
  4744. };
  4745. static const struct attribute_group *qeth_drv_attr_groups[] = {
  4746. &qeth_drv_attr_group,
  4747. NULL,
  4748. };
  4749. static struct {
  4750. const char str[ETH_GSTRING_LEN];
  4751. } qeth_ethtool_stats_keys[] = {
  4752. /* 0 */{"rx skbs"},
  4753. {"rx buffers"},
  4754. {"tx skbs"},
  4755. {"tx buffers"},
  4756. {"tx skbs no packing"},
  4757. {"tx buffers no packing"},
  4758. {"tx skbs packing"},
  4759. {"tx buffers packing"},
  4760. {"tx sg skbs"},
  4761. {"tx sg frags"},
  4762. /* 10 */{"rx sg skbs"},
  4763. {"rx sg frags"},
  4764. {"rx sg page allocs"},
  4765. {"tx large kbytes"},
  4766. {"tx large count"},
  4767. {"tx pk state ch n->p"},
  4768. {"tx pk state ch p->n"},
  4769. {"tx pk watermark low"},
  4770. {"tx pk watermark high"},
  4771. {"queue 0 buffer usage"},
  4772. /* 20 */{"queue 1 buffer usage"},
  4773. {"queue 2 buffer usage"},
  4774. {"queue 3 buffer usage"},
  4775. {"rx poll time"},
  4776. {"rx poll count"},
  4777. {"rx do_QDIO time"},
  4778. {"rx do_QDIO count"},
  4779. {"tx handler time"},
  4780. {"tx handler count"},
  4781. {"tx time"},
  4782. /* 30 */{"tx count"},
  4783. {"tx do_QDIO time"},
  4784. {"tx do_QDIO count"},
  4785. {"tx csum"},
  4786. {"tx lin"},
  4787. {"cq handler count"},
  4788. {"cq handler time"}
  4789. };
  4790. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4791. {
  4792. switch (stringset) {
  4793. case ETH_SS_STATS:
  4794. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4795. default:
  4796. return -EINVAL;
  4797. }
  4798. }
  4799. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4800. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4801. struct ethtool_stats *stats, u64 *data)
  4802. {
  4803. struct qeth_card *card = dev->ml_priv;
  4804. data[0] = card->stats.rx_packets -
  4805. card->perf_stats.initial_rx_packets;
  4806. data[1] = card->perf_stats.bufs_rec;
  4807. data[2] = card->stats.tx_packets -
  4808. card->perf_stats.initial_tx_packets;
  4809. data[3] = card->perf_stats.bufs_sent;
  4810. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4811. - card->perf_stats.skbs_sent_pack;
  4812. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4813. data[6] = card->perf_stats.skbs_sent_pack;
  4814. data[7] = card->perf_stats.bufs_sent_pack;
  4815. data[8] = card->perf_stats.sg_skbs_sent;
  4816. data[9] = card->perf_stats.sg_frags_sent;
  4817. data[10] = card->perf_stats.sg_skbs_rx;
  4818. data[11] = card->perf_stats.sg_frags_rx;
  4819. data[12] = card->perf_stats.sg_alloc_page_rx;
  4820. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4821. data[14] = card->perf_stats.large_send_cnt;
  4822. data[15] = card->perf_stats.sc_dp_p;
  4823. data[16] = card->perf_stats.sc_p_dp;
  4824. data[17] = QETH_LOW_WATERMARK_PACK;
  4825. data[18] = QETH_HIGH_WATERMARK_PACK;
  4826. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4827. data[20] = (card->qdio.no_out_queues > 1) ?
  4828. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4829. data[21] = (card->qdio.no_out_queues > 2) ?
  4830. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4831. data[22] = (card->qdio.no_out_queues > 3) ?
  4832. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4833. data[23] = card->perf_stats.inbound_time;
  4834. data[24] = card->perf_stats.inbound_cnt;
  4835. data[25] = card->perf_stats.inbound_do_qdio_time;
  4836. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4837. data[27] = card->perf_stats.outbound_handler_time;
  4838. data[28] = card->perf_stats.outbound_handler_cnt;
  4839. data[29] = card->perf_stats.outbound_time;
  4840. data[30] = card->perf_stats.outbound_cnt;
  4841. data[31] = card->perf_stats.outbound_do_qdio_time;
  4842. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4843. data[33] = card->perf_stats.tx_csum;
  4844. data[34] = card->perf_stats.tx_lin;
  4845. data[35] = card->perf_stats.cq_cnt;
  4846. data[36] = card->perf_stats.cq_time;
  4847. }
  4848. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4849. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4850. {
  4851. switch (stringset) {
  4852. case ETH_SS_STATS:
  4853. memcpy(data, &qeth_ethtool_stats_keys,
  4854. sizeof(qeth_ethtool_stats_keys));
  4855. break;
  4856. default:
  4857. WARN_ON(1);
  4858. break;
  4859. }
  4860. }
  4861. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4862. void qeth_core_get_drvinfo(struct net_device *dev,
  4863. struct ethtool_drvinfo *info)
  4864. {
  4865. struct qeth_card *card = dev->ml_priv;
  4866. strlcpy(info->driver, card->options.layer2 ? "qeth_l2" : "qeth_l3",
  4867. sizeof(info->driver));
  4868. strlcpy(info->version, "1.0", sizeof(info->version));
  4869. strlcpy(info->fw_version, card->info.mcl_level,
  4870. sizeof(info->fw_version));
  4871. snprintf(info->bus_info, sizeof(info->bus_info), "%s/%s/%s",
  4872. CARD_RDEV_ID(card), CARD_WDEV_ID(card), CARD_DDEV_ID(card));
  4873. }
  4874. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4875. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4876. struct ethtool_cmd *ecmd)
  4877. {
  4878. struct qeth_card *card = netdev->ml_priv;
  4879. enum qeth_link_types link_type;
  4880. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4881. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4882. else
  4883. link_type = card->info.link_type;
  4884. ecmd->transceiver = XCVR_INTERNAL;
  4885. ecmd->supported = SUPPORTED_Autoneg;
  4886. ecmd->advertising = ADVERTISED_Autoneg;
  4887. ecmd->duplex = DUPLEX_FULL;
  4888. ecmd->autoneg = AUTONEG_ENABLE;
  4889. switch (link_type) {
  4890. case QETH_LINK_TYPE_FAST_ETH:
  4891. case QETH_LINK_TYPE_LANE_ETH100:
  4892. ecmd->supported |= SUPPORTED_10baseT_Half |
  4893. SUPPORTED_10baseT_Full |
  4894. SUPPORTED_100baseT_Half |
  4895. SUPPORTED_100baseT_Full |
  4896. SUPPORTED_TP;
  4897. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4898. ADVERTISED_10baseT_Full |
  4899. ADVERTISED_100baseT_Half |
  4900. ADVERTISED_100baseT_Full |
  4901. ADVERTISED_TP;
  4902. ecmd->speed = SPEED_100;
  4903. ecmd->port = PORT_TP;
  4904. break;
  4905. case QETH_LINK_TYPE_GBIT_ETH:
  4906. case QETH_LINK_TYPE_LANE_ETH1000:
  4907. ecmd->supported |= SUPPORTED_10baseT_Half |
  4908. SUPPORTED_10baseT_Full |
  4909. SUPPORTED_100baseT_Half |
  4910. SUPPORTED_100baseT_Full |
  4911. SUPPORTED_1000baseT_Half |
  4912. SUPPORTED_1000baseT_Full |
  4913. SUPPORTED_FIBRE;
  4914. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4915. ADVERTISED_10baseT_Full |
  4916. ADVERTISED_100baseT_Half |
  4917. ADVERTISED_100baseT_Full |
  4918. ADVERTISED_1000baseT_Half |
  4919. ADVERTISED_1000baseT_Full |
  4920. ADVERTISED_FIBRE;
  4921. ecmd->speed = SPEED_1000;
  4922. ecmd->port = PORT_FIBRE;
  4923. break;
  4924. case QETH_LINK_TYPE_10GBIT_ETH:
  4925. ecmd->supported |= SUPPORTED_10baseT_Half |
  4926. SUPPORTED_10baseT_Full |
  4927. SUPPORTED_100baseT_Half |
  4928. SUPPORTED_100baseT_Full |
  4929. SUPPORTED_1000baseT_Half |
  4930. SUPPORTED_1000baseT_Full |
  4931. SUPPORTED_10000baseT_Full |
  4932. SUPPORTED_FIBRE;
  4933. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4934. ADVERTISED_10baseT_Full |
  4935. ADVERTISED_100baseT_Half |
  4936. ADVERTISED_100baseT_Full |
  4937. ADVERTISED_1000baseT_Half |
  4938. ADVERTISED_1000baseT_Full |
  4939. ADVERTISED_10000baseT_Full |
  4940. ADVERTISED_FIBRE;
  4941. ecmd->speed = SPEED_10000;
  4942. ecmd->port = PORT_FIBRE;
  4943. break;
  4944. default:
  4945. ecmd->supported |= SUPPORTED_10baseT_Half |
  4946. SUPPORTED_10baseT_Full |
  4947. SUPPORTED_TP;
  4948. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4949. ADVERTISED_10baseT_Full |
  4950. ADVERTISED_TP;
  4951. ecmd->speed = SPEED_10;
  4952. ecmd->port = PORT_TP;
  4953. }
  4954. return 0;
  4955. }
  4956. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4957. static int __init qeth_core_init(void)
  4958. {
  4959. int rc;
  4960. pr_info("loading core functions\n");
  4961. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4962. rwlock_init(&qeth_core_card_list.rwlock);
  4963. mutex_init(&qeth_mod_mutex);
  4964. rc = qeth_register_dbf_views();
  4965. if (rc)
  4966. goto out_err;
  4967. qeth_core_root_dev = root_device_register("qeth");
  4968. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4969. if (rc)
  4970. goto register_err;
  4971. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4972. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4973. if (!qeth_core_header_cache) {
  4974. rc = -ENOMEM;
  4975. goto slab_err;
  4976. }
  4977. qeth_qdio_outbuf_cache = kmem_cache_create("qeth_buf",
  4978. sizeof(struct qeth_qdio_out_buffer), 0, 0, NULL);
  4979. if (!qeth_qdio_outbuf_cache) {
  4980. rc = -ENOMEM;
  4981. goto cqslab_err;
  4982. }
  4983. rc = ccw_driver_register(&qeth_ccw_driver);
  4984. if (rc)
  4985. goto ccw_err;
  4986. qeth_core_ccwgroup_driver.driver.groups = qeth_drv_attr_groups;
  4987. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4988. if (rc)
  4989. goto ccwgroup_err;
  4990. return 0;
  4991. ccwgroup_err:
  4992. ccw_driver_unregister(&qeth_ccw_driver);
  4993. ccw_err:
  4994. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  4995. cqslab_err:
  4996. kmem_cache_destroy(qeth_core_header_cache);
  4997. slab_err:
  4998. root_device_unregister(qeth_core_root_dev);
  4999. register_err:
  5000. qeth_unregister_dbf_views();
  5001. out_err:
  5002. pr_err("Initializing the qeth device driver failed\n");
  5003. return rc;
  5004. }
  5005. static void __exit qeth_core_exit(void)
  5006. {
  5007. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  5008. ccw_driver_unregister(&qeth_ccw_driver);
  5009. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5010. kmem_cache_destroy(qeth_core_header_cache);
  5011. root_device_unregister(qeth_core_root_dev);
  5012. qeth_unregister_dbf_views();
  5013. pr_info("core functions removed\n");
  5014. }
  5015. module_init(qeth_core_init);
  5016. module_exit(qeth_core_exit);
  5017. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  5018. MODULE_DESCRIPTION("qeth core functions");
  5019. MODULE_LICENSE("GPL");