system.h 14 KB

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  1. #ifndef __ASM_ARM_SYSTEM_H
  2. #define __ASM_ARM_SYSTEM_H
  3. #ifdef __KERNEL__
  4. #define CPU_ARCH_UNKNOWN 0
  5. #define CPU_ARCH_ARMv3 1
  6. #define CPU_ARCH_ARMv4 2
  7. #define CPU_ARCH_ARMv4T 3
  8. #define CPU_ARCH_ARMv5 4
  9. #define CPU_ARCH_ARMv5T 5
  10. #define CPU_ARCH_ARMv5TE 6
  11. #define CPU_ARCH_ARMv5TEJ 7
  12. #define CPU_ARCH_ARMv6 8
  13. #define CPU_ARCH_ARMv7 9
  14. /*
  15. * CR1 bits (CP#15 CR1)
  16. */
  17. #define CR_M (1 << 0) /* MMU enable */
  18. #define CR_A (1 << 1) /* Alignment abort enable */
  19. #define CR_C (1 << 2) /* Dcache enable */
  20. #define CR_W (1 << 3) /* Write buffer enable */
  21. #define CR_P (1 << 4) /* 32-bit exception handler */
  22. #define CR_D (1 << 5) /* 32-bit data address range */
  23. #define CR_L (1 << 6) /* Implementation defined */
  24. #define CR_B (1 << 7) /* Big endian */
  25. #define CR_S (1 << 8) /* System MMU protection */
  26. #define CR_R (1 << 9) /* ROM MMU protection */
  27. #define CR_F (1 << 10) /* Implementation defined */
  28. #define CR_Z (1 << 11) /* Implementation defined */
  29. #define CR_I (1 << 12) /* Icache enable */
  30. #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
  31. #define CR_RR (1 << 14) /* Round Robin cache replacement */
  32. #define CR_L4 (1 << 15) /* LDR pc can set T bit */
  33. #define CR_DT (1 << 16)
  34. #define CR_IT (1 << 18)
  35. #define CR_ST (1 << 19)
  36. #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
  37. #define CR_U (1 << 22) /* Unaligned access operation */
  38. #define CR_XP (1 << 23) /* Extended page tables */
  39. #define CR_VE (1 << 24) /* Vectored interrupts */
  40. #define CR_EE (1 << 25) /* Exception (Big) Endian */
  41. #define CR_TRE (1 << 28) /* TEX remap enable */
  42. #define CR_AFE (1 << 29) /* Access flag enable */
  43. #define CR_TE (1 << 30) /* Thumb exception enable */
  44. /*
  45. * This is used to ensure the compiler did actually allocate the register we
  46. * asked it for some inline assembly sequences. Apparently we can't trust
  47. * the compiler from one version to another so a bit of paranoia won't hurt.
  48. * This string is meant to be concatenated with the inline asm string and
  49. * will cause compilation to stop on mismatch.
  50. * (for details, see gcc PR 15089)
  51. */
  52. #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
  53. #ifndef __ASSEMBLY__
  54. #include <linux/compiler.h>
  55. #include <linux/linkage.h>
  56. #include <linux/irqflags.h>
  57. #include <asm/outercache.h>
  58. struct thread_info;
  59. struct task_struct;
  60. /* information about the system we're running on */
  61. extern unsigned int system_rev;
  62. extern unsigned int system_serial_low;
  63. extern unsigned int system_serial_high;
  64. extern unsigned int mem_fclk_21285;
  65. struct pt_regs;
  66. void die(const char *msg, struct pt_regs *regs, int err);
  67. struct siginfo;
  68. void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
  69. unsigned long err, unsigned long trap);
  70. void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  71. struct pt_regs *),
  72. int sig, int code, const char *name);
  73. void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
  74. struct pt_regs *),
  75. int sig, int code, const char *name);
  76. #define xchg(ptr,x) \
  77. ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  78. extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
  79. struct mm_struct;
  80. extern void show_pte(struct mm_struct *mm, unsigned long addr);
  81. extern void __show_regs(struct pt_regs *);
  82. extern int __pure cpu_architecture(void);
  83. extern void cpu_init(void);
  84. void arm_machine_restart(char mode, const char *cmd);
  85. void soft_restart(unsigned long);
  86. extern void (*arm_pm_restart)(char str, const char *cmd);
  87. #define UDBG_UNDEFINED (1 << 0)
  88. #define UDBG_SYSCALL (1 << 1)
  89. #define UDBG_BADABORT (1 << 2)
  90. #define UDBG_SEGV (1 << 3)
  91. #define UDBG_BUS (1 << 4)
  92. extern unsigned int user_debug;
  93. #if __LINUX_ARM_ARCH__ >= 4
  94. #define vectors_high() (cr_alignment & CR_V)
  95. #else
  96. #define vectors_high() (0)
  97. #endif
  98. #if __LINUX_ARM_ARCH__ >= 7 || \
  99. (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
  100. #define sev() __asm__ __volatile__ ("sev" : : : "memory")
  101. #define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
  102. #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  103. #endif
  104. #if __LINUX_ARM_ARCH__ >= 7
  105. #define isb() __asm__ __volatile__ ("isb" : : : "memory")
  106. #define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
  107. #define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
  108. #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
  109. #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
  110. : : "r" (0) : "memory")
  111. #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
  112. : : "r" (0) : "memory")
  113. #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
  114. : : "r" (0) : "memory")
  115. #elif defined(CONFIG_CPU_FA526)
  116. #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
  117. : : "r" (0) : "memory")
  118. #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
  119. : : "r" (0) : "memory")
  120. #define dmb() __asm__ __volatile__ ("" : : : "memory")
  121. #else
  122. #define isb() __asm__ __volatile__ ("" : : : "memory")
  123. #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
  124. : : "r" (0) : "memory")
  125. #define dmb() __asm__ __volatile__ ("" : : : "memory")
  126. #endif
  127. #ifdef CONFIG_ARCH_HAS_BARRIERS
  128. #include <mach/barriers.h>
  129. #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
  130. #define mb() do { dsb(); outer_sync(); } while (0)
  131. #define rmb() dsb()
  132. #define wmb() mb()
  133. #else
  134. #include <asm/memory.h>
  135. #define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
  136. #define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
  137. #define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
  138. #endif
  139. #ifndef CONFIG_SMP
  140. #define smp_mb() barrier()
  141. #define smp_rmb() barrier()
  142. #define smp_wmb() barrier()
  143. #else
  144. #define smp_mb() dmb()
  145. #define smp_rmb() dmb()
  146. #define smp_wmb() dmb()
  147. #endif
  148. #define read_barrier_depends() do { } while(0)
  149. #define smp_read_barrier_depends() do { } while(0)
  150. #define set_mb(var, value) do { var = value; smp_mb(); } while (0)
  151. #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
  152. extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
  153. extern unsigned long cr_alignment; /* defined in entry-armv.S */
  154. static inline unsigned int get_cr(void)
  155. {
  156. unsigned int val;
  157. asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
  158. return val;
  159. }
  160. static inline void set_cr(unsigned int val)
  161. {
  162. asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
  163. : : "r" (val) : "cc");
  164. isb();
  165. }
  166. #ifndef CONFIG_SMP
  167. extern void adjust_cr(unsigned long mask, unsigned long set);
  168. #endif
  169. #define CPACC_FULL(n) (3 << (n * 2))
  170. #define CPACC_SVC(n) (1 << (n * 2))
  171. #define CPACC_DISABLE(n) (0 << (n * 2))
  172. static inline unsigned int get_copro_access(void)
  173. {
  174. unsigned int val;
  175. asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
  176. : "=r" (val) : : "cc");
  177. return val;
  178. }
  179. static inline void set_copro_access(unsigned int val)
  180. {
  181. asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
  182. : : "r" (val) : "cc");
  183. isb();
  184. }
  185. /*
  186. * switch_mm() may do a full cache flush over the context switch,
  187. * so enable interrupts over the context switch to avoid high
  188. * latency.
  189. */
  190. #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
  191. /*
  192. * switch_to(prev, next) should switch from task `prev' to `next'
  193. * `prev' will never be the same as `next'. schedule() itself
  194. * contains the memory barrier to tell GCC not to cache `current'.
  195. */
  196. extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
  197. #define switch_to(prev,next,last) \
  198. do { \
  199. last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
  200. } while (0)
  201. #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
  202. /*
  203. * On the StrongARM, "swp" is terminally broken since it bypasses the
  204. * cache totally. This means that the cache becomes inconsistent, and,
  205. * since we use normal loads/stores as well, this is really bad.
  206. * Typically, this causes oopsen in filp_close, but could have other,
  207. * more disastrous effects. There are two work-arounds:
  208. * 1. Disable interrupts and emulate the atomic swap
  209. * 2. Clean the cache, perform atomic swap, flush the cache
  210. *
  211. * We choose (1) since its the "easiest" to achieve here and is not
  212. * dependent on the processor type.
  213. *
  214. * NOTE that this solution won't work on an SMP system, so explcitly
  215. * forbid it here.
  216. */
  217. #define swp_is_buggy
  218. #endif
  219. static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
  220. {
  221. extern void __bad_xchg(volatile void *, int);
  222. unsigned long ret;
  223. #ifdef swp_is_buggy
  224. unsigned long flags;
  225. #endif
  226. #if __LINUX_ARM_ARCH__ >= 6
  227. unsigned int tmp;
  228. #endif
  229. smp_mb();
  230. switch (size) {
  231. #if __LINUX_ARM_ARCH__ >= 6
  232. case 1:
  233. asm volatile("@ __xchg1\n"
  234. "1: ldrexb %0, [%3]\n"
  235. " strexb %1, %2, [%3]\n"
  236. " teq %1, #0\n"
  237. " bne 1b"
  238. : "=&r" (ret), "=&r" (tmp)
  239. : "r" (x), "r" (ptr)
  240. : "memory", "cc");
  241. break;
  242. case 4:
  243. asm volatile("@ __xchg4\n"
  244. "1: ldrex %0, [%3]\n"
  245. " strex %1, %2, [%3]\n"
  246. " teq %1, #0\n"
  247. " bne 1b"
  248. : "=&r" (ret), "=&r" (tmp)
  249. : "r" (x), "r" (ptr)
  250. : "memory", "cc");
  251. break;
  252. #elif defined(swp_is_buggy)
  253. #ifdef CONFIG_SMP
  254. #error SMP is not supported on this platform
  255. #endif
  256. case 1:
  257. raw_local_irq_save(flags);
  258. ret = *(volatile unsigned char *)ptr;
  259. *(volatile unsigned char *)ptr = x;
  260. raw_local_irq_restore(flags);
  261. break;
  262. case 4:
  263. raw_local_irq_save(flags);
  264. ret = *(volatile unsigned long *)ptr;
  265. *(volatile unsigned long *)ptr = x;
  266. raw_local_irq_restore(flags);
  267. break;
  268. #else
  269. case 1:
  270. asm volatile("@ __xchg1\n"
  271. " swpb %0, %1, [%2]"
  272. : "=&r" (ret)
  273. : "r" (x), "r" (ptr)
  274. : "memory", "cc");
  275. break;
  276. case 4:
  277. asm volatile("@ __xchg4\n"
  278. " swp %0, %1, [%2]"
  279. : "=&r" (ret)
  280. : "r" (x), "r" (ptr)
  281. : "memory", "cc");
  282. break;
  283. #endif
  284. default:
  285. __bad_xchg(ptr, size), ret = 0;
  286. break;
  287. }
  288. smp_mb();
  289. return ret;
  290. }
  291. extern void disable_hlt(void);
  292. extern void enable_hlt(void);
  293. void cpu_idle_wait(void);
  294. #include <asm-generic/cmpxchg-local.h>
  295. #if __LINUX_ARM_ARCH__ < 6
  296. /* min ARCH < ARMv6 */
  297. #ifdef CONFIG_SMP
  298. #error "SMP is not supported on this platform"
  299. #endif
  300. /*
  301. * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
  302. * them available.
  303. */
  304. #define cmpxchg_local(ptr, o, n) \
  305. ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
  306. (unsigned long)(n), sizeof(*(ptr))))
  307. #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
  308. #ifndef CONFIG_SMP
  309. #include <asm-generic/cmpxchg.h>
  310. #endif
  311. #else /* min ARCH >= ARMv6 */
  312. extern void __bad_cmpxchg(volatile void *ptr, int size);
  313. /*
  314. * cmpxchg only support 32-bits operands on ARMv6.
  315. */
  316. static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
  317. unsigned long new, int size)
  318. {
  319. unsigned long oldval, res;
  320. switch (size) {
  321. #ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
  322. case 1:
  323. do {
  324. asm volatile("@ __cmpxchg1\n"
  325. " ldrexb %1, [%2]\n"
  326. " mov %0, #0\n"
  327. " teq %1, %3\n"
  328. " strexbeq %0, %4, [%2]\n"
  329. : "=&r" (res), "=&r" (oldval)
  330. : "r" (ptr), "Ir" (old), "r" (new)
  331. : "memory", "cc");
  332. } while (res);
  333. break;
  334. case 2:
  335. do {
  336. asm volatile("@ __cmpxchg1\n"
  337. " ldrexh %1, [%2]\n"
  338. " mov %0, #0\n"
  339. " teq %1, %3\n"
  340. " strexheq %0, %4, [%2]\n"
  341. : "=&r" (res), "=&r" (oldval)
  342. : "r" (ptr), "Ir" (old), "r" (new)
  343. : "memory", "cc");
  344. } while (res);
  345. break;
  346. #endif
  347. case 4:
  348. do {
  349. asm volatile("@ __cmpxchg4\n"
  350. " ldrex %1, [%2]\n"
  351. " mov %0, #0\n"
  352. " teq %1, %3\n"
  353. " strexeq %0, %4, [%2]\n"
  354. : "=&r" (res), "=&r" (oldval)
  355. : "r" (ptr), "Ir" (old), "r" (new)
  356. : "memory", "cc");
  357. } while (res);
  358. break;
  359. default:
  360. __bad_cmpxchg(ptr, size);
  361. oldval = 0;
  362. }
  363. return oldval;
  364. }
  365. static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
  366. unsigned long new, int size)
  367. {
  368. unsigned long ret;
  369. smp_mb();
  370. ret = __cmpxchg(ptr, old, new, size);
  371. smp_mb();
  372. return ret;
  373. }
  374. #define cmpxchg(ptr,o,n) \
  375. ((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \
  376. (unsigned long)(o), \
  377. (unsigned long)(n), \
  378. sizeof(*(ptr))))
  379. static inline unsigned long __cmpxchg_local(volatile void *ptr,
  380. unsigned long old,
  381. unsigned long new, int size)
  382. {
  383. unsigned long ret;
  384. switch (size) {
  385. #ifdef CONFIG_CPU_V6 /* min ARCH == ARMv6 */
  386. case 1:
  387. case 2:
  388. ret = __cmpxchg_local_generic(ptr, old, new, size);
  389. break;
  390. #endif
  391. default:
  392. ret = __cmpxchg(ptr, old, new, size);
  393. }
  394. return ret;
  395. }
  396. #define cmpxchg_local(ptr,o,n) \
  397. ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
  398. (unsigned long)(o), \
  399. (unsigned long)(n), \
  400. sizeof(*(ptr))))
  401. #ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
  402. /*
  403. * Note : ARMv7-M (currently unsupported by Linux) does not support
  404. * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
  405. * not be allowed to use __cmpxchg64.
  406. */
  407. static inline unsigned long long __cmpxchg64(volatile void *ptr,
  408. unsigned long long old,
  409. unsigned long long new)
  410. {
  411. register unsigned long long oldval asm("r0");
  412. register unsigned long long __old asm("r2") = old;
  413. register unsigned long long __new asm("r4") = new;
  414. unsigned long res;
  415. do {
  416. asm volatile(
  417. " @ __cmpxchg8\n"
  418. " ldrexd %1, %H1, [%2]\n"
  419. " mov %0, #0\n"
  420. " teq %1, %3\n"
  421. " teqeq %H1, %H3\n"
  422. " strexdeq %0, %4, %H4, [%2]\n"
  423. : "=&r" (res), "=&r" (oldval)
  424. : "r" (ptr), "Ir" (__old), "r" (__new)
  425. : "memory", "cc");
  426. } while (res);
  427. return oldval;
  428. }
  429. static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
  430. unsigned long long old,
  431. unsigned long long new)
  432. {
  433. unsigned long long ret;
  434. smp_mb();
  435. ret = __cmpxchg64(ptr, old, new);
  436. smp_mb();
  437. return ret;
  438. }
  439. #define cmpxchg64(ptr,o,n) \
  440. ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \
  441. (unsigned long long)(o), \
  442. (unsigned long long)(n)))
  443. #define cmpxchg64_local(ptr,o,n) \
  444. ((__typeof__(*(ptr)))__cmpxchg64((ptr), \
  445. (unsigned long long)(o), \
  446. (unsigned long long)(n)))
  447. #else /* min ARCH = ARMv6 */
  448. #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
  449. #endif
  450. #endif /* __LINUX_ARM_ARCH__ >= 6 */
  451. #endif /* __ASSEMBLY__ */
  452. #define arch_align_stack(x) (x)
  453. #endif /* __KERNEL__ */
  454. #endif