4965-mac.c 104 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/firmware.h>
  42. #include <linux/etherdevice.h>
  43. #include <linux/if_arp.h>
  44. #include <net/mac80211.h>
  45. #include <asm/div64.h>
  46. #define DRV_NAME "iwl4965"
  47. #include "iwl-eeprom.h"
  48. #include "iwl-dev.h"
  49. #include "iwl-core.h"
  50. #include "iwl-io.h"
  51. #include "iwl-helpers.h"
  52. #include "iwl-sta.h"
  53. #include "iwl-4965-calib.h"
  54. #include "iwl-4965.h"
  55. /******************************************************************************
  56. *
  57. * module boiler plate
  58. *
  59. ******************************************************************************/
  60. /*
  61. * module name, copyright, version, etc.
  62. */
  63. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
  64. #ifdef CONFIG_IWLEGACY_DEBUG
  65. #define VD "d"
  66. #else
  67. #define VD
  68. #endif
  69. #define DRV_VERSION IWLWIFI_VERSION VD
  70. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  71. MODULE_VERSION(DRV_VERSION);
  72. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  73. MODULE_LICENSE("GPL");
  74. MODULE_ALIAS("iwl4965");
  75. static struct il_link_quality_cmd *
  76. il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
  77. {
  78. int i, r;
  79. struct il_link_quality_cmd *link_cmd;
  80. u32 rate_flags = 0;
  81. __le32 rate_n_flags;
  82. link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
  83. if (!link_cmd) {
  84. IL_ERR("Unable to allocate memory for LQ cmd.\n");
  85. return NULL;
  86. }
  87. /* Set up the rate scaling to start at selected rate, fall back
  88. * all the way down to 1M in IEEE order, and then spin on 1M */
  89. if (il->band == IEEE80211_BAND_5GHZ)
  90. r = RATE_6M_IDX;
  91. else
  92. r = RATE_1M_IDX;
  93. if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
  94. rate_flags |= RATE_MCS_CCK_MSK;
  95. rate_flags |= il4965_first_antenna(il->hw_params.valid_tx_ant) <<
  96. RATE_MCS_ANT_POS;
  97. rate_n_flags = il4965_hw_set_rate_n_flags(il_rates[r].plcp,
  98. rate_flags);
  99. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
  100. link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
  101. link_cmd->general_params.single_stream_ant_msk =
  102. il4965_first_antenna(il->hw_params.valid_tx_ant);
  103. link_cmd->general_params.dual_stream_ant_msk =
  104. il->hw_params.valid_tx_ant &
  105. ~il4965_first_antenna(il->hw_params.valid_tx_ant);
  106. if (!link_cmd->general_params.dual_stream_ant_msk) {
  107. link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
  108. } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
  109. link_cmd->general_params.dual_stream_ant_msk =
  110. il->hw_params.valid_tx_ant;
  111. }
  112. link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
  113. link_cmd->agg_params.agg_time_limit =
  114. cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
  115. link_cmd->sta_id = sta_id;
  116. return link_cmd;
  117. }
  118. /*
  119. * il4965_add_bssid_station - Add the special IBSS BSSID station
  120. *
  121. * Function sleeps.
  122. */
  123. int
  124. il4965_add_bssid_station(struct il_priv *il, struct il_rxon_context *ctx,
  125. const u8 *addr, u8 *sta_id_r)
  126. {
  127. int ret;
  128. u8 sta_id;
  129. struct il_link_quality_cmd *link_cmd;
  130. unsigned long flags;
  131. if (sta_id_r)
  132. *sta_id_r = IL_INVALID_STATION;
  133. ret = il_add_station_common(il, ctx, addr, 0, NULL, &sta_id);
  134. if (ret) {
  135. IL_ERR("Unable to add station %pM\n", addr);
  136. return ret;
  137. }
  138. if (sta_id_r)
  139. *sta_id_r = sta_id;
  140. spin_lock_irqsave(&il->sta_lock, flags);
  141. il->stations[sta_id].used |= IL_STA_LOCAL;
  142. spin_unlock_irqrestore(&il->sta_lock, flags);
  143. /* Set up default rate scaling table in device's station table */
  144. link_cmd = il4965_sta_alloc_lq(il, sta_id);
  145. if (!link_cmd) {
  146. IL_ERR(
  147. "Unable to initialize rate scaling for station %pM.\n",
  148. addr);
  149. return -ENOMEM;
  150. }
  151. ret = il_send_lq_cmd(il, ctx, link_cmd, CMD_SYNC, true);
  152. if (ret)
  153. IL_ERR("Link quality command failed (%d)\n", ret);
  154. spin_lock_irqsave(&il->sta_lock, flags);
  155. il->stations[sta_id].lq = link_cmd;
  156. spin_unlock_irqrestore(&il->sta_lock, flags);
  157. return 0;
  158. }
  159. static int il4965_static_wepkey_cmd(struct il_priv *il,
  160. struct il_rxon_context *ctx,
  161. bool send_if_empty)
  162. {
  163. int i, not_empty = 0;
  164. u8 buff[sizeof(struct il_wep_cmd) +
  165. sizeof(struct il_wep_key) * WEP_KEYS_MAX];
  166. struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
  167. size_t cmd_size = sizeof(struct il_wep_cmd);
  168. struct il_host_cmd cmd = {
  169. .id = ctx->wep_key_cmd,
  170. .data = wep_cmd,
  171. .flags = CMD_SYNC,
  172. };
  173. might_sleep();
  174. memset(wep_cmd, 0, cmd_size +
  175. (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
  176. for (i = 0; i < WEP_KEYS_MAX ; i++) {
  177. wep_cmd->key[i].key_idx = i;
  178. if (ctx->wep_keys[i].key_size) {
  179. wep_cmd->key[i].key_offset = i;
  180. not_empty = 1;
  181. } else {
  182. wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
  183. }
  184. wep_cmd->key[i].key_size = ctx->wep_keys[i].key_size;
  185. memcpy(&wep_cmd->key[i].key[3], ctx->wep_keys[i].key,
  186. ctx->wep_keys[i].key_size);
  187. }
  188. wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
  189. wep_cmd->num_keys = WEP_KEYS_MAX;
  190. cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
  191. cmd.len = cmd_size;
  192. if (not_empty || send_if_empty)
  193. return il_send_cmd(il, &cmd);
  194. else
  195. return 0;
  196. }
  197. int il4965_restore_default_wep_keys(struct il_priv *il,
  198. struct il_rxon_context *ctx)
  199. {
  200. lockdep_assert_held(&il->mutex);
  201. return il4965_static_wepkey_cmd(il, ctx, false);
  202. }
  203. int il4965_remove_default_wep_key(struct il_priv *il,
  204. struct il_rxon_context *ctx,
  205. struct ieee80211_key_conf *keyconf)
  206. {
  207. int ret;
  208. lockdep_assert_held(&il->mutex);
  209. D_WEP("Removing default WEP key: idx=%d\n",
  210. keyconf->keyidx);
  211. memset(&ctx->wep_keys[keyconf->keyidx], 0, sizeof(ctx->wep_keys[0]));
  212. if (il_is_rfkill(il)) {
  213. D_WEP(
  214. "Not sending REPLY_WEPKEY command due to RFKILL.\n");
  215. /* but keys in device are clear anyway so return success */
  216. return 0;
  217. }
  218. ret = il4965_static_wepkey_cmd(il, ctx, 1);
  219. D_WEP("Remove default WEP key: idx=%d ret=%d\n",
  220. keyconf->keyidx, ret);
  221. return ret;
  222. }
  223. int il4965_set_default_wep_key(struct il_priv *il,
  224. struct il_rxon_context *ctx,
  225. struct ieee80211_key_conf *keyconf)
  226. {
  227. int ret;
  228. lockdep_assert_held(&il->mutex);
  229. if (keyconf->keylen != WEP_KEY_LEN_128 &&
  230. keyconf->keylen != WEP_KEY_LEN_64) {
  231. D_WEP("Bad WEP key length %d\n", keyconf->keylen);
  232. return -EINVAL;
  233. }
  234. keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
  235. keyconf->hw_key_idx = HW_KEY_DEFAULT;
  236. il->stations[ctx->ap_sta_id].keyinfo.cipher = keyconf->cipher;
  237. ctx->wep_keys[keyconf->keyidx].key_size = keyconf->keylen;
  238. memcpy(&ctx->wep_keys[keyconf->keyidx].key, &keyconf->key,
  239. keyconf->keylen);
  240. ret = il4965_static_wepkey_cmd(il, ctx, false);
  241. D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n",
  242. keyconf->keylen, keyconf->keyidx, ret);
  243. return ret;
  244. }
  245. static int il4965_set_wep_dynamic_key_info(struct il_priv *il,
  246. struct il_rxon_context *ctx,
  247. struct ieee80211_key_conf *keyconf,
  248. u8 sta_id)
  249. {
  250. unsigned long flags;
  251. __le16 key_flags = 0;
  252. struct il_addsta_cmd sta_cmd;
  253. lockdep_assert_held(&il->mutex);
  254. keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
  255. key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
  256. key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  257. key_flags &= ~STA_KEY_FLG_INVALID;
  258. if (keyconf->keylen == WEP_KEY_LEN_128)
  259. key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
  260. if (sta_id == ctx->bcast_sta_id)
  261. key_flags |= STA_KEY_MULTICAST_MSK;
  262. spin_lock_irqsave(&il->sta_lock, flags);
  263. il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
  264. il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  265. il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
  266. memcpy(il->stations[sta_id].keyinfo.key,
  267. keyconf->key, keyconf->keylen);
  268. memcpy(&il->stations[sta_id].sta.key.key[3],
  269. keyconf->key, keyconf->keylen);
  270. if ((il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
  271. == STA_KEY_FLG_NO_ENC)
  272. il->stations[sta_id].sta.key.key_offset =
  273. il_get_free_ucode_key_idx(il);
  274. /* else, we are overriding an existing key => no need to allocated room
  275. * in uCode. */
  276. WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
  277. "no space for a new key");
  278. il->stations[sta_id].sta.key.key_flags = key_flags;
  279. il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  280. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  281. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  282. sizeof(struct il_addsta_cmd));
  283. spin_unlock_irqrestore(&il->sta_lock, flags);
  284. return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  285. }
  286. static int il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
  287. struct il_rxon_context *ctx,
  288. struct ieee80211_key_conf *keyconf,
  289. u8 sta_id)
  290. {
  291. unsigned long flags;
  292. __le16 key_flags = 0;
  293. struct il_addsta_cmd sta_cmd;
  294. lockdep_assert_held(&il->mutex);
  295. key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
  296. key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  297. key_flags &= ~STA_KEY_FLG_INVALID;
  298. if (sta_id == ctx->bcast_sta_id)
  299. key_flags |= STA_KEY_MULTICAST_MSK;
  300. keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  301. spin_lock_irqsave(&il->sta_lock, flags);
  302. il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
  303. il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  304. memcpy(il->stations[sta_id].keyinfo.key, keyconf->key,
  305. keyconf->keylen);
  306. memcpy(il->stations[sta_id].sta.key.key, keyconf->key,
  307. keyconf->keylen);
  308. if ((il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
  309. == STA_KEY_FLG_NO_ENC)
  310. il->stations[sta_id].sta.key.key_offset =
  311. il_get_free_ucode_key_idx(il);
  312. /* else, we are overriding an existing key => no need to allocated room
  313. * in uCode. */
  314. WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
  315. "no space for a new key");
  316. il->stations[sta_id].sta.key.key_flags = key_flags;
  317. il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  318. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  319. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  320. sizeof(struct il_addsta_cmd));
  321. spin_unlock_irqrestore(&il->sta_lock, flags);
  322. return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  323. }
  324. static int il4965_set_tkip_dynamic_key_info(struct il_priv *il,
  325. struct il_rxon_context *ctx,
  326. struct ieee80211_key_conf *keyconf,
  327. u8 sta_id)
  328. {
  329. unsigned long flags;
  330. int ret = 0;
  331. __le16 key_flags = 0;
  332. key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
  333. key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  334. key_flags &= ~STA_KEY_FLG_INVALID;
  335. if (sta_id == ctx->bcast_sta_id)
  336. key_flags |= STA_KEY_MULTICAST_MSK;
  337. keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  338. keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  339. spin_lock_irqsave(&il->sta_lock, flags);
  340. il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
  341. il->stations[sta_id].keyinfo.keylen = 16;
  342. if ((il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
  343. == STA_KEY_FLG_NO_ENC)
  344. il->stations[sta_id].sta.key.key_offset =
  345. il_get_free_ucode_key_idx(il);
  346. /* else, we are overriding an existing key => no need to allocated room
  347. * in uCode. */
  348. WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
  349. "no space for a new key");
  350. il->stations[sta_id].sta.key.key_flags = key_flags;
  351. /* This copy is acutally not needed: we get the key with each TX */
  352. memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
  353. memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
  354. spin_unlock_irqrestore(&il->sta_lock, flags);
  355. return ret;
  356. }
  357. void il4965_update_tkip_key(struct il_priv *il,
  358. struct il_rxon_context *ctx,
  359. struct ieee80211_key_conf *keyconf,
  360. struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
  361. {
  362. u8 sta_id;
  363. unsigned long flags;
  364. int i;
  365. if (il_scan_cancel(il)) {
  366. /* cancel scan failed, just live w/ bad key and rely
  367. briefly on SW decryption */
  368. return;
  369. }
  370. sta_id = il_sta_id_or_broadcast(il, ctx, sta);
  371. if (sta_id == IL_INVALID_STATION)
  372. return;
  373. spin_lock_irqsave(&il->sta_lock, flags);
  374. il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
  375. for (i = 0; i < 5; i++)
  376. il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
  377. cpu_to_le16(phase1key[i]);
  378. il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  379. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  380. il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
  381. spin_unlock_irqrestore(&il->sta_lock, flags);
  382. }
  383. int il4965_remove_dynamic_key(struct il_priv *il,
  384. struct il_rxon_context *ctx,
  385. struct ieee80211_key_conf *keyconf,
  386. u8 sta_id)
  387. {
  388. unsigned long flags;
  389. u16 key_flags;
  390. u8 keyidx;
  391. struct il_addsta_cmd sta_cmd;
  392. lockdep_assert_held(&il->mutex);
  393. ctx->key_mapping_keys--;
  394. spin_lock_irqsave(&il->sta_lock, flags);
  395. key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
  396. keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
  397. D_WEP("Remove dynamic key: idx=%d sta=%d\n",
  398. keyconf->keyidx, sta_id);
  399. if (keyconf->keyidx != keyidx) {
  400. /* We need to remove a key with idx different that the one
  401. * in the uCode. This means that the key we need to remove has
  402. * been replaced by another one with different idx.
  403. * Don't do anything and return ok
  404. */
  405. spin_unlock_irqrestore(&il->sta_lock, flags);
  406. return 0;
  407. }
  408. if (il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) {
  409. IL_WARN("Removing wrong key %d 0x%x\n",
  410. keyconf->keyidx, key_flags);
  411. spin_unlock_irqrestore(&il->sta_lock, flags);
  412. return 0;
  413. }
  414. if (!test_and_clear_bit(il->stations[sta_id].sta.key.key_offset,
  415. &il->ucode_key_table))
  416. IL_ERR("idx %d not used in uCode key table.\n",
  417. il->stations[sta_id].sta.key.key_offset);
  418. memset(&il->stations[sta_id].keyinfo, 0,
  419. sizeof(struct il_hw_key));
  420. memset(&il->stations[sta_id].sta.key, 0,
  421. sizeof(struct il4965_keyinfo));
  422. il->stations[sta_id].sta.key.key_flags =
  423. STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
  424. il->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET;
  425. il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  426. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  427. if (il_is_rfkill(il)) {
  428. D_WEP(
  429. "Not sending REPLY_ADD_STA command because RFKILL enabled.\n");
  430. spin_unlock_irqrestore(&il->sta_lock, flags);
  431. return 0;
  432. }
  433. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  434. sizeof(struct il_addsta_cmd));
  435. spin_unlock_irqrestore(&il->sta_lock, flags);
  436. return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  437. }
  438. int il4965_set_dynamic_key(struct il_priv *il, struct il_rxon_context *ctx,
  439. struct ieee80211_key_conf *keyconf, u8 sta_id)
  440. {
  441. int ret;
  442. lockdep_assert_held(&il->mutex);
  443. ctx->key_mapping_keys++;
  444. keyconf->hw_key_idx = HW_KEY_DYNAMIC;
  445. switch (keyconf->cipher) {
  446. case WLAN_CIPHER_SUITE_CCMP:
  447. ret = il4965_set_ccmp_dynamic_key_info(il, ctx,
  448. keyconf, sta_id);
  449. break;
  450. case WLAN_CIPHER_SUITE_TKIP:
  451. ret = il4965_set_tkip_dynamic_key_info(il, ctx,
  452. keyconf, sta_id);
  453. break;
  454. case WLAN_CIPHER_SUITE_WEP40:
  455. case WLAN_CIPHER_SUITE_WEP104:
  456. ret = il4965_set_wep_dynamic_key_info(il, ctx,
  457. keyconf, sta_id);
  458. break;
  459. default:
  460. IL_ERR(
  461. "Unknown alg: %s cipher = %x\n", __func__,
  462. keyconf->cipher);
  463. ret = -EINVAL;
  464. }
  465. D_WEP(
  466. "Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
  467. keyconf->cipher, keyconf->keylen, keyconf->keyidx,
  468. sta_id, ret);
  469. return ret;
  470. }
  471. /**
  472. * il4965_alloc_bcast_station - add broadcast station into driver's station table.
  473. *
  474. * This adds the broadcast station into the driver's station table
  475. * and marks it driver active, so that it will be restored to the
  476. * device at the next best time.
  477. */
  478. int il4965_alloc_bcast_station(struct il_priv *il,
  479. struct il_rxon_context *ctx)
  480. {
  481. struct il_link_quality_cmd *link_cmd;
  482. unsigned long flags;
  483. u8 sta_id;
  484. spin_lock_irqsave(&il->sta_lock, flags);
  485. sta_id = il_prep_station(il, ctx, il_bcast_addr,
  486. false, NULL);
  487. if (sta_id == IL_INVALID_STATION) {
  488. IL_ERR("Unable to prepare broadcast station\n");
  489. spin_unlock_irqrestore(&il->sta_lock, flags);
  490. return -EINVAL;
  491. }
  492. il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
  493. il->stations[sta_id].used |= IL_STA_BCAST;
  494. spin_unlock_irqrestore(&il->sta_lock, flags);
  495. link_cmd = il4965_sta_alloc_lq(il, sta_id);
  496. if (!link_cmd) {
  497. IL_ERR(
  498. "Unable to initialize rate scaling for bcast station.\n");
  499. return -ENOMEM;
  500. }
  501. spin_lock_irqsave(&il->sta_lock, flags);
  502. il->stations[sta_id].lq = link_cmd;
  503. spin_unlock_irqrestore(&il->sta_lock, flags);
  504. return 0;
  505. }
  506. /**
  507. * il4965_update_bcast_station - update broadcast station's LQ command
  508. *
  509. * Only used by iwl4965. Placed here to have all bcast station management
  510. * code together.
  511. */
  512. static int il4965_update_bcast_station(struct il_priv *il,
  513. struct il_rxon_context *ctx)
  514. {
  515. unsigned long flags;
  516. struct il_link_quality_cmd *link_cmd;
  517. u8 sta_id = ctx->bcast_sta_id;
  518. link_cmd = il4965_sta_alloc_lq(il, sta_id);
  519. if (!link_cmd) {
  520. IL_ERR(
  521. "Unable to initialize rate scaling for bcast station.\n");
  522. return -ENOMEM;
  523. }
  524. spin_lock_irqsave(&il->sta_lock, flags);
  525. if (il->stations[sta_id].lq)
  526. kfree(il->stations[sta_id].lq);
  527. else
  528. D_INFO(
  529. "Bcast station rate scaling has not been initialized yet.\n");
  530. il->stations[sta_id].lq = link_cmd;
  531. spin_unlock_irqrestore(&il->sta_lock, flags);
  532. return 0;
  533. }
  534. int il4965_update_bcast_stations(struct il_priv *il)
  535. {
  536. return il4965_update_bcast_station(il, &il->ctx);
  537. }
  538. /**
  539. * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
  540. */
  541. int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
  542. {
  543. unsigned long flags;
  544. struct il_addsta_cmd sta_cmd;
  545. lockdep_assert_held(&il->mutex);
  546. /* Remove "disable" flag, to enable Tx for this TID */
  547. spin_lock_irqsave(&il->sta_lock, flags);
  548. il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  549. il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  550. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  551. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  552. sizeof(struct il_addsta_cmd));
  553. spin_unlock_irqrestore(&il->sta_lock, flags);
  554. return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  555. }
  556. int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta,
  557. int tid, u16 ssn)
  558. {
  559. unsigned long flags;
  560. int sta_id;
  561. struct il_addsta_cmd sta_cmd;
  562. lockdep_assert_held(&il->mutex);
  563. sta_id = il_sta_id(sta);
  564. if (sta_id == IL_INVALID_STATION)
  565. return -ENXIO;
  566. spin_lock_irqsave(&il->sta_lock, flags);
  567. il->stations[sta_id].sta.station_flags_msk = 0;
  568. il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  569. il->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  570. il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  571. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  572. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  573. sizeof(struct il_addsta_cmd));
  574. spin_unlock_irqrestore(&il->sta_lock, flags);
  575. return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  576. }
  577. int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta,
  578. int tid)
  579. {
  580. unsigned long flags;
  581. int sta_id;
  582. struct il_addsta_cmd sta_cmd;
  583. lockdep_assert_held(&il->mutex);
  584. sta_id = il_sta_id(sta);
  585. if (sta_id == IL_INVALID_STATION) {
  586. IL_ERR("Invalid station for AGG tid %d\n", tid);
  587. return -ENXIO;
  588. }
  589. spin_lock_irqsave(&il->sta_lock, flags);
  590. il->stations[sta_id].sta.station_flags_msk = 0;
  591. il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  592. il->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  593. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  594. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  595. sizeof(struct il_addsta_cmd));
  596. spin_unlock_irqrestore(&il->sta_lock, flags);
  597. return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  598. }
  599. void
  600. il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
  601. {
  602. unsigned long flags;
  603. spin_lock_irqsave(&il->sta_lock, flags);
  604. il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
  605. il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  606. il->stations[sta_id].sta.sta.modify_mask =
  607. STA_MODIFY_SLEEP_TX_COUNT_MSK;
  608. il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
  609. il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  610. il_send_add_sta(il,
  611. &il->stations[sta_id].sta, CMD_ASYNC);
  612. spin_unlock_irqrestore(&il->sta_lock, flags);
  613. }
  614. void il4965_update_chain_flags(struct il_priv *il)
  615. {
  616. if (il->cfg->ops->hcmd->set_rxon_chain) {
  617. il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
  618. if (il->ctx.active.rx_chain != il->ctx.staging.rx_chain)
  619. il_commit_rxon(il, &il->ctx);
  620. }
  621. }
  622. static void il4965_clear_free_frames(struct il_priv *il)
  623. {
  624. struct list_head *element;
  625. D_INFO("%d frames on pre-allocated heap on clear.\n",
  626. il->frames_count);
  627. while (!list_empty(&il->free_frames)) {
  628. element = il->free_frames.next;
  629. list_del(element);
  630. kfree(list_entry(element, struct il_frame, list));
  631. il->frames_count--;
  632. }
  633. if (il->frames_count) {
  634. IL_WARN("%d frames still in use. Did we lose one?\n",
  635. il->frames_count);
  636. il->frames_count = 0;
  637. }
  638. }
  639. static struct il_frame *il4965_get_free_frame(struct il_priv *il)
  640. {
  641. struct il_frame *frame;
  642. struct list_head *element;
  643. if (list_empty(&il->free_frames)) {
  644. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  645. if (!frame) {
  646. IL_ERR("Could not allocate frame!\n");
  647. return NULL;
  648. }
  649. il->frames_count++;
  650. return frame;
  651. }
  652. element = il->free_frames.next;
  653. list_del(element);
  654. return list_entry(element, struct il_frame, list);
  655. }
  656. static void il4965_free_frame(struct il_priv *il, struct il_frame *frame)
  657. {
  658. memset(frame, 0, sizeof(*frame));
  659. list_add(&frame->list, &il->free_frames);
  660. }
  661. static u32 il4965_fill_beacon_frame(struct il_priv *il,
  662. struct ieee80211_hdr *hdr,
  663. int left)
  664. {
  665. lockdep_assert_held(&il->mutex);
  666. if (!il->beacon_skb)
  667. return 0;
  668. if (il->beacon_skb->len > left)
  669. return 0;
  670. memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
  671. return il->beacon_skb->len;
  672. }
  673. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  674. static void il4965_set_beacon_tim(struct il_priv *il,
  675. struct il_tx_beacon_cmd *tx_beacon_cmd,
  676. u8 *beacon, u32 frame_size)
  677. {
  678. u16 tim_idx;
  679. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  680. /*
  681. * The idx is relative to frame start but we start looking at the
  682. * variable-length part of the beacon.
  683. */
  684. tim_idx = mgmt->u.beacon.variable - beacon;
  685. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  686. while ((tim_idx < (frame_size - 2)) &&
  687. (beacon[tim_idx] != WLAN_EID_TIM))
  688. tim_idx += beacon[tim_idx+1] + 2;
  689. /* If TIM field was found, set variables */
  690. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  691. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  692. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  693. } else
  694. IL_WARN("Unable to find TIM Element in beacon\n");
  695. }
  696. static unsigned int il4965_hw_get_beacon_cmd(struct il_priv *il,
  697. struct il_frame *frame)
  698. {
  699. struct il_tx_beacon_cmd *tx_beacon_cmd;
  700. u32 frame_size;
  701. u32 rate_flags;
  702. u32 rate;
  703. /*
  704. * We have to set up the TX command, the TX Beacon command, and the
  705. * beacon contents.
  706. */
  707. lockdep_assert_held(&il->mutex);
  708. if (!il->beacon_ctx) {
  709. IL_ERR("trying to build beacon w/o beacon context!\n");
  710. return 0;
  711. }
  712. /* Initialize memory */
  713. tx_beacon_cmd = &frame->u.beacon;
  714. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  715. /* Set up TX beacon contents */
  716. frame_size = il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
  717. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  718. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  719. return 0;
  720. if (!frame_size)
  721. return 0;
  722. /* Set up TX command fields */
  723. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  724. tx_beacon_cmd->tx.sta_id = il->beacon_ctx->bcast_sta_id;
  725. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  726. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  727. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  728. /* Set up TX beacon command fields */
  729. il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  730. frame_size);
  731. /* Set up packet rate and flags */
  732. rate = il_get_lowest_plcp(il, il->beacon_ctx);
  733. il->mgmt_tx_ant = il4965_toggle_tx_ant(il, il->mgmt_tx_ant,
  734. il->hw_params.valid_tx_ant);
  735. rate_flags = il4965_ant_idx_to_flags(il->mgmt_tx_ant);
  736. if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
  737. rate_flags |= RATE_MCS_CCK_MSK;
  738. tx_beacon_cmd->tx.rate_n_flags = il4965_hw_set_rate_n_flags(rate,
  739. rate_flags);
  740. return sizeof(*tx_beacon_cmd) + frame_size;
  741. }
  742. int il4965_send_beacon_cmd(struct il_priv *il)
  743. {
  744. struct il_frame *frame;
  745. unsigned int frame_size;
  746. int rc;
  747. frame = il4965_get_free_frame(il);
  748. if (!frame) {
  749. IL_ERR("Could not obtain free frame buffer for beacon "
  750. "command.\n");
  751. return -ENOMEM;
  752. }
  753. frame_size = il4965_hw_get_beacon_cmd(il, frame);
  754. if (!frame_size) {
  755. IL_ERR("Error configuring the beacon command\n");
  756. il4965_free_frame(il, frame);
  757. return -EINVAL;
  758. }
  759. rc = il_send_cmd_pdu(il, REPLY_TX_BEACON, frame_size,
  760. &frame->u.cmd[0]);
  761. il4965_free_frame(il, frame);
  762. return rc;
  763. }
  764. static inline dma_addr_t il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
  765. {
  766. struct il_tfd_tb *tb = &tfd->tbs[idx];
  767. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  768. if (sizeof(dma_addr_t) > sizeof(u32))
  769. addr |=
  770. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  771. return addr;
  772. }
  773. static inline u16 il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
  774. {
  775. struct il_tfd_tb *tb = &tfd->tbs[idx];
  776. return le16_to_cpu(tb->hi_n_len) >> 4;
  777. }
  778. static inline void il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx,
  779. dma_addr_t addr, u16 len)
  780. {
  781. struct il_tfd_tb *tb = &tfd->tbs[idx];
  782. u16 hi_n_len = len << 4;
  783. put_unaligned_le32(addr, &tb->lo);
  784. if (sizeof(dma_addr_t) > sizeof(u32))
  785. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  786. tb->hi_n_len = cpu_to_le16(hi_n_len);
  787. tfd->num_tbs = idx + 1;
  788. }
  789. static inline u8 il4965_tfd_get_num_tbs(struct il_tfd *tfd)
  790. {
  791. return tfd->num_tbs & 0x1f;
  792. }
  793. /**
  794. * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  795. * @il - driver ilate data
  796. * @txq - tx queue
  797. *
  798. * Does NOT advance any TFD circular buffer read/write idxes
  799. * Does NOT free the TFD itself (which is within circular buffer)
  800. */
  801. void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
  802. {
  803. struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
  804. struct il_tfd *tfd;
  805. struct pci_dev *dev = il->pci_dev;
  806. int idx = txq->q.read_ptr;
  807. int i;
  808. int num_tbs;
  809. tfd = &tfd_tmp[idx];
  810. /* Sanity check on number of chunks */
  811. num_tbs = il4965_tfd_get_num_tbs(tfd);
  812. if (num_tbs >= IL_NUM_OF_TBS) {
  813. IL_ERR("Too many chunks: %i\n", num_tbs);
  814. /* @todo issue fatal error, it is quite serious situation */
  815. return;
  816. }
  817. /* Unmap tx_cmd */
  818. if (num_tbs)
  819. pci_unmap_single(dev,
  820. dma_unmap_addr(&txq->meta[idx], mapping),
  821. dma_unmap_len(&txq->meta[idx], len),
  822. PCI_DMA_BIDIRECTIONAL);
  823. /* Unmap chunks, if any. */
  824. for (i = 1; i < num_tbs; i++)
  825. pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
  826. il4965_tfd_tb_get_len(tfd, i),
  827. PCI_DMA_TODEVICE);
  828. /* free SKB */
  829. if (txq->txb) {
  830. struct sk_buff *skb;
  831. skb = txq->txb[txq->q.read_ptr].skb;
  832. /* can be called from irqs-disabled context */
  833. if (skb) {
  834. dev_kfree_skb_any(skb);
  835. txq->txb[txq->q.read_ptr].skb = NULL;
  836. }
  837. }
  838. }
  839. int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il,
  840. struct il_tx_queue *txq,
  841. dma_addr_t addr, u16 len,
  842. u8 reset, u8 pad)
  843. {
  844. struct il_queue *q;
  845. struct il_tfd *tfd, *tfd_tmp;
  846. u32 num_tbs;
  847. q = &txq->q;
  848. tfd_tmp = (struct il_tfd *)txq->tfds;
  849. tfd = &tfd_tmp[q->write_ptr];
  850. if (reset)
  851. memset(tfd, 0, sizeof(*tfd));
  852. num_tbs = il4965_tfd_get_num_tbs(tfd);
  853. /* Each TFD can point to a maximum 20 Tx buffers */
  854. if (num_tbs >= IL_NUM_OF_TBS) {
  855. IL_ERR("Error can not send more than %d chunks\n",
  856. IL_NUM_OF_TBS);
  857. return -EINVAL;
  858. }
  859. BUG_ON(addr & ~DMA_BIT_MASK(36));
  860. if (unlikely(addr & ~IL_TX_DMA_MASK))
  861. IL_ERR("Unaligned address = %llx\n",
  862. (unsigned long long)addr);
  863. il4965_tfd_set_tb(tfd, num_tbs, addr, len);
  864. return 0;
  865. }
  866. /*
  867. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  868. * given Tx queue, and enable the DMA channel used for that queue.
  869. *
  870. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  871. * channels supported in hardware.
  872. */
  873. int il4965_hw_tx_queue_init(struct il_priv *il,
  874. struct il_tx_queue *txq)
  875. {
  876. int txq_id = txq->q.id;
  877. /* Circular buffer (TFD queue in DRAM) physical base address */
  878. il_wr(il, FH_MEM_CBBC_QUEUE(txq_id),
  879. txq->q.dma_addr >> 8);
  880. return 0;
  881. }
  882. /******************************************************************************
  883. *
  884. * Generic RX handler implementations
  885. *
  886. ******************************************************************************/
  887. static void il4965_rx_reply_alive(struct il_priv *il,
  888. struct il_rx_buf *rxb)
  889. {
  890. struct il_rx_pkt *pkt = rxb_addr(rxb);
  891. struct il_alive_resp *palive;
  892. struct delayed_work *pwork;
  893. palive = &pkt->u.alive_frame;
  894. D_INFO("Alive ucode status 0x%08X revision "
  895. "0x%01X 0x%01X\n",
  896. palive->is_valid, palive->ver_type,
  897. palive->ver_subtype);
  898. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  899. D_INFO("Initialization Alive received.\n");
  900. memcpy(&il->card_alive_init,
  901. &pkt->u.alive_frame,
  902. sizeof(struct il_init_alive_resp));
  903. pwork = &il->init_alive_start;
  904. } else {
  905. D_INFO("Runtime Alive received.\n");
  906. memcpy(&il->card_alive, &pkt->u.alive_frame,
  907. sizeof(struct il_alive_resp));
  908. pwork = &il->alive_start;
  909. }
  910. /* We delay the ALIVE response by 5ms to
  911. * give the HW RF Kill time to activate... */
  912. if (palive->is_valid == UCODE_VALID_OK)
  913. queue_delayed_work(il->workqueue, pwork,
  914. msecs_to_jiffies(5));
  915. else
  916. IL_WARN("uCode did not respond OK.\n");
  917. }
  918. /**
  919. * il4965_bg_stats_periodic - Timer callback to queue stats
  920. *
  921. * This callback is provided in order to send a stats request.
  922. *
  923. * This timer function is continually reset to execute within
  924. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  925. * was received. We need to ensure we receive the stats in order
  926. * to update the temperature used for calibrating the TXPOWER.
  927. */
  928. static void il4965_bg_stats_periodic(unsigned long data)
  929. {
  930. struct il_priv *il = (struct il_priv *)data;
  931. if (test_bit(STATUS_EXIT_PENDING, &il->status))
  932. return;
  933. /* dont send host command if rf-kill is on */
  934. if (!il_is_ready_rf(il))
  935. return;
  936. il_send_stats_request(il, CMD_ASYNC, false);
  937. }
  938. static void il4965_rx_beacon_notif(struct il_priv *il,
  939. struct il_rx_buf *rxb)
  940. {
  941. struct il_rx_pkt *pkt = rxb_addr(rxb);
  942. struct il4965_beacon_notif *beacon =
  943. (struct il4965_beacon_notif *)pkt->u.raw;
  944. #ifdef CONFIG_IWLEGACY_DEBUG
  945. u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  946. D_RX("beacon status %x retries %d iss %d "
  947. "tsf %d %d rate %d\n",
  948. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  949. beacon->beacon_notify_hdr.failure_frame,
  950. le32_to_cpu(beacon->ibss_mgr_status),
  951. le32_to_cpu(beacon->high_tsf),
  952. le32_to_cpu(beacon->low_tsf), rate);
  953. #endif
  954. il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
  955. }
  956. static void il4965_perform_ct_kill_task(struct il_priv *il)
  957. {
  958. unsigned long flags;
  959. D_POWER("Stop all queues\n");
  960. if (il->mac80211_registered)
  961. ieee80211_stop_queues(il->hw);
  962. _il_wr(il, CSR_UCODE_DRV_GP1_SET,
  963. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  964. _il_rd(il, CSR_UCODE_DRV_GP1);
  965. spin_lock_irqsave(&il->reg_lock, flags);
  966. if (!_il_grab_nic_access(il))
  967. _il_release_nic_access(il);
  968. spin_unlock_irqrestore(&il->reg_lock, flags);
  969. }
  970. /* Handle notification from uCode that card's power state is changing
  971. * due to software, hardware, or critical temperature RFKILL */
  972. static void il4965_rx_card_state_notif(struct il_priv *il,
  973. struct il_rx_buf *rxb)
  974. {
  975. struct il_rx_pkt *pkt = rxb_addr(rxb);
  976. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  977. unsigned long status = il->status;
  978. D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
  979. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  980. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  981. (flags & CT_CARD_DISABLED) ?
  982. "Reached" : "Not reached");
  983. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  984. CT_CARD_DISABLED)) {
  985. _il_wr(il, CSR_UCODE_DRV_GP1_SET,
  986. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  987. il_wr(il, HBUS_TARG_MBX_C,
  988. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  989. if (!(flags & RXON_CARD_DISABLED)) {
  990. _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
  991. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  992. il_wr(il, HBUS_TARG_MBX_C,
  993. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  994. }
  995. }
  996. if (flags & CT_CARD_DISABLED)
  997. il4965_perform_ct_kill_task(il);
  998. if (flags & HW_CARD_DISABLED)
  999. set_bit(STATUS_RF_KILL_HW, &il->status);
  1000. else
  1001. clear_bit(STATUS_RF_KILL_HW, &il->status);
  1002. if (!(flags & RXON_CARD_DISABLED))
  1003. il_scan_cancel(il);
  1004. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  1005. test_bit(STATUS_RF_KILL_HW, &il->status)))
  1006. wiphy_rfkill_set_hw_state(il->hw->wiphy,
  1007. test_bit(STATUS_RF_KILL_HW, &il->status));
  1008. else
  1009. wake_up(&il->wait_command_queue);
  1010. }
  1011. /**
  1012. * il4965_setup_rx_handlers - Initialize Rx handler callbacks
  1013. *
  1014. * Setup the RX handlers for each of the reply types sent from the uCode
  1015. * to the host.
  1016. *
  1017. * This function chains into the hardware specific files for them to setup
  1018. * any hardware specific handlers as well.
  1019. */
  1020. static void il4965_setup_rx_handlers(struct il_priv *il)
  1021. {
  1022. il->rx_handlers[REPLY_ALIVE] = il4965_rx_reply_alive;
  1023. il->rx_handlers[REPLY_ERROR] = il_rx_reply_error;
  1024. il->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = il_rx_csa;
  1025. il->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  1026. il_rx_spectrum_measure_notif;
  1027. il->rx_handlers[PM_SLEEP_NOTIFICATION] = il_rx_pm_sleep_notif;
  1028. il->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  1029. il_rx_pm_debug_stats_notif;
  1030. il->rx_handlers[BEACON_NOTIFICATION] = il4965_rx_beacon_notif;
  1031. /*
  1032. * The same handler is used for both the REPLY to a discrete
  1033. * stats request from the host as well as for the periodic
  1034. * stats notifications (after received beacons) from the uCode.
  1035. */
  1036. il->rx_handlers[REPLY_STATISTICS_CMD] = il4965_reply_stats;
  1037. il->rx_handlers[STATISTICS_NOTIFICATION] = il4965_rx_stats;
  1038. il_setup_rx_scan_handlers(il);
  1039. /* status change handler */
  1040. il->rx_handlers[CARD_STATE_NOTIFICATION] =
  1041. il4965_rx_card_state_notif;
  1042. il->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  1043. il4965_rx_missed_beacon_notif;
  1044. /* Rx handlers */
  1045. il->rx_handlers[REPLY_RX_PHY_CMD] = il4965_rx_reply_rx_phy;
  1046. il->rx_handlers[REPLY_RX_MPDU_CMD] = il4965_rx_reply_rx;
  1047. /* block ack */
  1048. il->rx_handlers[REPLY_COMPRESSED_BA] = il4965_rx_reply_compressed_ba;
  1049. /* Set up hardware specific Rx handlers */
  1050. il->cfg->ops->lib->rx_handler_setup(il);
  1051. }
  1052. /**
  1053. * il4965_rx_handle - Main entry function for receiving responses from uCode
  1054. *
  1055. * Uses the il->rx_handlers callback function array to invoke
  1056. * the appropriate handlers, including command responses,
  1057. * frame-received notifications, and other notifications.
  1058. */
  1059. void il4965_rx_handle(struct il_priv *il)
  1060. {
  1061. struct il_rx_buf *rxb;
  1062. struct il_rx_pkt *pkt;
  1063. struct il_rx_queue *rxq = &il->rxq;
  1064. u32 r, i;
  1065. int reclaim;
  1066. unsigned long flags;
  1067. u8 fill_rx = 0;
  1068. u32 count = 8;
  1069. int total_empty;
  1070. /* uCode's read idx (stored in shared DRAM) indicates the last Rx
  1071. * buffer that the driver may process (last buffer filled by ucode). */
  1072. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  1073. i = rxq->read;
  1074. /* Rx interrupt, but nothing sent from uCode */
  1075. if (i == r)
  1076. D_RX("r = %d, i = %d\n", r, i);
  1077. /* calculate total frames need to be restock after handling RX */
  1078. total_empty = r - rxq->write_actual;
  1079. if (total_empty < 0)
  1080. total_empty += RX_QUEUE_SIZE;
  1081. if (total_empty > (RX_QUEUE_SIZE / 2))
  1082. fill_rx = 1;
  1083. while (i != r) {
  1084. int len;
  1085. rxb = rxq->queue[i];
  1086. /* If an RXB doesn't have a Rx queue slot associated with it,
  1087. * then a bug has been introduced in the queue refilling
  1088. * routines -- catch it here */
  1089. BUG_ON(rxb == NULL);
  1090. rxq->queue[i] = NULL;
  1091. pci_unmap_page(il->pci_dev, rxb->page_dma,
  1092. PAGE_SIZE << il->hw_params.rx_page_order,
  1093. PCI_DMA_FROMDEVICE);
  1094. pkt = rxb_addr(rxb);
  1095. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1096. len += sizeof(u32); /* account for status word */
  1097. /* Reclaim a command buffer only if this packet is a response
  1098. * to a (driver-originated) command.
  1099. * If the packet (e.g. Rx frame) originated from uCode,
  1100. * there is no command buffer to reclaim.
  1101. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  1102. * but apparently a few don't get set; catch them here. */
  1103. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  1104. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  1105. (pkt->hdr.cmd != REPLY_RX) &&
  1106. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  1107. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  1108. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  1109. (pkt->hdr.cmd != REPLY_TX);
  1110. /* Based on type of command response or notification,
  1111. * handle those that need handling via function in
  1112. * rx_handlers table. See il4965_setup_rx_handlers() */
  1113. if (il->rx_handlers[pkt->hdr.cmd]) {
  1114. D_RX("r = %d, i = %d, %s, 0x%02x\n", r,
  1115. i, il_get_cmd_string(pkt->hdr.cmd),
  1116. pkt->hdr.cmd);
  1117. il->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  1118. il->rx_handlers[pkt->hdr.cmd] (il, rxb);
  1119. } else {
  1120. /* No handling needed */
  1121. D_RX(
  1122. "r %d i %d No handler needed for %s, 0x%02x\n",
  1123. r, i, il_get_cmd_string(pkt->hdr.cmd),
  1124. pkt->hdr.cmd);
  1125. }
  1126. /*
  1127. * XXX: After here, we should always check rxb->page
  1128. * against NULL before touching it or its virtual
  1129. * memory (pkt). Because some rx_handler might have
  1130. * already taken or freed the pages.
  1131. */
  1132. if (reclaim) {
  1133. /* Invoke any callbacks, transfer the buffer to caller,
  1134. * and fire off the (possibly) blocking il_send_cmd()
  1135. * as we reclaim the driver command queue */
  1136. if (rxb->page)
  1137. il_tx_cmd_complete(il, rxb);
  1138. else
  1139. IL_WARN("Claim null rxb?\n");
  1140. }
  1141. /* Reuse the page if possible. For notification packets and
  1142. * SKBs that fail to Rx correctly, add them back into the
  1143. * rx_free list for reuse later. */
  1144. spin_lock_irqsave(&rxq->lock, flags);
  1145. if (rxb->page != NULL) {
  1146. rxb->page_dma = pci_map_page(il->pci_dev, rxb->page,
  1147. 0, PAGE_SIZE << il->hw_params.rx_page_order,
  1148. PCI_DMA_FROMDEVICE);
  1149. list_add_tail(&rxb->list, &rxq->rx_free);
  1150. rxq->free_count++;
  1151. } else
  1152. list_add_tail(&rxb->list, &rxq->rx_used);
  1153. spin_unlock_irqrestore(&rxq->lock, flags);
  1154. i = (i + 1) & RX_QUEUE_MASK;
  1155. /* If there are a lot of unused frames,
  1156. * restock the Rx queue so ucode wont assert. */
  1157. if (fill_rx) {
  1158. count++;
  1159. if (count >= 8) {
  1160. rxq->read = i;
  1161. il4965_rx_replenish_now(il);
  1162. count = 0;
  1163. }
  1164. }
  1165. }
  1166. /* Backtrack one entry */
  1167. rxq->read = i;
  1168. if (fill_rx)
  1169. il4965_rx_replenish_now(il);
  1170. else
  1171. il4965_rx_queue_restock(il);
  1172. }
  1173. /* call this function to flush any scheduled tasklet */
  1174. static inline void il4965_synchronize_irq(struct il_priv *il)
  1175. {
  1176. /* wait to make sure we flush pending tasklet*/
  1177. synchronize_irq(il->pci_dev->irq);
  1178. tasklet_kill(&il->irq_tasklet);
  1179. }
  1180. static void il4965_irq_tasklet(struct il_priv *il)
  1181. {
  1182. u32 inta, handled = 0;
  1183. u32 inta_fh;
  1184. unsigned long flags;
  1185. u32 i;
  1186. #ifdef CONFIG_IWLEGACY_DEBUG
  1187. u32 inta_mask;
  1188. #endif
  1189. spin_lock_irqsave(&il->lock, flags);
  1190. /* Ack/clear/reset pending uCode interrupts.
  1191. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1192. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  1193. inta = _il_rd(il, CSR_INT);
  1194. _il_wr(il, CSR_INT, inta);
  1195. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  1196. * Any new interrupts that happen after this, either while we're
  1197. * in this tasklet, or later, will show up in next ISR/tasklet. */
  1198. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  1199. _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
  1200. #ifdef CONFIG_IWLEGACY_DEBUG
  1201. if (il_get_debug_level(il) & IL_DL_ISR) {
  1202. /* just for debug */
  1203. inta_mask = _il_rd(il, CSR_INT_MASK);
  1204. D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1205. inta, inta_mask, inta_fh);
  1206. }
  1207. #endif
  1208. spin_unlock_irqrestore(&il->lock, flags);
  1209. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  1210. * atomic, make sure that inta covers all the interrupts that
  1211. * we've discovered, even if FH interrupt came in just after
  1212. * reading CSR_INT. */
  1213. if (inta_fh & CSR49_FH_INT_RX_MASK)
  1214. inta |= CSR_INT_BIT_FH_RX;
  1215. if (inta_fh & CSR49_FH_INT_TX_MASK)
  1216. inta |= CSR_INT_BIT_FH_TX;
  1217. /* Now service all interrupt bits discovered above. */
  1218. if (inta & CSR_INT_BIT_HW_ERR) {
  1219. IL_ERR("Hardware error detected. Restarting.\n");
  1220. /* Tell the device to stop sending interrupts */
  1221. il_disable_interrupts(il);
  1222. il->isr_stats.hw++;
  1223. il_irq_handle_error(il);
  1224. handled |= CSR_INT_BIT_HW_ERR;
  1225. return;
  1226. }
  1227. #ifdef CONFIG_IWLEGACY_DEBUG
  1228. if (il_get_debug_level(il) & (IL_DL_ISR)) {
  1229. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1230. if (inta & CSR_INT_BIT_SCD) {
  1231. D_ISR("Scheduler finished to transmit "
  1232. "the frame/frames.\n");
  1233. il->isr_stats.sch++;
  1234. }
  1235. /* Alive notification via Rx interrupt will do the real work */
  1236. if (inta & CSR_INT_BIT_ALIVE) {
  1237. D_ISR("Alive interrupt\n");
  1238. il->isr_stats.alive++;
  1239. }
  1240. }
  1241. #endif
  1242. /* Safely ignore these bits for debug checks below */
  1243. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1244. /* HW RF KILL switch toggled */
  1245. if (inta & CSR_INT_BIT_RF_KILL) {
  1246. int hw_rf_kill = 0;
  1247. if (!(_il_rd(il, CSR_GP_CNTRL) &
  1248. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1249. hw_rf_kill = 1;
  1250. IL_WARN("RF_KILL bit toggled to %s.\n",
  1251. hw_rf_kill ? "disable radio" : "enable radio");
  1252. il->isr_stats.rfkill++;
  1253. /* driver only loads ucode once setting the interface up.
  1254. * the driver allows loading the ucode even if the radio
  1255. * is killed. Hence update the killswitch state here. The
  1256. * rfkill handler will care about restarting if needed.
  1257. */
  1258. if (!test_bit(STATUS_ALIVE, &il->status)) {
  1259. if (hw_rf_kill)
  1260. set_bit(STATUS_RF_KILL_HW, &il->status);
  1261. else
  1262. clear_bit(STATUS_RF_KILL_HW, &il->status);
  1263. wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
  1264. }
  1265. handled |= CSR_INT_BIT_RF_KILL;
  1266. }
  1267. /* Chip got too hot and stopped itself */
  1268. if (inta & CSR_INT_BIT_CT_KILL) {
  1269. IL_ERR("Microcode CT kill error detected.\n");
  1270. il->isr_stats.ctkill++;
  1271. handled |= CSR_INT_BIT_CT_KILL;
  1272. }
  1273. /* Error detected by uCode */
  1274. if (inta & CSR_INT_BIT_SW_ERR) {
  1275. IL_ERR("Microcode SW error detected. "
  1276. " Restarting 0x%X.\n", inta);
  1277. il->isr_stats.sw++;
  1278. il_irq_handle_error(il);
  1279. handled |= CSR_INT_BIT_SW_ERR;
  1280. }
  1281. /*
  1282. * uCode wakes up after power-down sleep.
  1283. * Tell device about any new tx or host commands enqueued,
  1284. * and about any Rx buffers made available while asleep.
  1285. */
  1286. if (inta & CSR_INT_BIT_WAKEUP) {
  1287. D_ISR("Wakeup interrupt\n");
  1288. il_rx_queue_update_write_ptr(il, &il->rxq);
  1289. for (i = 0; i < il->hw_params.max_txq_num; i++)
  1290. il_txq_update_write_ptr(il, &il->txq[i]);
  1291. il->isr_stats.wakeup++;
  1292. handled |= CSR_INT_BIT_WAKEUP;
  1293. }
  1294. /* All uCode command responses, including Tx command responses,
  1295. * Rx "responses" (frame-received notification), and other
  1296. * notifications from uCode come through here*/
  1297. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1298. il4965_rx_handle(il);
  1299. il->isr_stats.rx++;
  1300. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1301. }
  1302. /* This "Tx" DMA channel is used only for loading uCode */
  1303. if (inta & CSR_INT_BIT_FH_TX) {
  1304. D_ISR("uCode load interrupt\n");
  1305. il->isr_stats.tx++;
  1306. handled |= CSR_INT_BIT_FH_TX;
  1307. /* Wake up uCode load routine, now that load is complete */
  1308. il->ucode_write_complete = 1;
  1309. wake_up(&il->wait_command_queue);
  1310. }
  1311. if (inta & ~handled) {
  1312. IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1313. il->isr_stats.unhandled++;
  1314. }
  1315. if (inta & ~(il->inta_mask)) {
  1316. IL_WARN("Disabled INTA bits 0x%08x were pending\n",
  1317. inta & ~il->inta_mask);
  1318. IL_WARN(" with FH_INT = 0x%08x\n", inta_fh);
  1319. }
  1320. /* Re-enable all interrupts */
  1321. /* only Re-enable if disabled by irq */
  1322. if (test_bit(STATUS_INT_ENABLED, &il->status))
  1323. il_enable_interrupts(il);
  1324. /* Re-enable RF_KILL if it occurred */
  1325. else if (handled & CSR_INT_BIT_RF_KILL)
  1326. il_enable_rfkill_int(il);
  1327. #ifdef CONFIG_IWLEGACY_DEBUG
  1328. if (il_get_debug_level(il) & (IL_DL_ISR)) {
  1329. inta = _il_rd(il, CSR_INT);
  1330. inta_mask = _il_rd(il, CSR_INT_MASK);
  1331. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  1332. D_ISR(
  1333. "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1334. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1335. }
  1336. #endif
  1337. }
  1338. /*****************************************************************************
  1339. *
  1340. * sysfs attributes
  1341. *
  1342. *****************************************************************************/
  1343. #ifdef CONFIG_IWLEGACY_DEBUG
  1344. /*
  1345. * The following adds a new attribute to the sysfs representation
  1346. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1347. * used for controlling the debug level.
  1348. *
  1349. * See the level definitions in iwl for details.
  1350. *
  1351. * The debug_level being managed using sysfs below is a per device debug
  1352. * level that is used instead of the global debug level if it (the per
  1353. * device debug level) is set.
  1354. */
  1355. static ssize_t il4965_show_debug_level(struct device *d,
  1356. struct device_attribute *attr, char *buf)
  1357. {
  1358. struct il_priv *il = dev_get_drvdata(d);
  1359. return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
  1360. }
  1361. static ssize_t il4965_store_debug_level(struct device *d,
  1362. struct device_attribute *attr,
  1363. const char *buf, size_t count)
  1364. {
  1365. struct il_priv *il = dev_get_drvdata(d);
  1366. unsigned long val;
  1367. int ret;
  1368. ret = strict_strtoul(buf, 0, &val);
  1369. if (ret)
  1370. IL_ERR("%s is not in hex or decimal form.\n", buf);
  1371. else {
  1372. il->debug_level = val;
  1373. if (il_alloc_traffic_mem(il))
  1374. IL_ERR(
  1375. "Not enough memory to generate traffic log\n");
  1376. }
  1377. return strnlen(buf, count);
  1378. }
  1379. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1380. il4965_show_debug_level, il4965_store_debug_level);
  1381. #endif /* CONFIG_IWLEGACY_DEBUG */
  1382. static ssize_t il4965_show_temperature(struct device *d,
  1383. struct device_attribute *attr, char *buf)
  1384. {
  1385. struct il_priv *il = dev_get_drvdata(d);
  1386. if (!il_is_alive(il))
  1387. return -EAGAIN;
  1388. return sprintf(buf, "%d\n", il->temperature);
  1389. }
  1390. static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
  1391. static ssize_t il4965_show_tx_power(struct device *d,
  1392. struct device_attribute *attr, char *buf)
  1393. {
  1394. struct il_priv *il = dev_get_drvdata(d);
  1395. if (!il_is_ready_rf(il))
  1396. return sprintf(buf, "off\n");
  1397. else
  1398. return sprintf(buf, "%d\n", il->tx_power_user_lmt);
  1399. }
  1400. static ssize_t il4965_store_tx_power(struct device *d,
  1401. struct device_attribute *attr,
  1402. const char *buf, size_t count)
  1403. {
  1404. struct il_priv *il = dev_get_drvdata(d);
  1405. unsigned long val;
  1406. int ret;
  1407. ret = strict_strtoul(buf, 10, &val);
  1408. if (ret)
  1409. IL_INFO("%s is not in decimal form.\n", buf);
  1410. else {
  1411. ret = il_set_tx_power(il, val, false);
  1412. if (ret)
  1413. IL_ERR("failed setting tx power (0x%d).\n",
  1414. ret);
  1415. else
  1416. ret = count;
  1417. }
  1418. return ret;
  1419. }
  1420. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO,
  1421. il4965_show_tx_power, il4965_store_tx_power);
  1422. static struct attribute *il_sysfs_entries[] = {
  1423. &dev_attr_temperature.attr,
  1424. &dev_attr_tx_power.attr,
  1425. #ifdef CONFIG_IWLEGACY_DEBUG
  1426. &dev_attr_debug_level.attr,
  1427. #endif
  1428. NULL
  1429. };
  1430. static struct attribute_group il_attribute_group = {
  1431. .name = NULL, /* put in device directory */
  1432. .attrs = il_sysfs_entries,
  1433. };
  1434. /******************************************************************************
  1435. *
  1436. * uCode download functions
  1437. *
  1438. ******************************************************************************/
  1439. static void il4965_dealloc_ucode_pci(struct il_priv *il)
  1440. {
  1441. il_free_fw_desc(il->pci_dev, &il->ucode_code);
  1442. il_free_fw_desc(il->pci_dev, &il->ucode_data);
  1443. il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
  1444. il_free_fw_desc(il->pci_dev, &il->ucode_init);
  1445. il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
  1446. il_free_fw_desc(il->pci_dev, &il->ucode_boot);
  1447. }
  1448. static void il4965_nic_start(struct il_priv *il)
  1449. {
  1450. /* Remove all resets to allow NIC to operate */
  1451. _il_wr(il, CSR_RESET, 0);
  1452. }
  1453. static void il4965_ucode_callback(const struct firmware *ucode_raw,
  1454. void *context);
  1455. static int il4965_mac_setup_register(struct il_priv *il,
  1456. u32 max_probe_length);
  1457. static int __must_check il4965_request_firmware(struct il_priv *il, bool first)
  1458. {
  1459. const char *name_pre = il->cfg->fw_name_pre;
  1460. char tag[8];
  1461. if (first) {
  1462. il->fw_idx = il->cfg->ucode_api_max;
  1463. sprintf(tag, "%d", il->fw_idx);
  1464. } else {
  1465. il->fw_idx--;
  1466. sprintf(tag, "%d", il->fw_idx);
  1467. }
  1468. if (il->fw_idx < il->cfg->ucode_api_min) {
  1469. IL_ERR("no suitable firmware found!\n");
  1470. return -ENOENT;
  1471. }
  1472. sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
  1473. D_INFO("attempting to load firmware '%s'\n",
  1474. il->firmware_name);
  1475. return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
  1476. &il->pci_dev->dev, GFP_KERNEL, il,
  1477. il4965_ucode_callback);
  1478. }
  1479. struct il4965_firmware_pieces {
  1480. const void *inst, *data, *init, *init_data, *boot;
  1481. size_t inst_size, data_size, init_size, init_data_size, boot_size;
  1482. };
  1483. static int il4965_load_firmware(struct il_priv *il,
  1484. const struct firmware *ucode_raw,
  1485. struct il4965_firmware_pieces *pieces)
  1486. {
  1487. struct il_ucode_header *ucode = (void *)ucode_raw->data;
  1488. u32 api_ver, hdr_size;
  1489. const u8 *src;
  1490. il->ucode_ver = le32_to_cpu(ucode->ver);
  1491. api_ver = IL_UCODE_API(il->ucode_ver);
  1492. switch (api_ver) {
  1493. default:
  1494. case 0:
  1495. case 1:
  1496. case 2:
  1497. hdr_size = 24;
  1498. if (ucode_raw->size < hdr_size) {
  1499. IL_ERR("File size too small!\n");
  1500. return -EINVAL;
  1501. }
  1502. pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
  1503. pieces->data_size = le32_to_cpu(ucode->v1.data_size);
  1504. pieces->init_size = le32_to_cpu(ucode->v1.init_size);
  1505. pieces->init_data_size =
  1506. le32_to_cpu(ucode->v1.init_data_size);
  1507. pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
  1508. src = ucode->v1.data;
  1509. break;
  1510. }
  1511. /* Verify size of file vs. image size info in file's header */
  1512. if (ucode_raw->size != hdr_size + pieces->inst_size +
  1513. pieces->data_size + pieces->init_size +
  1514. pieces->init_data_size + pieces->boot_size) {
  1515. IL_ERR(
  1516. "uCode file size %d does not match expected size\n",
  1517. (int)ucode_raw->size);
  1518. return -EINVAL;
  1519. }
  1520. pieces->inst = src;
  1521. src += pieces->inst_size;
  1522. pieces->data = src;
  1523. src += pieces->data_size;
  1524. pieces->init = src;
  1525. src += pieces->init_size;
  1526. pieces->init_data = src;
  1527. src += pieces->init_data_size;
  1528. pieces->boot = src;
  1529. src += pieces->boot_size;
  1530. return 0;
  1531. }
  1532. /**
  1533. * il4965_ucode_callback - callback when firmware was loaded
  1534. *
  1535. * If loaded successfully, copies the firmware into buffers
  1536. * for the card to fetch (via DMA).
  1537. */
  1538. static void
  1539. il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
  1540. {
  1541. struct il_priv *il = context;
  1542. struct il_ucode_header *ucode;
  1543. int err;
  1544. struct il4965_firmware_pieces pieces;
  1545. const unsigned int api_max = il->cfg->ucode_api_max;
  1546. const unsigned int api_min = il->cfg->ucode_api_min;
  1547. u32 api_ver;
  1548. u32 max_probe_length = 200;
  1549. u32 standard_phy_calibration_size =
  1550. IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
  1551. memset(&pieces, 0, sizeof(pieces));
  1552. if (!ucode_raw) {
  1553. if (il->fw_idx <= il->cfg->ucode_api_max)
  1554. IL_ERR(
  1555. "request for firmware file '%s' failed.\n",
  1556. il->firmware_name);
  1557. goto try_again;
  1558. }
  1559. D_INFO("Loaded firmware file '%s' (%zd bytes).\n",
  1560. il->firmware_name, ucode_raw->size);
  1561. /* Make sure that we got at least the API version number */
  1562. if (ucode_raw->size < 4) {
  1563. IL_ERR("File size way too small!\n");
  1564. goto try_again;
  1565. }
  1566. /* Data from ucode file: header followed by uCode images */
  1567. ucode = (struct il_ucode_header *)ucode_raw->data;
  1568. err = il4965_load_firmware(il, ucode_raw, &pieces);
  1569. if (err)
  1570. goto try_again;
  1571. api_ver = IL_UCODE_API(il->ucode_ver);
  1572. /*
  1573. * api_ver should match the api version forming part of the
  1574. * firmware filename ... but we don't check for that and only rely
  1575. * on the API version read from firmware header from here on forward
  1576. */
  1577. if (api_ver < api_min || api_ver > api_max) {
  1578. IL_ERR(
  1579. "Driver unable to support your firmware API. "
  1580. "Driver supports v%u, firmware is v%u.\n",
  1581. api_max, api_ver);
  1582. goto try_again;
  1583. }
  1584. if (api_ver != api_max)
  1585. IL_ERR(
  1586. "Firmware has old API version. Expected v%u, "
  1587. "got v%u. New firmware can be obtained "
  1588. "from http://www.intellinuxwireless.org.\n",
  1589. api_max, api_ver);
  1590. IL_INFO("loaded firmware version %u.%u.%u.%u\n",
  1591. IL_UCODE_MAJOR(il->ucode_ver),
  1592. IL_UCODE_MINOR(il->ucode_ver),
  1593. IL_UCODE_API(il->ucode_ver),
  1594. IL_UCODE_SERIAL(il->ucode_ver));
  1595. snprintf(il->hw->wiphy->fw_version,
  1596. sizeof(il->hw->wiphy->fw_version),
  1597. "%u.%u.%u.%u",
  1598. IL_UCODE_MAJOR(il->ucode_ver),
  1599. IL_UCODE_MINOR(il->ucode_ver),
  1600. IL_UCODE_API(il->ucode_ver),
  1601. IL_UCODE_SERIAL(il->ucode_ver));
  1602. /*
  1603. * For any of the failures below (before allocating pci memory)
  1604. * we will try to load a version with a smaller API -- maybe the
  1605. * user just got a corrupted version of the latest API.
  1606. */
  1607. D_INFO("f/w package hdr ucode version raw = 0x%x\n",
  1608. il->ucode_ver);
  1609. D_INFO("f/w package hdr runtime inst size = %Zd\n",
  1610. pieces.inst_size);
  1611. D_INFO("f/w package hdr runtime data size = %Zd\n",
  1612. pieces.data_size);
  1613. D_INFO("f/w package hdr init inst size = %Zd\n",
  1614. pieces.init_size);
  1615. D_INFO("f/w package hdr init data size = %Zd\n",
  1616. pieces.init_data_size);
  1617. D_INFO("f/w package hdr boot inst size = %Zd\n",
  1618. pieces.boot_size);
  1619. /* Verify that uCode images will fit in card's SRAM */
  1620. if (pieces.inst_size > il->hw_params.max_inst_size) {
  1621. IL_ERR("uCode instr len %Zd too large to fit in\n",
  1622. pieces.inst_size);
  1623. goto try_again;
  1624. }
  1625. if (pieces.data_size > il->hw_params.max_data_size) {
  1626. IL_ERR("uCode data len %Zd too large to fit in\n",
  1627. pieces.data_size);
  1628. goto try_again;
  1629. }
  1630. if (pieces.init_size > il->hw_params.max_inst_size) {
  1631. IL_ERR("uCode init instr len %Zd too large to fit in\n",
  1632. pieces.init_size);
  1633. goto try_again;
  1634. }
  1635. if (pieces.init_data_size > il->hw_params.max_data_size) {
  1636. IL_ERR("uCode init data len %Zd too large to fit in\n",
  1637. pieces.init_data_size);
  1638. goto try_again;
  1639. }
  1640. if (pieces.boot_size > il->hw_params.max_bsm_size) {
  1641. IL_ERR("uCode boot instr len %Zd too large to fit in\n",
  1642. pieces.boot_size);
  1643. goto try_again;
  1644. }
  1645. /* Allocate ucode buffers for card's bus-master loading ... */
  1646. /* Runtime instructions and 2 copies of data:
  1647. * 1) unmodified from disk
  1648. * 2) backup cache for save/restore during power-downs */
  1649. il->ucode_code.len = pieces.inst_size;
  1650. il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
  1651. il->ucode_data.len = pieces.data_size;
  1652. il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
  1653. il->ucode_data_backup.len = pieces.data_size;
  1654. il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
  1655. if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
  1656. !il->ucode_data_backup.v_addr)
  1657. goto err_pci_alloc;
  1658. /* Initialization instructions and data */
  1659. if (pieces.init_size && pieces.init_data_size) {
  1660. il->ucode_init.len = pieces.init_size;
  1661. il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
  1662. il->ucode_init_data.len = pieces.init_data_size;
  1663. il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
  1664. if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
  1665. goto err_pci_alloc;
  1666. }
  1667. /* Bootstrap (instructions only, no data) */
  1668. if (pieces.boot_size) {
  1669. il->ucode_boot.len = pieces.boot_size;
  1670. il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
  1671. if (!il->ucode_boot.v_addr)
  1672. goto err_pci_alloc;
  1673. }
  1674. /* Now that we can no longer fail, copy information */
  1675. il->sta_key_max_num = STA_KEY_MAX_NUM;
  1676. /* Copy images into buffers for card's bus-master reads ... */
  1677. /* Runtime instructions (first block of data in file) */
  1678. D_INFO("Copying (but not loading) uCode instr len %Zd\n",
  1679. pieces.inst_size);
  1680. memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
  1681. D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1682. il->ucode_code.v_addr, (u32)il->ucode_code.p_addr);
  1683. /*
  1684. * Runtime data
  1685. * NOTE: Copy into backup buffer will be done in il_up()
  1686. */
  1687. D_INFO("Copying (but not loading) uCode data len %Zd\n",
  1688. pieces.data_size);
  1689. memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
  1690. memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
  1691. /* Initialization instructions */
  1692. if (pieces.init_size) {
  1693. D_INFO(
  1694. "Copying (but not loading) init instr len %Zd\n",
  1695. pieces.init_size);
  1696. memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
  1697. }
  1698. /* Initialization data */
  1699. if (pieces.init_data_size) {
  1700. D_INFO(
  1701. "Copying (but not loading) init data len %Zd\n",
  1702. pieces.init_data_size);
  1703. memcpy(il->ucode_init_data.v_addr, pieces.init_data,
  1704. pieces.init_data_size);
  1705. }
  1706. /* Bootstrap instructions */
  1707. D_INFO("Copying (but not loading) boot instr len %Zd\n",
  1708. pieces.boot_size);
  1709. memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
  1710. /*
  1711. * figure out the offset of chain noise reset and gain commands
  1712. * base on the size of standard phy calibration commands table size
  1713. */
  1714. il->_4965.phy_calib_chain_noise_reset_cmd =
  1715. standard_phy_calibration_size;
  1716. il->_4965.phy_calib_chain_noise_gain_cmd =
  1717. standard_phy_calibration_size + 1;
  1718. /**************************************************
  1719. * This is still part of probe() in a sense...
  1720. *
  1721. * 9. Setup and register with mac80211 and debugfs
  1722. **************************************************/
  1723. err = il4965_mac_setup_register(il, max_probe_length);
  1724. if (err)
  1725. goto out_unbind;
  1726. err = il_dbgfs_register(il, DRV_NAME);
  1727. if (err)
  1728. IL_ERR(
  1729. "failed to create debugfs files. Ignoring error: %d\n", err);
  1730. err = sysfs_create_group(&il->pci_dev->dev.kobj,
  1731. &il_attribute_group);
  1732. if (err) {
  1733. IL_ERR("failed to create sysfs device attributes\n");
  1734. goto out_unbind;
  1735. }
  1736. /* We have our copies now, allow OS release its copies */
  1737. release_firmware(ucode_raw);
  1738. complete(&il->_4965.firmware_loading_complete);
  1739. return;
  1740. try_again:
  1741. /* try next, if any */
  1742. if (il4965_request_firmware(il, false))
  1743. goto out_unbind;
  1744. release_firmware(ucode_raw);
  1745. return;
  1746. err_pci_alloc:
  1747. IL_ERR("failed to allocate pci memory\n");
  1748. il4965_dealloc_ucode_pci(il);
  1749. out_unbind:
  1750. complete(&il->_4965.firmware_loading_complete);
  1751. device_release_driver(&il->pci_dev->dev);
  1752. release_firmware(ucode_raw);
  1753. }
  1754. static const char * const desc_lookup_text[] = {
  1755. "OK",
  1756. "FAIL",
  1757. "BAD_PARAM",
  1758. "BAD_CHECKSUM",
  1759. "NMI_INTERRUPT_WDG",
  1760. "SYSASSERT",
  1761. "FATAL_ERROR",
  1762. "BAD_COMMAND",
  1763. "HW_ERROR_TUNE_LOCK",
  1764. "HW_ERROR_TEMPERATURE",
  1765. "ILLEGAL_CHAN_FREQ",
  1766. "VCC_NOT_STBL",
  1767. "FH_ERROR",
  1768. "NMI_INTERRUPT_HOST",
  1769. "NMI_INTERRUPT_ACTION_PT",
  1770. "NMI_INTERRUPT_UNKNOWN",
  1771. "UCODE_VERSION_MISMATCH",
  1772. "HW_ERROR_ABS_LOCK",
  1773. "HW_ERROR_CAL_LOCK_FAIL",
  1774. "NMI_INTERRUPT_INST_ACTION_PT",
  1775. "NMI_INTERRUPT_DATA_ACTION_PT",
  1776. "NMI_TRM_HW_ER",
  1777. "NMI_INTERRUPT_TRM",
  1778. "NMI_INTERRUPT_BREAK_POINT",
  1779. "DEBUG_0",
  1780. "DEBUG_1",
  1781. "DEBUG_2",
  1782. "DEBUG_3",
  1783. };
  1784. static struct { char *name; u8 num; } advanced_lookup[] = {
  1785. { "NMI_INTERRUPT_WDG", 0x34 },
  1786. { "SYSASSERT", 0x35 },
  1787. { "UCODE_VERSION_MISMATCH", 0x37 },
  1788. { "BAD_COMMAND", 0x38 },
  1789. { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
  1790. { "FATAL_ERROR", 0x3D },
  1791. { "NMI_TRM_HW_ERR", 0x46 },
  1792. { "NMI_INTERRUPT_TRM", 0x4C },
  1793. { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
  1794. { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
  1795. { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
  1796. { "NMI_INTERRUPT_HOST", 0x66 },
  1797. { "NMI_INTERRUPT_ACTION_PT", 0x7C },
  1798. { "NMI_INTERRUPT_UNKNOWN", 0x84 },
  1799. { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
  1800. { "ADVANCED_SYSASSERT", 0 },
  1801. };
  1802. static const char *il4965_desc_lookup(u32 num)
  1803. {
  1804. int i;
  1805. int max = ARRAY_SIZE(desc_lookup_text);
  1806. if (num < max)
  1807. return desc_lookup_text[num];
  1808. max = ARRAY_SIZE(advanced_lookup) - 1;
  1809. for (i = 0; i < max; i++) {
  1810. if (advanced_lookup[i].num == num)
  1811. break;
  1812. }
  1813. return advanced_lookup[i].name;
  1814. }
  1815. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1816. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1817. void il4965_dump_nic_error_log(struct il_priv *il)
  1818. {
  1819. u32 data2, line;
  1820. u32 desc, time, count, base, data1;
  1821. u32 blink1, blink2, ilink1, ilink2;
  1822. u32 pc, hcmd;
  1823. if (il->ucode_type == UCODE_INIT) {
  1824. base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
  1825. } else {
  1826. base = le32_to_cpu(il->card_alive.error_event_table_ptr);
  1827. }
  1828. if (!il->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1829. IL_ERR(
  1830. "Not valid error log pointer 0x%08X for %s uCode\n",
  1831. base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1832. return;
  1833. }
  1834. count = il_read_targ_mem(il, base);
  1835. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1836. IL_ERR("Start IWL Error Log Dump:\n");
  1837. IL_ERR("Status: 0x%08lX, count: %d\n",
  1838. il->status, count);
  1839. }
  1840. desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
  1841. il->isr_stats.err_code = desc;
  1842. pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
  1843. blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
  1844. blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
  1845. ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
  1846. ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
  1847. data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
  1848. data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
  1849. line = il_read_targ_mem(il, base + 9 * sizeof(u32));
  1850. time = il_read_targ_mem(il, base + 11 * sizeof(u32));
  1851. hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
  1852. IL_ERR("Desc Time "
  1853. "data1 data2 line\n");
  1854. IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
  1855. il4965_desc_lookup(desc), desc, time, data1, data2, line);
  1856. IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
  1857. IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
  1858. pc, blink1, blink2, ilink1, ilink2, hcmd);
  1859. }
  1860. static void il4965_rf_kill_ct_config(struct il_priv *il)
  1861. {
  1862. struct il_ct_kill_config cmd;
  1863. unsigned long flags;
  1864. int ret = 0;
  1865. spin_lock_irqsave(&il->lock, flags);
  1866. _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
  1867. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1868. spin_unlock_irqrestore(&il->lock, flags);
  1869. cmd.critical_temperature_R =
  1870. cpu_to_le32(il->hw_params.ct_kill_threshold);
  1871. ret = il_send_cmd_pdu(il, REPLY_CT_KILL_CONFIG_CMD,
  1872. sizeof(cmd), &cmd);
  1873. if (ret)
  1874. IL_ERR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  1875. else
  1876. D_INFO("REPLY_CT_KILL_CONFIG_CMD "
  1877. "succeeded, "
  1878. "critical temperature is %d\n",
  1879. il->hw_params.ct_kill_threshold);
  1880. }
  1881. static const s8 default_queue_to_tx_fifo[] = {
  1882. IL_TX_FIFO_VO,
  1883. IL_TX_FIFO_VI,
  1884. IL_TX_FIFO_BE,
  1885. IL_TX_FIFO_BK,
  1886. IL49_CMD_FIFO_NUM,
  1887. IL_TX_FIFO_UNUSED,
  1888. IL_TX_FIFO_UNUSED,
  1889. };
  1890. static int il4965_alive_notify(struct il_priv *il)
  1891. {
  1892. u32 a;
  1893. unsigned long flags;
  1894. int i, chan;
  1895. u32 reg_val;
  1896. spin_lock_irqsave(&il->lock, flags);
  1897. /* Clear 4965's internal Tx Scheduler data base */
  1898. il->scd_base_addr = il_rd_prph(il,
  1899. IL49_SCD_SRAM_BASE_ADDR);
  1900. a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
  1901. for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  1902. il_write_targ_mem(il, a, 0);
  1903. for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
  1904. il_write_targ_mem(il, a, 0);
  1905. for (; a < il->scd_base_addr +
  1906. IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num); a += 4)
  1907. il_write_targ_mem(il, a, 0);
  1908. /* Tel 4965 where to find Tx byte count tables */
  1909. il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR,
  1910. il->scd_bc_tbls.dma >> 10);
  1911. /* Enable DMA channel */
  1912. for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
  1913. il_wr(il,
  1914. FH_TCSR_CHNL_TX_CONFIG_REG(chan),
  1915. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  1916. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
  1917. /* Update FH chicken bits */
  1918. reg_val = il_rd(il, FH_TX_CHICKEN_BITS_REG);
  1919. il_wr(il, FH_TX_CHICKEN_BITS_REG,
  1920. reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
  1921. /* Disable chain mode for all queues */
  1922. il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
  1923. /* Initialize each Tx queue (including the command queue) */
  1924. for (i = 0; i < il->hw_params.max_txq_num; i++) {
  1925. /* TFD circular buffer read/write idxes */
  1926. il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
  1927. il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
  1928. /* Max Tx Window size for Scheduler-ACK mode */
  1929. il_write_targ_mem(il, il->scd_base_addr +
  1930. IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
  1931. (SCD_WIN_SIZE <<
  1932. IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  1933. IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  1934. /* Frame limit */
  1935. il_write_targ_mem(il, il->scd_base_addr +
  1936. IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
  1937. sizeof(u32),
  1938. (SCD_FRAME_LIMIT <<
  1939. IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  1940. IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  1941. }
  1942. il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
  1943. (1 << il->hw_params.max_txq_num) - 1);
  1944. /* Activate all Tx DMA/FIFO channels */
  1945. il4965_txq_set_sched(il, IL_MASK(0, 6));
  1946. il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
  1947. /* make sure all queue are not stopped */
  1948. memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
  1949. for (i = 0; i < 4; i++)
  1950. atomic_set(&il->queue_stop_count[i], 0);
  1951. /* reset to 0 to enable all the queue first */
  1952. il->txq_ctx_active_msk = 0;
  1953. /* Map each Tx/cmd queue to its corresponding fifo */
  1954. BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
  1955. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  1956. int ac = default_queue_to_tx_fifo[i];
  1957. il_txq_ctx_activate(il, i);
  1958. if (ac == IL_TX_FIFO_UNUSED)
  1959. continue;
  1960. il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
  1961. }
  1962. spin_unlock_irqrestore(&il->lock, flags);
  1963. return 0;
  1964. }
  1965. /**
  1966. * il4965_alive_start - called after REPLY_ALIVE notification received
  1967. * from protocol/runtime uCode (initialization uCode's
  1968. * Alive gets handled by il_init_alive_start()).
  1969. */
  1970. static void il4965_alive_start(struct il_priv *il)
  1971. {
  1972. int ret = 0;
  1973. struct il_rxon_context *ctx = &il->ctx;
  1974. D_INFO("Runtime Alive received.\n");
  1975. if (il->card_alive.is_valid != UCODE_VALID_OK) {
  1976. /* We had an error bringing up the hardware, so take it
  1977. * all the way back down so we can try again */
  1978. D_INFO("Alive failed.\n");
  1979. goto restart;
  1980. }
  1981. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1982. * This is a paranoid check, because we would not have gotten the
  1983. * "runtime" alive if code weren't properly loaded. */
  1984. if (il4965_verify_ucode(il)) {
  1985. /* Runtime instruction load was bad;
  1986. * take it all the way back down so we can try again */
  1987. D_INFO("Bad runtime uCode load.\n");
  1988. goto restart;
  1989. }
  1990. ret = il4965_alive_notify(il);
  1991. if (ret) {
  1992. IL_WARN(
  1993. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1994. goto restart;
  1995. }
  1996. /* After the ALIVE response, we can send host commands to the uCode */
  1997. set_bit(STATUS_ALIVE, &il->status);
  1998. /* Enable watchdog to monitor the driver tx queues */
  1999. il_setup_watchdog(il);
  2000. if (il_is_rfkill(il))
  2001. return;
  2002. ieee80211_wake_queues(il->hw);
  2003. il->active_rate = RATES_MASK;
  2004. if (il_is_associated_ctx(ctx)) {
  2005. struct il_rxon_cmd *active_rxon =
  2006. (struct il_rxon_cmd *)&ctx->active;
  2007. /* apply any changes in staging */
  2008. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2009. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2010. } else {
  2011. /* Initialize our rx_config data */
  2012. il_connection_init_rx_config(il, &il->ctx);
  2013. if (il->cfg->ops->hcmd->set_rxon_chain)
  2014. il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
  2015. }
  2016. /* Configure bluetooth coexistence if enabled */
  2017. il_send_bt_config(il);
  2018. il4965_reset_run_time_calib(il);
  2019. set_bit(STATUS_READY, &il->status);
  2020. /* Configure the adapter for unassociated operation */
  2021. il_commit_rxon(il, ctx);
  2022. /* At this point, the NIC is initialized and operational */
  2023. il4965_rf_kill_ct_config(il);
  2024. D_INFO("ALIVE processing complete.\n");
  2025. wake_up(&il->wait_command_queue);
  2026. il_power_update_mode(il, true);
  2027. D_INFO("Updated power mode\n");
  2028. return;
  2029. restart:
  2030. queue_work(il->workqueue, &il->restart);
  2031. }
  2032. static void il4965_cancel_deferred_work(struct il_priv *il);
  2033. static void __il4965_down(struct il_priv *il)
  2034. {
  2035. unsigned long flags;
  2036. int exit_pending;
  2037. D_INFO(DRV_NAME " is going down\n");
  2038. il_scan_cancel_timeout(il, 200);
  2039. exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &il->status);
  2040. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  2041. * to prevent rearm timer */
  2042. del_timer_sync(&il->watchdog);
  2043. il_clear_ucode_stations(il, NULL);
  2044. il_dealloc_bcast_stations(il);
  2045. il_clear_driver_stations(il);
  2046. /* Unblock any waiting calls */
  2047. wake_up_all(&il->wait_command_queue);
  2048. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2049. * exiting the module */
  2050. if (!exit_pending)
  2051. clear_bit(STATUS_EXIT_PENDING, &il->status);
  2052. /* stop and reset the on-board processor */
  2053. _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2054. /* tell the device to stop sending interrupts */
  2055. spin_lock_irqsave(&il->lock, flags);
  2056. il_disable_interrupts(il);
  2057. spin_unlock_irqrestore(&il->lock, flags);
  2058. il4965_synchronize_irq(il);
  2059. if (il->mac80211_registered)
  2060. ieee80211_stop_queues(il->hw);
  2061. /* If we have not previously called il_init() then
  2062. * clear all bits but the RF Kill bit and return */
  2063. if (!il_is_init(il)) {
  2064. il->status = test_bit(STATUS_RF_KILL_HW, &il->status) <<
  2065. STATUS_RF_KILL_HW |
  2066. test_bit(STATUS_GEO_CONFIGURED, &il->status) <<
  2067. STATUS_GEO_CONFIGURED |
  2068. test_bit(STATUS_EXIT_PENDING, &il->status) <<
  2069. STATUS_EXIT_PENDING;
  2070. goto exit;
  2071. }
  2072. /* ...otherwise clear out all the status bits but the RF Kill
  2073. * bit and continue taking the NIC down. */
  2074. il->status &= test_bit(STATUS_RF_KILL_HW, &il->status) <<
  2075. STATUS_RF_KILL_HW |
  2076. test_bit(STATUS_GEO_CONFIGURED, &il->status) <<
  2077. STATUS_GEO_CONFIGURED |
  2078. test_bit(STATUS_FW_ERROR, &il->status) <<
  2079. STATUS_FW_ERROR |
  2080. test_bit(STATUS_EXIT_PENDING, &il->status) <<
  2081. STATUS_EXIT_PENDING;
  2082. il4965_txq_ctx_stop(il);
  2083. il4965_rxq_stop(il);
  2084. /* Power-down device's busmaster DMA clocks */
  2085. il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2086. udelay(5);
  2087. /* Make sure (redundant) we've released our request to stay awake */
  2088. il_clear_bit(il, CSR_GP_CNTRL,
  2089. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2090. /* Stop the device, and put it in low power state */
  2091. il_apm_stop(il);
  2092. exit:
  2093. memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
  2094. dev_kfree_skb(il->beacon_skb);
  2095. il->beacon_skb = NULL;
  2096. /* clear out any free frames */
  2097. il4965_clear_free_frames(il);
  2098. }
  2099. static void il4965_down(struct il_priv *il)
  2100. {
  2101. mutex_lock(&il->mutex);
  2102. __il4965_down(il);
  2103. mutex_unlock(&il->mutex);
  2104. il4965_cancel_deferred_work(il);
  2105. }
  2106. #define HW_READY_TIMEOUT (50)
  2107. static int il4965_set_hw_ready(struct il_priv *il)
  2108. {
  2109. int ret = 0;
  2110. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  2111. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  2112. /* See if we got it */
  2113. ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
  2114. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2115. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2116. HW_READY_TIMEOUT);
  2117. if (ret != -ETIMEDOUT)
  2118. il->hw_ready = true;
  2119. else
  2120. il->hw_ready = false;
  2121. D_INFO("hardware %s\n",
  2122. (il->hw_ready == 1) ? "ready" : "not ready");
  2123. return ret;
  2124. }
  2125. static int il4965_prepare_card_hw(struct il_priv *il)
  2126. {
  2127. int ret = 0;
  2128. D_INFO("il4965_prepare_card_hw enter\n");
  2129. ret = il4965_set_hw_ready(il);
  2130. if (il->hw_ready)
  2131. return ret;
  2132. /* If HW is not ready, prepare the conditions to check again */
  2133. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  2134. CSR_HW_IF_CONFIG_REG_PREPARE);
  2135. ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
  2136. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  2137. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  2138. /* HW should be ready by now, check again. */
  2139. if (ret != -ETIMEDOUT)
  2140. il4965_set_hw_ready(il);
  2141. return ret;
  2142. }
  2143. #define MAX_HW_RESTARTS 5
  2144. static int __il4965_up(struct il_priv *il)
  2145. {
  2146. int i;
  2147. int ret;
  2148. if (test_bit(STATUS_EXIT_PENDING, &il->status)) {
  2149. IL_WARN("Exit pending; will not bring the NIC up\n");
  2150. return -EIO;
  2151. }
  2152. if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
  2153. IL_ERR("ucode not available for device bringup\n");
  2154. return -EIO;
  2155. }
  2156. ret = il4965_alloc_bcast_station(il, &il->ctx);
  2157. if (ret) {
  2158. il_dealloc_bcast_stations(il);
  2159. return ret;
  2160. }
  2161. il4965_prepare_card_hw(il);
  2162. if (!il->hw_ready) {
  2163. IL_WARN("Exit HW not ready\n");
  2164. return -EIO;
  2165. }
  2166. /* If platform's RF_KILL switch is NOT set to KILL */
  2167. if (_il_rd(il,
  2168. CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2169. clear_bit(STATUS_RF_KILL_HW, &il->status);
  2170. else
  2171. set_bit(STATUS_RF_KILL_HW, &il->status);
  2172. if (il_is_rfkill(il)) {
  2173. wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
  2174. il_enable_interrupts(il);
  2175. IL_WARN("Radio disabled by HW RF Kill switch\n");
  2176. return 0;
  2177. }
  2178. _il_wr(il, CSR_INT, 0xFFFFFFFF);
  2179. /* must be initialised before il_hw_nic_init */
  2180. il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
  2181. ret = il4965_hw_nic_init(il);
  2182. if (ret) {
  2183. IL_ERR("Unable to init nic\n");
  2184. return ret;
  2185. }
  2186. /* make sure rfkill handshake bits are cleared */
  2187. _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2188. _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
  2189. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2190. /* clear (again), then enable host interrupts */
  2191. _il_wr(il, CSR_INT, 0xFFFFFFFF);
  2192. il_enable_interrupts(il);
  2193. /* really make sure rfkill handshake bits are cleared */
  2194. _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2195. _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2196. /* Copy original ucode data image from disk into backup cache.
  2197. * This will be used to initialize the on-board processor's
  2198. * data SRAM for a clean start when the runtime program first loads. */
  2199. memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
  2200. il->ucode_data.len);
  2201. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2202. /* load bootstrap state machine,
  2203. * load bootstrap program into processor's memory,
  2204. * prepare to load the "initialize" uCode */
  2205. ret = il->cfg->ops->lib->load_ucode(il);
  2206. if (ret) {
  2207. IL_ERR("Unable to set up bootstrap uCode: %d\n",
  2208. ret);
  2209. continue;
  2210. }
  2211. /* start card; "initialize" will load runtime ucode */
  2212. il4965_nic_start(il);
  2213. D_INFO(DRV_NAME " is coming up\n");
  2214. return 0;
  2215. }
  2216. set_bit(STATUS_EXIT_PENDING, &il->status);
  2217. __il4965_down(il);
  2218. clear_bit(STATUS_EXIT_PENDING, &il->status);
  2219. /* tried to restart and config the device for as long as our
  2220. * patience could withstand */
  2221. IL_ERR("Unable to initialize device after %d attempts.\n", i);
  2222. return -EIO;
  2223. }
  2224. /*****************************************************************************
  2225. *
  2226. * Workqueue callbacks
  2227. *
  2228. *****************************************************************************/
  2229. static void il4965_bg_init_alive_start(struct work_struct *data)
  2230. {
  2231. struct il_priv *il =
  2232. container_of(data, struct il_priv, init_alive_start.work);
  2233. mutex_lock(&il->mutex);
  2234. if (test_bit(STATUS_EXIT_PENDING, &il->status))
  2235. goto out;
  2236. il->cfg->ops->lib->init_alive_start(il);
  2237. out:
  2238. mutex_unlock(&il->mutex);
  2239. }
  2240. static void il4965_bg_alive_start(struct work_struct *data)
  2241. {
  2242. struct il_priv *il =
  2243. container_of(data, struct il_priv, alive_start.work);
  2244. mutex_lock(&il->mutex);
  2245. if (test_bit(STATUS_EXIT_PENDING, &il->status))
  2246. goto out;
  2247. il4965_alive_start(il);
  2248. out:
  2249. mutex_unlock(&il->mutex);
  2250. }
  2251. static void il4965_bg_run_time_calib_work(struct work_struct *work)
  2252. {
  2253. struct il_priv *il = container_of(work, struct il_priv,
  2254. run_time_calib_work);
  2255. mutex_lock(&il->mutex);
  2256. if (test_bit(STATUS_EXIT_PENDING, &il->status) ||
  2257. test_bit(STATUS_SCANNING, &il->status)) {
  2258. mutex_unlock(&il->mutex);
  2259. return;
  2260. }
  2261. if (il->start_calib) {
  2262. il4965_chain_noise_calibration(il,
  2263. (void *)&il->_4965.stats);
  2264. il4965_sensitivity_calibration(il,
  2265. (void *)&il->_4965.stats);
  2266. }
  2267. mutex_unlock(&il->mutex);
  2268. }
  2269. static void il4965_bg_restart(struct work_struct *data)
  2270. {
  2271. struct il_priv *il = container_of(data, struct il_priv, restart);
  2272. if (test_bit(STATUS_EXIT_PENDING, &il->status))
  2273. return;
  2274. if (test_and_clear_bit(STATUS_FW_ERROR, &il->status)) {
  2275. mutex_lock(&il->mutex);
  2276. il->ctx.vif = NULL;
  2277. il->is_open = 0;
  2278. __il4965_down(il);
  2279. mutex_unlock(&il->mutex);
  2280. il4965_cancel_deferred_work(il);
  2281. ieee80211_restart_hw(il->hw);
  2282. } else {
  2283. il4965_down(il);
  2284. mutex_lock(&il->mutex);
  2285. if (test_bit(STATUS_EXIT_PENDING, &il->status)) {
  2286. mutex_unlock(&il->mutex);
  2287. return;
  2288. }
  2289. __il4965_up(il);
  2290. mutex_unlock(&il->mutex);
  2291. }
  2292. }
  2293. static void il4965_bg_rx_replenish(struct work_struct *data)
  2294. {
  2295. struct il_priv *il =
  2296. container_of(data, struct il_priv, rx_replenish);
  2297. if (test_bit(STATUS_EXIT_PENDING, &il->status))
  2298. return;
  2299. mutex_lock(&il->mutex);
  2300. il4965_rx_replenish(il);
  2301. mutex_unlock(&il->mutex);
  2302. }
  2303. /*****************************************************************************
  2304. *
  2305. * mac80211 entry point functions
  2306. *
  2307. *****************************************************************************/
  2308. #define UCODE_READY_TIMEOUT (4 * HZ)
  2309. /*
  2310. * Not a mac80211 entry point function, but it fits in with all the
  2311. * other mac80211 functions grouped here.
  2312. */
  2313. static int il4965_mac_setup_register(struct il_priv *il,
  2314. u32 max_probe_length)
  2315. {
  2316. int ret;
  2317. struct ieee80211_hw *hw = il->hw;
  2318. hw->rate_control_algorithm = "iwl-4965-rs";
  2319. /* Tell mac80211 our characteristics */
  2320. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2321. IEEE80211_HW_AMPDU_AGGREGATION |
  2322. IEEE80211_HW_NEED_DTIM_PERIOD |
  2323. IEEE80211_HW_SPECTRUM_MGMT |
  2324. IEEE80211_HW_REPORTS_TX_ACK_STATUS;
  2325. if (il->cfg->sku & IL_SKU_N)
  2326. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2327. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2328. hw->sta_data_size = sizeof(struct il_station_priv);
  2329. hw->vif_data_size = sizeof(struct il_vif_priv);
  2330. hw->wiphy->interface_modes |= il->ctx.interface_modes;
  2331. hw->wiphy->interface_modes |= il->ctx.exclusive_interface_modes;
  2332. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2333. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2334. /*
  2335. * For now, disable PS by default because it affects
  2336. * RX performance significantly.
  2337. */
  2338. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2339. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2340. /* we create the 802.11 header and a zero-length SSID element */
  2341. hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
  2342. /* Default value; 4 EDCA QOS priorities */
  2343. hw->queues = 4;
  2344. hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
  2345. if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
  2346. il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2347. &il->bands[IEEE80211_BAND_2GHZ];
  2348. if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
  2349. il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2350. &il->bands[IEEE80211_BAND_5GHZ];
  2351. il_leds_init(il);
  2352. ret = ieee80211_register_hw(il->hw);
  2353. if (ret) {
  2354. IL_ERR("Failed to register hw (error %d)\n", ret);
  2355. return ret;
  2356. }
  2357. il->mac80211_registered = 1;
  2358. return 0;
  2359. }
  2360. int il4965_mac_start(struct ieee80211_hw *hw)
  2361. {
  2362. struct il_priv *il = hw->priv;
  2363. int ret;
  2364. D_MAC80211("enter\n");
  2365. /* we should be verifying the device is ready to be opened */
  2366. mutex_lock(&il->mutex);
  2367. ret = __il4965_up(il);
  2368. mutex_unlock(&il->mutex);
  2369. if (ret)
  2370. return ret;
  2371. if (il_is_rfkill(il))
  2372. goto out;
  2373. D_INFO("Start UP work done.\n");
  2374. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2375. * mac80211 will not be run successfully. */
  2376. ret = wait_event_timeout(il->wait_command_queue,
  2377. test_bit(STATUS_READY, &il->status),
  2378. UCODE_READY_TIMEOUT);
  2379. if (!ret) {
  2380. if (!test_bit(STATUS_READY, &il->status)) {
  2381. IL_ERR("START_ALIVE timeout after %dms.\n",
  2382. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2383. return -ETIMEDOUT;
  2384. }
  2385. }
  2386. il4965_led_enable(il);
  2387. out:
  2388. il->is_open = 1;
  2389. D_MAC80211("leave\n");
  2390. return 0;
  2391. }
  2392. void il4965_mac_stop(struct ieee80211_hw *hw)
  2393. {
  2394. struct il_priv *il = hw->priv;
  2395. D_MAC80211("enter\n");
  2396. if (!il->is_open)
  2397. return;
  2398. il->is_open = 0;
  2399. il4965_down(il);
  2400. flush_workqueue(il->workqueue);
  2401. /* User space software may expect getting rfkill changes
  2402. * even if interface is down */
  2403. _il_wr(il, CSR_INT, 0xFFFFFFFF);
  2404. il_enable_rfkill_int(il);
  2405. D_MAC80211("leave\n");
  2406. }
  2407. void il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2408. {
  2409. struct il_priv *il = hw->priv;
  2410. D_MACDUMP("enter\n");
  2411. D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2412. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2413. if (il4965_tx_skb(il, skb))
  2414. dev_kfree_skb_any(skb);
  2415. D_MACDUMP("leave\n");
  2416. }
  2417. void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
  2418. struct ieee80211_vif *vif,
  2419. struct ieee80211_key_conf *keyconf,
  2420. struct ieee80211_sta *sta,
  2421. u32 iv32, u16 *phase1key)
  2422. {
  2423. struct il_priv *il = hw->priv;
  2424. struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
  2425. D_MAC80211("enter\n");
  2426. il4965_update_tkip_key(il, vif_priv->ctx, keyconf, sta,
  2427. iv32, phase1key);
  2428. D_MAC80211("leave\n");
  2429. }
  2430. int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2431. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  2432. struct ieee80211_key_conf *key)
  2433. {
  2434. struct il_priv *il = hw->priv;
  2435. struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
  2436. struct il_rxon_context *ctx = vif_priv->ctx;
  2437. int ret;
  2438. u8 sta_id;
  2439. bool is_default_wep_key = false;
  2440. D_MAC80211("enter\n");
  2441. if (il->cfg->mod_params->sw_crypto) {
  2442. D_MAC80211("leave - hwcrypto disabled\n");
  2443. return -EOPNOTSUPP;
  2444. }
  2445. sta_id = il_sta_id_or_broadcast(il, vif_priv->ctx, sta);
  2446. if (sta_id == IL_INVALID_STATION)
  2447. return -EINVAL;
  2448. mutex_lock(&il->mutex);
  2449. il_scan_cancel_timeout(il, 100);
  2450. /*
  2451. * If we are getting WEP group key and we didn't receive any key mapping
  2452. * so far, we are in legacy wep mode (group key only), otherwise we are
  2453. * in 1X mode.
  2454. * In legacy wep mode, we use another host command to the uCode.
  2455. */
  2456. if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  2457. key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
  2458. !sta) {
  2459. if (cmd == SET_KEY)
  2460. is_default_wep_key = !ctx->key_mapping_keys;
  2461. else
  2462. is_default_wep_key =
  2463. (key->hw_key_idx == HW_KEY_DEFAULT);
  2464. }
  2465. switch (cmd) {
  2466. case SET_KEY:
  2467. if (is_default_wep_key)
  2468. ret = il4965_set_default_wep_key(il,
  2469. vif_priv->ctx, key);
  2470. else
  2471. ret = il4965_set_dynamic_key(il, vif_priv->ctx,
  2472. key, sta_id);
  2473. D_MAC80211("enable hwcrypto key\n");
  2474. break;
  2475. case DISABLE_KEY:
  2476. if (is_default_wep_key)
  2477. ret = il4965_remove_default_wep_key(il, ctx, key);
  2478. else
  2479. ret = il4965_remove_dynamic_key(il, ctx,
  2480. key, sta_id);
  2481. D_MAC80211("disable hwcrypto key\n");
  2482. break;
  2483. default:
  2484. ret = -EINVAL;
  2485. }
  2486. mutex_unlock(&il->mutex);
  2487. D_MAC80211("leave\n");
  2488. return ret;
  2489. }
  2490. int il4965_mac_ampdu_action(struct ieee80211_hw *hw,
  2491. struct ieee80211_vif *vif,
  2492. enum ieee80211_ampdu_mlme_action action,
  2493. struct ieee80211_sta *sta, u16 tid, u16 *ssn,
  2494. u8 buf_size)
  2495. {
  2496. struct il_priv *il = hw->priv;
  2497. int ret = -EINVAL;
  2498. D_HT("A-MPDU action on addr %pM tid %d\n",
  2499. sta->addr, tid);
  2500. if (!(il->cfg->sku & IL_SKU_N))
  2501. return -EACCES;
  2502. mutex_lock(&il->mutex);
  2503. switch (action) {
  2504. case IEEE80211_AMPDU_RX_START:
  2505. D_HT("start Rx\n");
  2506. ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
  2507. break;
  2508. case IEEE80211_AMPDU_RX_STOP:
  2509. D_HT("stop Rx\n");
  2510. ret = il4965_sta_rx_agg_stop(il, sta, tid);
  2511. if (test_bit(STATUS_EXIT_PENDING, &il->status))
  2512. ret = 0;
  2513. break;
  2514. case IEEE80211_AMPDU_TX_START:
  2515. D_HT("start Tx\n");
  2516. ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
  2517. break;
  2518. case IEEE80211_AMPDU_TX_STOP:
  2519. D_HT("stop Tx\n");
  2520. ret = il4965_tx_agg_stop(il, vif, sta, tid);
  2521. if (test_bit(STATUS_EXIT_PENDING, &il->status))
  2522. ret = 0;
  2523. break;
  2524. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2525. ret = 0;
  2526. break;
  2527. }
  2528. mutex_unlock(&il->mutex);
  2529. return ret;
  2530. }
  2531. int il4965_mac_sta_add(struct ieee80211_hw *hw,
  2532. struct ieee80211_vif *vif,
  2533. struct ieee80211_sta *sta)
  2534. {
  2535. struct il_priv *il = hw->priv;
  2536. struct il_station_priv *sta_priv = (void *)sta->drv_priv;
  2537. struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
  2538. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2539. int ret;
  2540. u8 sta_id;
  2541. D_INFO("received request to add station %pM\n",
  2542. sta->addr);
  2543. mutex_lock(&il->mutex);
  2544. D_INFO("proceeding to add station %pM\n",
  2545. sta->addr);
  2546. sta_priv->common.sta_id = IL_INVALID_STATION;
  2547. atomic_set(&sta_priv->pending_frames, 0);
  2548. ret = il_add_station_common(il, vif_priv->ctx, sta->addr,
  2549. is_ap, sta, &sta_id);
  2550. if (ret) {
  2551. IL_ERR("Unable to add station %pM (%d)\n",
  2552. sta->addr, ret);
  2553. /* Should we return success if return code is EEXIST ? */
  2554. mutex_unlock(&il->mutex);
  2555. return ret;
  2556. }
  2557. sta_priv->common.sta_id = sta_id;
  2558. /* Initialize rate scaling */
  2559. D_INFO("Initializing rate scaling for station %pM\n",
  2560. sta->addr);
  2561. il4965_rs_rate_init(il, sta, sta_id);
  2562. mutex_unlock(&il->mutex);
  2563. return 0;
  2564. }
  2565. void il4965_mac_channel_switch(struct ieee80211_hw *hw,
  2566. struct ieee80211_channel_switch *ch_switch)
  2567. {
  2568. struct il_priv *il = hw->priv;
  2569. const struct il_channel_info *ch_info;
  2570. struct ieee80211_conf *conf = &hw->conf;
  2571. struct ieee80211_channel *channel = ch_switch->channel;
  2572. struct il_ht_config *ht_conf = &il->current_ht_config;
  2573. struct il_rxon_context *ctx = &il->ctx;
  2574. u16 ch;
  2575. D_MAC80211("enter\n");
  2576. mutex_lock(&il->mutex);
  2577. if (il_is_rfkill(il))
  2578. goto out;
  2579. if (test_bit(STATUS_EXIT_PENDING, &il->status) ||
  2580. test_bit(STATUS_SCANNING, &il->status) ||
  2581. test_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status))
  2582. goto out;
  2583. if (!il_is_associated_ctx(ctx))
  2584. goto out;
  2585. if (!il->cfg->ops->lib->set_channel_switch)
  2586. goto out;
  2587. ch = channel->hw_value;
  2588. if (le16_to_cpu(ctx->active.channel) == ch)
  2589. goto out;
  2590. ch_info = il_get_channel_info(il, channel->band, ch);
  2591. if (!il_is_channel_valid(ch_info)) {
  2592. D_MAC80211("invalid channel\n");
  2593. goto out;
  2594. }
  2595. spin_lock_irq(&il->lock);
  2596. il->current_ht_config.smps = conf->smps_mode;
  2597. /* Configure HT40 channels */
  2598. ctx->ht.enabled = conf_is_ht(conf);
  2599. if (ctx->ht.enabled) {
  2600. if (conf_is_ht40_minus(conf)) {
  2601. ctx->ht.extension_chan_offset =
  2602. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2603. ctx->ht.is_40mhz = true;
  2604. } else if (conf_is_ht40_plus(conf)) {
  2605. ctx->ht.extension_chan_offset =
  2606. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2607. ctx->ht.is_40mhz = true;
  2608. } else {
  2609. ctx->ht.extension_chan_offset =
  2610. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2611. ctx->ht.is_40mhz = false;
  2612. }
  2613. } else
  2614. ctx->ht.is_40mhz = false;
  2615. if ((le16_to_cpu(ctx->staging.channel) != ch))
  2616. ctx->staging.flags = 0;
  2617. il_set_rxon_channel(il, channel, ctx);
  2618. il_set_rxon_ht(il, ht_conf);
  2619. il_set_flags_for_band(il, ctx, channel->band, ctx->vif);
  2620. spin_unlock_irq(&il->lock);
  2621. il_set_rate(il);
  2622. /*
  2623. * at this point, staging_rxon has the
  2624. * configuration for channel switch
  2625. */
  2626. set_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status);
  2627. il->switch_channel = cpu_to_le16(ch);
  2628. if (il->cfg->ops->lib->set_channel_switch(il, ch_switch)) {
  2629. clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status);
  2630. il->switch_channel = 0;
  2631. ieee80211_chswitch_done(ctx->vif, false);
  2632. }
  2633. out:
  2634. mutex_unlock(&il->mutex);
  2635. D_MAC80211("leave\n");
  2636. }
  2637. void il4965_configure_filter(struct ieee80211_hw *hw,
  2638. unsigned int changed_flags,
  2639. unsigned int *total_flags,
  2640. u64 multicast)
  2641. {
  2642. struct il_priv *il = hw->priv;
  2643. __le32 filter_or = 0, filter_nand = 0;
  2644. #define CHK(test, flag) do { \
  2645. if (*total_flags & (test)) \
  2646. filter_or |= (flag); \
  2647. else \
  2648. filter_nand |= (flag); \
  2649. } while (0)
  2650. D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  2651. changed_flags, *total_flags);
  2652. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2653. /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
  2654. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
  2655. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2656. #undef CHK
  2657. mutex_lock(&il->mutex);
  2658. il->ctx.staging.filter_flags &= ~filter_nand;
  2659. il->ctx.staging.filter_flags |= filter_or;
  2660. /*
  2661. * Not committing directly because hardware can perform a scan,
  2662. * but we'll eventually commit the filter flags change anyway.
  2663. */
  2664. mutex_unlock(&il->mutex);
  2665. /*
  2666. * Receiving all multicast frames is always enabled by the
  2667. * default flags setup in il_connection_init_rx_config()
  2668. * since we currently do not support programming multicast
  2669. * filters into the device.
  2670. */
  2671. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2672. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2673. }
  2674. /*****************************************************************************
  2675. *
  2676. * driver setup and teardown
  2677. *
  2678. *****************************************************************************/
  2679. static void il4965_bg_txpower_work(struct work_struct *work)
  2680. {
  2681. struct il_priv *il = container_of(work, struct il_priv,
  2682. txpower_work);
  2683. mutex_lock(&il->mutex);
  2684. /* If a scan happened to start before we got here
  2685. * then just return; the stats notification will
  2686. * kick off another scheduled work to compensate for
  2687. * any temperature delta we missed here. */
  2688. if (test_bit(STATUS_EXIT_PENDING, &il->status) ||
  2689. test_bit(STATUS_SCANNING, &il->status))
  2690. goto out;
  2691. /* Regardless of if we are associated, we must reconfigure the
  2692. * TX power since frames can be sent on non-radar channels while
  2693. * not associated */
  2694. il->cfg->ops->lib->send_tx_power(il);
  2695. /* Update last_temperature to keep is_calib_needed from running
  2696. * when it isn't needed... */
  2697. il->last_temperature = il->temperature;
  2698. out:
  2699. mutex_unlock(&il->mutex);
  2700. }
  2701. static void il4965_setup_deferred_work(struct il_priv *il)
  2702. {
  2703. il->workqueue = create_singlethread_workqueue(DRV_NAME);
  2704. init_waitqueue_head(&il->wait_command_queue);
  2705. INIT_WORK(&il->restart, il4965_bg_restart);
  2706. INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
  2707. INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
  2708. INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
  2709. INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
  2710. il_setup_scan_deferred_work(il);
  2711. INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
  2712. init_timer(&il->stats_periodic);
  2713. il->stats_periodic.data = (unsigned long)il;
  2714. il->stats_periodic.function = il4965_bg_stats_periodic;
  2715. init_timer(&il->watchdog);
  2716. il->watchdog.data = (unsigned long)il;
  2717. il->watchdog.function = il_bg_watchdog;
  2718. tasklet_init(&il->irq_tasklet, (void (*)(unsigned long))
  2719. il4965_irq_tasklet, (unsigned long)il);
  2720. }
  2721. static void il4965_cancel_deferred_work(struct il_priv *il)
  2722. {
  2723. cancel_work_sync(&il->txpower_work);
  2724. cancel_delayed_work_sync(&il->init_alive_start);
  2725. cancel_delayed_work(&il->alive_start);
  2726. cancel_work_sync(&il->run_time_calib_work);
  2727. il_cancel_scan_deferred_work(il);
  2728. del_timer_sync(&il->stats_periodic);
  2729. }
  2730. static void il4965_init_hw_rates(struct il_priv *il,
  2731. struct ieee80211_rate *rates)
  2732. {
  2733. int i;
  2734. for (i = 0; i < RATE_COUNT_LEGACY; i++) {
  2735. rates[i].bitrate = il_rates[i].ieee * 5;
  2736. rates[i].hw_value = i; /* Rate scaling will work on idxes */
  2737. rates[i].hw_value_short = i;
  2738. rates[i].flags = 0;
  2739. if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
  2740. /*
  2741. * If CCK != 1M then set short preamble rate flag.
  2742. */
  2743. rates[i].flags |=
  2744. (il_rates[i].plcp == RATE_1M_PLCP) ?
  2745. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2746. }
  2747. }
  2748. }
  2749. /*
  2750. * Acquire il->lock before calling this function !
  2751. */
  2752. void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
  2753. {
  2754. il_wr(il, HBUS_TARG_WRPTR,
  2755. (idx & 0xff) | (txq_id << 8));
  2756. il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
  2757. }
  2758. void il4965_tx_queue_set_status(struct il_priv *il,
  2759. struct il_tx_queue *txq,
  2760. int tx_fifo_id, int scd_retry)
  2761. {
  2762. int txq_id = txq->q.id;
  2763. /* Find out whether to activate Tx queue */
  2764. int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
  2765. /* Set up and activate */
  2766. il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
  2767. (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  2768. (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
  2769. (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
  2770. (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  2771. IL49_SCD_QUEUE_STTS_REG_MSK);
  2772. txq->sched_retry = scd_retry;
  2773. D_INFO("%s %s Queue %d on AC %d\n",
  2774. active ? "Activate" : "Deactivate",
  2775. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  2776. }
  2777. static int il4965_init_drv(struct il_priv *il)
  2778. {
  2779. int ret;
  2780. spin_lock_init(&il->sta_lock);
  2781. spin_lock_init(&il->hcmd_lock);
  2782. INIT_LIST_HEAD(&il->free_frames);
  2783. mutex_init(&il->mutex);
  2784. il->ieee_channels = NULL;
  2785. il->ieee_rates = NULL;
  2786. il->band = IEEE80211_BAND_2GHZ;
  2787. il->iw_mode = NL80211_IFTYPE_STATION;
  2788. il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2789. il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
  2790. /* initialize force reset */
  2791. il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
  2792. /* Choose which receivers/antennas to use */
  2793. if (il->cfg->ops->hcmd->set_rxon_chain)
  2794. il->cfg->ops->hcmd->set_rxon_chain(il,
  2795. &il->ctx);
  2796. il_init_scan_params(il);
  2797. ret = il_init_channel_map(il);
  2798. if (ret) {
  2799. IL_ERR("initializing regulatory failed: %d\n", ret);
  2800. goto err;
  2801. }
  2802. ret = il_init_geos(il);
  2803. if (ret) {
  2804. IL_ERR("initializing geos failed: %d\n", ret);
  2805. goto err_free_channel_map;
  2806. }
  2807. il4965_init_hw_rates(il, il->ieee_rates);
  2808. return 0;
  2809. err_free_channel_map:
  2810. il_free_channel_map(il);
  2811. err:
  2812. return ret;
  2813. }
  2814. static void il4965_uninit_drv(struct il_priv *il)
  2815. {
  2816. il4965_calib_free_results(il);
  2817. il_free_geos(il);
  2818. il_free_channel_map(il);
  2819. kfree(il->scan_cmd);
  2820. }
  2821. static void il4965_hw_detect(struct il_priv *il)
  2822. {
  2823. il->hw_rev = _il_rd(il, CSR_HW_REV);
  2824. il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
  2825. il->rev_id = il->pci_dev->revision;
  2826. D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
  2827. }
  2828. static int il4965_set_hw_params(struct il_priv *il)
  2829. {
  2830. il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  2831. il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  2832. if (il->cfg->mod_params->amsdu_size_8K)
  2833. il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
  2834. else
  2835. il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
  2836. il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
  2837. if (il->cfg->mod_params->disable_11n)
  2838. il->cfg->sku &= ~IL_SKU_N;
  2839. /* Device-specific setup */
  2840. return il->cfg->ops->lib->set_hw_params(il);
  2841. }
  2842. static const u8 il4965_bss_ac_to_fifo[] = {
  2843. IL_TX_FIFO_VO,
  2844. IL_TX_FIFO_VI,
  2845. IL_TX_FIFO_BE,
  2846. IL_TX_FIFO_BK,
  2847. };
  2848. static const u8 il4965_bss_ac_to_queue[] = {
  2849. 0, 1, 2, 3,
  2850. };
  2851. static int
  2852. il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2853. {
  2854. int err = 0;
  2855. struct il_priv *il;
  2856. struct ieee80211_hw *hw;
  2857. struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
  2858. unsigned long flags;
  2859. u16 pci_cmd;
  2860. /************************
  2861. * 1. Allocating HW data
  2862. ************************/
  2863. hw = il_alloc_all(cfg);
  2864. if (!hw) {
  2865. err = -ENOMEM;
  2866. goto out;
  2867. }
  2868. il = hw->priv;
  2869. /* At this point both hw and il are allocated. */
  2870. il->ctx.ctxid = 0;
  2871. il->ctx.always_active = true;
  2872. il->ctx.is_active = true;
  2873. il->ctx.rxon_cmd = REPLY_RXON;
  2874. il->ctx.rxon_timing_cmd = REPLY_RXON_TIMING;
  2875. il->ctx.rxon_assoc_cmd = REPLY_RXON_ASSOC;
  2876. il->ctx.qos_cmd = REPLY_QOS_PARAM;
  2877. il->ctx.ap_sta_id = IL_AP_ID;
  2878. il->ctx.wep_key_cmd = REPLY_WEPKEY;
  2879. il->ctx.ac_to_fifo = il4965_bss_ac_to_fifo;
  2880. il->ctx.ac_to_queue = il4965_bss_ac_to_queue;
  2881. il->ctx.exclusive_interface_modes =
  2882. BIT(NL80211_IFTYPE_ADHOC);
  2883. il->ctx.interface_modes =
  2884. BIT(NL80211_IFTYPE_STATION);
  2885. il->ctx.ap_devtype = RXON_DEV_TYPE_AP;
  2886. il->ctx.ibss_devtype = RXON_DEV_TYPE_IBSS;
  2887. il->ctx.station_devtype = RXON_DEV_TYPE_ESS;
  2888. il->ctx.unused_devtype = RXON_DEV_TYPE_ESS;
  2889. SET_IEEE80211_DEV(hw, &pdev->dev);
  2890. D_INFO("*** LOAD DRIVER ***\n");
  2891. il->cfg = cfg;
  2892. il->pci_dev = pdev;
  2893. il->inta_mask = CSR_INI_SET_MASK;
  2894. if (il_alloc_traffic_mem(il))
  2895. IL_ERR("Not enough memory to generate traffic log\n");
  2896. /**************************
  2897. * 2. Initializing PCI bus
  2898. **************************/
  2899. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  2900. PCIE_LINK_STATE_CLKPM);
  2901. if (pci_enable_device(pdev)) {
  2902. err = -ENODEV;
  2903. goto out_ieee80211_free_hw;
  2904. }
  2905. pci_set_master(pdev);
  2906. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2907. if (!err)
  2908. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2909. if (err) {
  2910. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2911. if (!err)
  2912. err = pci_set_consistent_dma_mask(pdev,
  2913. DMA_BIT_MASK(32));
  2914. /* both attempts failed: */
  2915. if (err) {
  2916. IL_WARN("No suitable DMA available.\n");
  2917. goto out_pci_disable_device;
  2918. }
  2919. }
  2920. err = pci_request_regions(pdev, DRV_NAME);
  2921. if (err)
  2922. goto out_pci_disable_device;
  2923. pci_set_drvdata(pdev, il);
  2924. /***********************
  2925. * 3. Read REV register
  2926. ***********************/
  2927. il->hw_base = pci_iomap(pdev, 0, 0);
  2928. if (!il->hw_base) {
  2929. err = -ENODEV;
  2930. goto out_pci_release_regions;
  2931. }
  2932. D_INFO("pci_resource_len = 0x%08llx\n",
  2933. (unsigned long long) pci_resource_len(pdev, 0));
  2934. D_INFO("pci_resource_base = %p\n", il->hw_base);
  2935. /* these spin locks will be used in apm_ops.init and EEPROM access
  2936. * we should init now
  2937. */
  2938. spin_lock_init(&il->reg_lock);
  2939. spin_lock_init(&il->lock);
  2940. /*
  2941. * stop and reset the on-board processor just in case it is in a
  2942. * strange state ... like being left stranded by a primary kernel
  2943. * and this is now the kdump kernel trying to start up
  2944. */
  2945. _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2946. il4965_hw_detect(il);
  2947. IL_INFO("Detected %s, REV=0x%X\n",
  2948. il->cfg->name, il->hw_rev);
  2949. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2950. * PCI Tx retries from interfering with C3 CPU state */
  2951. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2952. il4965_prepare_card_hw(il);
  2953. if (!il->hw_ready) {
  2954. IL_WARN("Failed, HW not ready\n");
  2955. goto out_iounmap;
  2956. }
  2957. /*****************
  2958. * 4. Read EEPROM
  2959. *****************/
  2960. /* Read the EEPROM */
  2961. err = il_eeprom_init(il);
  2962. if (err) {
  2963. IL_ERR("Unable to init EEPROM\n");
  2964. goto out_iounmap;
  2965. }
  2966. err = il4965_eeprom_check_version(il);
  2967. if (err)
  2968. goto out_free_eeprom;
  2969. if (err)
  2970. goto out_free_eeprom;
  2971. /* extract MAC Address */
  2972. il4965_eeprom_get_mac(il, il->addresses[0].addr);
  2973. D_INFO("MAC address: %pM\n", il->addresses[0].addr);
  2974. il->hw->wiphy->addresses = il->addresses;
  2975. il->hw->wiphy->n_addresses = 1;
  2976. /************************
  2977. * 5. Setup HW constants
  2978. ************************/
  2979. if (il4965_set_hw_params(il)) {
  2980. IL_ERR("failed to set hw parameters\n");
  2981. goto out_free_eeprom;
  2982. }
  2983. /*******************
  2984. * 6. Setup il
  2985. *******************/
  2986. err = il4965_init_drv(il);
  2987. if (err)
  2988. goto out_free_eeprom;
  2989. /* At this point both hw and il are initialized. */
  2990. /********************
  2991. * 7. Setup services
  2992. ********************/
  2993. spin_lock_irqsave(&il->lock, flags);
  2994. il_disable_interrupts(il);
  2995. spin_unlock_irqrestore(&il->lock, flags);
  2996. pci_enable_msi(il->pci_dev);
  2997. err = request_irq(il->pci_dev->irq, il_isr,
  2998. IRQF_SHARED, DRV_NAME, il);
  2999. if (err) {
  3000. IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
  3001. goto out_disable_msi;
  3002. }
  3003. il4965_setup_deferred_work(il);
  3004. il4965_setup_rx_handlers(il);
  3005. /*********************************************
  3006. * 8. Enable interrupts and read RFKILL state
  3007. *********************************************/
  3008. /* enable rfkill interrupt: hw bug w/a */
  3009. pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
  3010. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3011. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3012. pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
  3013. }
  3014. il_enable_rfkill_int(il);
  3015. /* If platform's RF_KILL switch is NOT set to KILL */
  3016. if (_il_rd(il, CSR_GP_CNTRL) &
  3017. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3018. clear_bit(STATUS_RF_KILL_HW, &il->status);
  3019. else
  3020. set_bit(STATUS_RF_KILL_HW, &il->status);
  3021. wiphy_rfkill_set_hw_state(il->hw->wiphy,
  3022. test_bit(STATUS_RF_KILL_HW, &il->status));
  3023. il_power_initialize(il);
  3024. init_completion(&il->_4965.firmware_loading_complete);
  3025. err = il4965_request_firmware(il, true);
  3026. if (err)
  3027. goto out_destroy_workqueue;
  3028. return 0;
  3029. out_destroy_workqueue:
  3030. destroy_workqueue(il->workqueue);
  3031. il->workqueue = NULL;
  3032. free_irq(il->pci_dev->irq, il);
  3033. out_disable_msi:
  3034. pci_disable_msi(il->pci_dev);
  3035. il4965_uninit_drv(il);
  3036. out_free_eeprom:
  3037. il_eeprom_free(il);
  3038. out_iounmap:
  3039. pci_iounmap(pdev, il->hw_base);
  3040. out_pci_release_regions:
  3041. pci_set_drvdata(pdev, NULL);
  3042. pci_release_regions(pdev);
  3043. out_pci_disable_device:
  3044. pci_disable_device(pdev);
  3045. out_ieee80211_free_hw:
  3046. il_free_traffic_mem(il);
  3047. ieee80211_free_hw(il->hw);
  3048. out:
  3049. return err;
  3050. }
  3051. static void __devexit il4965_pci_remove(struct pci_dev *pdev)
  3052. {
  3053. struct il_priv *il = pci_get_drvdata(pdev);
  3054. unsigned long flags;
  3055. if (!il)
  3056. return;
  3057. wait_for_completion(&il->_4965.firmware_loading_complete);
  3058. D_INFO("*** UNLOAD DRIVER ***\n");
  3059. il_dbgfs_unregister(il);
  3060. sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
  3061. /* ieee80211_unregister_hw call wil cause il_mac_stop to
  3062. * to be called and il4965_down since we are removing the device
  3063. * we need to set STATUS_EXIT_PENDING bit.
  3064. */
  3065. set_bit(STATUS_EXIT_PENDING, &il->status);
  3066. il_leds_exit(il);
  3067. if (il->mac80211_registered) {
  3068. ieee80211_unregister_hw(il->hw);
  3069. il->mac80211_registered = 0;
  3070. } else {
  3071. il4965_down(il);
  3072. }
  3073. /*
  3074. * Make sure device is reset to low power before unloading driver.
  3075. * This may be redundant with il4965_down(), but there are paths to
  3076. * run il4965_down() without calling apm_ops.stop(), and there are
  3077. * paths to avoid running il4965_down() at all before leaving driver.
  3078. * This (inexpensive) call *makes sure* device is reset.
  3079. */
  3080. il_apm_stop(il);
  3081. /* make sure we flush any pending irq or
  3082. * tasklet for the driver
  3083. */
  3084. spin_lock_irqsave(&il->lock, flags);
  3085. il_disable_interrupts(il);
  3086. spin_unlock_irqrestore(&il->lock, flags);
  3087. il4965_synchronize_irq(il);
  3088. il4965_dealloc_ucode_pci(il);
  3089. if (il->rxq.bd)
  3090. il4965_rx_queue_free(il, &il->rxq);
  3091. il4965_hw_txq_ctx_free(il);
  3092. il_eeprom_free(il);
  3093. /*netif_stop_queue(dev); */
  3094. flush_workqueue(il->workqueue);
  3095. /* ieee80211_unregister_hw calls il_mac_stop, which flushes
  3096. * il->workqueue... so we can't take down the workqueue
  3097. * until now... */
  3098. destroy_workqueue(il->workqueue);
  3099. il->workqueue = NULL;
  3100. il_free_traffic_mem(il);
  3101. free_irq(il->pci_dev->irq, il);
  3102. pci_disable_msi(il->pci_dev);
  3103. pci_iounmap(pdev, il->hw_base);
  3104. pci_release_regions(pdev);
  3105. pci_disable_device(pdev);
  3106. pci_set_drvdata(pdev, NULL);
  3107. il4965_uninit_drv(il);
  3108. dev_kfree_skb(il->beacon_skb);
  3109. ieee80211_free_hw(il->hw);
  3110. }
  3111. /*
  3112. * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
  3113. * must be called under il->lock and mac access
  3114. */
  3115. void il4965_txq_set_sched(struct il_priv *il, u32 mask)
  3116. {
  3117. il_wr_prph(il, IL49_SCD_TXFACT, mask);
  3118. }
  3119. /*****************************************************************************
  3120. *
  3121. * driver and module entry point
  3122. *
  3123. *****************************************************************************/
  3124. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3125. static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
  3126. {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
  3127. {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
  3128. {0}
  3129. };
  3130. MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
  3131. static struct pci_driver il4965_driver = {
  3132. .name = DRV_NAME,
  3133. .id_table = il4965_hw_card_ids,
  3134. .probe = il4965_pci_probe,
  3135. .remove = __devexit_p(il4965_pci_remove),
  3136. .driver.pm = IL_LEGACY_PM_OPS,
  3137. };
  3138. static int __init il4965_init(void)
  3139. {
  3140. int ret;
  3141. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3142. pr_info(DRV_COPYRIGHT "\n");
  3143. ret = il4965_rate_control_register();
  3144. if (ret) {
  3145. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3146. return ret;
  3147. }
  3148. ret = pci_register_driver(&il4965_driver);
  3149. if (ret) {
  3150. pr_err("Unable to initialize PCI module\n");
  3151. goto error_register;
  3152. }
  3153. return ret;
  3154. error_register:
  3155. il4965_rate_control_unregister();
  3156. return ret;
  3157. }
  3158. static void __exit il4965_exit(void)
  3159. {
  3160. pci_unregister_driver(&il4965_driver);
  3161. il4965_rate_control_unregister();
  3162. }
  3163. module_exit(il4965_exit);
  3164. module_init(il4965_init);
  3165. #ifdef CONFIG_IWLEGACY_DEBUG
  3166. module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
  3167. MODULE_PARM_DESC(debug, "debug output mask");
  3168. #endif
  3169. module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
  3170. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3171. module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
  3172. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3173. module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
  3174. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3175. module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K,
  3176. int, S_IRUGO);
  3177. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3178. module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
  3179. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");