ohci-q.c 31 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127
  1. /*
  2. * OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * This file is licenced under the GPL.
  8. */
  9. #include <linux/irq.h>
  10. static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  11. {
  12. int last = urb_priv->length - 1;
  13. if (last >= 0) {
  14. int i;
  15. struct td *td;
  16. for (i = 0; i <= last; i++) {
  17. td = urb_priv->td [i];
  18. if (td)
  19. td_free (hc, td);
  20. }
  21. }
  22. list_del (&urb_priv->pending);
  23. kfree (urb_priv);
  24. }
  25. /*-------------------------------------------------------------------------*/
  26. /*
  27. * URB goes back to driver, and isn't reissued.
  28. * It's completely gone from HC data structures.
  29. * PRECONDITION: ohci lock held, irqs blocked.
  30. */
  31. static void
  32. finish_urb (struct ohci_hcd *ohci, struct urb *urb)
  33. __releases(ohci->lock)
  34. __acquires(ohci->lock)
  35. {
  36. // ASSERT (urb->hcpriv != 0);
  37. urb_free_priv (ohci, urb->hcpriv);
  38. spin_lock (&urb->lock);
  39. if (likely (urb->status == -EINPROGRESS))
  40. urb->status = 0;
  41. spin_unlock (&urb->lock);
  42. switch (usb_pipetype (urb->pipe)) {
  43. case PIPE_ISOCHRONOUS:
  44. ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  45. break;
  46. case PIPE_INTERRUPT:
  47. ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  48. break;
  49. }
  50. #ifdef OHCI_VERBOSE_DEBUG
  51. urb_print (urb, "RET", usb_pipeout (urb->pipe));
  52. #endif
  53. /* urb->complete() can reenter this HCD */
  54. usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  55. spin_unlock (&ohci->lock);
  56. usb_hcd_giveback_urb (ohci_to_hcd(ohci), urb);
  57. spin_lock (&ohci->lock);
  58. /* stop periodic dma if it's not needed */
  59. if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  60. && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  61. ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  62. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  63. }
  64. }
  65. /*-------------------------------------------------------------------------*
  66. * ED handling functions
  67. *-------------------------------------------------------------------------*/
  68. /* search for the right schedule branch to use for a periodic ed.
  69. * does some load balancing; returns the branch, or negative errno.
  70. */
  71. static int balance (struct ohci_hcd *ohci, int interval, int load)
  72. {
  73. int i, branch = -ENOSPC;
  74. /* iso periods can be huge; iso tds specify frame numbers */
  75. if (interval > NUM_INTS)
  76. interval = NUM_INTS;
  77. /* search for the least loaded schedule branch of that period
  78. * that has enough bandwidth left unreserved.
  79. */
  80. for (i = 0; i < interval ; i++) {
  81. if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
  82. int j;
  83. /* usb 1.1 says 90% of one frame */
  84. for (j = i; j < NUM_INTS; j += interval) {
  85. if ((ohci->load [j] + load) > 900)
  86. break;
  87. }
  88. if (j < NUM_INTS)
  89. continue;
  90. branch = i;
  91. }
  92. }
  93. return branch;
  94. }
  95. /*-------------------------------------------------------------------------*/
  96. /* both iso and interrupt requests have periods; this routine puts them
  97. * into the schedule tree in the apppropriate place. most iso devices use
  98. * 1msec periods, but that's not required.
  99. */
  100. static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
  101. {
  102. unsigned i;
  103. ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
  104. (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
  105. ed, ed->branch, ed->load, ed->interval);
  106. for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
  107. struct ed **prev = &ohci->periodic [i];
  108. __hc32 *prev_p = &ohci->hcca->int_table [i];
  109. struct ed *here = *prev;
  110. /* sorting each branch by period (slow before fast)
  111. * lets us share the faster parts of the tree.
  112. * (plus maybe: put interrupt eds before iso)
  113. */
  114. while (here && ed != here) {
  115. if (ed->interval > here->interval)
  116. break;
  117. prev = &here->ed_next;
  118. prev_p = &here->hwNextED;
  119. here = *prev;
  120. }
  121. if (ed != here) {
  122. ed->ed_next = here;
  123. if (here)
  124. ed->hwNextED = *prev_p;
  125. wmb ();
  126. *prev = ed;
  127. *prev_p = cpu_to_hc32(ohci, ed->dma);
  128. wmb();
  129. }
  130. ohci->load [i] += ed->load;
  131. }
  132. ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
  133. }
  134. /* link an ed into one of the HC chains */
  135. static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
  136. {
  137. int branch;
  138. if (ohci_to_hcd(ohci)->state == HC_STATE_QUIESCING)
  139. return -EAGAIN;
  140. ed->state = ED_OPER;
  141. ed->ed_prev = NULL;
  142. ed->ed_next = NULL;
  143. ed->hwNextED = 0;
  144. if (quirk_zfmicro(ohci)
  145. && (ed->type == PIPE_INTERRUPT)
  146. && !(ohci->eds_scheduled++))
  147. mod_timer(&ohci->unlink_watchdog, round_jiffies_relative(HZ));
  148. wmb ();
  149. /* we care about rm_list when setting CLE/BLE in case the HC was at
  150. * work on some TD when CLE/BLE was turned off, and isn't quiesced
  151. * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
  152. *
  153. * control and bulk EDs are doubly linked (ed_next, ed_prev), but
  154. * periodic ones are singly linked (ed_next). that's because the
  155. * periodic schedule encodes a tree like figure 3-5 in the ohci
  156. * spec: each qh can have several "previous" nodes, and the tree
  157. * doesn't have unused/idle descriptors.
  158. */
  159. switch (ed->type) {
  160. case PIPE_CONTROL:
  161. if (ohci->ed_controltail == NULL) {
  162. WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
  163. ohci_writel (ohci, ed->dma,
  164. &ohci->regs->ed_controlhead);
  165. } else {
  166. ohci->ed_controltail->ed_next = ed;
  167. ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
  168. ed->dma);
  169. }
  170. ed->ed_prev = ohci->ed_controltail;
  171. if (!ohci->ed_controltail && !ohci->ed_rm_list) {
  172. wmb();
  173. ohci->hc_control |= OHCI_CTRL_CLE;
  174. ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
  175. ohci_writel (ohci, ohci->hc_control,
  176. &ohci->regs->control);
  177. }
  178. ohci->ed_controltail = ed;
  179. break;
  180. case PIPE_BULK:
  181. if (ohci->ed_bulktail == NULL) {
  182. WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
  183. ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
  184. } else {
  185. ohci->ed_bulktail->ed_next = ed;
  186. ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
  187. ed->dma);
  188. }
  189. ed->ed_prev = ohci->ed_bulktail;
  190. if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
  191. wmb();
  192. ohci->hc_control |= OHCI_CTRL_BLE;
  193. ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
  194. ohci_writel (ohci, ohci->hc_control,
  195. &ohci->regs->control);
  196. }
  197. ohci->ed_bulktail = ed;
  198. break;
  199. // case PIPE_INTERRUPT:
  200. // case PIPE_ISOCHRONOUS:
  201. default:
  202. branch = balance (ohci, ed->interval, ed->load);
  203. if (branch < 0) {
  204. ohci_dbg (ohci,
  205. "ERR %d, interval %d msecs, load %d\n",
  206. branch, ed->interval, ed->load);
  207. // FIXME if there are TDs queued, fail them!
  208. return branch;
  209. }
  210. ed->branch = branch;
  211. periodic_link (ohci, ed);
  212. }
  213. /* the HC may not see the schedule updates yet, but if it does
  214. * then they'll be properly ordered.
  215. */
  216. return 0;
  217. }
  218. /*-------------------------------------------------------------------------*/
  219. /* scan the periodic table to find and unlink this ED */
  220. static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
  221. {
  222. int i;
  223. for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
  224. struct ed *temp;
  225. struct ed **prev = &ohci->periodic [i];
  226. __hc32 *prev_p = &ohci->hcca->int_table [i];
  227. while (*prev && (temp = *prev) != ed) {
  228. prev_p = &temp->hwNextED;
  229. prev = &temp->ed_next;
  230. }
  231. if (*prev) {
  232. *prev_p = ed->hwNextED;
  233. *prev = ed->ed_next;
  234. }
  235. ohci->load [i] -= ed->load;
  236. }
  237. ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
  238. ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
  239. (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
  240. ed, ed->branch, ed->load, ed->interval);
  241. }
  242. /* unlink an ed from one of the HC chains.
  243. * just the link to the ed is unlinked.
  244. * the link from the ed still points to another operational ed or 0
  245. * so the HC can eventually finish the processing of the unlinked ed
  246. * (assuming it already started that, which needn't be true).
  247. *
  248. * ED_UNLINK is a transient state: the HC may still see this ED, but soon
  249. * it won't. ED_SKIP means the HC will finish its current transaction,
  250. * but won't start anything new. The TD queue may still grow; device
  251. * drivers don't know about this HCD-internal state.
  252. *
  253. * When the HC can't see the ED, something changes ED_UNLINK to one of:
  254. *
  255. * - ED_OPER: when there's any request queued, the ED gets rescheduled
  256. * immediately. HC should be working on them.
  257. *
  258. * - ED_IDLE: when there's no TD queue. there's no reason for the HC
  259. * to care about this ED; safe to disable the endpoint.
  260. *
  261. * When finish_unlinks() runs later, after SOF interrupt, it will often
  262. * complete one or more URB unlinks before making that state change.
  263. */
  264. static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
  265. {
  266. ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
  267. wmb ();
  268. ed->state = ED_UNLINK;
  269. /* To deschedule something from the control or bulk list, just
  270. * clear CLE/BLE and wait. There's no safe way to scrub out list
  271. * head/current registers until later, and "later" isn't very
  272. * tightly specified. Figure 6-5 and Section 6.4.2.2 show how
  273. * the HC is reading the ED queues (while we modify them).
  274. *
  275. * For now, ed_schedule() is "later". It might be good paranoia
  276. * to scrub those registers in finish_unlinks(), in case of bugs
  277. * that make the HC try to use them.
  278. */
  279. switch (ed->type) {
  280. case PIPE_CONTROL:
  281. /* remove ED from the HC's list: */
  282. if (ed->ed_prev == NULL) {
  283. if (!ed->hwNextED) {
  284. ohci->hc_control &= ~OHCI_CTRL_CLE;
  285. ohci_writel (ohci, ohci->hc_control,
  286. &ohci->regs->control);
  287. // a ohci_readl() later syncs CLE with the HC
  288. } else
  289. ohci_writel (ohci,
  290. hc32_to_cpup (ohci, &ed->hwNextED),
  291. &ohci->regs->ed_controlhead);
  292. } else {
  293. ed->ed_prev->ed_next = ed->ed_next;
  294. ed->ed_prev->hwNextED = ed->hwNextED;
  295. }
  296. /* remove ED from the HCD's list: */
  297. if (ohci->ed_controltail == ed) {
  298. ohci->ed_controltail = ed->ed_prev;
  299. if (ohci->ed_controltail)
  300. ohci->ed_controltail->ed_next = NULL;
  301. } else if (ed->ed_next) {
  302. ed->ed_next->ed_prev = ed->ed_prev;
  303. }
  304. break;
  305. case PIPE_BULK:
  306. /* remove ED from the HC's list: */
  307. if (ed->ed_prev == NULL) {
  308. if (!ed->hwNextED) {
  309. ohci->hc_control &= ~OHCI_CTRL_BLE;
  310. ohci_writel (ohci, ohci->hc_control,
  311. &ohci->regs->control);
  312. // a ohci_readl() later syncs BLE with the HC
  313. } else
  314. ohci_writel (ohci,
  315. hc32_to_cpup (ohci, &ed->hwNextED),
  316. &ohci->regs->ed_bulkhead);
  317. } else {
  318. ed->ed_prev->ed_next = ed->ed_next;
  319. ed->ed_prev->hwNextED = ed->hwNextED;
  320. }
  321. /* remove ED from the HCD's list: */
  322. if (ohci->ed_bulktail == ed) {
  323. ohci->ed_bulktail = ed->ed_prev;
  324. if (ohci->ed_bulktail)
  325. ohci->ed_bulktail->ed_next = NULL;
  326. } else if (ed->ed_next) {
  327. ed->ed_next->ed_prev = ed->ed_prev;
  328. }
  329. break;
  330. // case PIPE_INTERRUPT:
  331. // case PIPE_ISOCHRONOUS:
  332. default:
  333. periodic_unlink (ohci, ed);
  334. break;
  335. }
  336. }
  337. /*-------------------------------------------------------------------------*/
  338. /* get and maybe (re)init an endpoint. init _should_ be done only as part
  339. * of enumeration, usb_set_configuration() or usb_set_interface().
  340. */
  341. static struct ed *ed_get (
  342. struct ohci_hcd *ohci,
  343. struct usb_host_endpoint *ep,
  344. struct usb_device *udev,
  345. unsigned int pipe,
  346. int interval
  347. ) {
  348. struct ed *ed;
  349. unsigned long flags;
  350. spin_lock_irqsave (&ohci->lock, flags);
  351. if (!(ed = ep->hcpriv)) {
  352. struct td *td;
  353. int is_out;
  354. u32 info;
  355. ed = ed_alloc (ohci, GFP_ATOMIC);
  356. if (!ed) {
  357. /* out of memory */
  358. goto done;
  359. }
  360. /* dummy td; end of td list for ed */
  361. td = td_alloc (ohci, GFP_ATOMIC);
  362. if (!td) {
  363. /* out of memory */
  364. ed_free (ohci, ed);
  365. ed = NULL;
  366. goto done;
  367. }
  368. ed->dummy = td;
  369. ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
  370. ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
  371. ed->state = ED_IDLE;
  372. is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
  373. /* FIXME usbcore changes dev->devnum before SET_ADDRESS
  374. * suceeds ... otherwise we wouldn't need "pipe".
  375. */
  376. info = usb_pipedevice (pipe);
  377. ed->type = usb_pipetype(pipe);
  378. info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
  379. info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16;
  380. if (udev->speed == USB_SPEED_LOW)
  381. info |= ED_LOWSPEED;
  382. /* only control transfers store pids in tds */
  383. if (ed->type != PIPE_CONTROL) {
  384. info |= is_out ? ED_OUT : ED_IN;
  385. if (ed->type != PIPE_BULK) {
  386. /* periodic transfers... */
  387. if (ed->type == PIPE_ISOCHRONOUS)
  388. info |= ED_ISO;
  389. else if (interval > 32) /* iso can be bigger */
  390. interval = 32;
  391. ed->interval = interval;
  392. ed->load = usb_calc_bus_time (
  393. udev->speed, !is_out,
  394. ed->type == PIPE_ISOCHRONOUS,
  395. le16_to_cpu(ep->desc.wMaxPacketSize))
  396. / 1000;
  397. }
  398. }
  399. ed->hwINFO = cpu_to_hc32(ohci, info);
  400. ep->hcpriv = ed;
  401. }
  402. done:
  403. spin_unlock_irqrestore (&ohci->lock, flags);
  404. return ed;
  405. }
  406. /*-------------------------------------------------------------------------*/
  407. /* request unlinking of an endpoint from an operational HC.
  408. * put the ep on the rm_list
  409. * real work is done at the next start frame (SF) hardware interrupt
  410. * caller guarantees HCD is running, so hardware access is safe,
  411. * and that ed->state is ED_OPER
  412. */
  413. static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
  414. {
  415. ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
  416. ed_deschedule (ohci, ed);
  417. /* rm_list is just singly linked, for simplicity */
  418. ed->ed_next = ohci->ed_rm_list;
  419. ed->ed_prev = NULL;
  420. ohci->ed_rm_list = ed;
  421. /* enable SOF interrupt */
  422. ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
  423. ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
  424. // flush those writes, and get latest HCCA contents
  425. (void) ohci_readl (ohci, &ohci->regs->control);
  426. /* SF interrupt might get delayed; record the frame counter value that
  427. * indicates when the HC isn't looking at it, so concurrent unlinks
  428. * behave. frame_no wraps every 2^16 msec, and changes right before
  429. * SF is triggered.
  430. */
  431. ed->tick = ohci_frame_no(ohci) + 1;
  432. }
  433. /*-------------------------------------------------------------------------*
  434. * TD handling functions
  435. *-------------------------------------------------------------------------*/
  436. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  437. static void
  438. td_fill (struct ohci_hcd *ohci, u32 info,
  439. dma_addr_t data, int len,
  440. struct urb *urb, int index)
  441. {
  442. struct td *td, *td_pt;
  443. struct urb_priv *urb_priv = urb->hcpriv;
  444. int is_iso = info & TD_ISO;
  445. int hash;
  446. // ASSERT (index < urb_priv->length);
  447. /* aim for only one interrupt per urb. mostly applies to control
  448. * and iso; other urbs rarely need more than one TD per urb.
  449. * this way, only final tds (or ones with an error) cause IRQs.
  450. * at least immediately; use DI=6 in case any control request is
  451. * tempted to die part way through. (and to force the hc to flush
  452. * its donelist soonish, even on unlink paths.)
  453. *
  454. * NOTE: could delay interrupts even for the last TD, and get fewer
  455. * interrupts ... increasing per-urb latency by sharing interrupts.
  456. * Drivers that queue bulk urbs may request that behavior.
  457. */
  458. if (index != (urb_priv->length - 1)
  459. || (urb->transfer_flags & URB_NO_INTERRUPT))
  460. info |= TD_DI_SET (6);
  461. /* use this td as the next dummy */
  462. td_pt = urb_priv->td [index];
  463. /* fill the old dummy TD */
  464. td = urb_priv->td [index] = urb_priv->ed->dummy;
  465. urb_priv->ed->dummy = td_pt;
  466. td->ed = urb_priv->ed;
  467. td->next_dl_td = NULL;
  468. td->index = index;
  469. td->urb = urb;
  470. td->data_dma = data;
  471. if (!len)
  472. data = 0;
  473. td->hwINFO = cpu_to_hc32 (ohci, info);
  474. if (is_iso) {
  475. td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
  476. *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
  477. (data & 0x0FFF) | 0xE000);
  478. td->ed->last_iso = info & 0xffff;
  479. } else {
  480. td->hwCBP = cpu_to_hc32 (ohci, data);
  481. }
  482. if (data)
  483. td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
  484. else
  485. td->hwBE = 0;
  486. td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
  487. /* append to queue */
  488. list_add_tail (&td->td_list, &td->ed->td_list);
  489. /* hash it for later reverse mapping */
  490. hash = TD_HASH_FUNC (td->td_dma);
  491. td->td_hash = ohci->td_hash [hash];
  492. ohci->td_hash [hash] = td;
  493. /* HC might read the TD (or cachelines) right away ... */
  494. wmb ();
  495. td->ed->hwTailP = td->hwNextTD;
  496. }
  497. /*-------------------------------------------------------------------------*/
  498. /* Prepare all TDs of a transfer, and queue them onto the ED.
  499. * Caller guarantees HC is active.
  500. * Usually the ED is already on the schedule, so TDs might be
  501. * processed as soon as they're queued.
  502. */
  503. static void td_submit_urb (
  504. struct ohci_hcd *ohci,
  505. struct urb *urb
  506. ) {
  507. struct urb_priv *urb_priv = urb->hcpriv;
  508. dma_addr_t data;
  509. int data_len = urb->transfer_buffer_length;
  510. int cnt = 0;
  511. u32 info = 0;
  512. int is_out = usb_pipeout (urb->pipe);
  513. int periodic = 0;
  514. /* OHCI handles the bulk/interrupt data toggles itself. We just
  515. * use the device toggle bits for resetting, and rely on the fact
  516. * that resetting toggle is meaningless if the endpoint is active.
  517. */
  518. if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
  519. usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
  520. is_out, 1);
  521. urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
  522. }
  523. urb_priv->td_cnt = 0;
  524. list_add (&urb_priv->pending, &ohci->pending);
  525. if (data_len)
  526. data = urb->transfer_dma;
  527. else
  528. data = 0;
  529. /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
  530. * using TD_CC_GET, as well as by seeing them on the done list.
  531. * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
  532. */
  533. switch (urb_priv->ed->type) {
  534. /* Bulk and interrupt are identical except for where in the schedule
  535. * their EDs live.
  536. */
  537. case PIPE_INTERRUPT:
  538. /* ... and periodic urbs have extra accounting */
  539. periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
  540. && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
  541. /* FALLTHROUGH */
  542. case PIPE_BULK:
  543. info = is_out
  544. ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
  545. : TD_T_TOGGLE | TD_CC | TD_DP_IN;
  546. /* TDs _could_ transfer up to 8K each */
  547. while (data_len > 4096) {
  548. td_fill (ohci, info, data, 4096, urb, cnt);
  549. data += 4096;
  550. data_len -= 4096;
  551. cnt++;
  552. }
  553. /* maybe avoid ED halt on final TD short read */
  554. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  555. info |= TD_R;
  556. td_fill (ohci, info, data, data_len, urb, cnt);
  557. cnt++;
  558. if ((urb->transfer_flags & URB_ZERO_PACKET)
  559. && cnt < urb_priv->length) {
  560. td_fill (ohci, info, 0, 0, urb, cnt);
  561. cnt++;
  562. }
  563. /* maybe kickstart bulk list */
  564. if (urb_priv->ed->type == PIPE_BULK) {
  565. wmb ();
  566. ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
  567. }
  568. break;
  569. /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
  570. * any DATA phase works normally, and the STATUS ack is special.
  571. */
  572. case PIPE_CONTROL:
  573. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  574. td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
  575. if (data_len > 0) {
  576. info = TD_CC | TD_R | TD_T_DATA1;
  577. info |= is_out ? TD_DP_OUT : TD_DP_IN;
  578. /* NOTE: mishandles transfers >8K, some >4K */
  579. td_fill (ohci, info, data, data_len, urb, cnt++);
  580. }
  581. info = (is_out || data_len == 0)
  582. ? TD_CC | TD_DP_IN | TD_T_DATA1
  583. : TD_CC | TD_DP_OUT | TD_T_DATA1;
  584. td_fill (ohci, info, data, 0, urb, cnt++);
  585. /* maybe kickstart control list */
  586. wmb ();
  587. ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
  588. break;
  589. /* ISO has no retransmit, so no toggle; and it uses special TDs.
  590. * Each TD could handle multiple consecutive frames (interval 1);
  591. * we could often reduce the number of TDs here.
  592. */
  593. case PIPE_ISOCHRONOUS:
  594. for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
  595. int frame = urb->start_frame;
  596. // FIXME scheduling should handle frame counter
  597. // roll-around ... exotic case (and OHCI has
  598. // a 2^16 iso range, vs other HCs max of 2^10)
  599. frame += cnt * urb->interval;
  600. frame &= 0xffff;
  601. td_fill (ohci, TD_CC | TD_ISO | frame,
  602. data + urb->iso_frame_desc [cnt].offset,
  603. urb->iso_frame_desc [cnt].length, urb, cnt);
  604. }
  605. periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
  606. && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
  607. break;
  608. }
  609. /* start periodic dma if needed */
  610. if (periodic) {
  611. wmb ();
  612. ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
  613. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  614. }
  615. // ASSERT (urb_priv->length == cnt);
  616. }
  617. /*-------------------------------------------------------------------------*
  618. * Done List handling functions
  619. *-------------------------------------------------------------------------*/
  620. /* calculate transfer length/status and update the urb
  621. * PRECONDITION: irqsafe (only for urb->status locking)
  622. */
  623. static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td)
  624. {
  625. u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
  626. int cc = 0;
  627. list_del (&td->td_list);
  628. /* ISO ... drivers see per-TD length/status */
  629. if (tdINFO & TD_ISO) {
  630. u16 tdPSW = ohci_hwPSW (ohci, td, 0);
  631. int dlen = 0;
  632. /* NOTE: assumes FC in tdINFO == 0, and that
  633. * only the first of 0..MAXPSW psws is used.
  634. */
  635. cc = (tdPSW >> 12) & 0xF;
  636. if (tdINFO & TD_CC) /* hc didn't touch? */
  637. return;
  638. if (usb_pipeout (urb->pipe))
  639. dlen = urb->iso_frame_desc [td->index].length;
  640. else {
  641. /* short reads are always OK for ISO */
  642. if (cc == TD_DATAUNDERRUN)
  643. cc = TD_CC_NOERROR;
  644. dlen = tdPSW & 0x3ff;
  645. }
  646. urb->actual_length += dlen;
  647. urb->iso_frame_desc [td->index].actual_length = dlen;
  648. urb->iso_frame_desc [td->index].status = cc_to_error [cc];
  649. if (cc != TD_CC_NOERROR)
  650. ohci_vdbg (ohci,
  651. "urb %p iso td %p (%d) len %d cc %d\n",
  652. urb, td, 1 + td->index, dlen, cc);
  653. /* BULK, INT, CONTROL ... drivers see aggregate length/status,
  654. * except that "setup" bytes aren't counted and "short" transfers
  655. * might not be reported as errors.
  656. */
  657. } else {
  658. int type = usb_pipetype (urb->pipe);
  659. u32 tdBE = hc32_to_cpup (ohci, &td->hwBE);
  660. cc = TD_CC_GET (tdINFO);
  661. /* update packet status if needed (short is normally ok) */
  662. if (cc == TD_DATAUNDERRUN
  663. && !(urb->transfer_flags & URB_SHORT_NOT_OK))
  664. cc = TD_CC_NOERROR;
  665. if (cc != TD_CC_NOERROR && cc < 0x0E) {
  666. spin_lock (&urb->lock);
  667. urb->status = cc_to_error[cc];
  668. spin_unlock (&urb->lock);
  669. }
  670. /* count all non-empty packets except control SETUP packet */
  671. if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
  672. if (td->hwCBP == 0)
  673. urb->actual_length += tdBE - td->data_dma + 1;
  674. else
  675. urb->actual_length +=
  676. hc32_to_cpup (ohci, &td->hwCBP)
  677. - td->data_dma;
  678. }
  679. if (cc != TD_CC_NOERROR && cc < 0x0E)
  680. ohci_vdbg (ohci,
  681. "urb %p td %p (%d) cc %d, len=%d/%d\n",
  682. urb, td, 1 + td->index, cc,
  683. urb->actual_length,
  684. urb->transfer_buffer_length);
  685. }
  686. }
  687. /*-------------------------------------------------------------------------*/
  688. static inline struct td *
  689. ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev)
  690. {
  691. struct urb *urb = td->urb;
  692. struct ed *ed = td->ed;
  693. struct list_head *tmp = td->td_list.next;
  694. __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
  695. /* clear ed halt; this is the td that caused it, but keep it inactive
  696. * until its urb->complete() has a chance to clean up.
  697. */
  698. ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
  699. wmb ();
  700. ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
  701. /* put any later tds from this urb onto the donelist, after 'td',
  702. * order won't matter here: no errors, and nothing was transferred.
  703. * also patch the ed so it looks as if those tds completed normally.
  704. */
  705. while (tmp != &ed->td_list) {
  706. struct td *next;
  707. __hc32 info;
  708. next = list_entry (tmp, struct td, td_list);
  709. tmp = next->td_list.next;
  710. if (next->urb != urb)
  711. break;
  712. /* NOTE: if multi-td control DATA segments get supported,
  713. * this urb had one of them, this td wasn't the last td
  714. * in that segment (TD_R clear), this ed halted because
  715. * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
  716. * then we need to leave the control STATUS packet queued
  717. * and clear ED_SKIP.
  718. */
  719. info = next->hwINFO;
  720. info |= cpu_to_hc32 (ohci, TD_DONE);
  721. info &= ~cpu_to_hc32 (ohci, TD_CC);
  722. next->hwINFO = info;
  723. next->next_dl_td = rev;
  724. rev = next;
  725. ed->hwHeadP = next->hwNextTD | toggle;
  726. }
  727. /* help for troubleshooting: report anything that
  728. * looks odd ... that doesn't include protocol stalls
  729. * (or maybe some other things)
  730. */
  731. switch (cc) {
  732. case TD_DATAUNDERRUN:
  733. if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
  734. break;
  735. /* fallthrough */
  736. case TD_CC_STALL:
  737. if (usb_pipecontrol (urb->pipe))
  738. break;
  739. /* fallthrough */
  740. default:
  741. ohci_dbg (ohci,
  742. "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
  743. urb, urb->dev->devpath,
  744. usb_pipeendpoint (urb->pipe),
  745. usb_pipein (urb->pipe) ? "in" : "out",
  746. hc32_to_cpu (ohci, td->hwINFO),
  747. cc, cc_to_error [cc]);
  748. }
  749. return rev;
  750. }
  751. /* replies to the request have to be on a FIFO basis so
  752. * we unreverse the hc-reversed done-list
  753. */
  754. static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
  755. {
  756. u32 td_dma;
  757. struct td *td_rev = NULL;
  758. struct td *td = NULL;
  759. td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
  760. ohci->hcca->done_head = 0;
  761. wmb();
  762. /* get TD from hc's singly linked list, and
  763. * prepend to ours. ed->td_list changes later.
  764. */
  765. while (td_dma) {
  766. int cc;
  767. td = dma_to_td (ohci, td_dma);
  768. if (!td) {
  769. ohci_err (ohci, "bad entry %8x\n", td_dma);
  770. break;
  771. }
  772. td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
  773. cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
  774. /* Non-iso endpoints can halt on error; un-halt,
  775. * and dequeue any other TDs from this urb.
  776. * No other TD could have caused the halt.
  777. */
  778. if (cc != TD_CC_NOERROR
  779. && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
  780. td_rev = ed_halted (ohci, td, cc, td_rev);
  781. td->next_dl_td = td_rev;
  782. td_rev = td;
  783. td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
  784. }
  785. return td_rev;
  786. }
  787. /*-------------------------------------------------------------------------*/
  788. /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
  789. static void
  790. finish_unlinks (struct ohci_hcd *ohci, u16 tick)
  791. {
  792. struct ed *ed, **last;
  793. rescan_all:
  794. for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
  795. struct list_head *entry, *tmp;
  796. int completed, modified;
  797. __hc32 *prev;
  798. /* only take off EDs that the HC isn't using, accounting for
  799. * frame counter wraps and EDs with partially retired TDs
  800. */
  801. if (likely (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) {
  802. if (tick_before (tick, ed->tick)) {
  803. skip_ed:
  804. last = &ed->ed_next;
  805. continue;
  806. }
  807. if (!list_empty (&ed->td_list)) {
  808. struct td *td;
  809. u32 head;
  810. td = list_entry (ed->td_list.next, struct td,
  811. td_list);
  812. head = hc32_to_cpu (ohci, ed->hwHeadP) &
  813. TD_MASK;
  814. /* INTR_WDH may need to clean up first */
  815. if (td->td_dma != head) {
  816. if (ed == ohci->ed_to_check)
  817. ohci->ed_to_check = NULL;
  818. else
  819. goto skip_ed;
  820. }
  821. }
  822. }
  823. /* reentrancy: if we drop the schedule lock, someone might
  824. * have modified this list. normally it's just prepending
  825. * entries (which we'd ignore), but paranoia won't hurt.
  826. */
  827. *last = ed->ed_next;
  828. ed->ed_next = NULL;
  829. modified = 0;
  830. /* unlink urbs as requested, but rescan the list after
  831. * we call a completion since it might have unlinked
  832. * another (earlier) urb
  833. *
  834. * When we get here, the HC doesn't see this ed. But it
  835. * must not be rescheduled until all completed URBs have
  836. * been given back to the driver.
  837. */
  838. rescan_this:
  839. completed = 0;
  840. prev = &ed->hwHeadP;
  841. list_for_each_safe (entry, tmp, &ed->td_list) {
  842. struct td *td;
  843. struct urb *urb;
  844. urb_priv_t *urb_priv;
  845. __hc32 savebits;
  846. td = list_entry (entry, struct td, td_list);
  847. urb = td->urb;
  848. urb_priv = td->urb->hcpriv;
  849. if (!urb->unlinked) {
  850. prev = &td->hwNextTD;
  851. continue;
  852. }
  853. /* patch pointer hc uses */
  854. savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
  855. *prev = td->hwNextTD | savebits;
  856. /* HC may have partly processed this TD */
  857. td_done (ohci, urb, td);
  858. urb_priv->td_cnt++;
  859. /* if URB is done, clean up */
  860. if (urb_priv->td_cnt == urb_priv->length) {
  861. modified = completed = 1;
  862. finish_urb (ohci, urb);
  863. }
  864. }
  865. if (completed && !list_empty (&ed->td_list))
  866. goto rescan_this;
  867. /* ED's now officially unlinked, hc doesn't see */
  868. ed->state = ED_IDLE;
  869. if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
  870. ohci->eds_scheduled--;
  871. ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
  872. ed->hwNextED = 0;
  873. wmb ();
  874. ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
  875. /* but if there's work queued, reschedule */
  876. if (!list_empty (&ed->td_list)) {
  877. if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))
  878. ed_schedule (ohci, ed);
  879. }
  880. if (modified)
  881. goto rescan_all;
  882. }
  883. /* maybe reenable control and bulk lists */
  884. if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)
  885. && ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING
  886. && !ohci->ed_rm_list) {
  887. u32 command = 0, control = 0;
  888. if (ohci->ed_controltail) {
  889. command |= OHCI_CLF;
  890. if (quirk_zfmicro(ohci))
  891. mdelay(1);
  892. if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
  893. control |= OHCI_CTRL_CLE;
  894. ohci_writel (ohci, 0,
  895. &ohci->regs->ed_controlcurrent);
  896. }
  897. }
  898. if (ohci->ed_bulktail) {
  899. command |= OHCI_BLF;
  900. if (quirk_zfmicro(ohci))
  901. mdelay(1);
  902. if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
  903. control |= OHCI_CTRL_BLE;
  904. ohci_writel (ohci, 0,
  905. &ohci->regs->ed_bulkcurrent);
  906. }
  907. }
  908. /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
  909. if (control) {
  910. ohci->hc_control |= control;
  911. if (quirk_zfmicro(ohci))
  912. mdelay(1);
  913. ohci_writel (ohci, ohci->hc_control,
  914. &ohci->regs->control);
  915. }
  916. if (command) {
  917. if (quirk_zfmicro(ohci))
  918. mdelay(1);
  919. ohci_writel (ohci, command, &ohci->regs->cmdstatus);
  920. }
  921. }
  922. }
  923. /*-------------------------------------------------------------------------*/
  924. /*
  925. * Used to take back a TD from the host controller. This would normally be
  926. * called from within dl_done_list, however it may be called directly if the
  927. * HC no longer sees the TD and it has not appeared on the donelist (after
  928. * two frames). This bug has been observed on ZF Micro systems.
  929. */
  930. static void takeback_td(struct ohci_hcd *ohci, struct td *td)
  931. {
  932. struct urb *urb = td->urb;
  933. urb_priv_t *urb_priv = urb->hcpriv;
  934. struct ed *ed = td->ed;
  935. /* update URB's length and status from TD */
  936. td_done(ohci, urb, td);
  937. urb_priv->td_cnt++;
  938. /* If all this urb's TDs are done, call complete() */
  939. if (urb_priv->td_cnt == urb_priv->length)
  940. finish_urb(ohci, urb);
  941. /* clean schedule: unlink EDs that are no longer busy */
  942. if (list_empty(&ed->td_list)) {
  943. if (ed->state == ED_OPER)
  944. start_ed_unlink(ohci, ed);
  945. /* ... reenabling halted EDs only after fault cleanup */
  946. } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
  947. == cpu_to_hc32(ohci, ED_SKIP)) {
  948. td = list_entry(ed->td_list.next, struct td, td_list);
  949. if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
  950. ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
  951. /* ... hc may need waking-up */
  952. switch (ed->type) {
  953. case PIPE_CONTROL:
  954. ohci_writel(ohci, OHCI_CLF,
  955. &ohci->regs->cmdstatus);
  956. break;
  957. case PIPE_BULK:
  958. ohci_writel(ohci, OHCI_BLF,
  959. &ohci->regs->cmdstatus);
  960. break;
  961. }
  962. }
  963. }
  964. }
  965. /*
  966. * Process normal completions (error or success) and clean the schedules.
  967. *
  968. * This is the main path for handing urbs back to drivers. The only other
  969. * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
  970. * instead of scanning the (re-reversed) donelist as this does. There's
  971. * an abnormal path too, handling a quirk in some Compaq silicon: URBs
  972. * with TDs that appear to be orphaned are directly reclaimed.
  973. */
  974. static void
  975. dl_done_list (struct ohci_hcd *ohci)
  976. {
  977. struct td *td = dl_reverse_done_list (ohci);
  978. while (td) {
  979. struct td *td_next = td->next_dl_td;
  980. takeback_td(ohci, td);
  981. td = td_next;
  982. }
  983. }