omap-mcpdm.c 14 KB

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  1. /*
  2. * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
  3. *
  4. * Copyright (C) 2009 - 2011 Texas Instruments
  5. *
  6. * Author: Misael Lopez Cruz <misael.lopez@ti.com>
  7. * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
  8. * Margarita Olaya <magi.olaya@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/err.h>
  31. #include <linux/io.h>
  32. #include <linux/irq.h>
  33. #include <linux/slab.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/of_device.h>
  36. #include <sound/core.h>
  37. #include <sound/pcm.h>
  38. #include <sound/pcm_params.h>
  39. #include <sound/soc.h>
  40. #include <plat/omap_hwmod.h>
  41. #include "omap-mcpdm.h"
  42. #include "omap-pcm.h"
  43. #define OMAP44XX_MCPDM_L3_BASE 0x49032000
  44. struct omap_mcpdm {
  45. struct device *dev;
  46. unsigned long phys_base;
  47. void __iomem *io_base;
  48. int irq;
  49. struct mutex mutex;
  50. /* channel data */
  51. u32 dn_channels;
  52. u32 up_channels;
  53. /* McPDM FIFO thresholds */
  54. u32 dn_threshold;
  55. u32 up_threshold;
  56. /* McPDM dn offsets for rx1, and 2 channels */
  57. u32 dn_rx_offset;
  58. };
  59. /*
  60. * Stream DMA parameters
  61. */
  62. static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
  63. {
  64. .name = "Audio playback",
  65. },
  66. {
  67. .name = "Audio capture",
  68. },
  69. };
  70. static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
  71. {
  72. __raw_writel(val, mcpdm->io_base + reg);
  73. }
  74. static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
  75. {
  76. return __raw_readl(mcpdm->io_base + reg);
  77. }
  78. #ifdef DEBUG
  79. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
  80. {
  81. dev_dbg(mcpdm->dev, "***********************\n");
  82. dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
  83. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
  84. dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
  85. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
  86. dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
  87. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
  88. dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
  89. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
  90. dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
  91. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
  92. dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
  93. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
  94. dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
  95. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
  96. dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
  97. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
  98. dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
  99. omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
  100. dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
  101. omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
  102. dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
  103. omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
  104. dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
  105. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
  106. dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
  107. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
  108. dev_dbg(mcpdm->dev, "***********************\n");
  109. }
  110. #else
  111. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
  112. #endif
  113. /*
  114. * Enables the transfer through the PDM interface to/from the Phoenix
  115. * codec by enabling the corresponding UP or DN channels.
  116. */
  117. static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
  118. {
  119. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  120. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  121. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  122. ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
  123. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  124. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  125. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  126. }
  127. /*
  128. * Disables the transfer through the PDM interface to/from the Phoenix
  129. * codec by disabling the corresponding UP or DN channels.
  130. */
  131. static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
  132. {
  133. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  134. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  135. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  136. ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
  137. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  138. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  139. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  140. }
  141. /*
  142. * Is the physical McPDM interface active.
  143. */
  144. static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
  145. {
  146. return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
  147. (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
  148. }
  149. /*
  150. * Configures McPDM uplink, and downlink for audio.
  151. * This function should be called before omap_mcpdm_start.
  152. */
  153. static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
  154. {
  155. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
  156. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
  157. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  158. /* Enable DN RX1/2 offset cancellation feature, if configured */
  159. if (mcpdm->dn_rx_offset) {
  160. u32 dn_offset = mcpdm->dn_rx_offset;
  161. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  162. dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
  163. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  164. }
  165. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
  166. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
  167. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
  168. MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
  169. }
  170. /*
  171. * Cleans McPDM uplink, and downlink configuration.
  172. * This function should be called when the stream is closed.
  173. */
  174. static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
  175. {
  176. /* Disable irq request generation for downlink */
  177. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  178. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
  179. /* Disable DMA request generation for downlink */
  180. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
  181. /* Disable irq request generation for uplink */
  182. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  183. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  184. /* Disable DMA request generation for uplink */
  185. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
  186. /* Disable RX1/2 offset cancellation */
  187. if (mcpdm->dn_rx_offset)
  188. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
  189. }
  190. static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
  191. {
  192. struct omap_mcpdm *mcpdm = dev_id;
  193. int irq_status;
  194. irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
  195. /* Acknowledge irq event */
  196. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
  197. if (irq_status & MCPDM_DN_IRQ_FULL)
  198. dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
  199. if (irq_status & MCPDM_DN_IRQ_EMPTY)
  200. dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
  201. if (irq_status & MCPDM_DN_IRQ)
  202. dev_dbg(mcpdm->dev, "DN (playback) write request\n");
  203. if (irq_status & MCPDM_UP_IRQ_FULL)
  204. dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
  205. if (irq_status & MCPDM_UP_IRQ_EMPTY)
  206. dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
  207. if (irq_status & MCPDM_UP_IRQ)
  208. dev_dbg(mcpdm->dev, "UP (capture) write request\n");
  209. return IRQ_HANDLED;
  210. }
  211. static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
  212. struct snd_soc_dai *dai)
  213. {
  214. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  215. mutex_lock(&mcpdm->mutex);
  216. if (!dai->active) {
  217. /* Enable watch dog for ES above ES 1.0 to avoid saturation */
  218. if (omap_rev() != OMAP4430_REV_ES1_0) {
  219. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  220. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
  221. ctrl | MCPDM_WD_EN);
  222. }
  223. omap_mcpdm_open_streams(mcpdm);
  224. }
  225. mutex_unlock(&mcpdm->mutex);
  226. snd_soc_dai_set_dma_data(dai, substream,
  227. &omap_mcpdm_dai_dma_params[substream->stream]);
  228. return 0;
  229. }
  230. static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
  231. struct snd_soc_dai *dai)
  232. {
  233. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  234. mutex_lock(&mcpdm->mutex);
  235. if (!dai->active) {
  236. if (omap_mcpdm_active(mcpdm)) {
  237. omap_mcpdm_stop(mcpdm);
  238. omap_mcpdm_close_streams(mcpdm);
  239. }
  240. }
  241. mutex_unlock(&mcpdm->mutex);
  242. }
  243. static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
  244. struct snd_pcm_hw_params *params,
  245. struct snd_soc_dai *dai)
  246. {
  247. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  248. int stream = substream->stream;
  249. struct omap_pcm_dma_data *dma_data;
  250. int channels;
  251. int link_mask = 0;
  252. channels = params_channels(params);
  253. switch (channels) {
  254. case 5:
  255. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  256. /* up to 3 channels for capture */
  257. return -EINVAL;
  258. link_mask |= 1 << 4;
  259. case 4:
  260. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  261. /* up to 3 channels for capture */
  262. return -EINVAL;
  263. link_mask |= 1 << 3;
  264. case 3:
  265. link_mask |= 1 << 2;
  266. case 2:
  267. link_mask |= 1 << 1;
  268. case 1:
  269. link_mask |= 1 << 0;
  270. break;
  271. default:
  272. /* unsupported number of channels */
  273. return -EINVAL;
  274. }
  275. dma_data = snd_soc_dai_get_dma_data(dai, substream);
  276. /* Configure McPDM channels, and DMA packet size */
  277. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  278. mcpdm->dn_channels = link_mask << 3;
  279. dma_data->packet_size =
  280. (MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
  281. } else {
  282. mcpdm->up_channels = link_mask << 0;
  283. dma_data->packet_size = mcpdm->up_threshold * channels;
  284. }
  285. return 0;
  286. }
  287. static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
  288. struct snd_soc_dai *dai)
  289. {
  290. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  291. if (!omap_mcpdm_active(mcpdm)) {
  292. omap_mcpdm_start(mcpdm);
  293. omap_mcpdm_reg_dump(mcpdm);
  294. }
  295. return 0;
  296. }
  297. static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
  298. .startup = omap_mcpdm_dai_startup,
  299. .shutdown = omap_mcpdm_dai_shutdown,
  300. .hw_params = omap_mcpdm_dai_hw_params,
  301. .prepare = omap_mcpdm_prepare,
  302. };
  303. static int omap_mcpdm_probe(struct snd_soc_dai *dai)
  304. {
  305. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  306. int ret;
  307. pm_runtime_enable(mcpdm->dev);
  308. /* Disable lines while request is ongoing */
  309. pm_runtime_get_sync(mcpdm->dev);
  310. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
  311. ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
  312. 0, "McPDM", (void *)mcpdm);
  313. pm_runtime_put_sync(mcpdm->dev);
  314. if (ret) {
  315. dev_err(mcpdm->dev, "Request for IRQ failed\n");
  316. pm_runtime_disable(mcpdm->dev);
  317. }
  318. /* Configure McPDM threshold values */
  319. mcpdm->dn_threshold = 2;
  320. mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
  321. return ret;
  322. }
  323. static int omap_mcpdm_remove(struct snd_soc_dai *dai)
  324. {
  325. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  326. free_irq(mcpdm->irq, (void *)mcpdm);
  327. pm_runtime_disable(mcpdm->dev);
  328. return 0;
  329. }
  330. #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  331. #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
  332. static struct snd_soc_dai_driver omap_mcpdm_dai = {
  333. .probe = omap_mcpdm_probe,
  334. .remove = omap_mcpdm_remove,
  335. .probe_order = SND_SOC_COMP_ORDER_LATE,
  336. .remove_order = SND_SOC_COMP_ORDER_EARLY,
  337. .playback = {
  338. .channels_min = 1,
  339. .channels_max = 5,
  340. .rates = OMAP_MCPDM_RATES,
  341. .formats = OMAP_MCPDM_FORMATS,
  342. .sig_bits = 24,
  343. },
  344. .capture = {
  345. .channels_min = 1,
  346. .channels_max = 3,
  347. .rates = OMAP_MCPDM_RATES,
  348. .formats = OMAP_MCPDM_FORMATS,
  349. .sig_bits = 24,
  350. },
  351. .ops = &omap_mcpdm_dai_ops,
  352. };
  353. void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
  354. u8 rx1, u8 rx2)
  355. {
  356. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  357. mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
  358. }
  359. EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
  360. static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
  361. {
  362. struct omap_mcpdm *mcpdm;
  363. struct resource *res;
  364. mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
  365. if (!mcpdm)
  366. return -ENOMEM;
  367. platform_set_drvdata(pdev, mcpdm);
  368. mutex_init(&mcpdm->mutex);
  369. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  370. if (res == NULL)
  371. return -ENOMEM;
  372. omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
  373. omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;
  374. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  375. if (res == NULL)
  376. return -ENOMEM;
  377. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
  378. if (!res)
  379. return -ENODEV;
  380. omap_mcpdm_dai_dma_params[0].dma_req = res->start;
  381. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
  382. if (!res)
  383. return -ENODEV;
  384. omap_mcpdm_dai_dma_params[1].dma_req = res->start;
  385. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  386. if (res == NULL)
  387. return -ENOMEM;
  388. if (!devm_request_mem_region(&pdev->dev, res->start,
  389. resource_size(res), "McPDM"))
  390. return -EBUSY;
  391. mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
  392. resource_size(res));
  393. if (!mcpdm->io_base)
  394. return -ENOMEM;
  395. mcpdm->irq = platform_get_irq(pdev, 0);
  396. if (mcpdm->irq < 0)
  397. return mcpdm->irq;
  398. mcpdm->dev = &pdev->dev;
  399. return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
  400. }
  401. static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
  402. {
  403. snd_soc_unregister_dai(&pdev->dev);
  404. return 0;
  405. }
  406. static const struct of_device_id omap_mcpdm_of_match[] = {
  407. { .compatible = "ti,omap4-mcpdm", },
  408. { }
  409. };
  410. MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
  411. static struct platform_driver asoc_mcpdm_driver = {
  412. .driver = {
  413. .name = "omap-mcpdm",
  414. .owner = THIS_MODULE,
  415. .of_match_table = omap_mcpdm_of_match,
  416. },
  417. .probe = asoc_mcpdm_probe,
  418. .remove = __devexit_p(asoc_mcpdm_remove),
  419. };
  420. module_platform_driver(asoc_mcpdm_driver);
  421. MODULE_ALIAS("platform:omap-mcpdm");
  422. MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
  423. MODULE_DESCRIPTION("OMAP PDM SoC Interface");
  424. MODULE_LICENSE("GPL");