wm8994.c 119 KB

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  1. /*
  2. * wm8994.c -- WM8994 ALSA SoC Audio driver
  3. *
  4. * Copyright 2009-12 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/i2c.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <sound/core.h>
  24. #include <sound/jack.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include <sound/soc.h>
  28. #include <sound/initval.h>
  29. #include <sound/tlv.h>
  30. #include <trace/events/asoc.h>
  31. #include <linux/mfd/wm8994/core.h>
  32. #include <linux/mfd/wm8994/registers.h>
  33. #include <linux/mfd/wm8994/pdata.h>
  34. #include <linux/mfd/wm8994/gpio.h>
  35. #include "wm8994.h"
  36. #include "wm_hubs.h"
  37. #define WM1811_JACKDET_MODE_NONE 0x0000
  38. #define WM1811_JACKDET_MODE_JACK 0x0100
  39. #define WM1811_JACKDET_MODE_MIC 0x0080
  40. #define WM1811_JACKDET_MODE_AUDIO 0x0180
  41. #define WM8994_NUM_DRC 3
  42. #define WM8994_NUM_EQ 3
  43. static struct {
  44. unsigned int reg;
  45. unsigned int mask;
  46. } wm8994_vu_bits[] = {
  47. { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  48. { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  49. { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  50. { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  51. { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
  52. { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
  53. { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  54. { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  55. { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  56. { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  57. { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
  58. { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
  59. { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
  60. { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
  61. { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
  62. { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
  63. { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
  64. { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
  65. { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
  66. { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  67. { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
  68. { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  69. { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
  70. { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
  71. { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
  72. { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
  73. };
  74. static int wm8994_drc_base[] = {
  75. WM8994_AIF1_DRC1_1,
  76. WM8994_AIF1_DRC2_1,
  77. WM8994_AIF2_DRC_1,
  78. };
  79. static int wm8994_retune_mobile_base[] = {
  80. WM8994_AIF1_DAC1_EQ_GAINS_1,
  81. WM8994_AIF1_DAC2_EQ_GAINS_1,
  82. WM8994_AIF2_EQ_GAINS_1,
  83. };
  84. static void wm8958_default_micdet(u16 status, void *data);
  85. static const struct wm8958_micd_rate micdet_rates[] = {
  86. { 32768, true, 1, 4 },
  87. { 32768, false, 1, 1 },
  88. { 44100 * 256, true, 7, 10 },
  89. { 44100 * 256, false, 7, 10 },
  90. };
  91. static const struct wm8958_micd_rate jackdet_rates[] = {
  92. { 32768, true, 0, 1 },
  93. { 32768, false, 0, 1 },
  94. { 44100 * 256, true, 10, 10 },
  95. { 44100 * 256, false, 7, 8 },
  96. };
  97. static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
  98. {
  99. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  100. int best, i, sysclk, val;
  101. bool idle;
  102. const struct wm8958_micd_rate *rates;
  103. int num_rates;
  104. if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
  105. wm8994->jack_cb != wm8958_default_micdet)
  106. return;
  107. idle = !wm8994->jack_mic;
  108. sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
  109. if (sysclk & WM8994_SYSCLK_SRC)
  110. sysclk = wm8994->aifclk[1];
  111. else
  112. sysclk = wm8994->aifclk[0];
  113. if (wm8994->pdata && wm8994->pdata->micd_rates) {
  114. rates = wm8994->pdata->micd_rates;
  115. num_rates = wm8994->pdata->num_micd_rates;
  116. } else if (wm8994->jackdet) {
  117. rates = jackdet_rates;
  118. num_rates = ARRAY_SIZE(jackdet_rates);
  119. } else {
  120. rates = micdet_rates;
  121. num_rates = ARRAY_SIZE(micdet_rates);
  122. }
  123. best = 0;
  124. for (i = 0; i < num_rates; i++) {
  125. if (rates[i].idle != idle)
  126. continue;
  127. if (abs(rates[i].sysclk - sysclk) <
  128. abs(rates[best].sysclk - sysclk))
  129. best = i;
  130. else if (rates[best].idle != idle)
  131. best = i;
  132. }
  133. val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
  134. | rates[best].rate << WM8958_MICD_RATE_SHIFT;
  135. dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
  136. rates[best].start, rates[best].rate, sysclk,
  137. idle ? "idle" : "active");
  138. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  139. WM8958_MICD_BIAS_STARTTIME_MASK |
  140. WM8958_MICD_RATE_MASK, val);
  141. }
  142. static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
  143. {
  144. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  145. int rate;
  146. int reg1 = 0;
  147. int offset;
  148. if (aif)
  149. offset = 4;
  150. else
  151. offset = 0;
  152. switch (wm8994->sysclk[aif]) {
  153. case WM8994_SYSCLK_MCLK1:
  154. rate = wm8994->mclk[0];
  155. break;
  156. case WM8994_SYSCLK_MCLK2:
  157. reg1 |= 0x8;
  158. rate = wm8994->mclk[1];
  159. break;
  160. case WM8994_SYSCLK_FLL1:
  161. reg1 |= 0x10;
  162. rate = wm8994->fll[0].out;
  163. break;
  164. case WM8994_SYSCLK_FLL2:
  165. reg1 |= 0x18;
  166. rate = wm8994->fll[1].out;
  167. break;
  168. default:
  169. return -EINVAL;
  170. }
  171. if (rate >= 13500000) {
  172. rate /= 2;
  173. reg1 |= WM8994_AIF1CLK_DIV;
  174. dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
  175. aif + 1, rate);
  176. }
  177. wm8994->aifclk[aif] = rate;
  178. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
  179. WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
  180. reg1);
  181. return 0;
  182. }
  183. static int configure_clock(struct snd_soc_codec *codec)
  184. {
  185. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  186. int change, new;
  187. /* Bring up the AIF clocks first */
  188. configure_aif_clock(codec, 0);
  189. configure_aif_clock(codec, 1);
  190. /* Then switch CLK_SYS over to the higher of them; a change
  191. * can only happen as a result of a clocking change which can
  192. * only be made outside of DAPM so we can safely redo the
  193. * clocking.
  194. */
  195. /* If they're equal it doesn't matter which is used */
  196. if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
  197. wm8958_micd_set_rate(codec);
  198. return 0;
  199. }
  200. if (wm8994->aifclk[0] < wm8994->aifclk[1])
  201. new = WM8994_SYSCLK_SRC;
  202. else
  203. new = 0;
  204. change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  205. WM8994_SYSCLK_SRC, new);
  206. if (change)
  207. snd_soc_dapm_sync(&codec->dapm);
  208. wm8958_micd_set_rate(codec);
  209. return 0;
  210. }
  211. static int check_clk_sys(struct snd_soc_dapm_widget *source,
  212. struct snd_soc_dapm_widget *sink)
  213. {
  214. int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
  215. const char *clk;
  216. /* Check what we're currently using for CLK_SYS */
  217. if (reg & WM8994_SYSCLK_SRC)
  218. clk = "AIF2CLK";
  219. else
  220. clk = "AIF1CLK";
  221. return strcmp(source->name, clk) == 0;
  222. }
  223. static const char *sidetone_hpf_text[] = {
  224. "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
  225. };
  226. static const struct soc_enum sidetone_hpf =
  227. SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
  228. static const char *adc_hpf_text[] = {
  229. "HiFi", "Voice 1", "Voice 2", "Voice 3"
  230. };
  231. static const struct soc_enum aif1adc1_hpf =
  232. SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
  233. static const struct soc_enum aif1adc2_hpf =
  234. SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
  235. static const struct soc_enum aif2adc_hpf =
  236. SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
  237. static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
  238. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  239. static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
  240. static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
  241. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  242. static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
  243. static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
  244. #define WM8994_DRC_SWITCH(xname, reg, shift) \
  245. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  246. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  247. .put = wm8994_put_drc_sw, \
  248. .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
  249. static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
  250. struct snd_ctl_elem_value *ucontrol)
  251. {
  252. struct soc_mixer_control *mc =
  253. (struct soc_mixer_control *)kcontrol->private_value;
  254. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  255. int mask, ret;
  256. /* Can't enable both ADC and DAC paths simultaneously */
  257. if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
  258. mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
  259. WM8994_AIF1ADC1R_DRC_ENA_MASK;
  260. else
  261. mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
  262. ret = snd_soc_read(codec, mc->reg);
  263. if (ret < 0)
  264. return ret;
  265. if (ret & mask)
  266. return -EINVAL;
  267. return snd_soc_put_volsw(kcontrol, ucontrol);
  268. }
  269. static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
  270. {
  271. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  272. struct wm8994_pdata *pdata = wm8994->pdata;
  273. int base = wm8994_drc_base[drc];
  274. int cfg = wm8994->drc_cfg[drc];
  275. int save, i;
  276. /* Save any enables; the configuration should clear them. */
  277. save = snd_soc_read(codec, base);
  278. save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
  279. WM8994_AIF1ADC1R_DRC_ENA;
  280. for (i = 0; i < WM8994_DRC_REGS; i++)
  281. snd_soc_update_bits(codec, base + i, 0xffff,
  282. pdata->drc_cfgs[cfg].regs[i]);
  283. snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
  284. WM8994_AIF1ADC1L_DRC_ENA |
  285. WM8994_AIF1ADC1R_DRC_ENA, save);
  286. }
  287. /* Icky as hell but saves code duplication */
  288. static int wm8994_get_drc(const char *name)
  289. {
  290. if (strcmp(name, "AIF1DRC1 Mode") == 0)
  291. return 0;
  292. if (strcmp(name, "AIF1DRC2 Mode") == 0)
  293. return 1;
  294. if (strcmp(name, "AIF2DRC Mode") == 0)
  295. return 2;
  296. return -EINVAL;
  297. }
  298. static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
  299. struct snd_ctl_elem_value *ucontrol)
  300. {
  301. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  302. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  303. struct wm8994_pdata *pdata = wm8994->pdata;
  304. int drc = wm8994_get_drc(kcontrol->id.name);
  305. int value = ucontrol->value.integer.value[0];
  306. if (drc < 0)
  307. return drc;
  308. if (value >= pdata->num_drc_cfgs)
  309. return -EINVAL;
  310. wm8994->drc_cfg[drc] = value;
  311. wm8994_set_drc(codec, drc);
  312. return 0;
  313. }
  314. static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
  315. struct snd_ctl_elem_value *ucontrol)
  316. {
  317. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  318. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  319. int drc = wm8994_get_drc(kcontrol->id.name);
  320. ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
  321. return 0;
  322. }
  323. static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
  324. {
  325. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  326. struct wm8994_pdata *pdata = wm8994->pdata;
  327. int base = wm8994_retune_mobile_base[block];
  328. int iface, best, best_val, save, i, cfg;
  329. if (!pdata || !wm8994->num_retune_mobile_texts)
  330. return;
  331. switch (block) {
  332. case 0:
  333. case 1:
  334. iface = 0;
  335. break;
  336. case 2:
  337. iface = 1;
  338. break;
  339. default:
  340. return;
  341. }
  342. /* Find the version of the currently selected configuration
  343. * with the nearest sample rate. */
  344. cfg = wm8994->retune_mobile_cfg[block];
  345. best = 0;
  346. best_val = INT_MAX;
  347. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  348. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  349. wm8994->retune_mobile_texts[cfg]) == 0 &&
  350. abs(pdata->retune_mobile_cfgs[i].rate
  351. - wm8994->dac_rates[iface]) < best_val) {
  352. best = i;
  353. best_val = abs(pdata->retune_mobile_cfgs[i].rate
  354. - wm8994->dac_rates[iface]);
  355. }
  356. }
  357. dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
  358. block,
  359. pdata->retune_mobile_cfgs[best].name,
  360. pdata->retune_mobile_cfgs[best].rate,
  361. wm8994->dac_rates[iface]);
  362. /* The EQ will be disabled while reconfiguring it, remember the
  363. * current configuration.
  364. */
  365. save = snd_soc_read(codec, base);
  366. save &= WM8994_AIF1DAC1_EQ_ENA;
  367. for (i = 0; i < WM8994_EQ_REGS; i++)
  368. snd_soc_update_bits(codec, base + i, 0xffff,
  369. pdata->retune_mobile_cfgs[best].regs[i]);
  370. snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
  371. }
  372. /* Icky as hell but saves code duplication */
  373. static int wm8994_get_retune_mobile_block(const char *name)
  374. {
  375. if (strcmp(name, "AIF1.1 EQ Mode") == 0)
  376. return 0;
  377. if (strcmp(name, "AIF1.2 EQ Mode") == 0)
  378. return 1;
  379. if (strcmp(name, "AIF2 EQ Mode") == 0)
  380. return 2;
  381. return -EINVAL;
  382. }
  383. static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  384. struct snd_ctl_elem_value *ucontrol)
  385. {
  386. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  387. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  388. struct wm8994_pdata *pdata = wm8994->pdata;
  389. int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
  390. int value = ucontrol->value.integer.value[0];
  391. if (block < 0)
  392. return block;
  393. if (value >= pdata->num_retune_mobile_cfgs)
  394. return -EINVAL;
  395. wm8994->retune_mobile_cfg[block] = value;
  396. wm8994_set_retune_mobile(codec, block);
  397. return 0;
  398. }
  399. static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  400. struct snd_ctl_elem_value *ucontrol)
  401. {
  402. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  403. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  404. int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
  405. ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
  406. return 0;
  407. }
  408. static const char *aif_chan_src_text[] = {
  409. "Left", "Right"
  410. };
  411. static const struct soc_enum aif1adcl_src =
  412. SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
  413. static const struct soc_enum aif1adcr_src =
  414. SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
  415. static const struct soc_enum aif2adcl_src =
  416. SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
  417. static const struct soc_enum aif2adcr_src =
  418. SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
  419. static const struct soc_enum aif1dacl_src =
  420. SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
  421. static const struct soc_enum aif1dacr_src =
  422. SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
  423. static const struct soc_enum aif2dacl_src =
  424. SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
  425. static const struct soc_enum aif2dacr_src =
  426. SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
  427. static const char *osr_text[] = {
  428. "Low Power", "High Performance",
  429. };
  430. static const struct soc_enum dac_osr =
  431. SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
  432. static const struct soc_enum adc_osr =
  433. SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
  434. static const struct snd_kcontrol_new wm8994_snd_controls[] = {
  435. SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
  436. WM8994_AIF1_ADC1_RIGHT_VOLUME,
  437. 1, 119, 0, digital_tlv),
  438. SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
  439. WM8994_AIF1_ADC2_RIGHT_VOLUME,
  440. 1, 119, 0, digital_tlv),
  441. SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
  442. WM8994_AIF2_ADC_RIGHT_VOLUME,
  443. 1, 119, 0, digital_tlv),
  444. SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
  445. SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
  446. SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
  447. SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
  448. SOC_ENUM("AIF1DACL Source", aif1dacl_src),
  449. SOC_ENUM("AIF1DACR Source", aif1dacr_src),
  450. SOC_ENUM("AIF2DACL Source", aif2dacl_src),
  451. SOC_ENUM("AIF2DACR Source", aif2dacr_src),
  452. SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
  453. WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  454. SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
  455. WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  456. SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
  457. WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  458. SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
  459. SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
  460. SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
  461. SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
  462. SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
  463. WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
  464. WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
  465. WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
  466. WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
  467. WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
  468. WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
  469. WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
  470. WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
  471. WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
  472. SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
  473. 5, 12, 0, st_tlv),
  474. SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
  475. 0, 12, 0, st_tlv),
  476. SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
  477. 5, 12, 0, st_tlv),
  478. SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
  479. 0, 12, 0, st_tlv),
  480. SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
  481. SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
  482. SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
  483. SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
  484. SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
  485. SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
  486. SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
  487. SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
  488. SOC_ENUM("ADC OSR", adc_osr),
  489. SOC_ENUM("DAC OSR", dac_osr),
  490. SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
  491. WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  492. SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
  493. WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
  494. SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
  495. WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  496. SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
  497. WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
  498. SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
  499. 6, 1, 1, wm_hubs_spkmix_tlv),
  500. SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
  501. 2, 1, 1, wm_hubs_spkmix_tlv),
  502. SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
  503. 6, 1, 1, wm_hubs_spkmix_tlv),
  504. SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
  505. 2, 1, 1, wm_hubs_spkmix_tlv),
  506. SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
  507. 10, 15, 0, wm8994_3d_tlv),
  508. SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
  509. 8, 1, 0),
  510. SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
  511. 10, 15, 0, wm8994_3d_tlv),
  512. SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
  513. 8, 1, 0),
  514. SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
  515. 10, 15, 0, wm8994_3d_tlv),
  516. SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
  517. 8, 1, 0),
  518. };
  519. static const struct snd_kcontrol_new wm8994_eq_controls[] = {
  520. SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
  521. eq_tlv),
  522. SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
  523. eq_tlv),
  524. SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
  525. eq_tlv),
  526. SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
  527. eq_tlv),
  528. SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
  529. eq_tlv),
  530. SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
  531. eq_tlv),
  532. SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
  533. eq_tlv),
  534. SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
  535. eq_tlv),
  536. SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
  537. eq_tlv),
  538. SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
  539. eq_tlv),
  540. SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
  541. eq_tlv),
  542. SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
  543. eq_tlv),
  544. SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
  545. eq_tlv),
  546. SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
  547. eq_tlv),
  548. SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
  549. eq_tlv),
  550. };
  551. static const struct snd_kcontrol_new wm8994_drc_controls[] = {
  552. SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
  553. WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
  554. WM8994_AIF1ADC1R_DRC_ENA),
  555. SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
  556. WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
  557. WM8994_AIF1ADC2R_DRC_ENA),
  558. SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
  559. WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
  560. WM8994_AIF2ADCR_DRC_ENA),
  561. };
  562. static const char *wm8958_ng_text[] = {
  563. "30ms", "125ms", "250ms", "500ms",
  564. };
  565. static const struct soc_enum wm8958_aif1dac1_ng_hold =
  566. SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
  567. WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
  568. static const struct soc_enum wm8958_aif1dac2_ng_hold =
  569. SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
  570. WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
  571. static const struct soc_enum wm8958_aif2dac_ng_hold =
  572. SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
  573. WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
  574. static const struct snd_kcontrol_new wm8958_snd_controls[] = {
  575. SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
  576. SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
  577. WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
  578. SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
  579. SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
  580. WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
  581. 7, 1, ng_tlv),
  582. SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
  583. WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
  584. SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
  585. SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
  586. WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
  587. 7, 1, ng_tlv),
  588. SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
  589. WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
  590. SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
  591. SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
  592. WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
  593. 7, 1, ng_tlv),
  594. };
  595. static const struct snd_kcontrol_new wm1811_snd_controls[] = {
  596. SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
  597. mixin_boost_tlv),
  598. SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
  599. mixin_boost_tlv),
  600. };
  601. /* We run all mode setting through a function to enforce audio mode */
  602. static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
  603. {
  604. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  605. if (!wm8994->jackdet || !wm8994->jack_cb)
  606. return;
  607. if (wm8994->active_refcount)
  608. mode = WM1811_JACKDET_MODE_AUDIO;
  609. if (mode == wm8994->jackdet_mode)
  610. return;
  611. wm8994->jackdet_mode = mode;
  612. /* Always use audio mode to detect while the system is active */
  613. if (mode != WM1811_JACKDET_MODE_NONE)
  614. mode = WM1811_JACKDET_MODE_AUDIO;
  615. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  616. WM1811_JACKDET_MODE_MASK, mode);
  617. }
  618. static void active_reference(struct snd_soc_codec *codec)
  619. {
  620. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  621. mutex_lock(&wm8994->accdet_lock);
  622. wm8994->active_refcount++;
  623. dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
  624. wm8994->active_refcount);
  625. /* If we're using jack detection go into audio mode */
  626. wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
  627. mutex_unlock(&wm8994->accdet_lock);
  628. }
  629. static void active_dereference(struct snd_soc_codec *codec)
  630. {
  631. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  632. u16 mode;
  633. mutex_lock(&wm8994->accdet_lock);
  634. wm8994->active_refcount--;
  635. dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
  636. wm8994->active_refcount);
  637. if (wm8994->active_refcount == 0) {
  638. /* Go into appropriate detection only mode */
  639. if (wm8994->jack_mic || wm8994->mic_detecting)
  640. mode = WM1811_JACKDET_MODE_MIC;
  641. else
  642. mode = WM1811_JACKDET_MODE_JACK;
  643. wm1811_jackdet_set_mode(codec, mode);
  644. }
  645. mutex_unlock(&wm8994->accdet_lock);
  646. }
  647. static int clk_sys_event(struct snd_soc_dapm_widget *w,
  648. struct snd_kcontrol *kcontrol, int event)
  649. {
  650. struct snd_soc_codec *codec = w->codec;
  651. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  652. switch (event) {
  653. case SND_SOC_DAPM_PRE_PMU:
  654. return configure_clock(codec);
  655. case SND_SOC_DAPM_POST_PMU:
  656. /*
  657. * JACKDET won't run until we start the clock and it
  658. * only reports deltas, make sure we notify the state
  659. * up the stack on startup. Use a *very* generous
  660. * timeout for paranoia, there's no urgency and we
  661. * don't want false reports.
  662. */
  663. if (wm8994->jackdet && !wm8994->clk_has_run) {
  664. schedule_delayed_work(&wm8994->jackdet_bootstrap,
  665. msecs_to_jiffies(1000));
  666. wm8994->clk_has_run = true;
  667. }
  668. break;
  669. case SND_SOC_DAPM_POST_PMD:
  670. configure_clock(codec);
  671. break;
  672. }
  673. return 0;
  674. }
  675. static void vmid_reference(struct snd_soc_codec *codec)
  676. {
  677. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  678. pm_runtime_get_sync(codec->dev);
  679. wm8994->vmid_refcount++;
  680. dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
  681. wm8994->vmid_refcount);
  682. if (wm8994->vmid_refcount == 1) {
  683. snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
  684. WM8994_LINEOUT1_DISCH |
  685. WM8994_LINEOUT2_DISCH, 0);
  686. wm_hubs_vmid_ena(codec);
  687. switch (wm8994->vmid_mode) {
  688. default:
  689. WARN_ON(NULL == "Invalid VMID mode");
  690. case WM8994_VMID_NORMAL:
  691. /* Startup bias, VMID ramp & buffer */
  692. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  693. WM8994_BIAS_SRC |
  694. WM8994_VMID_DISCH |
  695. WM8994_STARTUP_BIAS_ENA |
  696. WM8994_VMID_BUF_ENA |
  697. WM8994_VMID_RAMP_MASK,
  698. WM8994_BIAS_SRC |
  699. WM8994_STARTUP_BIAS_ENA |
  700. WM8994_VMID_BUF_ENA |
  701. (0x3 << WM8994_VMID_RAMP_SHIFT));
  702. /* Main bias enable, VMID=2x40k */
  703. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  704. WM8994_BIAS_ENA |
  705. WM8994_VMID_SEL_MASK,
  706. WM8994_BIAS_ENA | 0x2);
  707. msleep(50);
  708. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  709. WM8994_VMID_RAMP_MASK |
  710. WM8994_BIAS_SRC,
  711. 0);
  712. break;
  713. case WM8994_VMID_FORCE:
  714. /* Startup bias, slow VMID ramp & buffer */
  715. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  716. WM8994_BIAS_SRC |
  717. WM8994_VMID_DISCH |
  718. WM8994_STARTUP_BIAS_ENA |
  719. WM8994_VMID_BUF_ENA |
  720. WM8994_VMID_RAMP_MASK,
  721. WM8994_BIAS_SRC |
  722. WM8994_STARTUP_BIAS_ENA |
  723. WM8994_VMID_BUF_ENA |
  724. (0x2 << WM8994_VMID_RAMP_SHIFT));
  725. /* Main bias enable, VMID=2x40k */
  726. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  727. WM8994_BIAS_ENA |
  728. WM8994_VMID_SEL_MASK,
  729. WM8994_BIAS_ENA | 0x2);
  730. msleep(400);
  731. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  732. WM8994_VMID_RAMP_MASK |
  733. WM8994_BIAS_SRC,
  734. 0);
  735. break;
  736. }
  737. }
  738. }
  739. static void vmid_dereference(struct snd_soc_codec *codec)
  740. {
  741. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  742. wm8994->vmid_refcount--;
  743. dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
  744. wm8994->vmid_refcount);
  745. if (wm8994->vmid_refcount == 0) {
  746. if (wm8994->hubs.lineout1_se)
  747. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
  748. WM8994_LINEOUT1N_ENA |
  749. WM8994_LINEOUT1P_ENA,
  750. WM8994_LINEOUT1N_ENA |
  751. WM8994_LINEOUT1P_ENA);
  752. if (wm8994->hubs.lineout2_se)
  753. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
  754. WM8994_LINEOUT2N_ENA |
  755. WM8994_LINEOUT2P_ENA,
  756. WM8994_LINEOUT2N_ENA |
  757. WM8994_LINEOUT2P_ENA);
  758. /* Start discharging VMID */
  759. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  760. WM8994_BIAS_SRC |
  761. WM8994_VMID_DISCH,
  762. WM8994_BIAS_SRC |
  763. WM8994_VMID_DISCH);
  764. switch (wm8994->vmid_mode) {
  765. case WM8994_VMID_FORCE:
  766. msleep(350);
  767. break;
  768. default:
  769. break;
  770. }
  771. snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
  772. WM8994_VROI, WM8994_VROI);
  773. /* Active discharge */
  774. snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
  775. WM8994_LINEOUT1_DISCH |
  776. WM8994_LINEOUT2_DISCH,
  777. WM8994_LINEOUT1_DISCH |
  778. WM8994_LINEOUT2_DISCH);
  779. msleep(150);
  780. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
  781. WM8994_LINEOUT1N_ENA |
  782. WM8994_LINEOUT1P_ENA |
  783. WM8994_LINEOUT2N_ENA |
  784. WM8994_LINEOUT2P_ENA, 0);
  785. snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
  786. WM8994_VROI, 0);
  787. /* Switch off startup biases */
  788. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  789. WM8994_BIAS_SRC |
  790. WM8994_STARTUP_BIAS_ENA |
  791. WM8994_VMID_BUF_ENA |
  792. WM8994_VMID_RAMP_MASK, 0);
  793. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  794. WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
  795. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  796. WM8994_VMID_RAMP_MASK, 0);
  797. }
  798. pm_runtime_put(codec->dev);
  799. }
  800. static int vmid_event(struct snd_soc_dapm_widget *w,
  801. struct snd_kcontrol *kcontrol, int event)
  802. {
  803. struct snd_soc_codec *codec = w->codec;
  804. switch (event) {
  805. case SND_SOC_DAPM_PRE_PMU:
  806. vmid_reference(codec);
  807. break;
  808. case SND_SOC_DAPM_POST_PMD:
  809. vmid_dereference(codec);
  810. break;
  811. }
  812. return 0;
  813. }
  814. static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
  815. {
  816. int source = 0; /* GCC flow analysis can't track enable */
  817. int reg, reg_r;
  818. /* We also need the same AIF source for L/R and only one path */
  819. reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
  820. switch (reg) {
  821. case WM8994_AIF2DACL_TO_DAC1L:
  822. dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
  823. source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  824. break;
  825. case WM8994_AIF1DAC2L_TO_DAC1L:
  826. dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
  827. source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  828. break;
  829. case WM8994_AIF1DAC1L_TO_DAC1L:
  830. dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
  831. source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  832. break;
  833. default:
  834. dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
  835. return false;
  836. }
  837. reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
  838. if (reg_r != reg) {
  839. dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
  840. return false;
  841. }
  842. /* Set the source up */
  843. snd_soc_update_bits(codec, WM8994_CLASS_W_1,
  844. WM8994_CP_DYN_SRC_SEL_MASK, source);
  845. return true;
  846. }
  847. static int aif1clk_ev(struct snd_soc_dapm_widget *w,
  848. struct snd_kcontrol *kcontrol, int event)
  849. {
  850. struct snd_soc_codec *codec = w->codec;
  851. struct wm8994 *control = codec->control_data;
  852. int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
  853. int i;
  854. int dac;
  855. int adc;
  856. int val;
  857. switch (control->type) {
  858. case WM8994:
  859. case WM8958:
  860. mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
  861. break;
  862. default:
  863. break;
  864. }
  865. switch (event) {
  866. case SND_SOC_DAPM_PRE_PMU:
  867. val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
  868. if ((val & WM8994_AIF1ADCL_SRC) &&
  869. (val & WM8994_AIF1ADCR_SRC))
  870. adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
  871. else if (!(val & WM8994_AIF1ADCL_SRC) &&
  872. !(val & WM8994_AIF1ADCR_SRC))
  873. adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
  874. else
  875. adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
  876. WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
  877. val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
  878. if ((val & WM8994_AIF1DACL_SRC) &&
  879. (val & WM8994_AIF1DACR_SRC))
  880. dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
  881. else if (!(val & WM8994_AIF1DACL_SRC) &&
  882. !(val & WM8994_AIF1DACR_SRC))
  883. dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
  884. else
  885. dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
  886. WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
  887. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
  888. mask, adc);
  889. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
  890. mask, dac);
  891. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  892. WM8994_AIF1DSPCLK_ENA |
  893. WM8994_SYSDSPCLK_ENA,
  894. WM8994_AIF1DSPCLK_ENA |
  895. WM8994_SYSDSPCLK_ENA);
  896. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
  897. WM8994_AIF1ADC1R_ENA |
  898. WM8994_AIF1ADC1L_ENA |
  899. WM8994_AIF1ADC2R_ENA |
  900. WM8994_AIF1ADC2L_ENA);
  901. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
  902. WM8994_AIF1DAC1R_ENA |
  903. WM8994_AIF1DAC1L_ENA |
  904. WM8994_AIF1DAC2R_ENA |
  905. WM8994_AIF1DAC2L_ENA);
  906. break;
  907. case SND_SOC_DAPM_POST_PMU:
  908. for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
  909. snd_soc_write(codec, wm8994_vu_bits[i].reg,
  910. snd_soc_read(codec,
  911. wm8994_vu_bits[i].reg));
  912. break;
  913. case SND_SOC_DAPM_PRE_PMD:
  914. case SND_SOC_DAPM_POST_PMD:
  915. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
  916. mask, 0);
  917. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
  918. mask, 0);
  919. val = snd_soc_read(codec, WM8994_CLOCKING_1);
  920. if (val & WM8994_AIF2DSPCLK_ENA)
  921. val = WM8994_SYSDSPCLK_ENA;
  922. else
  923. val = 0;
  924. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  925. WM8994_SYSDSPCLK_ENA |
  926. WM8994_AIF1DSPCLK_ENA, val);
  927. break;
  928. }
  929. return 0;
  930. }
  931. static int aif2clk_ev(struct snd_soc_dapm_widget *w,
  932. struct snd_kcontrol *kcontrol, int event)
  933. {
  934. struct snd_soc_codec *codec = w->codec;
  935. int i;
  936. int dac;
  937. int adc;
  938. int val;
  939. switch (event) {
  940. case SND_SOC_DAPM_PRE_PMU:
  941. val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
  942. if ((val & WM8994_AIF2ADCL_SRC) &&
  943. (val & WM8994_AIF2ADCR_SRC))
  944. adc = WM8994_AIF2ADCR_ENA;
  945. else if (!(val & WM8994_AIF2ADCL_SRC) &&
  946. !(val & WM8994_AIF2ADCR_SRC))
  947. adc = WM8994_AIF2ADCL_ENA;
  948. else
  949. adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
  950. val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
  951. if ((val & WM8994_AIF2DACL_SRC) &&
  952. (val & WM8994_AIF2DACR_SRC))
  953. dac = WM8994_AIF2DACR_ENA;
  954. else if (!(val & WM8994_AIF2DACL_SRC) &&
  955. !(val & WM8994_AIF2DACR_SRC))
  956. dac = WM8994_AIF2DACL_ENA;
  957. else
  958. dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
  959. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
  960. WM8994_AIF2ADCL_ENA |
  961. WM8994_AIF2ADCR_ENA, adc);
  962. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
  963. WM8994_AIF2DACL_ENA |
  964. WM8994_AIF2DACR_ENA, dac);
  965. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  966. WM8994_AIF2DSPCLK_ENA |
  967. WM8994_SYSDSPCLK_ENA,
  968. WM8994_AIF2DSPCLK_ENA |
  969. WM8994_SYSDSPCLK_ENA);
  970. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
  971. WM8994_AIF2ADCL_ENA |
  972. WM8994_AIF2ADCR_ENA,
  973. WM8994_AIF2ADCL_ENA |
  974. WM8994_AIF2ADCR_ENA);
  975. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
  976. WM8994_AIF2DACL_ENA |
  977. WM8994_AIF2DACR_ENA,
  978. WM8994_AIF2DACL_ENA |
  979. WM8994_AIF2DACR_ENA);
  980. break;
  981. case SND_SOC_DAPM_POST_PMU:
  982. for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
  983. snd_soc_write(codec, wm8994_vu_bits[i].reg,
  984. snd_soc_read(codec,
  985. wm8994_vu_bits[i].reg));
  986. break;
  987. case SND_SOC_DAPM_PRE_PMD:
  988. case SND_SOC_DAPM_POST_PMD:
  989. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
  990. WM8994_AIF2DACL_ENA |
  991. WM8994_AIF2DACR_ENA, 0);
  992. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
  993. WM8994_AIF2ADCL_ENA |
  994. WM8994_AIF2ADCR_ENA, 0);
  995. val = snd_soc_read(codec, WM8994_CLOCKING_1);
  996. if (val & WM8994_AIF1DSPCLK_ENA)
  997. val = WM8994_SYSDSPCLK_ENA;
  998. else
  999. val = 0;
  1000. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  1001. WM8994_SYSDSPCLK_ENA |
  1002. WM8994_AIF2DSPCLK_ENA, val);
  1003. break;
  1004. }
  1005. return 0;
  1006. }
  1007. static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
  1008. struct snd_kcontrol *kcontrol, int event)
  1009. {
  1010. struct snd_soc_codec *codec = w->codec;
  1011. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1012. switch (event) {
  1013. case SND_SOC_DAPM_PRE_PMU:
  1014. wm8994->aif1clk_enable = 1;
  1015. break;
  1016. case SND_SOC_DAPM_POST_PMD:
  1017. wm8994->aif1clk_disable = 1;
  1018. break;
  1019. }
  1020. return 0;
  1021. }
  1022. static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
  1023. struct snd_kcontrol *kcontrol, int event)
  1024. {
  1025. struct snd_soc_codec *codec = w->codec;
  1026. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1027. switch (event) {
  1028. case SND_SOC_DAPM_PRE_PMU:
  1029. wm8994->aif2clk_enable = 1;
  1030. break;
  1031. case SND_SOC_DAPM_POST_PMD:
  1032. wm8994->aif2clk_disable = 1;
  1033. break;
  1034. }
  1035. return 0;
  1036. }
  1037. static int late_enable_ev(struct snd_soc_dapm_widget *w,
  1038. struct snd_kcontrol *kcontrol, int event)
  1039. {
  1040. struct snd_soc_codec *codec = w->codec;
  1041. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1042. switch (event) {
  1043. case SND_SOC_DAPM_PRE_PMU:
  1044. if (wm8994->aif1clk_enable) {
  1045. aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
  1046. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
  1047. WM8994_AIF1CLK_ENA_MASK,
  1048. WM8994_AIF1CLK_ENA);
  1049. aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
  1050. wm8994->aif1clk_enable = 0;
  1051. }
  1052. if (wm8994->aif2clk_enable) {
  1053. aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
  1054. snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
  1055. WM8994_AIF2CLK_ENA_MASK,
  1056. WM8994_AIF2CLK_ENA);
  1057. aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
  1058. wm8994->aif2clk_enable = 0;
  1059. }
  1060. break;
  1061. }
  1062. /* We may also have postponed startup of DSP, handle that. */
  1063. wm8958_aif_ev(w, kcontrol, event);
  1064. return 0;
  1065. }
  1066. static int late_disable_ev(struct snd_soc_dapm_widget *w,
  1067. struct snd_kcontrol *kcontrol, int event)
  1068. {
  1069. struct snd_soc_codec *codec = w->codec;
  1070. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1071. switch (event) {
  1072. case SND_SOC_DAPM_POST_PMD:
  1073. if (wm8994->aif1clk_disable) {
  1074. aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
  1075. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
  1076. WM8994_AIF1CLK_ENA_MASK, 0);
  1077. aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
  1078. wm8994->aif1clk_disable = 0;
  1079. }
  1080. if (wm8994->aif2clk_disable) {
  1081. aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
  1082. snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
  1083. WM8994_AIF2CLK_ENA_MASK, 0);
  1084. aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
  1085. wm8994->aif2clk_disable = 0;
  1086. }
  1087. break;
  1088. }
  1089. return 0;
  1090. }
  1091. static int adc_mux_ev(struct snd_soc_dapm_widget *w,
  1092. struct snd_kcontrol *kcontrol, int event)
  1093. {
  1094. late_enable_ev(w, kcontrol, event);
  1095. return 0;
  1096. }
  1097. static int micbias_ev(struct snd_soc_dapm_widget *w,
  1098. struct snd_kcontrol *kcontrol, int event)
  1099. {
  1100. late_enable_ev(w, kcontrol, event);
  1101. return 0;
  1102. }
  1103. static int dac_ev(struct snd_soc_dapm_widget *w,
  1104. struct snd_kcontrol *kcontrol, int event)
  1105. {
  1106. struct snd_soc_codec *codec = w->codec;
  1107. unsigned int mask = 1 << w->shift;
  1108. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
  1109. mask, mask);
  1110. return 0;
  1111. }
  1112. static const char *adc_mux_text[] = {
  1113. "ADC",
  1114. "DMIC",
  1115. };
  1116. static const struct soc_enum adc_enum =
  1117. SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
  1118. static const struct snd_kcontrol_new adcl_mux =
  1119. SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
  1120. static const struct snd_kcontrol_new adcr_mux =
  1121. SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
  1122. static const struct snd_kcontrol_new left_speaker_mixer[] = {
  1123. SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
  1124. SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
  1125. SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
  1126. SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
  1127. SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
  1128. };
  1129. static const struct snd_kcontrol_new right_speaker_mixer[] = {
  1130. SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
  1131. SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
  1132. SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
  1133. SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
  1134. SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
  1135. };
  1136. /* Debugging; dump chip status after DAPM transitions */
  1137. static int post_ev(struct snd_soc_dapm_widget *w,
  1138. struct snd_kcontrol *kcontrol, int event)
  1139. {
  1140. struct snd_soc_codec *codec = w->codec;
  1141. dev_dbg(codec->dev, "SRC status: %x\n",
  1142. snd_soc_read(codec,
  1143. WM8994_RATE_STATUS));
  1144. return 0;
  1145. }
  1146. static const struct snd_kcontrol_new aif1adc1l_mix[] = {
  1147. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
  1148. 1, 1, 0),
  1149. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
  1150. 0, 1, 0),
  1151. };
  1152. static const struct snd_kcontrol_new aif1adc1r_mix[] = {
  1153. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  1154. 1, 1, 0),
  1155. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  1156. 0, 1, 0),
  1157. };
  1158. static const struct snd_kcontrol_new aif1adc2l_mix[] = {
  1159. SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
  1160. 1, 1, 0),
  1161. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
  1162. 0, 1, 0),
  1163. };
  1164. static const struct snd_kcontrol_new aif1adc2r_mix[] = {
  1165. SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  1166. 1, 1, 0),
  1167. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  1168. 0, 1, 0),
  1169. };
  1170. static const struct snd_kcontrol_new aif2dac2l_mix[] = {
  1171. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1172. 5, 1, 0),
  1173. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1174. 4, 1, 0),
  1175. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1176. 2, 1, 0),
  1177. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1178. 1, 1, 0),
  1179. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1180. 0, 1, 0),
  1181. };
  1182. static const struct snd_kcontrol_new aif2dac2r_mix[] = {
  1183. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1184. 5, 1, 0),
  1185. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1186. 4, 1, 0),
  1187. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1188. 2, 1, 0),
  1189. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1190. 1, 1, 0),
  1191. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1192. 0, 1, 0),
  1193. };
  1194. #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
  1195. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1196. .info = snd_soc_info_volsw, \
  1197. .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
  1198. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
  1199. static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
  1200. struct snd_ctl_elem_value *ucontrol)
  1201. {
  1202. struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
  1203. struct snd_soc_dapm_widget *w = wlist->widgets[0];
  1204. struct snd_soc_codec *codec = w->codec;
  1205. int ret;
  1206. ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
  1207. wm_hubs_update_class_w(codec);
  1208. return ret;
  1209. }
  1210. static const struct snd_kcontrol_new dac1l_mix[] = {
  1211. WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1212. 5, 1, 0),
  1213. WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1214. 4, 1, 0),
  1215. WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1216. 2, 1, 0),
  1217. WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1218. 1, 1, 0),
  1219. WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1220. 0, 1, 0),
  1221. };
  1222. static const struct snd_kcontrol_new dac1r_mix[] = {
  1223. WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1224. 5, 1, 0),
  1225. WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1226. 4, 1, 0),
  1227. WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1228. 2, 1, 0),
  1229. WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1230. 1, 1, 0),
  1231. WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1232. 0, 1, 0),
  1233. };
  1234. static const char *sidetone_text[] = {
  1235. "ADC/DMIC1", "DMIC2",
  1236. };
  1237. static const struct soc_enum sidetone1_enum =
  1238. SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
  1239. static const struct snd_kcontrol_new sidetone1_mux =
  1240. SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
  1241. static const struct soc_enum sidetone2_enum =
  1242. SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
  1243. static const struct snd_kcontrol_new sidetone2_mux =
  1244. SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
  1245. static const char *aif1dac_text[] = {
  1246. "AIF1DACDAT", "AIF3DACDAT",
  1247. };
  1248. static const struct soc_enum aif1dac_enum =
  1249. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
  1250. static const struct snd_kcontrol_new aif1dac_mux =
  1251. SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
  1252. static const char *aif2dac_text[] = {
  1253. "AIF2DACDAT", "AIF3DACDAT",
  1254. };
  1255. static const struct soc_enum aif2dac_enum =
  1256. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
  1257. static const struct snd_kcontrol_new aif2dac_mux =
  1258. SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
  1259. static const char *aif2adc_text[] = {
  1260. "AIF2ADCDAT", "AIF3DACDAT",
  1261. };
  1262. static const struct soc_enum aif2adc_enum =
  1263. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
  1264. static const struct snd_kcontrol_new aif2adc_mux =
  1265. SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
  1266. static const char *aif3adc_text[] = {
  1267. "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
  1268. };
  1269. static const struct soc_enum wm8994_aif3adc_enum =
  1270. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
  1271. static const struct snd_kcontrol_new wm8994_aif3adc_mux =
  1272. SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
  1273. static const struct soc_enum wm8958_aif3adc_enum =
  1274. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
  1275. static const struct snd_kcontrol_new wm8958_aif3adc_mux =
  1276. SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
  1277. static const char *mono_pcm_out_text[] = {
  1278. "None", "AIF2ADCL", "AIF2ADCR",
  1279. };
  1280. static const struct soc_enum mono_pcm_out_enum =
  1281. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
  1282. static const struct snd_kcontrol_new mono_pcm_out_mux =
  1283. SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
  1284. static const char *aif2dac_src_text[] = {
  1285. "AIF2", "AIF3",
  1286. };
  1287. /* Note that these two control shouldn't be simultaneously switched to AIF3 */
  1288. static const struct soc_enum aif2dacl_src_enum =
  1289. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
  1290. static const struct snd_kcontrol_new aif2dacl_src_mux =
  1291. SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
  1292. static const struct soc_enum aif2dacr_src_enum =
  1293. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
  1294. static const struct snd_kcontrol_new aif2dacr_src_mux =
  1295. SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
  1296. static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
  1297. SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
  1298. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1299. SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
  1300. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1301. SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  1302. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1303. SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  1304. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1305. SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  1306. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1307. SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  1308. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1309. SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
  1310. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1311. SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
  1312. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
  1313. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1314. SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
  1315. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
  1316. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1317. SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
  1318. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1319. SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
  1320. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1321. SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
  1322. };
  1323. static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
  1324. SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
  1325. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1326. SND_SOC_DAPM_PRE_PMD),
  1327. SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
  1328. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1329. SND_SOC_DAPM_PRE_PMD),
  1330. SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
  1331. SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
  1332. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
  1333. SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
  1334. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
  1335. SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
  1336. SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
  1337. };
  1338. static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
  1339. SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
  1340. dac_ev, SND_SOC_DAPM_PRE_PMU),
  1341. SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
  1342. dac_ev, SND_SOC_DAPM_PRE_PMU),
  1343. SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
  1344. dac_ev, SND_SOC_DAPM_PRE_PMU),
  1345. SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
  1346. dac_ev, SND_SOC_DAPM_PRE_PMU),
  1347. };
  1348. static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
  1349. SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
  1350. SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
  1351. SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
  1352. SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
  1353. };
  1354. static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
  1355. SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
  1356. adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
  1357. SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
  1358. adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
  1359. };
  1360. static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
  1361. SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
  1362. SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
  1363. };
  1364. static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
  1365. SND_SOC_DAPM_INPUT("DMIC1DAT"),
  1366. SND_SOC_DAPM_INPUT("DMIC2DAT"),
  1367. SND_SOC_DAPM_INPUT("Clock"),
  1368. SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
  1369. SND_SOC_DAPM_PRE_PMU),
  1370. SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
  1371. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1372. SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
  1373. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1374. SND_SOC_DAPM_PRE_PMD),
  1375. SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
  1376. SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
  1377. SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
  1378. SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
  1379. 0, SND_SOC_NOPM, 9, 0),
  1380. SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
  1381. 0, SND_SOC_NOPM, 8, 0),
  1382. SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
  1383. SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
  1384. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1385. SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
  1386. SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
  1387. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1388. SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
  1389. 0, SND_SOC_NOPM, 11, 0),
  1390. SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
  1391. 0, SND_SOC_NOPM, 10, 0),
  1392. SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
  1393. SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
  1394. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1395. SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
  1396. SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
  1397. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1398. SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
  1399. aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
  1400. SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
  1401. aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
  1402. SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
  1403. aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
  1404. SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
  1405. aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
  1406. SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
  1407. aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
  1408. SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
  1409. aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
  1410. SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
  1411. SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
  1412. SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
  1413. dac1l_mix, ARRAY_SIZE(dac1l_mix)),
  1414. SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
  1415. dac1r_mix, ARRAY_SIZE(dac1r_mix)),
  1416. SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
  1417. SND_SOC_NOPM, 13, 0),
  1418. SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
  1419. SND_SOC_NOPM, 12, 0),
  1420. SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
  1421. SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
  1422. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1423. SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
  1424. SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
  1425. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1426. SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1427. SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1428. SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1429. SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1430. SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
  1431. SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
  1432. SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
  1433. SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1434. SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1435. SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
  1436. SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
  1437. SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
  1438. SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
  1439. SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
  1440. /* Power is done with the muxes since the ADC power also controls the
  1441. * downsampling chain, the chip will automatically manage the analogue
  1442. * specific portions.
  1443. */
  1444. SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
  1445. SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
  1446. SND_SOC_DAPM_POST("Debug log", post_ev),
  1447. };
  1448. static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
  1449. SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
  1450. };
  1451. static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
  1452. SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
  1453. SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
  1454. SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
  1455. SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
  1456. SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
  1457. };
  1458. static const struct snd_soc_dapm_route intercon[] = {
  1459. { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
  1460. { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
  1461. { "DSP1CLK", NULL, "CLK_SYS" },
  1462. { "DSP2CLK", NULL, "CLK_SYS" },
  1463. { "DSPINTCLK", NULL, "CLK_SYS" },
  1464. { "AIF1ADC1L", NULL, "AIF1CLK" },
  1465. { "AIF1ADC1L", NULL, "DSP1CLK" },
  1466. { "AIF1ADC1R", NULL, "AIF1CLK" },
  1467. { "AIF1ADC1R", NULL, "DSP1CLK" },
  1468. { "AIF1ADC1R", NULL, "DSPINTCLK" },
  1469. { "AIF1DAC1L", NULL, "AIF1CLK" },
  1470. { "AIF1DAC1L", NULL, "DSP1CLK" },
  1471. { "AIF1DAC1R", NULL, "AIF1CLK" },
  1472. { "AIF1DAC1R", NULL, "DSP1CLK" },
  1473. { "AIF1DAC1R", NULL, "DSPINTCLK" },
  1474. { "AIF1ADC2L", NULL, "AIF1CLK" },
  1475. { "AIF1ADC2L", NULL, "DSP1CLK" },
  1476. { "AIF1ADC2R", NULL, "AIF1CLK" },
  1477. { "AIF1ADC2R", NULL, "DSP1CLK" },
  1478. { "AIF1ADC2R", NULL, "DSPINTCLK" },
  1479. { "AIF1DAC2L", NULL, "AIF1CLK" },
  1480. { "AIF1DAC2L", NULL, "DSP1CLK" },
  1481. { "AIF1DAC2R", NULL, "AIF1CLK" },
  1482. { "AIF1DAC2R", NULL, "DSP1CLK" },
  1483. { "AIF1DAC2R", NULL, "DSPINTCLK" },
  1484. { "AIF2ADCL", NULL, "AIF2CLK" },
  1485. { "AIF2ADCL", NULL, "DSP2CLK" },
  1486. { "AIF2ADCR", NULL, "AIF2CLK" },
  1487. { "AIF2ADCR", NULL, "DSP2CLK" },
  1488. { "AIF2ADCR", NULL, "DSPINTCLK" },
  1489. { "AIF2DACL", NULL, "AIF2CLK" },
  1490. { "AIF2DACL", NULL, "DSP2CLK" },
  1491. { "AIF2DACR", NULL, "AIF2CLK" },
  1492. { "AIF2DACR", NULL, "DSP2CLK" },
  1493. { "AIF2DACR", NULL, "DSPINTCLK" },
  1494. { "DMIC1L", NULL, "DMIC1DAT" },
  1495. { "DMIC1L", NULL, "CLK_SYS" },
  1496. { "DMIC1R", NULL, "DMIC1DAT" },
  1497. { "DMIC1R", NULL, "CLK_SYS" },
  1498. { "DMIC2L", NULL, "DMIC2DAT" },
  1499. { "DMIC2L", NULL, "CLK_SYS" },
  1500. { "DMIC2R", NULL, "DMIC2DAT" },
  1501. { "DMIC2R", NULL, "CLK_SYS" },
  1502. { "ADCL", NULL, "AIF1CLK" },
  1503. { "ADCL", NULL, "DSP1CLK" },
  1504. { "ADCL", NULL, "DSPINTCLK" },
  1505. { "ADCR", NULL, "AIF1CLK" },
  1506. { "ADCR", NULL, "DSP1CLK" },
  1507. { "ADCR", NULL, "DSPINTCLK" },
  1508. { "ADCL Mux", "ADC", "ADCL" },
  1509. { "ADCL Mux", "DMIC", "DMIC1L" },
  1510. { "ADCR Mux", "ADC", "ADCR" },
  1511. { "ADCR Mux", "DMIC", "DMIC1R" },
  1512. { "DAC1L", NULL, "AIF1CLK" },
  1513. { "DAC1L", NULL, "DSP1CLK" },
  1514. { "DAC1L", NULL, "DSPINTCLK" },
  1515. { "DAC1R", NULL, "AIF1CLK" },
  1516. { "DAC1R", NULL, "DSP1CLK" },
  1517. { "DAC1R", NULL, "DSPINTCLK" },
  1518. { "DAC2L", NULL, "AIF2CLK" },
  1519. { "DAC2L", NULL, "DSP2CLK" },
  1520. { "DAC2L", NULL, "DSPINTCLK" },
  1521. { "DAC2R", NULL, "AIF2DACR" },
  1522. { "DAC2R", NULL, "AIF2CLK" },
  1523. { "DAC2R", NULL, "DSP2CLK" },
  1524. { "DAC2R", NULL, "DSPINTCLK" },
  1525. { "TOCLK", NULL, "CLK_SYS" },
  1526. { "AIF1DACDAT", NULL, "AIF1 Playback" },
  1527. { "AIF2DACDAT", NULL, "AIF2 Playback" },
  1528. { "AIF3DACDAT", NULL, "AIF3 Playback" },
  1529. { "AIF1 Capture", NULL, "AIF1ADCDAT" },
  1530. { "AIF2 Capture", NULL, "AIF2ADCDAT" },
  1531. { "AIF3 Capture", NULL, "AIF3ADCDAT" },
  1532. /* AIF1 outputs */
  1533. { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
  1534. { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
  1535. { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
  1536. { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
  1537. { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
  1538. { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
  1539. { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
  1540. { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
  1541. { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
  1542. { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
  1543. { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
  1544. { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
  1545. /* Pin level routing for AIF3 */
  1546. { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
  1547. { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
  1548. { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
  1549. { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
  1550. { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
  1551. { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
  1552. { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
  1553. { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
  1554. { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
  1555. { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
  1556. { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
  1557. /* DAC1 inputs */
  1558. { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
  1559. { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  1560. { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  1561. { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1562. { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1563. { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
  1564. { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  1565. { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  1566. { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1567. { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1568. /* DAC2/AIF2 outputs */
  1569. { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
  1570. { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
  1571. { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  1572. { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  1573. { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1574. { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1575. { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
  1576. { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
  1577. { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  1578. { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  1579. { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1580. { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1581. { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
  1582. { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
  1583. { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
  1584. { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
  1585. { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
  1586. /* AIF3 output */
  1587. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
  1588. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
  1589. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
  1590. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
  1591. { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
  1592. { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
  1593. { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
  1594. { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
  1595. /* Sidetone */
  1596. { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
  1597. { "Left Sidetone", "DMIC2", "DMIC2L" },
  1598. { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
  1599. { "Right Sidetone", "DMIC2", "DMIC2R" },
  1600. /* Output stages */
  1601. { "Left Output Mixer", "DAC Switch", "DAC1L" },
  1602. { "Right Output Mixer", "DAC Switch", "DAC1R" },
  1603. { "SPKL", "DAC1 Switch", "DAC1L" },
  1604. { "SPKL", "DAC2 Switch", "DAC2L" },
  1605. { "SPKR", "DAC1 Switch", "DAC1R" },
  1606. { "SPKR", "DAC2 Switch", "DAC2R" },
  1607. { "Left Headphone Mux", "DAC", "DAC1L" },
  1608. { "Right Headphone Mux", "DAC", "DAC1R" },
  1609. };
  1610. static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
  1611. { "DAC1L", NULL, "Late DAC1L Enable PGA" },
  1612. { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
  1613. { "DAC1R", NULL, "Late DAC1R Enable PGA" },
  1614. { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
  1615. { "DAC2L", NULL, "Late DAC2L Enable PGA" },
  1616. { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
  1617. { "DAC2R", NULL, "Late DAC2R Enable PGA" },
  1618. { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
  1619. };
  1620. static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
  1621. { "DAC1L", NULL, "DAC1L Mixer" },
  1622. { "DAC1R", NULL, "DAC1R Mixer" },
  1623. { "DAC2L", NULL, "AIF2DAC2L Mixer" },
  1624. { "DAC2R", NULL, "AIF2DAC2R Mixer" },
  1625. };
  1626. static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
  1627. { "AIF1DACDAT", NULL, "AIF2DACDAT" },
  1628. { "AIF2DACDAT", NULL, "AIF1DACDAT" },
  1629. { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
  1630. { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
  1631. { "MICBIAS1", NULL, "CLK_SYS" },
  1632. { "MICBIAS1", NULL, "MICBIAS Supply" },
  1633. { "MICBIAS2", NULL, "CLK_SYS" },
  1634. { "MICBIAS2", NULL, "MICBIAS Supply" },
  1635. };
  1636. static const struct snd_soc_dapm_route wm8994_intercon[] = {
  1637. { "AIF2DACL", NULL, "AIF2DAC Mux" },
  1638. { "AIF2DACR", NULL, "AIF2DAC Mux" },
  1639. { "MICBIAS1", NULL, "VMID" },
  1640. { "MICBIAS2", NULL, "VMID" },
  1641. };
  1642. static const struct snd_soc_dapm_route wm8958_intercon[] = {
  1643. { "AIF2DACL", NULL, "AIF2DACL Mux" },
  1644. { "AIF2DACR", NULL, "AIF2DACR Mux" },
  1645. { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
  1646. { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
  1647. { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
  1648. { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
  1649. { "AIF3DACDAT", NULL, "AIF3" },
  1650. { "AIF3ADCDAT", NULL, "AIF3" },
  1651. { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
  1652. { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
  1653. { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
  1654. };
  1655. /* The size in bits of the FLL divide multiplied by 10
  1656. * to allow rounding later */
  1657. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1658. struct fll_div {
  1659. u16 outdiv;
  1660. u16 n;
  1661. u16 k;
  1662. u16 clk_ref_div;
  1663. u16 fll_fratio;
  1664. };
  1665. static int wm8994_get_fll_config(struct fll_div *fll,
  1666. int freq_in, int freq_out)
  1667. {
  1668. u64 Kpart;
  1669. unsigned int K, Ndiv, Nmod;
  1670. pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
  1671. /* Scale the input frequency down to <= 13.5MHz */
  1672. fll->clk_ref_div = 0;
  1673. while (freq_in > 13500000) {
  1674. fll->clk_ref_div++;
  1675. freq_in /= 2;
  1676. if (fll->clk_ref_div > 3)
  1677. return -EINVAL;
  1678. }
  1679. pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
  1680. /* Scale the output to give 90MHz<=Fvco<=100MHz */
  1681. fll->outdiv = 3;
  1682. while (freq_out * (fll->outdiv + 1) < 90000000) {
  1683. fll->outdiv++;
  1684. if (fll->outdiv > 63)
  1685. return -EINVAL;
  1686. }
  1687. freq_out *= fll->outdiv + 1;
  1688. pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
  1689. if (freq_in > 1000000) {
  1690. fll->fll_fratio = 0;
  1691. } else if (freq_in > 256000) {
  1692. fll->fll_fratio = 1;
  1693. freq_in *= 2;
  1694. } else if (freq_in > 128000) {
  1695. fll->fll_fratio = 2;
  1696. freq_in *= 4;
  1697. } else if (freq_in > 64000) {
  1698. fll->fll_fratio = 3;
  1699. freq_in *= 8;
  1700. } else {
  1701. fll->fll_fratio = 4;
  1702. freq_in *= 16;
  1703. }
  1704. pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
  1705. /* Now, calculate N.K */
  1706. Ndiv = freq_out / freq_in;
  1707. fll->n = Ndiv;
  1708. Nmod = freq_out % freq_in;
  1709. pr_debug("Nmod=%d\n", Nmod);
  1710. /* Calculate fractional part - scale up so we can round. */
  1711. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  1712. do_div(Kpart, freq_in);
  1713. K = Kpart & 0xFFFFFFFF;
  1714. if ((K % 10) >= 5)
  1715. K += 5;
  1716. /* Move down to proper range now rounding is done */
  1717. fll->k = K / 10;
  1718. pr_debug("N=%x K=%x\n", fll->n, fll->k);
  1719. return 0;
  1720. }
  1721. static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
  1722. unsigned int freq_in, unsigned int freq_out)
  1723. {
  1724. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1725. struct wm8994 *control = wm8994->wm8994;
  1726. int reg_offset, ret;
  1727. struct fll_div fll;
  1728. u16 reg, clk1, aif_reg, aif_src;
  1729. unsigned long timeout;
  1730. bool was_enabled;
  1731. switch (id) {
  1732. case WM8994_FLL1:
  1733. reg_offset = 0;
  1734. id = 0;
  1735. aif_src = 0x10;
  1736. break;
  1737. case WM8994_FLL2:
  1738. reg_offset = 0x20;
  1739. id = 1;
  1740. aif_src = 0x18;
  1741. break;
  1742. default:
  1743. return -EINVAL;
  1744. }
  1745. reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
  1746. was_enabled = reg & WM8994_FLL1_ENA;
  1747. switch (src) {
  1748. case 0:
  1749. /* Allow no source specification when stopping */
  1750. if (freq_out)
  1751. return -EINVAL;
  1752. src = wm8994->fll[id].src;
  1753. break;
  1754. case WM8994_FLL_SRC_MCLK1:
  1755. case WM8994_FLL_SRC_MCLK2:
  1756. case WM8994_FLL_SRC_LRCLK:
  1757. case WM8994_FLL_SRC_BCLK:
  1758. break;
  1759. case WM8994_FLL_SRC_INTERNAL:
  1760. freq_in = 12000000;
  1761. freq_out = 12000000;
  1762. break;
  1763. default:
  1764. return -EINVAL;
  1765. }
  1766. /* Are we changing anything? */
  1767. if (wm8994->fll[id].src == src &&
  1768. wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
  1769. return 0;
  1770. /* If we're stopping the FLL redo the old config - no
  1771. * registers will actually be written but we avoid GCC flow
  1772. * analysis bugs spewing warnings.
  1773. */
  1774. if (freq_out)
  1775. ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
  1776. else
  1777. ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
  1778. wm8994->fll[id].out);
  1779. if (ret < 0)
  1780. return ret;
  1781. /* Make sure that we're not providing SYSCLK right now */
  1782. clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
  1783. if (clk1 & WM8994_SYSCLK_SRC)
  1784. aif_reg = WM8994_AIF2_CLOCKING_1;
  1785. else
  1786. aif_reg = WM8994_AIF1_CLOCKING_1;
  1787. reg = snd_soc_read(codec, aif_reg);
  1788. if ((reg & WM8994_AIF1CLK_ENA) &&
  1789. (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
  1790. dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
  1791. id + 1);
  1792. return -EBUSY;
  1793. }
  1794. /* We always need to disable the FLL while reconfiguring */
  1795. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
  1796. WM8994_FLL1_ENA, 0);
  1797. if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
  1798. freq_in == freq_out && freq_out) {
  1799. dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
  1800. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
  1801. WM8958_FLL1_BYP, WM8958_FLL1_BYP);
  1802. goto out;
  1803. }
  1804. reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
  1805. (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
  1806. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
  1807. WM8994_FLL1_OUTDIV_MASK |
  1808. WM8994_FLL1_FRATIO_MASK, reg);
  1809. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
  1810. WM8994_FLL1_K_MASK, fll.k);
  1811. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
  1812. WM8994_FLL1_N_MASK,
  1813. fll.n << WM8994_FLL1_N_SHIFT);
  1814. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
  1815. WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
  1816. WM8994_FLL1_REFCLK_DIV_MASK |
  1817. WM8994_FLL1_REFCLK_SRC_MASK,
  1818. ((src == WM8994_FLL_SRC_INTERNAL)
  1819. << WM8994_FLL1_FRC_NCO_SHIFT) |
  1820. (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
  1821. (src - 1));
  1822. /* Clear any pending completion from a previous failure */
  1823. try_wait_for_completion(&wm8994->fll_locked[id]);
  1824. /* Enable (with fractional mode if required) */
  1825. if (freq_out) {
  1826. /* Enable VMID if we need it */
  1827. if (!was_enabled) {
  1828. active_reference(codec);
  1829. switch (control->type) {
  1830. case WM8994:
  1831. vmid_reference(codec);
  1832. break;
  1833. case WM8958:
  1834. if (wm8994->revision < 1)
  1835. vmid_reference(codec);
  1836. break;
  1837. default:
  1838. break;
  1839. }
  1840. }
  1841. reg = WM8994_FLL1_ENA;
  1842. if (fll.k)
  1843. reg |= WM8994_FLL1_FRAC;
  1844. if (src == WM8994_FLL_SRC_INTERNAL)
  1845. reg |= WM8994_FLL1_OSC_ENA;
  1846. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
  1847. WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
  1848. WM8994_FLL1_FRAC, reg);
  1849. if (wm8994->fll_locked_irq) {
  1850. timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
  1851. msecs_to_jiffies(10));
  1852. if (timeout == 0)
  1853. dev_warn(codec->dev,
  1854. "Timed out waiting for FLL lock\n");
  1855. } else {
  1856. msleep(5);
  1857. }
  1858. } else {
  1859. if (was_enabled) {
  1860. switch (control->type) {
  1861. case WM8994:
  1862. vmid_dereference(codec);
  1863. break;
  1864. case WM8958:
  1865. if (wm8994->revision < 1)
  1866. vmid_dereference(codec);
  1867. break;
  1868. default:
  1869. break;
  1870. }
  1871. active_dereference(codec);
  1872. }
  1873. }
  1874. out:
  1875. wm8994->fll[id].in = freq_in;
  1876. wm8994->fll[id].out = freq_out;
  1877. wm8994->fll[id].src = src;
  1878. configure_clock(codec);
  1879. return 0;
  1880. }
  1881. static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
  1882. {
  1883. struct completion *completion = data;
  1884. complete(completion);
  1885. return IRQ_HANDLED;
  1886. }
  1887. static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
  1888. static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
  1889. unsigned int freq_in, unsigned int freq_out)
  1890. {
  1891. return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
  1892. }
  1893. static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
  1894. int clk_id, unsigned int freq, int dir)
  1895. {
  1896. struct snd_soc_codec *codec = dai->codec;
  1897. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1898. int i;
  1899. switch (dai->id) {
  1900. case 1:
  1901. case 2:
  1902. break;
  1903. default:
  1904. /* AIF3 shares clocking with AIF1/2 */
  1905. return -EINVAL;
  1906. }
  1907. switch (clk_id) {
  1908. case WM8994_SYSCLK_MCLK1:
  1909. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
  1910. wm8994->mclk[0] = freq;
  1911. dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
  1912. dai->id, freq);
  1913. break;
  1914. case WM8994_SYSCLK_MCLK2:
  1915. /* TODO: Set GPIO AF */
  1916. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
  1917. wm8994->mclk[1] = freq;
  1918. dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
  1919. dai->id, freq);
  1920. break;
  1921. case WM8994_SYSCLK_FLL1:
  1922. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
  1923. dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
  1924. break;
  1925. case WM8994_SYSCLK_FLL2:
  1926. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
  1927. dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
  1928. break;
  1929. case WM8994_SYSCLK_OPCLK:
  1930. /* Special case - a division (times 10) is given and
  1931. * no effect on main clocking.
  1932. */
  1933. if (freq) {
  1934. for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
  1935. if (opclk_divs[i] == freq)
  1936. break;
  1937. if (i == ARRAY_SIZE(opclk_divs))
  1938. return -EINVAL;
  1939. snd_soc_update_bits(codec, WM8994_CLOCKING_2,
  1940. WM8994_OPCLK_DIV_MASK, i);
  1941. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
  1942. WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
  1943. } else {
  1944. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
  1945. WM8994_OPCLK_ENA, 0);
  1946. }
  1947. default:
  1948. return -EINVAL;
  1949. }
  1950. configure_clock(codec);
  1951. return 0;
  1952. }
  1953. static int wm8994_set_bias_level(struct snd_soc_codec *codec,
  1954. enum snd_soc_bias_level level)
  1955. {
  1956. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1957. struct wm8994 *control = wm8994->wm8994;
  1958. wm_hubs_set_bias_level(codec, level);
  1959. switch (level) {
  1960. case SND_SOC_BIAS_ON:
  1961. break;
  1962. case SND_SOC_BIAS_PREPARE:
  1963. /* MICBIAS into regulating mode */
  1964. switch (control->type) {
  1965. case WM8958:
  1966. case WM1811:
  1967. snd_soc_update_bits(codec, WM8958_MICBIAS1,
  1968. WM8958_MICB1_MODE, 0);
  1969. snd_soc_update_bits(codec, WM8958_MICBIAS2,
  1970. WM8958_MICB2_MODE, 0);
  1971. break;
  1972. default:
  1973. break;
  1974. }
  1975. if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
  1976. active_reference(codec);
  1977. break;
  1978. case SND_SOC_BIAS_STANDBY:
  1979. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  1980. switch (control->type) {
  1981. case WM8958:
  1982. if (wm8994->revision == 0) {
  1983. /* Optimise performance for rev A */
  1984. snd_soc_update_bits(codec,
  1985. WM8958_CHARGE_PUMP_2,
  1986. WM8958_CP_DISCH,
  1987. WM8958_CP_DISCH);
  1988. }
  1989. break;
  1990. default:
  1991. break;
  1992. }
  1993. /* Discharge LINEOUT1 & 2 */
  1994. snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
  1995. WM8994_LINEOUT1_DISCH |
  1996. WM8994_LINEOUT2_DISCH,
  1997. WM8994_LINEOUT1_DISCH |
  1998. WM8994_LINEOUT2_DISCH);
  1999. }
  2000. if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
  2001. active_dereference(codec);
  2002. /* MICBIAS into bypass mode on newer devices */
  2003. switch (control->type) {
  2004. case WM8958:
  2005. case WM1811:
  2006. snd_soc_update_bits(codec, WM8958_MICBIAS1,
  2007. WM8958_MICB1_MODE,
  2008. WM8958_MICB1_MODE);
  2009. snd_soc_update_bits(codec, WM8958_MICBIAS2,
  2010. WM8958_MICB2_MODE,
  2011. WM8958_MICB2_MODE);
  2012. break;
  2013. default:
  2014. break;
  2015. }
  2016. break;
  2017. case SND_SOC_BIAS_OFF:
  2018. if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
  2019. wm8994->cur_fw = NULL;
  2020. break;
  2021. }
  2022. codec->dapm.bias_level = level;
  2023. return 0;
  2024. }
  2025. int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
  2026. {
  2027. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2028. switch (mode) {
  2029. case WM8994_VMID_NORMAL:
  2030. if (wm8994->hubs.lineout1_se) {
  2031. snd_soc_dapm_disable_pin(&codec->dapm,
  2032. "LINEOUT1N Driver");
  2033. snd_soc_dapm_disable_pin(&codec->dapm,
  2034. "LINEOUT1P Driver");
  2035. }
  2036. if (wm8994->hubs.lineout2_se) {
  2037. snd_soc_dapm_disable_pin(&codec->dapm,
  2038. "LINEOUT2N Driver");
  2039. snd_soc_dapm_disable_pin(&codec->dapm,
  2040. "LINEOUT2P Driver");
  2041. }
  2042. /* Do the sync with the old mode to allow it to clean up */
  2043. snd_soc_dapm_sync(&codec->dapm);
  2044. wm8994->vmid_mode = mode;
  2045. break;
  2046. case WM8994_VMID_FORCE:
  2047. if (wm8994->hubs.lineout1_se) {
  2048. snd_soc_dapm_force_enable_pin(&codec->dapm,
  2049. "LINEOUT1N Driver");
  2050. snd_soc_dapm_force_enable_pin(&codec->dapm,
  2051. "LINEOUT1P Driver");
  2052. }
  2053. if (wm8994->hubs.lineout2_se) {
  2054. snd_soc_dapm_force_enable_pin(&codec->dapm,
  2055. "LINEOUT2N Driver");
  2056. snd_soc_dapm_force_enable_pin(&codec->dapm,
  2057. "LINEOUT2P Driver");
  2058. }
  2059. wm8994->vmid_mode = mode;
  2060. snd_soc_dapm_sync(&codec->dapm);
  2061. break;
  2062. default:
  2063. return -EINVAL;
  2064. }
  2065. return 0;
  2066. }
  2067. static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  2068. {
  2069. struct snd_soc_codec *codec = dai->codec;
  2070. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2071. struct wm8994 *control = wm8994->wm8994;
  2072. int ms_reg;
  2073. int aif1_reg;
  2074. int ms = 0;
  2075. int aif1 = 0;
  2076. switch (dai->id) {
  2077. case 1:
  2078. ms_reg = WM8994_AIF1_MASTER_SLAVE;
  2079. aif1_reg = WM8994_AIF1_CONTROL_1;
  2080. break;
  2081. case 2:
  2082. ms_reg = WM8994_AIF2_MASTER_SLAVE;
  2083. aif1_reg = WM8994_AIF2_CONTROL_1;
  2084. break;
  2085. default:
  2086. return -EINVAL;
  2087. }
  2088. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  2089. case SND_SOC_DAIFMT_CBS_CFS:
  2090. break;
  2091. case SND_SOC_DAIFMT_CBM_CFM:
  2092. ms = WM8994_AIF1_MSTR;
  2093. break;
  2094. default:
  2095. return -EINVAL;
  2096. }
  2097. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2098. case SND_SOC_DAIFMT_DSP_B:
  2099. aif1 |= WM8994_AIF1_LRCLK_INV;
  2100. case SND_SOC_DAIFMT_DSP_A:
  2101. aif1 |= 0x18;
  2102. break;
  2103. case SND_SOC_DAIFMT_I2S:
  2104. aif1 |= 0x10;
  2105. break;
  2106. case SND_SOC_DAIFMT_RIGHT_J:
  2107. break;
  2108. case SND_SOC_DAIFMT_LEFT_J:
  2109. aif1 |= 0x8;
  2110. break;
  2111. default:
  2112. return -EINVAL;
  2113. }
  2114. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2115. case SND_SOC_DAIFMT_DSP_A:
  2116. case SND_SOC_DAIFMT_DSP_B:
  2117. /* frame inversion not valid for DSP modes */
  2118. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2119. case SND_SOC_DAIFMT_NB_NF:
  2120. break;
  2121. case SND_SOC_DAIFMT_IB_NF:
  2122. aif1 |= WM8994_AIF1_BCLK_INV;
  2123. break;
  2124. default:
  2125. return -EINVAL;
  2126. }
  2127. break;
  2128. case SND_SOC_DAIFMT_I2S:
  2129. case SND_SOC_DAIFMT_RIGHT_J:
  2130. case SND_SOC_DAIFMT_LEFT_J:
  2131. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2132. case SND_SOC_DAIFMT_NB_NF:
  2133. break;
  2134. case SND_SOC_DAIFMT_IB_IF:
  2135. aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
  2136. break;
  2137. case SND_SOC_DAIFMT_IB_NF:
  2138. aif1 |= WM8994_AIF1_BCLK_INV;
  2139. break;
  2140. case SND_SOC_DAIFMT_NB_IF:
  2141. aif1 |= WM8994_AIF1_LRCLK_INV;
  2142. break;
  2143. default:
  2144. return -EINVAL;
  2145. }
  2146. break;
  2147. default:
  2148. return -EINVAL;
  2149. }
  2150. /* The AIF2 format configuration needs to be mirrored to AIF3
  2151. * on WM8958 if it's in use so just do it all the time. */
  2152. switch (control->type) {
  2153. case WM1811:
  2154. case WM8958:
  2155. if (dai->id == 2)
  2156. snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
  2157. WM8994_AIF1_LRCLK_INV |
  2158. WM8958_AIF3_FMT_MASK, aif1);
  2159. break;
  2160. default:
  2161. break;
  2162. }
  2163. snd_soc_update_bits(codec, aif1_reg,
  2164. WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
  2165. WM8994_AIF1_FMT_MASK,
  2166. aif1);
  2167. snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
  2168. ms);
  2169. return 0;
  2170. }
  2171. static struct {
  2172. int val, rate;
  2173. } srs[] = {
  2174. { 0, 8000 },
  2175. { 1, 11025 },
  2176. { 2, 12000 },
  2177. { 3, 16000 },
  2178. { 4, 22050 },
  2179. { 5, 24000 },
  2180. { 6, 32000 },
  2181. { 7, 44100 },
  2182. { 8, 48000 },
  2183. { 9, 88200 },
  2184. { 10, 96000 },
  2185. };
  2186. static int fs_ratios[] = {
  2187. 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
  2188. };
  2189. static int bclk_divs[] = {
  2190. 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
  2191. 640, 880, 960, 1280, 1760, 1920
  2192. };
  2193. static int wm8994_hw_params(struct snd_pcm_substream *substream,
  2194. struct snd_pcm_hw_params *params,
  2195. struct snd_soc_dai *dai)
  2196. {
  2197. struct snd_soc_codec *codec = dai->codec;
  2198. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2199. int aif1_reg;
  2200. int aif2_reg;
  2201. int bclk_reg;
  2202. int lrclk_reg;
  2203. int rate_reg;
  2204. int aif1 = 0;
  2205. int aif2 = 0;
  2206. int bclk = 0;
  2207. int lrclk = 0;
  2208. int rate_val = 0;
  2209. int id = dai->id - 1;
  2210. int i, cur_val, best_val, bclk_rate, best;
  2211. switch (dai->id) {
  2212. case 1:
  2213. aif1_reg = WM8994_AIF1_CONTROL_1;
  2214. aif2_reg = WM8994_AIF1_CONTROL_2;
  2215. bclk_reg = WM8994_AIF1_BCLK;
  2216. rate_reg = WM8994_AIF1_RATE;
  2217. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  2218. wm8994->lrclk_shared[0]) {
  2219. lrclk_reg = WM8994_AIF1DAC_LRCLK;
  2220. } else {
  2221. lrclk_reg = WM8994_AIF1ADC_LRCLK;
  2222. dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
  2223. }
  2224. break;
  2225. case 2:
  2226. aif1_reg = WM8994_AIF2_CONTROL_1;
  2227. aif2_reg = WM8994_AIF2_CONTROL_2;
  2228. bclk_reg = WM8994_AIF2_BCLK;
  2229. rate_reg = WM8994_AIF2_RATE;
  2230. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  2231. wm8994->lrclk_shared[1]) {
  2232. lrclk_reg = WM8994_AIF2DAC_LRCLK;
  2233. } else {
  2234. lrclk_reg = WM8994_AIF2ADC_LRCLK;
  2235. dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
  2236. }
  2237. break;
  2238. default:
  2239. return -EINVAL;
  2240. }
  2241. bclk_rate = params_rate(params) * 4;
  2242. switch (params_format(params)) {
  2243. case SNDRV_PCM_FORMAT_S16_LE:
  2244. bclk_rate *= 16;
  2245. break;
  2246. case SNDRV_PCM_FORMAT_S20_3LE:
  2247. bclk_rate *= 20;
  2248. aif1 |= 0x20;
  2249. break;
  2250. case SNDRV_PCM_FORMAT_S24_LE:
  2251. bclk_rate *= 24;
  2252. aif1 |= 0x40;
  2253. break;
  2254. case SNDRV_PCM_FORMAT_S32_LE:
  2255. bclk_rate *= 32;
  2256. aif1 |= 0x60;
  2257. break;
  2258. default:
  2259. return -EINVAL;
  2260. }
  2261. /* Try to find an appropriate sample rate; look for an exact match. */
  2262. for (i = 0; i < ARRAY_SIZE(srs); i++)
  2263. if (srs[i].rate == params_rate(params))
  2264. break;
  2265. if (i == ARRAY_SIZE(srs))
  2266. return -EINVAL;
  2267. rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
  2268. dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
  2269. dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
  2270. dai->id, wm8994->aifclk[id], bclk_rate);
  2271. if (params_channels(params) == 1 &&
  2272. (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
  2273. aif2 |= WM8994_AIF1_MONO;
  2274. if (wm8994->aifclk[id] == 0) {
  2275. dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
  2276. return -EINVAL;
  2277. }
  2278. /* AIFCLK/fs ratio; look for a close match in either direction */
  2279. best = 0;
  2280. best_val = abs((fs_ratios[0] * params_rate(params))
  2281. - wm8994->aifclk[id]);
  2282. for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
  2283. cur_val = abs((fs_ratios[i] * params_rate(params))
  2284. - wm8994->aifclk[id]);
  2285. if (cur_val >= best_val)
  2286. continue;
  2287. best = i;
  2288. best_val = cur_val;
  2289. }
  2290. dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
  2291. dai->id, fs_ratios[best]);
  2292. rate_val |= best;
  2293. /* We may not get quite the right frequency if using
  2294. * approximate clocks so look for the closest match that is
  2295. * higher than the target (we need to ensure that there enough
  2296. * BCLKs to clock out the samples).
  2297. */
  2298. best = 0;
  2299. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  2300. cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
  2301. if (cur_val < 0) /* BCLK table is sorted */
  2302. break;
  2303. best = i;
  2304. }
  2305. bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
  2306. dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
  2307. bclk_divs[best], bclk_rate);
  2308. bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
  2309. lrclk = bclk_rate / params_rate(params);
  2310. if (!lrclk) {
  2311. dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
  2312. bclk_rate);
  2313. return -EINVAL;
  2314. }
  2315. dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
  2316. lrclk, bclk_rate / lrclk);
  2317. snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
  2318. snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
  2319. snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
  2320. snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
  2321. lrclk);
  2322. snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
  2323. WM8994_AIF1CLK_RATE_MASK, rate_val);
  2324. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2325. switch (dai->id) {
  2326. case 1:
  2327. wm8994->dac_rates[0] = params_rate(params);
  2328. wm8994_set_retune_mobile(codec, 0);
  2329. wm8994_set_retune_mobile(codec, 1);
  2330. break;
  2331. case 2:
  2332. wm8994->dac_rates[1] = params_rate(params);
  2333. wm8994_set_retune_mobile(codec, 2);
  2334. break;
  2335. }
  2336. }
  2337. return 0;
  2338. }
  2339. static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
  2340. struct snd_pcm_hw_params *params,
  2341. struct snd_soc_dai *dai)
  2342. {
  2343. struct snd_soc_codec *codec = dai->codec;
  2344. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2345. struct wm8994 *control = wm8994->wm8994;
  2346. int aif1_reg;
  2347. int aif1 = 0;
  2348. switch (dai->id) {
  2349. case 3:
  2350. switch (control->type) {
  2351. case WM1811:
  2352. case WM8958:
  2353. aif1_reg = WM8958_AIF3_CONTROL_1;
  2354. break;
  2355. default:
  2356. return 0;
  2357. }
  2358. default:
  2359. return 0;
  2360. }
  2361. switch (params_format(params)) {
  2362. case SNDRV_PCM_FORMAT_S16_LE:
  2363. break;
  2364. case SNDRV_PCM_FORMAT_S20_3LE:
  2365. aif1 |= 0x20;
  2366. break;
  2367. case SNDRV_PCM_FORMAT_S24_LE:
  2368. aif1 |= 0x40;
  2369. break;
  2370. case SNDRV_PCM_FORMAT_S32_LE:
  2371. aif1 |= 0x60;
  2372. break;
  2373. default:
  2374. return -EINVAL;
  2375. }
  2376. return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
  2377. }
  2378. static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
  2379. {
  2380. struct snd_soc_codec *codec = codec_dai->codec;
  2381. int mute_reg;
  2382. int reg;
  2383. switch (codec_dai->id) {
  2384. case 1:
  2385. mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
  2386. break;
  2387. case 2:
  2388. mute_reg = WM8994_AIF2_DAC_FILTERS_1;
  2389. break;
  2390. default:
  2391. return -EINVAL;
  2392. }
  2393. if (mute)
  2394. reg = WM8994_AIF1DAC1_MUTE;
  2395. else
  2396. reg = 0;
  2397. snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
  2398. return 0;
  2399. }
  2400. static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
  2401. {
  2402. struct snd_soc_codec *codec = codec_dai->codec;
  2403. int reg, val, mask;
  2404. switch (codec_dai->id) {
  2405. case 1:
  2406. reg = WM8994_AIF1_MASTER_SLAVE;
  2407. mask = WM8994_AIF1_TRI;
  2408. break;
  2409. case 2:
  2410. reg = WM8994_AIF2_MASTER_SLAVE;
  2411. mask = WM8994_AIF2_TRI;
  2412. break;
  2413. default:
  2414. return -EINVAL;
  2415. }
  2416. if (tristate)
  2417. val = mask;
  2418. else
  2419. val = 0;
  2420. return snd_soc_update_bits(codec, reg, mask, val);
  2421. }
  2422. static int wm8994_aif2_probe(struct snd_soc_dai *dai)
  2423. {
  2424. struct snd_soc_codec *codec = dai->codec;
  2425. /* Disable the pulls on the AIF if we're using it to save power. */
  2426. snd_soc_update_bits(codec, WM8994_GPIO_3,
  2427. WM8994_GPN_PU | WM8994_GPN_PD, 0);
  2428. snd_soc_update_bits(codec, WM8994_GPIO_4,
  2429. WM8994_GPN_PU | WM8994_GPN_PD, 0);
  2430. snd_soc_update_bits(codec, WM8994_GPIO_5,
  2431. WM8994_GPN_PU | WM8994_GPN_PD, 0);
  2432. return 0;
  2433. }
  2434. #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
  2435. #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  2436. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  2437. static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
  2438. .set_sysclk = wm8994_set_dai_sysclk,
  2439. .set_fmt = wm8994_set_dai_fmt,
  2440. .hw_params = wm8994_hw_params,
  2441. .digital_mute = wm8994_aif_mute,
  2442. .set_pll = wm8994_set_fll,
  2443. .set_tristate = wm8994_set_tristate,
  2444. };
  2445. static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
  2446. .set_sysclk = wm8994_set_dai_sysclk,
  2447. .set_fmt = wm8994_set_dai_fmt,
  2448. .hw_params = wm8994_hw_params,
  2449. .digital_mute = wm8994_aif_mute,
  2450. .set_pll = wm8994_set_fll,
  2451. .set_tristate = wm8994_set_tristate,
  2452. };
  2453. static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
  2454. .hw_params = wm8994_aif3_hw_params,
  2455. };
  2456. static struct snd_soc_dai_driver wm8994_dai[] = {
  2457. {
  2458. .name = "wm8994-aif1",
  2459. .id = 1,
  2460. .playback = {
  2461. .stream_name = "AIF1 Playback",
  2462. .channels_min = 1,
  2463. .channels_max = 2,
  2464. .rates = WM8994_RATES,
  2465. .formats = WM8994_FORMATS,
  2466. .sig_bits = 24,
  2467. },
  2468. .capture = {
  2469. .stream_name = "AIF1 Capture",
  2470. .channels_min = 1,
  2471. .channels_max = 2,
  2472. .rates = WM8994_RATES,
  2473. .formats = WM8994_FORMATS,
  2474. .sig_bits = 24,
  2475. },
  2476. .ops = &wm8994_aif1_dai_ops,
  2477. },
  2478. {
  2479. .name = "wm8994-aif2",
  2480. .id = 2,
  2481. .playback = {
  2482. .stream_name = "AIF2 Playback",
  2483. .channels_min = 1,
  2484. .channels_max = 2,
  2485. .rates = WM8994_RATES,
  2486. .formats = WM8994_FORMATS,
  2487. .sig_bits = 24,
  2488. },
  2489. .capture = {
  2490. .stream_name = "AIF2 Capture",
  2491. .channels_min = 1,
  2492. .channels_max = 2,
  2493. .rates = WM8994_RATES,
  2494. .formats = WM8994_FORMATS,
  2495. .sig_bits = 24,
  2496. },
  2497. .probe = wm8994_aif2_probe,
  2498. .ops = &wm8994_aif2_dai_ops,
  2499. },
  2500. {
  2501. .name = "wm8994-aif3",
  2502. .id = 3,
  2503. .playback = {
  2504. .stream_name = "AIF3 Playback",
  2505. .channels_min = 1,
  2506. .channels_max = 2,
  2507. .rates = WM8994_RATES,
  2508. .formats = WM8994_FORMATS,
  2509. .sig_bits = 24,
  2510. },
  2511. .capture = {
  2512. .stream_name = "AIF3 Capture",
  2513. .channels_min = 1,
  2514. .channels_max = 2,
  2515. .rates = WM8994_RATES,
  2516. .formats = WM8994_FORMATS,
  2517. .sig_bits = 24,
  2518. },
  2519. .ops = &wm8994_aif3_dai_ops,
  2520. }
  2521. };
  2522. #ifdef CONFIG_PM
  2523. static int wm8994_codec_suspend(struct snd_soc_codec *codec)
  2524. {
  2525. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2526. int i, ret;
  2527. for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
  2528. memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
  2529. sizeof(struct wm8994_fll_config));
  2530. ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
  2531. if (ret < 0)
  2532. dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
  2533. i + 1, ret);
  2534. }
  2535. wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
  2536. return 0;
  2537. }
  2538. static int wm8994_codec_resume(struct snd_soc_codec *codec)
  2539. {
  2540. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2541. struct wm8994 *control = wm8994->wm8994;
  2542. int i, ret;
  2543. unsigned int val, mask;
  2544. if (wm8994->revision < 4) {
  2545. /* force a HW read */
  2546. ret = regmap_read(control->regmap,
  2547. WM8994_POWER_MANAGEMENT_5, &val);
  2548. /* modify the cache only */
  2549. codec->cache_only = 1;
  2550. mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
  2551. WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
  2552. val &= mask;
  2553. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
  2554. mask, val);
  2555. codec->cache_only = 0;
  2556. }
  2557. for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
  2558. if (!wm8994->fll_suspend[i].out)
  2559. continue;
  2560. ret = _wm8994_set_fll(codec, i + 1,
  2561. wm8994->fll_suspend[i].src,
  2562. wm8994->fll_suspend[i].in,
  2563. wm8994->fll_suspend[i].out);
  2564. if (ret < 0)
  2565. dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
  2566. i + 1, ret);
  2567. }
  2568. return 0;
  2569. }
  2570. #else
  2571. #define wm8994_codec_suspend NULL
  2572. #define wm8994_codec_resume NULL
  2573. #endif
  2574. static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
  2575. {
  2576. struct snd_soc_codec *codec = wm8994->hubs.codec;
  2577. struct wm8994_pdata *pdata = wm8994->pdata;
  2578. struct snd_kcontrol_new controls[] = {
  2579. SOC_ENUM_EXT("AIF1.1 EQ Mode",
  2580. wm8994->retune_mobile_enum,
  2581. wm8994_get_retune_mobile_enum,
  2582. wm8994_put_retune_mobile_enum),
  2583. SOC_ENUM_EXT("AIF1.2 EQ Mode",
  2584. wm8994->retune_mobile_enum,
  2585. wm8994_get_retune_mobile_enum,
  2586. wm8994_put_retune_mobile_enum),
  2587. SOC_ENUM_EXT("AIF2 EQ Mode",
  2588. wm8994->retune_mobile_enum,
  2589. wm8994_get_retune_mobile_enum,
  2590. wm8994_put_retune_mobile_enum),
  2591. };
  2592. int ret, i, j;
  2593. const char **t;
  2594. /* We need an array of texts for the enum API but the number
  2595. * of texts is likely to be less than the number of
  2596. * configurations due to the sample rate dependency of the
  2597. * configurations. */
  2598. wm8994->num_retune_mobile_texts = 0;
  2599. wm8994->retune_mobile_texts = NULL;
  2600. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  2601. for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
  2602. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  2603. wm8994->retune_mobile_texts[j]) == 0)
  2604. break;
  2605. }
  2606. if (j != wm8994->num_retune_mobile_texts)
  2607. continue;
  2608. /* Expand the array... */
  2609. t = krealloc(wm8994->retune_mobile_texts,
  2610. sizeof(char *) *
  2611. (wm8994->num_retune_mobile_texts + 1),
  2612. GFP_KERNEL);
  2613. if (t == NULL)
  2614. continue;
  2615. /* ...store the new entry... */
  2616. t[wm8994->num_retune_mobile_texts] =
  2617. pdata->retune_mobile_cfgs[i].name;
  2618. /* ...and remember the new version. */
  2619. wm8994->num_retune_mobile_texts++;
  2620. wm8994->retune_mobile_texts = t;
  2621. }
  2622. dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
  2623. wm8994->num_retune_mobile_texts);
  2624. wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
  2625. wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
  2626. ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
  2627. ARRAY_SIZE(controls));
  2628. if (ret != 0)
  2629. dev_err(wm8994->hubs.codec->dev,
  2630. "Failed to add ReTune Mobile controls: %d\n", ret);
  2631. }
  2632. static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
  2633. {
  2634. struct snd_soc_codec *codec = wm8994->hubs.codec;
  2635. struct wm8994_pdata *pdata = wm8994->pdata;
  2636. int ret, i;
  2637. if (!pdata)
  2638. return;
  2639. wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
  2640. pdata->lineout2_diff,
  2641. pdata->lineout1fb,
  2642. pdata->lineout2fb,
  2643. pdata->jd_scthr,
  2644. pdata->jd_thr,
  2645. pdata->micb1_delay,
  2646. pdata->micb2_delay,
  2647. pdata->micbias1_lvl,
  2648. pdata->micbias2_lvl);
  2649. dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
  2650. if (pdata->num_drc_cfgs) {
  2651. struct snd_kcontrol_new controls[] = {
  2652. SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
  2653. wm8994_get_drc_enum, wm8994_put_drc_enum),
  2654. SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
  2655. wm8994_get_drc_enum, wm8994_put_drc_enum),
  2656. SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
  2657. wm8994_get_drc_enum, wm8994_put_drc_enum),
  2658. };
  2659. /* We need an array of texts for the enum API */
  2660. wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
  2661. sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
  2662. if (!wm8994->drc_texts) {
  2663. dev_err(wm8994->hubs.codec->dev,
  2664. "Failed to allocate %d DRC config texts\n",
  2665. pdata->num_drc_cfgs);
  2666. return;
  2667. }
  2668. for (i = 0; i < pdata->num_drc_cfgs; i++)
  2669. wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
  2670. wm8994->drc_enum.max = pdata->num_drc_cfgs;
  2671. wm8994->drc_enum.texts = wm8994->drc_texts;
  2672. ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
  2673. ARRAY_SIZE(controls));
  2674. for (i = 0; i < WM8994_NUM_DRC; i++)
  2675. wm8994_set_drc(codec, i);
  2676. } else {
  2677. ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
  2678. wm8994_drc_controls,
  2679. ARRAY_SIZE(wm8994_drc_controls));
  2680. }
  2681. if (ret != 0)
  2682. dev_err(wm8994->hubs.codec->dev,
  2683. "Failed to add DRC mode controls: %d\n", ret);
  2684. dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
  2685. pdata->num_retune_mobile_cfgs);
  2686. if (pdata->num_retune_mobile_cfgs)
  2687. wm8994_handle_retune_mobile_pdata(wm8994);
  2688. else
  2689. snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
  2690. ARRAY_SIZE(wm8994_eq_controls));
  2691. for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
  2692. if (pdata->micbias[i]) {
  2693. snd_soc_write(codec, WM8958_MICBIAS1 + i,
  2694. pdata->micbias[i] & 0xffff);
  2695. }
  2696. }
  2697. }
  2698. /**
  2699. * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
  2700. *
  2701. * @codec: WM8994 codec
  2702. * @jack: jack to report detection events on
  2703. * @micbias: microphone bias to detect on
  2704. *
  2705. * Enable microphone detection via IRQ on the WM8994. If GPIOs are
  2706. * being used to bring out signals to the processor then only platform
  2707. * data configuration is needed for WM8994 and processor GPIOs should
  2708. * be configured using snd_soc_jack_add_gpios() instead.
  2709. *
  2710. * Configuration of detection levels is available via the micbias1_lvl
  2711. * and micbias2_lvl platform data members.
  2712. */
  2713. int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
  2714. int micbias)
  2715. {
  2716. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2717. struct wm8994_micdet *micdet;
  2718. struct wm8994 *control = wm8994->wm8994;
  2719. int reg, ret;
  2720. if (control->type != WM8994) {
  2721. dev_warn(codec->dev, "Not a WM8994\n");
  2722. return -EINVAL;
  2723. }
  2724. switch (micbias) {
  2725. case 1:
  2726. micdet = &wm8994->micdet[0];
  2727. if (jack)
  2728. ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
  2729. "MICBIAS1");
  2730. else
  2731. ret = snd_soc_dapm_disable_pin(&codec->dapm,
  2732. "MICBIAS1");
  2733. break;
  2734. case 2:
  2735. micdet = &wm8994->micdet[1];
  2736. if (jack)
  2737. ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
  2738. "MICBIAS1");
  2739. else
  2740. ret = snd_soc_dapm_disable_pin(&codec->dapm,
  2741. "MICBIAS1");
  2742. break;
  2743. default:
  2744. dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
  2745. return -EINVAL;
  2746. }
  2747. if (ret != 0)
  2748. dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
  2749. micbias, ret);
  2750. dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
  2751. micbias, jack);
  2752. /* Store the configuration */
  2753. micdet->jack = jack;
  2754. micdet->detecting = true;
  2755. /* If either of the jacks is set up then enable detection */
  2756. if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
  2757. reg = WM8994_MICD_ENA;
  2758. else
  2759. reg = 0;
  2760. snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
  2761. /* enable MICDET and MICSHRT deboune */
  2762. snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
  2763. WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
  2764. WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
  2765. WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
  2766. snd_soc_dapm_sync(&codec->dapm);
  2767. return 0;
  2768. }
  2769. EXPORT_SYMBOL_GPL(wm8994_mic_detect);
  2770. static void wm8994_mic_work(struct work_struct *work)
  2771. {
  2772. struct wm8994_priv *priv = container_of(work,
  2773. struct wm8994_priv,
  2774. mic_work.work);
  2775. struct regmap *regmap = priv->wm8994->regmap;
  2776. struct device *dev = priv->wm8994->dev;
  2777. unsigned int reg;
  2778. int ret;
  2779. int report;
  2780. pm_runtime_get_sync(dev);
  2781. ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
  2782. if (ret < 0) {
  2783. dev_err(dev, "Failed to read microphone status: %d\n",
  2784. ret);
  2785. pm_runtime_put(dev);
  2786. return;
  2787. }
  2788. dev_dbg(dev, "Microphone status: %x\n", reg);
  2789. report = 0;
  2790. if (reg & WM8994_MIC1_DET_STS) {
  2791. if (priv->micdet[0].detecting)
  2792. report = SND_JACK_HEADSET;
  2793. }
  2794. if (reg & WM8994_MIC1_SHRT_STS) {
  2795. if (priv->micdet[0].detecting)
  2796. report = SND_JACK_HEADPHONE;
  2797. else
  2798. report |= SND_JACK_BTN_0;
  2799. }
  2800. if (report)
  2801. priv->micdet[0].detecting = false;
  2802. else
  2803. priv->micdet[0].detecting = true;
  2804. snd_soc_jack_report(priv->micdet[0].jack, report,
  2805. SND_JACK_HEADSET | SND_JACK_BTN_0);
  2806. report = 0;
  2807. if (reg & WM8994_MIC2_DET_STS) {
  2808. if (priv->micdet[1].detecting)
  2809. report = SND_JACK_HEADSET;
  2810. }
  2811. if (reg & WM8994_MIC2_SHRT_STS) {
  2812. if (priv->micdet[1].detecting)
  2813. report = SND_JACK_HEADPHONE;
  2814. else
  2815. report |= SND_JACK_BTN_0;
  2816. }
  2817. if (report)
  2818. priv->micdet[1].detecting = false;
  2819. else
  2820. priv->micdet[1].detecting = true;
  2821. snd_soc_jack_report(priv->micdet[1].jack, report,
  2822. SND_JACK_HEADSET | SND_JACK_BTN_0);
  2823. pm_runtime_put(dev);
  2824. }
  2825. static irqreturn_t wm8994_mic_irq(int irq, void *data)
  2826. {
  2827. struct wm8994_priv *priv = data;
  2828. struct snd_soc_codec *codec = priv->hubs.codec;
  2829. #ifndef CONFIG_SND_SOC_WM8994_MODULE
  2830. trace_snd_soc_jack_irq(dev_name(codec->dev));
  2831. #endif
  2832. pm_wakeup_event(codec->dev, 300);
  2833. schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
  2834. return IRQ_HANDLED;
  2835. }
  2836. /* Default microphone detection handler for WM8958 - the user can
  2837. * override this if they wish.
  2838. */
  2839. static void wm8958_default_micdet(u16 status, void *data)
  2840. {
  2841. struct snd_soc_codec *codec = data;
  2842. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2843. int report;
  2844. dev_dbg(codec->dev, "MICDET %x\n", status);
  2845. /* Either nothing present or just starting detection */
  2846. if (!(status & WM8958_MICD_STS)) {
  2847. if (!wm8994->jackdet) {
  2848. /* If nothing present then clear our statuses */
  2849. dev_dbg(codec->dev, "Detected open circuit\n");
  2850. wm8994->jack_mic = false;
  2851. wm8994->mic_detecting = true;
  2852. wm8958_micd_set_rate(codec);
  2853. snd_soc_jack_report(wm8994->micdet[0].jack, 0,
  2854. wm8994->btn_mask |
  2855. SND_JACK_HEADSET);
  2856. }
  2857. return;
  2858. }
  2859. /* If the measurement is showing a high impedence we've got a
  2860. * microphone.
  2861. */
  2862. if (wm8994->mic_detecting && (status & 0x600)) {
  2863. dev_dbg(codec->dev, "Detected microphone\n");
  2864. wm8994->mic_detecting = false;
  2865. wm8994->jack_mic = true;
  2866. wm8958_micd_set_rate(codec);
  2867. snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
  2868. SND_JACK_HEADSET);
  2869. }
  2870. if (wm8994->mic_detecting && status & 0xfc) {
  2871. dev_dbg(codec->dev, "Detected headphone\n");
  2872. wm8994->mic_detecting = false;
  2873. wm8958_micd_set_rate(codec);
  2874. /* If we have jackdet that will detect removal */
  2875. if (wm8994->jackdet) {
  2876. mutex_lock(&wm8994->accdet_lock);
  2877. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  2878. WM8958_MICD_ENA, 0);
  2879. wm1811_jackdet_set_mode(codec,
  2880. WM1811_JACKDET_MODE_JACK);
  2881. mutex_unlock(&wm8994->accdet_lock);
  2882. if (wm8994->pdata->jd_ext_cap)
  2883. snd_soc_dapm_disable_pin(&codec->dapm,
  2884. "MICBIAS2");
  2885. }
  2886. snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
  2887. SND_JACK_HEADSET);
  2888. }
  2889. /* Report short circuit as a button */
  2890. if (wm8994->jack_mic) {
  2891. report = 0;
  2892. if (status & 0x4)
  2893. report |= SND_JACK_BTN_0;
  2894. if (status & 0x8)
  2895. report |= SND_JACK_BTN_1;
  2896. if (status & 0x10)
  2897. report |= SND_JACK_BTN_2;
  2898. if (status & 0x20)
  2899. report |= SND_JACK_BTN_3;
  2900. if (status & 0x40)
  2901. report |= SND_JACK_BTN_4;
  2902. if (status & 0x80)
  2903. report |= SND_JACK_BTN_5;
  2904. snd_soc_jack_report(wm8994->micdet[0].jack, report,
  2905. wm8994->btn_mask);
  2906. }
  2907. }
  2908. static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
  2909. {
  2910. struct wm8994_priv *wm8994 = data;
  2911. struct snd_soc_codec *codec = wm8994->hubs.codec;
  2912. int reg;
  2913. bool present;
  2914. pm_runtime_get_sync(codec->dev);
  2915. mutex_lock(&wm8994->accdet_lock);
  2916. reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
  2917. if (reg < 0) {
  2918. dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
  2919. mutex_unlock(&wm8994->accdet_lock);
  2920. pm_runtime_put(codec->dev);
  2921. return IRQ_NONE;
  2922. }
  2923. dev_dbg(codec->dev, "JACKDET %x\n", reg);
  2924. present = reg & WM1811_JACKDET_LVL;
  2925. if (present) {
  2926. dev_dbg(codec->dev, "Jack detected\n");
  2927. wm8958_micd_set_rate(codec);
  2928. snd_soc_update_bits(codec, WM8958_MICBIAS2,
  2929. WM8958_MICB2_DISCH, 0);
  2930. /* Disable debounce while inserted */
  2931. snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
  2932. WM1811_JACKDET_DB, 0);
  2933. /*
  2934. * Start off measument of microphone impedence to find
  2935. * out what's actually there.
  2936. */
  2937. wm8994->mic_detecting = true;
  2938. wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
  2939. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  2940. WM8958_MICD_ENA, WM8958_MICD_ENA);
  2941. } else {
  2942. dev_dbg(codec->dev, "Jack not detected\n");
  2943. snd_soc_update_bits(codec, WM8958_MICBIAS2,
  2944. WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
  2945. /* Enable debounce while removed */
  2946. snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
  2947. WM1811_JACKDET_DB, WM1811_JACKDET_DB);
  2948. wm8994->mic_detecting = false;
  2949. wm8994->jack_mic = false;
  2950. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  2951. WM8958_MICD_ENA, 0);
  2952. wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
  2953. }
  2954. mutex_unlock(&wm8994->accdet_lock);
  2955. /* If required for an external cap force MICBIAS on */
  2956. if (wm8994->pdata->jd_ext_cap) {
  2957. if (present)
  2958. snd_soc_dapm_force_enable_pin(&codec->dapm,
  2959. "MICBIAS2");
  2960. else
  2961. snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
  2962. }
  2963. if (present)
  2964. snd_soc_jack_report(wm8994->micdet[0].jack,
  2965. SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
  2966. else
  2967. snd_soc_jack_report(wm8994->micdet[0].jack, 0,
  2968. SND_JACK_MECHANICAL | SND_JACK_HEADSET |
  2969. wm8994->btn_mask);
  2970. /* Since we only report deltas force an update, ensures we
  2971. * avoid bootstrapping issues with the core. */
  2972. snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
  2973. pm_runtime_put(codec->dev);
  2974. return IRQ_HANDLED;
  2975. }
  2976. static void wm1811_jackdet_bootstrap(struct work_struct *work)
  2977. {
  2978. struct wm8994_priv *wm8994 = container_of(work,
  2979. struct wm8994_priv,
  2980. jackdet_bootstrap.work);
  2981. wm1811_jackdet_irq(0, wm8994);
  2982. }
  2983. /**
  2984. * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
  2985. *
  2986. * @codec: WM8958 codec
  2987. * @jack: jack to report detection events on
  2988. *
  2989. * Enable microphone detection functionality for the WM8958. By
  2990. * default simple detection which supports the detection of up to 6
  2991. * buttons plus video and microphone functionality is supported.
  2992. *
  2993. * The WM8958 has an advanced jack detection facility which is able to
  2994. * support complex accessory detection, especially when used in
  2995. * conjunction with external circuitry. In order to provide maximum
  2996. * flexiblity a callback is provided which allows a completely custom
  2997. * detection algorithm.
  2998. */
  2999. int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
  3000. wm8958_micdet_cb cb, void *cb_data)
  3001. {
  3002. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  3003. struct wm8994 *control = wm8994->wm8994;
  3004. u16 micd_lvl_sel;
  3005. switch (control->type) {
  3006. case WM1811:
  3007. case WM8958:
  3008. break;
  3009. default:
  3010. return -EINVAL;
  3011. }
  3012. if (jack) {
  3013. if (!cb) {
  3014. dev_dbg(codec->dev, "Using default micdet callback\n");
  3015. cb = wm8958_default_micdet;
  3016. cb_data = codec;
  3017. }
  3018. snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
  3019. snd_soc_dapm_sync(&codec->dapm);
  3020. wm8994->micdet[0].jack = jack;
  3021. wm8994->jack_cb = cb;
  3022. wm8994->jack_cb_data = cb_data;
  3023. wm8994->mic_detecting = true;
  3024. wm8994->jack_mic = false;
  3025. wm8958_micd_set_rate(codec);
  3026. /* Detect microphones and short circuits by default */
  3027. if (wm8994->pdata->micd_lvl_sel)
  3028. micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
  3029. else
  3030. micd_lvl_sel = 0x41;
  3031. wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  3032. SND_JACK_BTN_2 | SND_JACK_BTN_3 |
  3033. SND_JACK_BTN_4 | SND_JACK_BTN_5;
  3034. snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
  3035. WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
  3036. WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
  3037. /*
  3038. * If we can use jack detection start off with that,
  3039. * otherwise jump straight to microphone detection.
  3040. */
  3041. if (wm8994->jackdet) {
  3042. /* Disable debounce for the initial detect */
  3043. snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
  3044. WM1811_JACKDET_DB, 0);
  3045. snd_soc_update_bits(codec, WM8958_MICBIAS2,
  3046. WM8958_MICB2_DISCH,
  3047. WM8958_MICB2_DISCH);
  3048. snd_soc_update_bits(codec, WM8994_LDO_1,
  3049. WM8994_LDO1_DISCH, 0);
  3050. wm1811_jackdet_set_mode(codec,
  3051. WM1811_JACKDET_MODE_JACK);
  3052. } else {
  3053. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  3054. WM8958_MICD_ENA, WM8958_MICD_ENA);
  3055. }
  3056. } else {
  3057. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  3058. WM8958_MICD_ENA, 0);
  3059. wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
  3060. snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
  3061. snd_soc_dapm_sync(&codec->dapm);
  3062. }
  3063. return 0;
  3064. }
  3065. EXPORT_SYMBOL_GPL(wm8958_mic_detect);
  3066. static irqreturn_t wm8958_mic_irq(int irq, void *data)
  3067. {
  3068. struct wm8994_priv *wm8994 = data;
  3069. struct snd_soc_codec *codec = wm8994->hubs.codec;
  3070. int reg, count;
  3071. /*
  3072. * Jack detection may have detected a removal simulataneously
  3073. * with an update of the MICDET status; if so it will have
  3074. * stopped detection and we can ignore this interrupt.
  3075. */
  3076. if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
  3077. return IRQ_HANDLED;
  3078. pm_runtime_get_sync(codec->dev);
  3079. /* We may occasionally read a detection without an impedence
  3080. * range being provided - if that happens loop again.
  3081. */
  3082. count = 10;
  3083. do {
  3084. reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
  3085. if (reg < 0) {
  3086. dev_err(codec->dev,
  3087. "Failed to read mic detect status: %d\n",
  3088. reg);
  3089. pm_runtime_put(codec->dev);
  3090. return IRQ_NONE;
  3091. }
  3092. if (!(reg & WM8958_MICD_VALID)) {
  3093. dev_dbg(codec->dev, "Mic detect data not valid\n");
  3094. goto out;
  3095. }
  3096. if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
  3097. break;
  3098. msleep(1);
  3099. } while (count--);
  3100. if (count == 0)
  3101. dev_warn(codec->dev, "No impedence range reported for jack\n");
  3102. #ifndef CONFIG_SND_SOC_WM8994_MODULE
  3103. trace_snd_soc_jack_irq(dev_name(codec->dev));
  3104. #endif
  3105. if (wm8994->jack_cb)
  3106. wm8994->jack_cb(reg, wm8994->jack_cb_data);
  3107. else
  3108. dev_warn(codec->dev, "Accessory detection with no callback\n");
  3109. out:
  3110. pm_runtime_put(codec->dev);
  3111. return IRQ_HANDLED;
  3112. }
  3113. static irqreturn_t wm8994_fifo_error(int irq, void *data)
  3114. {
  3115. struct snd_soc_codec *codec = data;
  3116. dev_err(codec->dev, "FIFO error\n");
  3117. return IRQ_HANDLED;
  3118. }
  3119. static irqreturn_t wm8994_temp_warn(int irq, void *data)
  3120. {
  3121. struct snd_soc_codec *codec = data;
  3122. dev_err(codec->dev, "Thermal warning\n");
  3123. return IRQ_HANDLED;
  3124. }
  3125. static irqreturn_t wm8994_temp_shut(int irq, void *data)
  3126. {
  3127. struct snd_soc_codec *codec = data;
  3128. dev_crit(codec->dev, "Thermal shutdown\n");
  3129. return IRQ_HANDLED;
  3130. }
  3131. static int wm8994_codec_probe(struct snd_soc_codec *codec)
  3132. {
  3133. struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
  3134. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  3135. struct snd_soc_dapm_context *dapm = &codec->dapm;
  3136. unsigned int reg;
  3137. int ret, i;
  3138. wm8994->hubs.codec = codec;
  3139. codec->control_data = control->regmap;
  3140. snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
  3141. mutex_init(&wm8994->accdet_lock);
  3142. INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
  3143. INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
  3144. wm1811_jackdet_bootstrap);
  3145. for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
  3146. init_completion(&wm8994->fll_locked[i]);
  3147. if (wm8994->pdata && wm8994->pdata->micdet_irq)
  3148. wm8994->micdet_irq = wm8994->pdata->micdet_irq;
  3149. pm_runtime_enable(codec->dev);
  3150. pm_runtime_idle(codec->dev);
  3151. /* By default use idle_bias_off, will override for WM8994 */
  3152. codec->dapm.idle_bias_off = 1;
  3153. /* Set revision-specific configuration */
  3154. wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
  3155. switch (control->type) {
  3156. case WM8994:
  3157. /* Single ended line outputs should have VMID on. */
  3158. if (!wm8994->pdata->lineout1_diff ||
  3159. !wm8994->pdata->lineout2_diff)
  3160. codec->dapm.idle_bias_off = 0;
  3161. switch (wm8994->revision) {
  3162. case 2:
  3163. case 3:
  3164. wm8994->hubs.dcs_codes_l = -5;
  3165. wm8994->hubs.dcs_codes_r = -5;
  3166. wm8994->hubs.hp_startup_mode = 1;
  3167. wm8994->hubs.dcs_readback_mode = 1;
  3168. wm8994->hubs.series_startup = 1;
  3169. break;
  3170. default:
  3171. wm8994->hubs.dcs_readback_mode = 2;
  3172. break;
  3173. }
  3174. break;
  3175. case WM8958:
  3176. wm8994->hubs.dcs_readback_mode = 1;
  3177. wm8994->hubs.hp_startup_mode = 1;
  3178. switch (wm8994->revision) {
  3179. case 0:
  3180. break;
  3181. default:
  3182. wm8994->fll_byp = true;
  3183. break;
  3184. }
  3185. break;
  3186. case WM1811:
  3187. wm8994->hubs.dcs_readback_mode = 2;
  3188. wm8994->hubs.no_series_update = 1;
  3189. wm8994->hubs.hp_startup_mode = 1;
  3190. wm8994->hubs.no_cache_dac_hp_direct = true;
  3191. wm8994->fll_byp = true;
  3192. switch (control->cust_id) {
  3193. case 0:
  3194. case 2:
  3195. wm8994->hubs.dcs_codes_l = -9;
  3196. wm8994->hubs.dcs_codes_r = -7;
  3197. break;
  3198. case 1:
  3199. case 3:
  3200. wm8994->hubs.dcs_codes_l = -8;
  3201. wm8994->hubs.dcs_codes_r = -7;
  3202. break;
  3203. default:
  3204. break;
  3205. }
  3206. snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
  3207. WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
  3208. break;
  3209. default:
  3210. break;
  3211. }
  3212. wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
  3213. wm8994_fifo_error, "FIFO error", codec);
  3214. wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
  3215. wm8994_temp_warn, "Thermal warning", codec);
  3216. wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
  3217. wm8994_temp_shut, "Thermal shutdown", codec);
  3218. ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
  3219. wm_hubs_dcs_done, "DC servo done",
  3220. &wm8994->hubs);
  3221. if (ret == 0)
  3222. wm8994->hubs.dcs_done_irq = true;
  3223. switch (control->type) {
  3224. case WM8994:
  3225. if (wm8994->micdet_irq) {
  3226. ret = request_threaded_irq(wm8994->micdet_irq, NULL,
  3227. wm8994_mic_irq,
  3228. IRQF_TRIGGER_RISING,
  3229. "Mic1 detect",
  3230. wm8994);
  3231. if (ret != 0)
  3232. dev_warn(codec->dev,
  3233. "Failed to request Mic1 detect IRQ: %d\n",
  3234. ret);
  3235. }
  3236. ret = wm8994_request_irq(wm8994->wm8994,
  3237. WM8994_IRQ_MIC1_SHRT,
  3238. wm8994_mic_irq, "Mic 1 short",
  3239. wm8994);
  3240. if (ret != 0)
  3241. dev_warn(codec->dev,
  3242. "Failed to request Mic1 short IRQ: %d\n",
  3243. ret);
  3244. ret = wm8994_request_irq(wm8994->wm8994,
  3245. WM8994_IRQ_MIC2_DET,
  3246. wm8994_mic_irq, "Mic 2 detect",
  3247. wm8994);
  3248. if (ret != 0)
  3249. dev_warn(codec->dev,
  3250. "Failed to request Mic2 detect IRQ: %d\n",
  3251. ret);
  3252. ret = wm8994_request_irq(wm8994->wm8994,
  3253. WM8994_IRQ_MIC2_SHRT,
  3254. wm8994_mic_irq, "Mic 2 short",
  3255. wm8994);
  3256. if (ret != 0)
  3257. dev_warn(codec->dev,
  3258. "Failed to request Mic2 short IRQ: %d\n",
  3259. ret);
  3260. break;
  3261. case WM8958:
  3262. case WM1811:
  3263. if (wm8994->micdet_irq) {
  3264. ret = request_threaded_irq(wm8994->micdet_irq, NULL,
  3265. wm8958_mic_irq,
  3266. IRQF_TRIGGER_RISING,
  3267. "Mic detect",
  3268. wm8994);
  3269. if (ret != 0)
  3270. dev_warn(codec->dev,
  3271. "Failed to request Mic detect IRQ: %d\n",
  3272. ret);
  3273. } else {
  3274. wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
  3275. wm8958_mic_irq, "Mic detect",
  3276. wm8994);
  3277. }
  3278. }
  3279. switch (control->type) {
  3280. case WM1811:
  3281. if (control->cust_id > 1 || wm8994->revision > 1) {
  3282. ret = wm8994_request_irq(wm8994->wm8994,
  3283. WM8994_IRQ_GPIO(6),
  3284. wm1811_jackdet_irq, "JACKDET",
  3285. wm8994);
  3286. if (ret == 0)
  3287. wm8994->jackdet = true;
  3288. }
  3289. break;
  3290. default:
  3291. break;
  3292. }
  3293. wm8994->fll_locked_irq = true;
  3294. for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
  3295. ret = wm8994_request_irq(wm8994->wm8994,
  3296. WM8994_IRQ_FLL1_LOCK + i,
  3297. wm8994_fll_locked_irq, "FLL lock",
  3298. &wm8994->fll_locked[i]);
  3299. if (ret != 0)
  3300. wm8994->fll_locked_irq = false;
  3301. }
  3302. /* Make sure we can read from the GPIOs if they're inputs */
  3303. pm_runtime_get_sync(codec->dev);
  3304. /* Remember if AIFnLRCLK is configured as a GPIO. This should be
  3305. * configured on init - if a system wants to do this dynamically
  3306. * at runtime we can deal with that then.
  3307. */
  3308. ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
  3309. if (ret < 0) {
  3310. dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
  3311. goto err_irq;
  3312. }
  3313. if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
  3314. wm8994->lrclk_shared[0] = 1;
  3315. wm8994_dai[0].symmetric_rates = 1;
  3316. } else {
  3317. wm8994->lrclk_shared[0] = 0;
  3318. }
  3319. ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
  3320. if (ret < 0) {
  3321. dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
  3322. goto err_irq;
  3323. }
  3324. if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
  3325. wm8994->lrclk_shared[1] = 1;
  3326. wm8994_dai[1].symmetric_rates = 1;
  3327. } else {
  3328. wm8994->lrclk_shared[1] = 0;
  3329. }
  3330. pm_runtime_put(codec->dev);
  3331. /* Latch volume update bits */
  3332. for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
  3333. snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
  3334. wm8994_vu_bits[i].mask,
  3335. wm8994_vu_bits[i].mask);
  3336. /* Set the low bit of the 3D stereo depth so TLV matches */
  3337. snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
  3338. 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
  3339. 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
  3340. snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
  3341. 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
  3342. 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
  3343. snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
  3344. 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
  3345. 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
  3346. /* Unconditionally enable AIF1 ADC TDM mode on chips which can
  3347. * use this; it only affects behaviour on idle TDM clock
  3348. * cycles. */
  3349. switch (control->type) {
  3350. case WM8994:
  3351. case WM8958:
  3352. snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
  3353. WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
  3354. break;
  3355. default:
  3356. break;
  3357. }
  3358. /* Put MICBIAS into bypass mode by default on newer devices */
  3359. switch (control->type) {
  3360. case WM8958:
  3361. case WM1811:
  3362. snd_soc_update_bits(codec, WM8958_MICBIAS1,
  3363. WM8958_MICB1_MODE, WM8958_MICB1_MODE);
  3364. snd_soc_update_bits(codec, WM8958_MICBIAS2,
  3365. WM8958_MICB2_MODE, WM8958_MICB2_MODE);
  3366. break;
  3367. default:
  3368. break;
  3369. }
  3370. wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
  3371. wm_hubs_update_class_w(codec);
  3372. wm8994_handle_pdata(wm8994);
  3373. wm_hubs_add_analogue_controls(codec);
  3374. snd_soc_add_codec_controls(codec, wm8994_snd_controls,
  3375. ARRAY_SIZE(wm8994_snd_controls));
  3376. snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
  3377. ARRAY_SIZE(wm8994_dapm_widgets));
  3378. switch (control->type) {
  3379. case WM8994:
  3380. snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
  3381. ARRAY_SIZE(wm8994_specific_dapm_widgets));
  3382. if (wm8994->revision < 4) {
  3383. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
  3384. ARRAY_SIZE(wm8994_lateclk_revd_widgets));
  3385. snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
  3386. ARRAY_SIZE(wm8994_adc_revd_widgets));
  3387. snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
  3388. ARRAY_SIZE(wm8994_dac_revd_widgets));
  3389. } else {
  3390. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
  3391. ARRAY_SIZE(wm8994_lateclk_widgets));
  3392. snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
  3393. ARRAY_SIZE(wm8994_adc_widgets));
  3394. snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
  3395. ARRAY_SIZE(wm8994_dac_widgets));
  3396. }
  3397. break;
  3398. case WM8958:
  3399. snd_soc_add_codec_controls(codec, wm8958_snd_controls,
  3400. ARRAY_SIZE(wm8958_snd_controls));
  3401. snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
  3402. ARRAY_SIZE(wm8958_dapm_widgets));
  3403. if (wm8994->revision < 1) {
  3404. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
  3405. ARRAY_SIZE(wm8994_lateclk_revd_widgets));
  3406. snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
  3407. ARRAY_SIZE(wm8994_adc_revd_widgets));
  3408. snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
  3409. ARRAY_SIZE(wm8994_dac_revd_widgets));
  3410. } else {
  3411. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
  3412. ARRAY_SIZE(wm8994_lateclk_widgets));
  3413. snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
  3414. ARRAY_SIZE(wm8994_adc_widgets));
  3415. snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
  3416. ARRAY_SIZE(wm8994_dac_widgets));
  3417. }
  3418. break;
  3419. case WM1811:
  3420. snd_soc_add_codec_controls(codec, wm8958_snd_controls,
  3421. ARRAY_SIZE(wm8958_snd_controls));
  3422. snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
  3423. ARRAY_SIZE(wm8958_dapm_widgets));
  3424. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
  3425. ARRAY_SIZE(wm8994_lateclk_widgets));
  3426. snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
  3427. ARRAY_SIZE(wm8994_adc_widgets));
  3428. snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
  3429. ARRAY_SIZE(wm8994_dac_widgets));
  3430. break;
  3431. }
  3432. wm_hubs_add_analogue_routes(codec, 0, 0);
  3433. snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
  3434. switch (control->type) {
  3435. case WM8994:
  3436. snd_soc_dapm_add_routes(dapm, wm8994_intercon,
  3437. ARRAY_SIZE(wm8994_intercon));
  3438. if (wm8994->revision < 4) {
  3439. snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
  3440. ARRAY_SIZE(wm8994_revd_intercon));
  3441. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
  3442. ARRAY_SIZE(wm8994_lateclk_revd_intercon));
  3443. } else {
  3444. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
  3445. ARRAY_SIZE(wm8994_lateclk_intercon));
  3446. }
  3447. break;
  3448. case WM8958:
  3449. if (wm8994->revision < 1) {
  3450. snd_soc_dapm_add_routes(dapm, wm8994_intercon,
  3451. ARRAY_SIZE(wm8994_intercon));
  3452. snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
  3453. ARRAY_SIZE(wm8994_revd_intercon));
  3454. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
  3455. ARRAY_SIZE(wm8994_lateclk_revd_intercon));
  3456. } else {
  3457. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
  3458. ARRAY_SIZE(wm8994_lateclk_intercon));
  3459. snd_soc_dapm_add_routes(dapm, wm8958_intercon,
  3460. ARRAY_SIZE(wm8958_intercon));
  3461. }
  3462. wm8958_dsp2_init(codec);
  3463. break;
  3464. case WM1811:
  3465. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
  3466. ARRAY_SIZE(wm8994_lateclk_intercon));
  3467. snd_soc_dapm_add_routes(dapm, wm8958_intercon,
  3468. ARRAY_SIZE(wm8958_intercon));
  3469. break;
  3470. }
  3471. return 0;
  3472. err_irq:
  3473. if (wm8994->jackdet)
  3474. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
  3475. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
  3476. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
  3477. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
  3478. if (wm8994->micdet_irq)
  3479. free_irq(wm8994->micdet_irq, wm8994);
  3480. for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
  3481. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
  3482. &wm8994->fll_locked[i]);
  3483. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
  3484. &wm8994->hubs);
  3485. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
  3486. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
  3487. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
  3488. return ret;
  3489. }
  3490. static int wm8994_codec_remove(struct snd_soc_codec *codec)
  3491. {
  3492. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  3493. struct wm8994 *control = wm8994->wm8994;
  3494. int i;
  3495. wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
  3496. pm_runtime_disable(codec->dev);
  3497. for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
  3498. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
  3499. &wm8994->fll_locked[i]);
  3500. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
  3501. &wm8994->hubs);
  3502. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
  3503. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
  3504. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
  3505. if (wm8994->jackdet)
  3506. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
  3507. switch (control->type) {
  3508. case WM8994:
  3509. if (wm8994->micdet_irq)
  3510. free_irq(wm8994->micdet_irq, wm8994);
  3511. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
  3512. wm8994);
  3513. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
  3514. wm8994);
  3515. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
  3516. wm8994);
  3517. break;
  3518. case WM1811:
  3519. case WM8958:
  3520. if (wm8994->micdet_irq)
  3521. free_irq(wm8994->micdet_irq, wm8994);
  3522. break;
  3523. }
  3524. release_firmware(wm8994->mbc);
  3525. release_firmware(wm8994->mbc_vss);
  3526. release_firmware(wm8994->enh_eq);
  3527. kfree(wm8994->retune_mobile_texts);
  3528. return 0;
  3529. }
  3530. static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
  3531. .probe = wm8994_codec_probe,
  3532. .remove = wm8994_codec_remove,
  3533. .suspend = wm8994_codec_suspend,
  3534. .resume = wm8994_codec_resume,
  3535. .set_bias_level = wm8994_set_bias_level,
  3536. };
  3537. static int __devinit wm8994_probe(struct platform_device *pdev)
  3538. {
  3539. struct wm8994_priv *wm8994;
  3540. wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
  3541. GFP_KERNEL);
  3542. if (wm8994 == NULL)
  3543. return -ENOMEM;
  3544. platform_set_drvdata(pdev, wm8994);
  3545. wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
  3546. wm8994->pdata = dev_get_platdata(pdev->dev.parent);
  3547. return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
  3548. wm8994_dai, ARRAY_SIZE(wm8994_dai));
  3549. }
  3550. static int __devexit wm8994_remove(struct platform_device *pdev)
  3551. {
  3552. snd_soc_unregister_codec(&pdev->dev);
  3553. return 0;
  3554. }
  3555. #ifdef CONFIG_PM_SLEEP
  3556. static int wm8994_suspend(struct device *dev)
  3557. {
  3558. struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
  3559. /* Drop down to power saving mode when system is suspended */
  3560. if (wm8994->jackdet && !wm8994->active_refcount)
  3561. regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
  3562. WM1811_JACKDET_MODE_MASK,
  3563. wm8994->jackdet_mode);
  3564. return 0;
  3565. }
  3566. static int wm8994_resume(struct device *dev)
  3567. {
  3568. struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
  3569. if (wm8994->jackdet && wm8994->jack_cb)
  3570. regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
  3571. WM1811_JACKDET_MODE_MASK,
  3572. WM1811_JACKDET_MODE_AUDIO);
  3573. return 0;
  3574. }
  3575. #endif
  3576. static const struct dev_pm_ops wm8994_pm_ops = {
  3577. SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
  3578. };
  3579. static struct platform_driver wm8994_codec_driver = {
  3580. .driver = {
  3581. .name = "wm8994-codec",
  3582. .owner = THIS_MODULE,
  3583. .pm = &wm8994_pm_ops,
  3584. },
  3585. .probe = wm8994_probe,
  3586. .remove = __devexit_p(wm8994_remove),
  3587. };
  3588. module_platform_driver(wm8994_codec_driver);
  3589. MODULE_DESCRIPTION("ASoC WM8994 driver");
  3590. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  3591. MODULE_LICENSE("GPL");
  3592. MODULE_ALIAS("platform:wm8994-codec");