be_main.c 135 KB

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  1. /**
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. static unsigned int gcrashmode = 0;
  48. static unsigned int num_hba = 0;
  49. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  50. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  51. MODULE_VERSION(BUILD_STR);
  52. MODULE_AUTHOR("Emulex Corporation");
  53. MODULE_LICENSE("GPL");
  54. module_param(be_iopoll_budget, int, 0);
  55. module_param(enable_msix, int, 0);
  56. module_param(be_max_phys_size, uint, S_IRUGO);
  57. MODULE_PARM_DESC(be_max_phys_size,
  58. "Maximum Size (In Kilobytes) of physically contiguous "
  59. "memory that can be allocated. Range is 16 - 128");
  60. #define beiscsi_disp_param(_name)\
  61. ssize_t \
  62. beiscsi_##_name##_disp(struct device *dev,\
  63. struct device_attribute *attrib, char *buf) \
  64. { \
  65. struct Scsi_Host *shost = class_to_shost(dev);\
  66. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  67. uint32_t param_val = 0; \
  68. param_val = phba->attr_##_name;\
  69. return snprintf(buf, PAGE_SIZE, "%d\n",\
  70. phba->attr_##_name);\
  71. }
  72. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  73. int \
  74. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  75. {\
  76. if (val >= _minval && val <= _maxval) {\
  77. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  78. "BA_%d : beiscsi_"#_name" updated "\
  79. "from 0x%x ==> 0x%x\n",\
  80. phba->attr_##_name, val); \
  81. phba->attr_##_name = val;\
  82. return 0;\
  83. } \
  84. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  85. "BA_%d beiscsi_"#_name" attribute "\
  86. "cannot be updated to 0x%x, "\
  87. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  88. return -EINVAL;\
  89. }
  90. #define beiscsi_store_param(_name) \
  91. ssize_t \
  92. beiscsi_##_name##_store(struct device *dev,\
  93. struct device_attribute *attr, const char *buf,\
  94. size_t count) \
  95. { \
  96. struct Scsi_Host *shost = class_to_shost(dev);\
  97. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  98. uint32_t param_val = 0;\
  99. if (!isdigit(buf[0]))\
  100. return -EINVAL;\
  101. if (sscanf(buf, "%i", &param_val) != 1)\
  102. return -EINVAL;\
  103. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  104. return strlen(buf);\
  105. else \
  106. return -EINVAL;\
  107. }
  108. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  109. int \
  110. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  111. { \
  112. if (val >= _minval && val <= _maxval) {\
  113. phba->attr_##_name = val;\
  114. return 0;\
  115. } \
  116. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  117. "BA_%d beiscsi_"#_name" attribute " \
  118. "cannot be updated to 0x%x, "\
  119. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  120. phba->attr_##_name = _defval;\
  121. return -EINVAL;\
  122. }
  123. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  124. static uint beiscsi_##_name = _defval;\
  125. module_param(beiscsi_##_name, uint, S_IRUGO);\
  126. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  127. beiscsi_disp_param(_name)\
  128. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  129. beiscsi_store_param(_name)\
  130. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  131. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  132. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  133. /*
  134. * When new log level added update the
  135. * the MAX allowed value for log_enable
  136. */
  137. BEISCSI_RW_ATTR(log_enable, 0x00,
  138. 0xFF, 0x00, "Enable logging Bit Mask\n"
  139. "\t\t\t\tInitialization Events : 0x01\n"
  140. "\t\t\t\tMailbox Events : 0x02\n"
  141. "\t\t\t\tMiscellaneous Events : 0x04\n"
  142. "\t\t\t\tError Handling : 0x08\n"
  143. "\t\t\t\tIO Path Events : 0x10\n"
  144. "\t\t\t\tConfiguration Path : 0x20\n");
  145. struct device_attribute *beiscsi_attrs[] = {
  146. &dev_attr_beiscsi_log_enable,
  147. NULL,
  148. };
  149. static int beiscsi_slave_configure(struct scsi_device *sdev)
  150. {
  151. blk_queue_max_segment_size(sdev->request_queue, 65536);
  152. return 0;
  153. }
  154. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  155. {
  156. struct iscsi_cls_session *cls_session;
  157. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  158. struct beiscsi_io_task *aborted_io_task;
  159. struct iscsi_conn *conn;
  160. struct beiscsi_conn *beiscsi_conn;
  161. struct beiscsi_hba *phba;
  162. struct iscsi_session *session;
  163. struct invalidate_command_table *inv_tbl;
  164. struct be_dma_mem nonemb_cmd;
  165. unsigned int cid, tag, num_invalidate;
  166. cls_session = starget_to_session(scsi_target(sc->device));
  167. session = cls_session->dd_data;
  168. spin_lock_bh(&session->lock);
  169. if (!aborted_task || !aborted_task->sc) {
  170. /* we raced */
  171. spin_unlock_bh(&session->lock);
  172. return SUCCESS;
  173. }
  174. aborted_io_task = aborted_task->dd_data;
  175. if (!aborted_io_task->scsi_cmnd) {
  176. /* raced or invalid command */
  177. spin_unlock_bh(&session->lock);
  178. return SUCCESS;
  179. }
  180. spin_unlock_bh(&session->lock);
  181. conn = aborted_task->conn;
  182. beiscsi_conn = conn->dd_data;
  183. phba = beiscsi_conn->phba;
  184. /* invalidate iocb */
  185. cid = beiscsi_conn->beiscsi_conn_cid;
  186. inv_tbl = phba->inv_tbl;
  187. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  188. inv_tbl->cid = cid;
  189. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  190. num_invalidate = 1;
  191. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  192. sizeof(struct invalidate_commands_params_in),
  193. &nonemb_cmd.dma);
  194. if (nonemb_cmd.va == NULL) {
  195. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  196. "BM_%d : Failed to allocate memory for"
  197. "mgmt_invalidate_icds\n");
  198. return FAILED;
  199. }
  200. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  201. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  202. cid, &nonemb_cmd);
  203. if (!tag) {
  204. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  205. "BM_%d : mgmt_invalidate_icds could not be"
  206. "submitted\n");
  207. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  208. nonemb_cmd.va, nonemb_cmd.dma);
  209. return FAILED;
  210. } else {
  211. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  212. phba->ctrl.mcc_numtag[tag]);
  213. free_mcc_tag(&phba->ctrl, tag);
  214. }
  215. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  216. nonemb_cmd.va, nonemb_cmd.dma);
  217. return iscsi_eh_abort(sc);
  218. }
  219. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  220. {
  221. struct iscsi_task *abrt_task;
  222. struct beiscsi_io_task *abrt_io_task;
  223. struct iscsi_conn *conn;
  224. struct beiscsi_conn *beiscsi_conn;
  225. struct beiscsi_hba *phba;
  226. struct iscsi_session *session;
  227. struct iscsi_cls_session *cls_session;
  228. struct invalidate_command_table *inv_tbl;
  229. struct be_dma_mem nonemb_cmd;
  230. unsigned int cid, tag, i, num_invalidate;
  231. /* invalidate iocbs */
  232. cls_session = starget_to_session(scsi_target(sc->device));
  233. session = cls_session->dd_data;
  234. spin_lock_bh(&session->lock);
  235. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  236. spin_unlock_bh(&session->lock);
  237. return FAILED;
  238. }
  239. conn = session->leadconn;
  240. beiscsi_conn = conn->dd_data;
  241. phba = beiscsi_conn->phba;
  242. cid = beiscsi_conn->beiscsi_conn_cid;
  243. inv_tbl = phba->inv_tbl;
  244. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  245. num_invalidate = 0;
  246. for (i = 0; i < conn->session->cmds_max; i++) {
  247. abrt_task = conn->session->cmds[i];
  248. abrt_io_task = abrt_task->dd_data;
  249. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  250. continue;
  251. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  252. continue;
  253. inv_tbl->cid = cid;
  254. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  255. num_invalidate++;
  256. inv_tbl++;
  257. }
  258. spin_unlock_bh(&session->lock);
  259. inv_tbl = phba->inv_tbl;
  260. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  261. sizeof(struct invalidate_commands_params_in),
  262. &nonemb_cmd.dma);
  263. if (nonemb_cmd.va == NULL) {
  264. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  265. "BM_%d : Failed to allocate memory for"
  266. "mgmt_invalidate_icds\n");
  267. return FAILED;
  268. }
  269. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  270. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  271. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  272. cid, &nonemb_cmd);
  273. if (!tag) {
  274. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  275. "BM_%d : mgmt_invalidate_icds could not be"
  276. " submitted\n");
  277. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  278. nonemb_cmd.va, nonemb_cmd.dma);
  279. return FAILED;
  280. } else {
  281. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  282. phba->ctrl.mcc_numtag[tag]);
  283. free_mcc_tag(&phba->ctrl, tag);
  284. }
  285. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  286. nonemb_cmd.va, nonemb_cmd.dma);
  287. return iscsi_eh_device_reset(sc);
  288. }
  289. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  290. {
  291. struct beiscsi_hba *phba = data;
  292. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  293. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  294. char *str = buf;
  295. int rc;
  296. switch (type) {
  297. case ISCSI_BOOT_TGT_NAME:
  298. rc = sprintf(buf, "%.*s\n",
  299. (int)strlen(boot_sess->target_name),
  300. (char *)&boot_sess->target_name);
  301. break;
  302. case ISCSI_BOOT_TGT_IP_ADDR:
  303. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  304. rc = sprintf(buf, "%pI4\n",
  305. (char *)&boot_conn->dest_ipaddr.addr);
  306. else
  307. rc = sprintf(str, "%pI6\n",
  308. (char *)&boot_conn->dest_ipaddr.addr);
  309. break;
  310. case ISCSI_BOOT_TGT_PORT:
  311. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  312. break;
  313. case ISCSI_BOOT_TGT_CHAP_NAME:
  314. rc = sprintf(str, "%.*s\n",
  315. boot_conn->negotiated_login_options.auth_data.chap.
  316. target_chap_name_length,
  317. (char *)&boot_conn->negotiated_login_options.
  318. auth_data.chap.target_chap_name);
  319. break;
  320. case ISCSI_BOOT_TGT_CHAP_SECRET:
  321. rc = sprintf(str, "%.*s\n",
  322. boot_conn->negotiated_login_options.auth_data.chap.
  323. target_secret_length,
  324. (char *)&boot_conn->negotiated_login_options.
  325. auth_data.chap.target_secret);
  326. break;
  327. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  328. rc = sprintf(str, "%.*s\n",
  329. boot_conn->negotiated_login_options.auth_data.chap.
  330. intr_chap_name_length,
  331. (char *)&boot_conn->negotiated_login_options.
  332. auth_data.chap.intr_chap_name);
  333. break;
  334. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  335. rc = sprintf(str, "%.*s\n",
  336. boot_conn->negotiated_login_options.auth_data.chap.
  337. intr_secret_length,
  338. (char *)&boot_conn->negotiated_login_options.
  339. auth_data.chap.intr_secret);
  340. break;
  341. case ISCSI_BOOT_TGT_FLAGS:
  342. rc = sprintf(str, "2\n");
  343. break;
  344. case ISCSI_BOOT_TGT_NIC_ASSOC:
  345. rc = sprintf(str, "0\n");
  346. break;
  347. default:
  348. rc = -ENOSYS;
  349. break;
  350. }
  351. return rc;
  352. }
  353. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  354. {
  355. struct beiscsi_hba *phba = data;
  356. char *str = buf;
  357. int rc;
  358. switch (type) {
  359. case ISCSI_BOOT_INI_INITIATOR_NAME:
  360. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  361. break;
  362. default:
  363. rc = -ENOSYS;
  364. break;
  365. }
  366. return rc;
  367. }
  368. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  369. {
  370. struct beiscsi_hba *phba = data;
  371. char *str = buf;
  372. int rc;
  373. switch (type) {
  374. case ISCSI_BOOT_ETH_FLAGS:
  375. rc = sprintf(str, "2\n");
  376. break;
  377. case ISCSI_BOOT_ETH_INDEX:
  378. rc = sprintf(str, "0\n");
  379. break;
  380. case ISCSI_BOOT_ETH_MAC:
  381. rc = beiscsi_get_macaddr(str, phba);
  382. break;
  383. default:
  384. rc = -ENOSYS;
  385. break;
  386. }
  387. return rc;
  388. }
  389. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  390. {
  391. umode_t rc;
  392. switch (type) {
  393. case ISCSI_BOOT_TGT_NAME:
  394. case ISCSI_BOOT_TGT_IP_ADDR:
  395. case ISCSI_BOOT_TGT_PORT:
  396. case ISCSI_BOOT_TGT_CHAP_NAME:
  397. case ISCSI_BOOT_TGT_CHAP_SECRET:
  398. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  399. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  400. case ISCSI_BOOT_TGT_NIC_ASSOC:
  401. case ISCSI_BOOT_TGT_FLAGS:
  402. rc = S_IRUGO;
  403. break;
  404. default:
  405. rc = 0;
  406. break;
  407. }
  408. return rc;
  409. }
  410. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  411. {
  412. umode_t rc;
  413. switch (type) {
  414. case ISCSI_BOOT_INI_INITIATOR_NAME:
  415. rc = S_IRUGO;
  416. break;
  417. default:
  418. rc = 0;
  419. break;
  420. }
  421. return rc;
  422. }
  423. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  424. {
  425. umode_t rc;
  426. switch (type) {
  427. case ISCSI_BOOT_ETH_FLAGS:
  428. case ISCSI_BOOT_ETH_MAC:
  429. case ISCSI_BOOT_ETH_INDEX:
  430. rc = S_IRUGO;
  431. break;
  432. default:
  433. rc = 0;
  434. break;
  435. }
  436. return rc;
  437. }
  438. /*------------------- PCI Driver operations and data ----------------- */
  439. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  440. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  441. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  442. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  443. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  444. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  445. { 0 }
  446. };
  447. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  448. static struct scsi_host_template beiscsi_sht = {
  449. .module = THIS_MODULE,
  450. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  451. .proc_name = DRV_NAME,
  452. .queuecommand = iscsi_queuecommand,
  453. .change_queue_depth = iscsi_change_queue_depth,
  454. .slave_configure = beiscsi_slave_configure,
  455. .target_alloc = iscsi_target_alloc,
  456. .eh_abort_handler = beiscsi_eh_abort,
  457. .eh_device_reset_handler = beiscsi_eh_device_reset,
  458. .eh_target_reset_handler = iscsi_eh_session_reset,
  459. .shost_attrs = beiscsi_attrs,
  460. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  461. .can_queue = BE2_IO_DEPTH,
  462. .this_id = -1,
  463. .max_sectors = BEISCSI_MAX_SECTORS,
  464. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  465. .use_clustering = ENABLE_CLUSTERING,
  466. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  467. };
  468. static struct scsi_transport_template *beiscsi_scsi_transport;
  469. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  470. {
  471. struct beiscsi_hba *phba;
  472. struct Scsi_Host *shost;
  473. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  474. if (!shost) {
  475. dev_err(&pcidev->dev,
  476. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  477. return NULL;
  478. }
  479. shost->dma_boundary = pcidev->dma_mask;
  480. shost->max_id = BE2_MAX_SESSIONS;
  481. shost->max_channel = 0;
  482. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  483. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  484. shost->transportt = beiscsi_scsi_transport;
  485. phba = iscsi_host_priv(shost);
  486. memset(phba, 0, sizeof(*phba));
  487. phba->shost = shost;
  488. phba->pcidev = pci_dev_get(pcidev);
  489. pci_set_drvdata(pcidev, phba);
  490. phba->interface_handle = 0xFFFFFFFF;
  491. if (iscsi_host_add(shost, &phba->pcidev->dev))
  492. goto free_devices;
  493. return phba;
  494. free_devices:
  495. pci_dev_put(phba->pcidev);
  496. iscsi_host_free(phba->shost);
  497. return NULL;
  498. }
  499. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  500. {
  501. if (phba->csr_va) {
  502. iounmap(phba->csr_va);
  503. phba->csr_va = NULL;
  504. }
  505. if (phba->db_va) {
  506. iounmap(phba->db_va);
  507. phba->db_va = NULL;
  508. }
  509. if (phba->pci_va) {
  510. iounmap(phba->pci_va);
  511. phba->pci_va = NULL;
  512. }
  513. }
  514. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  515. struct pci_dev *pcidev)
  516. {
  517. u8 __iomem *addr;
  518. int pcicfg_reg;
  519. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  520. pci_resource_len(pcidev, 2));
  521. if (addr == NULL)
  522. return -ENOMEM;
  523. phba->ctrl.csr = addr;
  524. phba->csr_va = addr;
  525. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  526. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  527. if (addr == NULL)
  528. goto pci_map_err;
  529. phba->ctrl.db = addr;
  530. phba->db_va = addr;
  531. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  532. if (phba->generation == BE_GEN2)
  533. pcicfg_reg = 1;
  534. else
  535. pcicfg_reg = 0;
  536. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  537. pci_resource_len(pcidev, pcicfg_reg));
  538. if (addr == NULL)
  539. goto pci_map_err;
  540. phba->ctrl.pcicfg = addr;
  541. phba->pci_va = addr;
  542. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  543. return 0;
  544. pci_map_err:
  545. beiscsi_unmap_pci_function(phba);
  546. return -ENOMEM;
  547. }
  548. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  549. {
  550. int ret;
  551. ret = pci_enable_device(pcidev);
  552. if (ret) {
  553. dev_err(&pcidev->dev,
  554. "beiscsi_enable_pci - enable device failed\n");
  555. return ret;
  556. }
  557. pci_set_master(pcidev);
  558. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  559. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  560. if (ret) {
  561. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  562. pci_disable_device(pcidev);
  563. return ret;
  564. }
  565. }
  566. return 0;
  567. }
  568. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  569. {
  570. struct be_ctrl_info *ctrl = &phba->ctrl;
  571. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  572. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  573. int status = 0;
  574. ctrl->pdev = pdev;
  575. status = beiscsi_map_pci_bars(phba, pdev);
  576. if (status)
  577. return status;
  578. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  579. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  580. mbox_mem_alloc->size,
  581. &mbox_mem_alloc->dma);
  582. if (!mbox_mem_alloc->va) {
  583. beiscsi_unmap_pci_function(phba);
  584. return -ENOMEM;
  585. }
  586. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  587. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  588. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  589. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  590. spin_lock_init(&ctrl->mbox_lock);
  591. spin_lock_init(&phba->ctrl.mcc_lock);
  592. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  593. return status;
  594. }
  595. static void beiscsi_get_params(struct beiscsi_hba *phba)
  596. {
  597. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  598. - (phba->fw_config.iscsi_cid_count
  599. + BE2_TMFS
  600. + BE2_NOPOUT_REQ));
  601. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  602. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  603. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  604. phba->params.num_sge_per_io = BE2_SGE;
  605. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  606. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  607. phba->params.eq_timer = 64;
  608. phba->params.num_eq_entries =
  609. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  610. + BE2_TMFS) / 512) + 1) * 512;
  611. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  612. ? 1024 : phba->params.num_eq_entries;
  613. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  614. "BM_%d : phba->params.num_eq_entries=%d\n",
  615. phba->params.num_eq_entries);
  616. phba->params.num_cq_entries =
  617. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  618. + BE2_TMFS) / 512) + 1) * 512;
  619. phba->params.wrbs_per_cxn = 256;
  620. }
  621. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  622. unsigned int id, unsigned int clr_interrupt,
  623. unsigned int num_processed,
  624. unsigned char rearm, unsigned char event)
  625. {
  626. u32 val = 0;
  627. val |= id & DB_EQ_RING_ID_MASK;
  628. if (rearm)
  629. val |= 1 << DB_EQ_REARM_SHIFT;
  630. if (clr_interrupt)
  631. val |= 1 << DB_EQ_CLR_SHIFT;
  632. if (event)
  633. val |= 1 << DB_EQ_EVNT_SHIFT;
  634. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  635. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  636. }
  637. /**
  638. * be_isr_mcc - The isr routine of the driver.
  639. * @irq: Not used
  640. * @dev_id: Pointer to host adapter structure
  641. */
  642. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  643. {
  644. struct beiscsi_hba *phba;
  645. struct be_eq_entry *eqe = NULL;
  646. struct be_queue_info *eq;
  647. struct be_queue_info *mcc;
  648. unsigned int num_eq_processed;
  649. struct be_eq_obj *pbe_eq;
  650. unsigned long flags;
  651. pbe_eq = dev_id;
  652. eq = &pbe_eq->q;
  653. phba = pbe_eq->phba;
  654. mcc = &phba->ctrl.mcc_obj.cq;
  655. eqe = queue_tail_node(eq);
  656. num_eq_processed = 0;
  657. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  658. & EQE_VALID_MASK) {
  659. if (((eqe->dw[offsetof(struct amap_eq_entry,
  660. resource_id) / 32] &
  661. EQE_RESID_MASK) >> 16) == mcc->id) {
  662. spin_lock_irqsave(&phba->isr_lock, flags);
  663. phba->todo_mcc_cq = 1;
  664. spin_unlock_irqrestore(&phba->isr_lock, flags);
  665. }
  666. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  667. queue_tail_inc(eq);
  668. eqe = queue_tail_node(eq);
  669. num_eq_processed++;
  670. }
  671. if (phba->todo_mcc_cq)
  672. queue_work(phba->wq, &phba->work_cqs);
  673. if (num_eq_processed)
  674. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  675. return IRQ_HANDLED;
  676. }
  677. /**
  678. * be_isr_msix - The isr routine of the driver.
  679. * @irq: Not used
  680. * @dev_id: Pointer to host adapter structure
  681. */
  682. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  683. {
  684. struct beiscsi_hba *phba;
  685. struct be_eq_entry *eqe = NULL;
  686. struct be_queue_info *eq;
  687. struct be_queue_info *cq;
  688. unsigned int num_eq_processed;
  689. struct be_eq_obj *pbe_eq;
  690. unsigned long flags;
  691. pbe_eq = dev_id;
  692. eq = &pbe_eq->q;
  693. cq = pbe_eq->cq;
  694. eqe = queue_tail_node(eq);
  695. phba = pbe_eq->phba;
  696. num_eq_processed = 0;
  697. if (blk_iopoll_enabled) {
  698. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  699. & EQE_VALID_MASK) {
  700. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  701. blk_iopoll_sched(&pbe_eq->iopoll);
  702. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  703. queue_tail_inc(eq);
  704. eqe = queue_tail_node(eq);
  705. num_eq_processed++;
  706. }
  707. if (num_eq_processed)
  708. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  709. return IRQ_HANDLED;
  710. } else {
  711. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  712. & EQE_VALID_MASK) {
  713. spin_lock_irqsave(&phba->isr_lock, flags);
  714. phba->todo_cq = 1;
  715. spin_unlock_irqrestore(&phba->isr_lock, flags);
  716. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  717. queue_tail_inc(eq);
  718. eqe = queue_tail_node(eq);
  719. num_eq_processed++;
  720. }
  721. if (phba->todo_cq)
  722. queue_work(phba->wq, &phba->work_cqs);
  723. if (num_eq_processed)
  724. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  725. return IRQ_HANDLED;
  726. }
  727. }
  728. /**
  729. * be_isr - The isr routine of the driver.
  730. * @irq: Not used
  731. * @dev_id: Pointer to host adapter structure
  732. */
  733. static irqreturn_t be_isr(int irq, void *dev_id)
  734. {
  735. struct beiscsi_hba *phba;
  736. struct hwi_controller *phwi_ctrlr;
  737. struct hwi_context_memory *phwi_context;
  738. struct be_eq_entry *eqe = NULL;
  739. struct be_queue_info *eq;
  740. struct be_queue_info *cq;
  741. struct be_queue_info *mcc;
  742. unsigned long flags, index;
  743. unsigned int num_mcceq_processed, num_ioeq_processed;
  744. struct be_ctrl_info *ctrl;
  745. struct be_eq_obj *pbe_eq;
  746. int isr;
  747. phba = dev_id;
  748. ctrl = &phba->ctrl;
  749. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  750. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  751. if (!isr)
  752. return IRQ_NONE;
  753. phwi_ctrlr = phba->phwi_ctrlr;
  754. phwi_context = phwi_ctrlr->phwi_ctxt;
  755. pbe_eq = &phwi_context->be_eq[0];
  756. eq = &phwi_context->be_eq[0].q;
  757. mcc = &phba->ctrl.mcc_obj.cq;
  758. index = 0;
  759. eqe = queue_tail_node(eq);
  760. num_ioeq_processed = 0;
  761. num_mcceq_processed = 0;
  762. if (blk_iopoll_enabled) {
  763. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  764. & EQE_VALID_MASK) {
  765. if (((eqe->dw[offsetof(struct amap_eq_entry,
  766. resource_id) / 32] &
  767. EQE_RESID_MASK) >> 16) == mcc->id) {
  768. spin_lock_irqsave(&phba->isr_lock, flags);
  769. phba->todo_mcc_cq = 1;
  770. spin_unlock_irqrestore(&phba->isr_lock, flags);
  771. num_mcceq_processed++;
  772. } else {
  773. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  774. blk_iopoll_sched(&pbe_eq->iopoll);
  775. num_ioeq_processed++;
  776. }
  777. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  778. queue_tail_inc(eq);
  779. eqe = queue_tail_node(eq);
  780. }
  781. if (num_ioeq_processed || num_mcceq_processed) {
  782. if (phba->todo_mcc_cq)
  783. queue_work(phba->wq, &phba->work_cqs);
  784. if ((num_mcceq_processed) && (!num_ioeq_processed))
  785. hwi_ring_eq_db(phba, eq->id, 0,
  786. (num_ioeq_processed +
  787. num_mcceq_processed) , 1, 1);
  788. else
  789. hwi_ring_eq_db(phba, eq->id, 0,
  790. (num_ioeq_processed +
  791. num_mcceq_processed), 0, 1);
  792. return IRQ_HANDLED;
  793. } else
  794. return IRQ_NONE;
  795. } else {
  796. cq = &phwi_context->be_cq[0];
  797. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  798. & EQE_VALID_MASK) {
  799. if (((eqe->dw[offsetof(struct amap_eq_entry,
  800. resource_id) / 32] &
  801. EQE_RESID_MASK) >> 16) != cq->id) {
  802. spin_lock_irqsave(&phba->isr_lock, flags);
  803. phba->todo_mcc_cq = 1;
  804. spin_unlock_irqrestore(&phba->isr_lock, flags);
  805. } else {
  806. spin_lock_irqsave(&phba->isr_lock, flags);
  807. phba->todo_cq = 1;
  808. spin_unlock_irqrestore(&phba->isr_lock, flags);
  809. }
  810. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  811. queue_tail_inc(eq);
  812. eqe = queue_tail_node(eq);
  813. num_ioeq_processed++;
  814. }
  815. if (phba->todo_cq || phba->todo_mcc_cq)
  816. queue_work(phba->wq, &phba->work_cqs);
  817. if (num_ioeq_processed) {
  818. hwi_ring_eq_db(phba, eq->id, 0,
  819. num_ioeq_processed, 1, 1);
  820. return IRQ_HANDLED;
  821. } else
  822. return IRQ_NONE;
  823. }
  824. }
  825. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  826. {
  827. struct pci_dev *pcidev = phba->pcidev;
  828. struct hwi_controller *phwi_ctrlr;
  829. struct hwi_context_memory *phwi_context;
  830. int ret, msix_vec, i, j;
  831. phwi_ctrlr = phba->phwi_ctrlr;
  832. phwi_context = phwi_ctrlr->phwi_ctxt;
  833. if (phba->msix_enabled) {
  834. for (i = 0; i < phba->num_cpus; i++) {
  835. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  836. GFP_KERNEL);
  837. if (!phba->msi_name[i]) {
  838. ret = -ENOMEM;
  839. goto free_msix_irqs;
  840. }
  841. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  842. phba->shost->host_no, i);
  843. msix_vec = phba->msix_entries[i].vector;
  844. ret = request_irq(msix_vec, be_isr_msix, 0,
  845. phba->msi_name[i],
  846. &phwi_context->be_eq[i]);
  847. if (ret) {
  848. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  849. "BM_%d : beiscsi_init_irqs-Failed to"
  850. "register msix for i = %d\n",
  851. i);
  852. kfree(phba->msi_name[i]);
  853. goto free_msix_irqs;
  854. }
  855. }
  856. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  857. if (!phba->msi_name[i]) {
  858. ret = -ENOMEM;
  859. goto free_msix_irqs;
  860. }
  861. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  862. phba->shost->host_no);
  863. msix_vec = phba->msix_entries[i].vector;
  864. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  865. &phwi_context->be_eq[i]);
  866. if (ret) {
  867. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  868. "BM_%d : beiscsi_init_irqs-"
  869. "Failed to register beiscsi_msix_mcc\n");
  870. kfree(phba->msi_name[i]);
  871. goto free_msix_irqs;
  872. }
  873. } else {
  874. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  875. "beiscsi", phba);
  876. if (ret) {
  877. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  878. "BM_%d : beiscsi_init_irqs-"
  879. "Failed to register irq\\n");
  880. return ret;
  881. }
  882. }
  883. return 0;
  884. free_msix_irqs:
  885. for (j = i - 1; j >= 0; j--) {
  886. kfree(phba->msi_name[j]);
  887. msix_vec = phba->msix_entries[j].vector;
  888. free_irq(msix_vec, &phwi_context->be_eq[j]);
  889. }
  890. return ret;
  891. }
  892. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  893. unsigned int id, unsigned int num_processed,
  894. unsigned char rearm, unsigned char event)
  895. {
  896. u32 val = 0;
  897. val |= id & DB_CQ_RING_ID_MASK;
  898. if (rearm)
  899. val |= 1 << DB_CQ_REARM_SHIFT;
  900. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  901. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  902. }
  903. static unsigned int
  904. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  905. struct beiscsi_hba *phba,
  906. unsigned short cid,
  907. struct pdu_base *ppdu,
  908. unsigned long pdu_len,
  909. void *pbuffer, unsigned long buf_len)
  910. {
  911. struct iscsi_conn *conn = beiscsi_conn->conn;
  912. struct iscsi_session *session = conn->session;
  913. struct iscsi_task *task;
  914. struct beiscsi_io_task *io_task;
  915. struct iscsi_hdr *login_hdr;
  916. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  917. PDUBASE_OPCODE_MASK) {
  918. case ISCSI_OP_NOOP_IN:
  919. pbuffer = NULL;
  920. buf_len = 0;
  921. break;
  922. case ISCSI_OP_ASYNC_EVENT:
  923. break;
  924. case ISCSI_OP_REJECT:
  925. WARN_ON(!pbuffer);
  926. WARN_ON(!(buf_len == 48));
  927. beiscsi_log(phba, KERN_ERR,
  928. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  929. "BM_%d : In ISCSI_OP_REJECT\n");
  930. break;
  931. case ISCSI_OP_LOGIN_RSP:
  932. case ISCSI_OP_TEXT_RSP:
  933. task = conn->login_task;
  934. io_task = task->dd_data;
  935. login_hdr = (struct iscsi_hdr *)ppdu;
  936. login_hdr->itt = io_task->libiscsi_itt;
  937. break;
  938. default:
  939. beiscsi_log(phba, KERN_WARNING,
  940. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  941. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  942. (ppdu->
  943. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  944. & PDUBASE_OPCODE_MASK));
  945. return 1;
  946. }
  947. spin_lock_bh(&session->lock);
  948. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  949. spin_unlock_bh(&session->lock);
  950. return 0;
  951. }
  952. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  953. {
  954. struct sgl_handle *psgl_handle;
  955. if (phba->io_sgl_hndl_avbl) {
  956. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  957. "BM_%d : In alloc_io_sgl_handle,"
  958. " io_sgl_alloc_index=%d\n",
  959. phba->io_sgl_alloc_index);
  960. psgl_handle = phba->io_sgl_hndl_base[phba->
  961. io_sgl_alloc_index];
  962. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  963. phba->io_sgl_hndl_avbl--;
  964. if (phba->io_sgl_alloc_index == (phba->params.
  965. ios_per_ctrl - 1))
  966. phba->io_sgl_alloc_index = 0;
  967. else
  968. phba->io_sgl_alloc_index++;
  969. } else
  970. psgl_handle = NULL;
  971. return psgl_handle;
  972. }
  973. static void
  974. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  975. {
  976. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  977. "BM_%d : In free_,io_sgl_free_index=%d\n",
  978. phba->io_sgl_free_index);
  979. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  980. /*
  981. * this can happen if clean_task is called on a task that
  982. * failed in xmit_task or alloc_pdu.
  983. */
  984. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  985. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  986. "value there=%p\n", phba->io_sgl_free_index,
  987. phba->io_sgl_hndl_base
  988. [phba->io_sgl_free_index]);
  989. return;
  990. }
  991. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  992. phba->io_sgl_hndl_avbl++;
  993. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  994. phba->io_sgl_free_index = 0;
  995. else
  996. phba->io_sgl_free_index++;
  997. }
  998. /**
  999. * alloc_wrb_handle - To allocate a wrb handle
  1000. * @phba: The hba pointer
  1001. * @cid: The cid to use for allocation
  1002. *
  1003. * This happens under session_lock until submission to chip
  1004. */
  1005. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1006. {
  1007. struct hwi_wrb_context *pwrb_context;
  1008. struct hwi_controller *phwi_ctrlr;
  1009. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1010. phwi_ctrlr = phba->phwi_ctrlr;
  1011. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  1012. if (pwrb_context->wrb_handles_available >= 2) {
  1013. pwrb_handle = pwrb_context->pwrb_handle_base[
  1014. pwrb_context->alloc_index];
  1015. pwrb_context->wrb_handles_available--;
  1016. if (pwrb_context->alloc_index ==
  1017. (phba->params.wrbs_per_cxn - 1))
  1018. pwrb_context->alloc_index = 0;
  1019. else
  1020. pwrb_context->alloc_index++;
  1021. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1022. pwrb_context->alloc_index];
  1023. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1024. } else
  1025. pwrb_handle = NULL;
  1026. return pwrb_handle;
  1027. }
  1028. /**
  1029. * free_wrb_handle - To free the wrb handle back to pool
  1030. * @phba: The hba pointer
  1031. * @pwrb_context: The context to free from
  1032. * @pwrb_handle: The wrb_handle to free
  1033. *
  1034. * This happens under session_lock until submission to chip
  1035. */
  1036. static void
  1037. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1038. struct wrb_handle *pwrb_handle)
  1039. {
  1040. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1041. pwrb_context->wrb_handles_available++;
  1042. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1043. pwrb_context->free_index = 0;
  1044. else
  1045. pwrb_context->free_index++;
  1046. beiscsi_log(phba, KERN_INFO,
  1047. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1048. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1049. "wrb_handles_available=%d\n",
  1050. pwrb_handle, pwrb_context->free_index,
  1051. pwrb_context->wrb_handles_available);
  1052. }
  1053. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1054. {
  1055. struct sgl_handle *psgl_handle;
  1056. if (phba->eh_sgl_hndl_avbl) {
  1057. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1058. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1059. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1060. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1061. phba->eh_sgl_alloc_index,
  1062. phba->eh_sgl_alloc_index);
  1063. phba->eh_sgl_hndl_avbl--;
  1064. if (phba->eh_sgl_alloc_index ==
  1065. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1066. 1))
  1067. phba->eh_sgl_alloc_index = 0;
  1068. else
  1069. phba->eh_sgl_alloc_index++;
  1070. } else
  1071. psgl_handle = NULL;
  1072. return psgl_handle;
  1073. }
  1074. void
  1075. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1076. {
  1077. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1078. "BM_%d : In free_mgmt_sgl_handle,"
  1079. "eh_sgl_free_index=%d\n",
  1080. phba->eh_sgl_free_index);
  1081. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1082. /*
  1083. * this can happen if clean_task is called on a task that
  1084. * failed in xmit_task or alloc_pdu.
  1085. */
  1086. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1087. "BM_%d : Double Free in eh SGL ,"
  1088. "eh_sgl_free_index=%d\n",
  1089. phba->eh_sgl_free_index);
  1090. return;
  1091. }
  1092. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1093. phba->eh_sgl_hndl_avbl++;
  1094. if (phba->eh_sgl_free_index ==
  1095. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1096. phba->eh_sgl_free_index = 0;
  1097. else
  1098. phba->eh_sgl_free_index++;
  1099. }
  1100. static void
  1101. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1102. struct iscsi_task *task, struct sol_cqe *psol)
  1103. {
  1104. struct beiscsi_io_task *io_task = task->dd_data;
  1105. struct be_status_bhs *sts_bhs =
  1106. (struct be_status_bhs *)io_task->cmd_bhs;
  1107. struct iscsi_conn *conn = beiscsi_conn->conn;
  1108. unsigned char *sense;
  1109. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1110. u8 rsp, status, flags;
  1111. exp_cmdsn = (psol->
  1112. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1113. & SOL_EXP_CMD_SN_MASK);
  1114. max_cmdsn = ((psol->
  1115. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1116. & SOL_EXP_CMD_SN_MASK) +
  1117. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1118. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1119. rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
  1120. & SOL_RESP_MASK) >> 16);
  1121. status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
  1122. & SOL_STS_MASK) >> 8);
  1123. flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1124. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1125. if (!task->sc) {
  1126. if (io_task->scsi_cmnd)
  1127. scsi_dma_unmap(io_task->scsi_cmnd);
  1128. return;
  1129. }
  1130. task->sc->result = (DID_OK << 16) | status;
  1131. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1132. task->sc->result = DID_ERROR << 16;
  1133. goto unmap;
  1134. }
  1135. /* bidi not initially supported */
  1136. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1137. resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
  1138. 32] & SOL_RES_CNT_MASK);
  1139. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1140. task->sc->result = DID_ERROR << 16;
  1141. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1142. scsi_set_resid(task->sc, resid);
  1143. if (!status && (scsi_bufflen(task->sc) - resid <
  1144. task->sc->underflow))
  1145. task->sc->result = DID_ERROR << 16;
  1146. }
  1147. }
  1148. if (status == SAM_STAT_CHECK_CONDITION) {
  1149. u16 sense_len;
  1150. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1151. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1152. sense_len = be16_to_cpu(*slen);
  1153. memcpy(task->sc->sense_buffer, sense,
  1154. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1155. }
  1156. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
  1157. if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1158. & SOL_RES_CNT_MASK)
  1159. conn->rxdata_octets += (psol->
  1160. dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1161. & SOL_RES_CNT_MASK);
  1162. }
  1163. unmap:
  1164. scsi_dma_unmap(io_task->scsi_cmnd);
  1165. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1166. }
  1167. static void
  1168. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1169. struct iscsi_task *task, struct sol_cqe *psol)
  1170. {
  1171. struct iscsi_logout_rsp *hdr;
  1172. struct beiscsi_io_task *io_task = task->dd_data;
  1173. struct iscsi_conn *conn = beiscsi_conn->conn;
  1174. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1175. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1176. hdr->t2wait = 5;
  1177. hdr->t2retain = 0;
  1178. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1179. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1180. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1181. 32] & SOL_RESP_MASK);
  1182. hdr->exp_cmdsn = cpu_to_be32(psol->
  1183. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1184. & SOL_EXP_CMD_SN_MASK);
  1185. hdr->max_cmdsn = be32_to_cpu((psol->
  1186. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1187. & SOL_EXP_CMD_SN_MASK) +
  1188. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1189. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1190. hdr->dlength[0] = 0;
  1191. hdr->dlength[1] = 0;
  1192. hdr->dlength[2] = 0;
  1193. hdr->hlength = 0;
  1194. hdr->itt = io_task->libiscsi_itt;
  1195. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1196. }
  1197. static void
  1198. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1199. struct iscsi_task *task, struct sol_cqe *psol)
  1200. {
  1201. struct iscsi_tm_rsp *hdr;
  1202. struct iscsi_conn *conn = beiscsi_conn->conn;
  1203. struct beiscsi_io_task *io_task = task->dd_data;
  1204. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1205. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1206. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1207. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1208. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1209. 32] & SOL_RESP_MASK);
  1210. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1211. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1212. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1213. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1214. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1215. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1216. hdr->itt = io_task->libiscsi_itt;
  1217. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1218. }
  1219. static void
  1220. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1221. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1222. {
  1223. struct hwi_wrb_context *pwrb_context;
  1224. struct wrb_handle *pwrb_handle = NULL;
  1225. struct hwi_controller *phwi_ctrlr;
  1226. struct iscsi_task *task;
  1227. struct beiscsi_io_task *io_task;
  1228. struct iscsi_conn *conn = beiscsi_conn->conn;
  1229. struct iscsi_session *session = conn->session;
  1230. phwi_ctrlr = phba->phwi_ctrlr;
  1231. pwrb_context = &phwi_ctrlr->wrb_context[((psol->
  1232. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1233. SOL_CID_MASK) >> 6) -
  1234. phba->fw_config.iscsi_cid_start];
  1235. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1236. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1237. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1238. task = pwrb_handle->pio_handle;
  1239. io_task = task->dd_data;
  1240. spin_lock_bh(&phba->mgmt_sgl_lock);
  1241. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1242. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1243. spin_lock_bh(&session->lock);
  1244. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1245. spin_unlock_bh(&session->lock);
  1246. }
  1247. static void
  1248. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1249. struct iscsi_task *task, struct sol_cqe *psol)
  1250. {
  1251. struct iscsi_nopin *hdr;
  1252. struct iscsi_conn *conn = beiscsi_conn->conn;
  1253. struct beiscsi_io_task *io_task = task->dd_data;
  1254. hdr = (struct iscsi_nopin *)task->hdr;
  1255. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1256. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1257. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1258. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1259. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1260. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1261. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1262. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1263. hdr->opcode = ISCSI_OP_NOOP_IN;
  1264. hdr->itt = io_task->libiscsi_itt;
  1265. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1266. }
  1267. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1268. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1269. {
  1270. struct hwi_wrb_context *pwrb_context;
  1271. struct wrb_handle *pwrb_handle;
  1272. struct iscsi_wrb *pwrb = NULL;
  1273. struct hwi_controller *phwi_ctrlr;
  1274. struct iscsi_task *task;
  1275. unsigned int type;
  1276. struct iscsi_conn *conn = beiscsi_conn->conn;
  1277. struct iscsi_session *session = conn->session;
  1278. phwi_ctrlr = phba->phwi_ctrlr;
  1279. pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
  1280. (struct amap_sol_cqe, cid) / 32]
  1281. & SOL_CID_MASK) >> 6) -
  1282. phba->fw_config.iscsi_cid_start];
  1283. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1284. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1285. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1286. task = pwrb_handle->pio_handle;
  1287. pwrb = pwrb_handle->pwrb;
  1288. type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
  1289. WRB_TYPE_MASK) >> 28;
  1290. spin_lock_bh(&session->lock);
  1291. switch (type) {
  1292. case HWH_TYPE_IO:
  1293. case HWH_TYPE_IO_RD:
  1294. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1295. ISCSI_OP_NOOP_OUT)
  1296. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1297. else
  1298. be_complete_io(beiscsi_conn, task, psol);
  1299. break;
  1300. case HWH_TYPE_LOGOUT:
  1301. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1302. be_complete_logout(beiscsi_conn, task, psol);
  1303. else
  1304. be_complete_tmf(beiscsi_conn, task, psol);
  1305. break;
  1306. case HWH_TYPE_LOGIN:
  1307. beiscsi_log(phba, KERN_ERR,
  1308. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1309. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1310. " hwi_complete_cmd- Solicited path\n");
  1311. break;
  1312. case HWH_TYPE_NOP:
  1313. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1314. break;
  1315. default:
  1316. beiscsi_log(phba, KERN_WARNING,
  1317. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1318. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1319. "wrb_index 0x%x CID 0x%x\n", type,
  1320. ((psol->dw[offsetof(struct amap_iscsi_wrb,
  1321. type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
  1322. ((psol->dw[offsetof(struct amap_sol_cqe,
  1323. cid) / 32] & SOL_CID_MASK) >> 6));
  1324. break;
  1325. }
  1326. spin_unlock_bh(&session->lock);
  1327. }
  1328. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1329. *pasync_ctx, unsigned int is_header,
  1330. unsigned int host_write_ptr)
  1331. {
  1332. if (is_header)
  1333. return &pasync_ctx->async_entry[host_write_ptr].
  1334. header_busy_list;
  1335. else
  1336. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1337. }
  1338. static struct async_pdu_handle *
  1339. hwi_get_async_handle(struct beiscsi_hba *phba,
  1340. struct beiscsi_conn *beiscsi_conn,
  1341. struct hwi_async_pdu_context *pasync_ctx,
  1342. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1343. {
  1344. struct be_bus_address phys_addr;
  1345. struct list_head *pbusy_list;
  1346. struct async_pdu_handle *pasync_handle = NULL;
  1347. unsigned char is_header = 0;
  1348. phys_addr.u.a32.address_lo =
  1349. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
  1350. ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1351. & PDUCQE_DPL_MASK) >> 16);
  1352. phys_addr.u.a32.address_hi =
  1353. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
  1354. phys_addr.u.a64.address =
  1355. *((unsigned long long *)(&phys_addr.u.a64.address));
  1356. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1357. & PDUCQE_CODE_MASK) {
  1358. case UNSOL_HDR_NOTIFY:
  1359. is_header = 1;
  1360. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
  1361. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1362. index) / 32] & PDUCQE_INDEX_MASK));
  1363. break;
  1364. case UNSOL_DATA_NOTIFY:
  1365. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
  1366. dw[offsetof(struct amap_i_t_dpdu_cqe,
  1367. index) / 32] & PDUCQE_INDEX_MASK));
  1368. break;
  1369. default:
  1370. pbusy_list = NULL;
  1371. beiscsi_log(phba, KERN_WARNING,
  1372. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1373. "BM_%d : Unexpected code=%d\n",
  1374. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1375. code) / 32] & PDUCQE_CODE_MASK);
  1376. return NULL;
  1377. }
  1378. WARN_ON(list_empty(pbusy_list));
  1379. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1380. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1381. break;
  1382. }
  1383. WARN_ON(!pasync_handle);
  1384. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1385. phba->fw_config.iscsi_cid_start;
  1386. pasync_handle->is_header = is_header;
  1387. pasync_handle->buffer_len = ((pdpdu_cqe->
  1388. dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1389. & PDUCQE_DPL_MASK) >> 16);
  1390. *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1391. index) / 32] & PDUCQE_INDEX_MASK);
  1392. return pasync_handle;
  1393. }
  1394. static unsigned int
  1395. hwi_update_async_writables(struct beiscsi_hba *phba,
  1396. struct hwi_async_pdu_context *pasync_ctx,
  1397. unsigned int is_header, unsigned int cq_index)
  1398. {
  1399. struct list_head *pbusy_list;
  1400. struct async_pdu_handle *pasync_handle;
  1401. unsigned int num_entries, writables = 0;
  1402. unsigned int *pep_read_ptr, *pwritables;
  1403. num_entries = pasync_ctx->num_entries;
  1404. if (is_header) {
  1405. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1406. pwritables = &pasync_ctx->async_header.writables;
  1407. } else {
  1408. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1409. pwritables = &pasync_ctx->async_data.writables;
  1410. }
  1411. while ((*pep_read_ptr) != cq_index) {
  1412. (*pep_read_ptr)++;
  1413. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1414. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1415. *pep_read_ptr);
  1416. if (writables == 0)
  1417. WARN_ON(list_empty(pbusy_list));
  1418. if (!list_empty(pbusy_list)) {
  1419. pasync_handle = list_entry(pbusy_list->next,
  1420. struct async_pdu_handle,
  1421. link);
  1422. WARN_ON(!pasync_handle);
  1423. pasync_handle->consumed = 1;
  1424. }
  1425. writables++;
  1426. }
  1427. if (!writables) {
  1428. beiscsi_log(phba, KERN_ERR,
  1429. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1430. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1431. cq_index);
  1432. WARN_ON(1);
  1433. }
  1434. *pwritables = *pwritables + writables;
  1435. return 0;
  1436. }
  1437. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1438. unsigned int cri)
  1439. {
  1440. struct hwi_controller *phwi_ctrlr;
  1441. struct hwi_async_pdu_context *pasync_ctx;
  1442. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1443. struct list_head *plist;
  1444. phwi_ctrlr = phba->phwi_ctrlr;
  1445. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1446. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1447. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1448. list_del(&pasync_handle->link);
  1449. if (pasync_handle->is_header) {
  1450. list_add_tail(&pasync_handle->link,
  1451. &pasync_ctx->async_header.free_list);
  1452. pasync_ctx->async_header.free_entries++;
  1453. } else {
  1454. list_add_tail(&pasync_handle->link,
  1455. &pasync_ctx->async_data.free_list);
  1456. pasync_ctx->async_data.free_entries++;
  1457. }
  1458. }
  1459. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1460. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1461. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1462. }
  1463. static struct phys_addr *
  1464. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1465. unsigned int is_header, unsigned int host_write_ptr)
  1466. {
  1467. struct phys_addr *pasync_sge = NULL;
  1468. if (is_header)
  1469. pasync_sge = pasync_ctx->async_header.ring_base;
  1470. else
  1471. pasync_sge = pasync_ctx->async_data.ring_base;
  1472. return pasync_sge + host_write_ptr;
  1473. }
  1474. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1475. unsigned int is_header)
  1476. {
  1477. struct hwi_controller *phwi_ctrlr;
  1478. struct hwi_async_pdu_context *pasync_ctx;
  1479. struct async_pdu_handle *pasync_handle;
  1480. struct list_head *pfree_link, *pbusy_list;
  1481. struct phys_addr *pasync_sge;
  1482. unsigned int ring_id, num_entries;
  1483. unsigned int host_write_num;
  1484. unsigned int writables;
  1485. unsigned int i = 0;
  1486. u32 doorbell = 0;
  1487. phwi_ctrlr = phba->phwi_ctrlr;
  1488. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1489. num_entries = pasync_ctx->num_entries;
  1490. if (is_header) {
  1491. writables = min(pasync_ctx->async_header.writables,
  1492. pasync_ctx->async_header.free_entries);
  1493. pfree_link = pasync_ctx->async_header.free_list.next;
  1494. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1495. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1496. } else {
  1497. writables = min(pasync_ctx->async_data.writables,
  1498. pasync_ctx->async_data.free_entries);
  1499. pfree_link = pasync_ctx->async_data.free_list.next;
  1500. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1501. ring_id = phwi_ctrlr->default_pdu_data.id;
  1502. }
  1503. writables = (writables / 8) * 8;
  1504. if (writables) {
  1505. for (i = 0; i < writables; i++) {
  1506. pbusy_list =
  1507. hwi_get_async_busy_list(pasync_ctx, is_header,
  1508. host_write_num);
  1509. pasync_handle =
  1510. list_entry(pfree_link, struct async_pdu_handle,
  1511. link);
  1512. WARN_ON(!pasync_handle);
  1513. pasync_handle->consumed = 0;
  1514. pfree_link = pfree_link->next;
  1515. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1516. is_header, host_write_num);
  1517. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1518. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1519. list_move(&pasync_handle->link, pbusy_list);
  1520. host_write_num++;
  1521. host_write_num = host_write_num % num_entries;
  1522. }
  1523. if (is_header) {
  1524. pasync_ctx->async_header.host_write_ptr =
  1525. host_write_num;
  1526. pasync_ctx->async_header.free_entries -= writables;
  1527. pasync_ctx->async_header.writables -= writables;
  1528. pasync_ctx->async_header.busy_entries += writables;
  1529. } else {
  1530. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1531. pasync_ctx->async_data.free_entries -= writables;
  1532. pasync_ctx->async_data.writables -= writables;
  1533. pasync_ctx->async_data.busy_entries += writables;
  1534. }
  1535. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1536. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1537. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1538. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1539. << DB_DEF_PDU_CQPROC_SHIFT;
  1540. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1541. }
  1542. }
  1543. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1544. struct beiscsi_conn *beiscsi_conn,
  1545. struct i_t_dpdu_cqe *pdpdu_cqe)
  1546. {
  1547. struct hwi_controller *phwi_ctrlr;
  1548. struct hwi_async_pdu_context *pasync_ctx;
  1549. struct async_pdu_handle *pasync_handle = NULL;
  1550. unsigned int cq_index = -1;
  1551. phwi_ctrlr = phba->phwi_ctrlr;
  1552. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1553. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1554. pdpdu_cqe, &cq_index);
  1555. BUG_ON(pasync_handle->is_header != 0);
  1556. if (pasync_handle->consumed == 0)
  1557. hwi_update_async_writables(phba, pasync_ctx,
  1558. pasync_handle->is_header, cq_index);
  1559. hwi_free_async_msg(phba, pasync_handle->cri);
  1560. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1561. }
  1562. static unsigned int
  1563. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1564. struct beiscsi_hba *phba,
  1565. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1566. {
  1567. struct list_head *plist;
  1568. struct async_pdu_handle *pasync_handle;
  1569. void *phdr = NULL;
  1570. unsigned int hdr_len = 0, buf_len = 0;
  1571. unsigned int status, index = 0, offset = 0;
  1572. void *pfirst_buffer = NULL;
  1573. unsigned int num_buf = 0;
  1574. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1575. list_for_each_entry(pasync_handle, plist, link) {
  1576. if (index == 0) {
  1577. phdr = pasync_handle->pbuffer;
  1578. hdr_len = pasync_handle->buffer_len;
  1579. } else {
  1580. buf_len = pasync_handle->buffer_len;
  1581. if (!num_buf) {
  1582. pfirst_buffer = pasync_handle->pbuffer;
  1583. num_buf++;
  1584. }
  1585. memcpy(pfirst_buffer + offset,
  1586. pasync_handle->pbuffer, buf_len);
  1587. offset += buf_len;
  1588. }
  1589. index++;
  1590. }
  1591. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1592. (beiscsi_conn->beiscsi_conn_cid -
  1593. phba->fw_config.iscsi_cid_start),
  1594. phdr, hdr_len, pfirst_buffer,
  1595. offset);
  1596. hwi_free_async_msg(phba, cri);
  1597. return 0;
  1598. }
  1599. static unsigned int
  1600. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1601. struct beiscsi_hba *phba,
  1602. struct async_pdu_handle *pasync_handle)
  1603. {
  1604. struct hwi_async_pdu_context *pasync_ctx;
  1605. struct hwi_controller *phwi_ctrlr;
  1606. unsigned int bytes_needed = 0, status = 0;
  1607. unsigned short cri = pasync_handle->cri;
  1608. struct pdu_base *ppdu;
  1609. phwi_ctrlr = phba->phwi_ctrlr;
  1610. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1611. list_del(&pasync_handle->link);
  1612. if (pasync_handle->is_header) {
  1613. pasync_ctx->async_header.busy_entries--;
  1614. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1615. hwi_free_async_msg(phba, cri);
  1616. BUG();
  1617. }
  1618. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1619. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1620. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1621. (unsigned short)pasync_handle->buffer_len;
  1622. list_add_tail(&pasync_handle->link,
  1623. &pasync_ctx->async_entry[cri].wait_queue.list);
  1624. ppdu = pasync_handle->pbuffer;
  1625. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1626. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1627. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1628. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1629. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1630. if (status == 0) {
  1631. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1632. bytes_needed;
  1633. if (bytes_needed == 0)
  1634. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1635. pasync_ctx, cri);
  1636. }
  1637. } else {
  1638. pasync_ctx->async_data.busy_entries--;
  1639. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1640. list_add_tail(&pasync_handle->link,
  1641. &pasync_ctx->async_entry[cri].wait_queue.
  1642. list);
  1643. pasync_ctx->async_entry[cri].wait_queue.
  1644. bytes_received +=
  1645. (unsigned short)pasync_handle->buffer_len;
  1646. if (pasync_ctx->async_entry[cri].wait_queue.
  1647. bytes_received >=
  1648. pasync_ctx->async_entry[cri].wait_queue.
  1649. bytes_needed)
  1650. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1651. pasync_ctx, cri);
  1652. }
  1653. }
  1654. return status;
  1655. }
  1656. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1657. struct beiscsi_hba *phba,
  1658. struct i_t_dpdu_cqe *pdpdu_cqe)
  1659. {
  1660. struct hwi_controller *phwi_ctrlr;
  1661. struct hwi_async_pdu_context *pasync_ctx;
  1662. struct async_pdu_handle *pasync_handle = NULL;
  1663. unsigned int cq_index = -1;
  1664. phwi_ctrlr = phba->phwi_ctrlr;
  1665. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1666. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1667. pdpdu_cqe, &cq_index);
  1668. if (pasync_handle->consumed == 0)
  1669. hwi_update_async_writables(phba, pasync_ctx,
  1670. pasync_handle->is_header, cq_index);
  1671. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1672. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1673. }
  1674. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1675. {
  1676. struct be_queue_info *mcc_cq;
  1677. struct be_mcc_compl *mcc_compl;
  1678. unsigned int num_processed = 0;
  1679. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1680. mcc_compl = queue_tail_node(mcc_cq);
  1681. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1682. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1683. if (num_processed >= 32) {
  1684. hwi_ring_cq_db(phba, mcc_cq->id,
  1685. num_processed, 0, 0);
  1686. num_processed = 0;
  1687. }
  1688. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1689. /* Interpret flags as an async trailer */
  1690. if (is_link_state_evt(mcc_compl->flags))
  1691. /* Interpret compl as a async link evt */
  1692. beiscsi_async_link_state_process(phba,
  1693. (struct be_async_event_link_state *) mcc_compl);
  1694. else
  1695. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1696. "BM_%d : Unsupported Async Event, flags"
  1697. " = 0x%08x\n",
  1698. mcc_compl->flags);
  1699. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1700. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1701. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1702. }
  1703. mcc_compl->flags = 0;
  1704. queue_tail_inc(mcc_cq);
  1705. mcc_compl = queue_tail_node(mcc_cq);
  1706. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1707. num_processed++;
  1708. }
  1709. if (num_processed > 0)
  1710. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1711. }
  1712. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1713. {
  1714. struct be_queue_info *cq;
  1715. struct sol_cqe *sol;
  1716. struct dmsg_cqe *dmsg;
  1717. unsigned int num_processed = 0;
  1718. unsigned int tot_nump = 0;
  1719. unsigned short code = 0, cid = 0;
  1720. struct beiscsi_conn *beiscsi_conn;
  1721. struct beiscsi_endpoint *beiscsi_ep;
  1722. struct iscsi_endpoint *ep;
  1723. struct beiscsi_hba *phba;
  1724. cq = pbe_eq->cq;
  1725. sol = queue_tail_node(cq);
  1726. phba = pbe_eq->phba;
  1727. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1728. CQE_VALID_MASK) {
  1729. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1730. cid = ((sol->dw[offsetof(struct amap_sol_cqe, cid)/32] &
  1731. CQE_CID_MASK) >> 6);
  1732. code = (sol->dw[offsetof(struct amap_sol_cqe, code)/32] &
  1733. CQE_CODE_MASK);
  1734. ep = phba->ep_array[cid - phba->fw_config.iscsi_cid_start];
  1735. beiscsi_ep = ep->dd_data;
  1736. beiscsi_conn = beiscsi_ep->conn;
  1737. if (num_processed >= 32) {
  1738. hwi_ring_cq_db(phba, cq->id,
  1739. num_processed, 0, 0);
  1740. tot_nump += num_processed;
  1741. num_processed = 0;
  1742. }
  1743. switch (code) {
  1744. case SOL_CMD_COMPLETE:
  1745. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1746. break;
  1747. case DRIVERMSG_NOTIFY:
  1748. beiscsi_log(phba, KERN_INFO,
  1749. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1750. "BM_%d : Received DRIVERMSG_NOTIFY\n");
  1751. dmsg = (struct dmsg_cqe *)sol;
  1752. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1753. break;
  1754. case UNSOL_HDR_NOTIFY:
  1755. beiscsi_log(phba, KERN_INFO,
  1756. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1757. "BM_%d : Received UNSOL_HDR_ NOTIFY\n");
  1758. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1759. (struct i_t_dpdu_cqe *)sol);
  1760. break;
  1761. case UNSOL_DATA_NOTIFY:
  1762. beiscsi_log(phba, KERN_INFO,
  1763. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1764. "BM_%d : Received UNSOL_DATA_NOTIFY\n");
  1765. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1766. (struct i_t_dpdu_cqe *)sol);
  1767. break;
  1768. case CXN_INVALIDATE_INDEX_NOTIFY:
  1769. case CMD_INVALIDATED_NOTIFY:
  1770. case CXN_INVALIDATE_NOTIFY:
  1771. beiscsi_log(phba, KERN_ERR,
  1772. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1773. "BM_%d : Ignoring CQ Error notification for"
  1774. " cmd/cxn invalidate\n");
  1775. break;
  1776. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1777. case CMD_KILLED_INVALID_STATSN_RCVD:
  1778. case CMD_KILLED_INVALID_R2T_RCVD:
  1779. case CMD_CXN_KILLED_LUN_INVALID:
  1780. case CMD_CXN_KILLED_ICD_INVALID:
  1781. case CMD_CXN_KILLED_ITT_INVALID:
  1782. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1783. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1784. beiscsi_log(phba, KERN_ERR,
  1785. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1786. "BM_%d : CQ Error notification for cmd.. "
  1787. "code %d cid 0x%x\n", code, cid);
  1788. break;
  1789. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1790. beiscsi_log(phba, KERN_ERR,
  1791. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1792. "BM_%d : Digest error on def pdu ring,"
  1793. " dropping..\n");
  1794. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1795. (struct i_t_dpdu_cqe *) sol);
  1796. break;
  1797. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1798. case CXN_KILLED_BURST_LEN_MISMATCH:
  1799. case CXN_KILLED_AHS_RCVD:
  1800. case CXN_KILLED_HDR_DIGEST_ERR:
  1801. case CXN_KILLED_UNKNOWN_HDR:
  1802. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1803. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1804. case CXN_KILLED_TIMED_OUT:
  1805. case CXN_KILLED_FIN_RCVD:
  1806. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1807. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1808. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1809. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1810. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1811. beiscsi_log(phba, KERN_ERR,
  1812. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1813. "BM_%d : CQ Error %d, reset CID 0x%x...\n",
  1814. code, cid);
  1815. if (beiscsi_conn)
  1816. iscsi_conn_failure(beiscsi_conn->conn,
  1817. ISCSI_ERR_CONN_FAILED);
  1818. break;
  1819. case CXN_KILLED_RST_SENT:
  1820. case CXN_KILLED_RST_RCVD:
  1821. beiscsi_log(phba, KERN_ERR,
  1822. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1823. "BM_%d : CQ Error %d, reset"
  1824. "received/sent on CID 0x%x...\n",
  1825. code, cid);
  1826. if (beiscsi_conn)
  1827. iscsi_conn_failure(beiscsi_conn->conn,
  1828. ISCSI_ERR_CONN_FAILED);
  1829. break;
  1830. default:
  1831. beiscsi_log(phba, KERN_ERR,
  1832. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1833. "BM_%d : CQ Error Invalid code= %d "
  1834. "received on CID 0x%x...\n",
  1835. code, cid);
  1836. break;
  1837. }
  1838. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1839. queue_tail_inc(cq);
  1840. sol = queue_tail_node(cq);
  1841. num_processed++;
  1842. }
  1843. if (num_processed > 0) {
  1844. tot_nump += num_processed;
  1845. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1846. }
  1847. return tot_nump;
  1848. }
  1849. void beiscsi_process_all_cqs(struct work_struct *work)
  1850. {
  1851. unsigned long flags;
  1852. struct hwi_controller *phwi_ctrlr;
  1853. struct hwi_context_memory *phwi_context;
  1854. struct be_eq_obj *pbe_eq;
  1855. struct beiscsi_hba *phba =
  1856. container_of(work, struct beiscsi_hba, work_cqs);
  1857. phwi_ctrlr = phba->phwi_ctrlr;
  1858. phwi_context = phwi_ctrlr->phwi_ctxt;
  1859. if (phba->msix_enabled)
  1860. pbe_eq = &phwi_context->be_eq[phba->num_cpus];
  1861. else
  1862. pbe_eq = &phwi_context->be_eq[0];
  1863. if (phba->todo_mcc_cq) {
  1864. spin_lock_irqsave(&phba->isr_lock, flags);
  1865. phba->todo_mcc_cq = 0;
  1866. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1867. beiscsi_process_mcc_isr(phba);
  1868. }
  1869. if (phba->todo_cq) {
  1870. spin_lock_irqsave(&phba->isr_lock, flags);
  1871. phba->todo_cq = 0;
  1872. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1873. beiscsi_process_cq(pbe_eq);
  1874. }
  1875. }
  1876. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1877. {
  1878. static unsigned int ret;
  1879. struct beiscsi_hba *phba;
  1880. struct be_eq_obj *pbe_eq;
  1881. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1882. ret = beiscsi_process_cq(pbe_eq);
  1883. if (ret < budget) {
  1884. phba = pbe_eq->phba;
  1885. blk_iopoll_complete(iop);
  1886. beiscsi_log(phba, KERN_INFO,
  1887. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1888. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1889. pbe_eq->q.id);
  1890. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1891. }
  1892. return ret;
  1893. }
  1894. static void
  1895. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1896. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1897. {
  1898. struct iscsi_sge *psgl;
  1899. unsigned int sg_len, index;
  1900. unsigned int sge_len = 0;
  1901. unsigned long long addr;
  1902. struct scatterlist *l_sg;
  1903. unsigned int offset;
  1904. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1905. io_task->bhs_pa.u.a32.address_lo);
  1906. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1907. io_task->bhs_pa.u.a32.address_hi);
  1908. l_sg = sg;
  1909. for (index = 0; (index < num_sg) && (index < 2); index++,
  1910. sg = sg_next(sg)) {
  1911. if (index == 0) {
  1912. sg_len = sg_dma_len(sg);
  1913. addr = (u64) sg_dma_address(sg);
  1914. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1915. ((u32)(addr & 0xFFFFFFFF)));
  1916. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1917. ((u32)(addr >> 32)));
  1918. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1919. sg_len);
  1920. sge_len = sg_len;
  1921. } else {
  1922. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  1923. pwrb, sge_len);
  1924. sg_len = sg_dma_len(sg);
  1925. addr = (u64) sg_dma_address(sg);
  1926. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  1927. ((u32)(addr & 0xFFFFFFFF)));
  1928. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  1929. ((u32)(addr >> 32)));
  1930. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  1931. sg_len);
  1932. }
  1933. }
  1934. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1935. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  1936. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  1937. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1938. io_task->bhs_pa.u.a32.address_hi);
  1939. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1940. io_task->bhs_pa.u.a32.address_lo);
  1941. if (num_sg == 1) {
  1942. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1943. 1);
  1944. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1945. 0);
  1946. } else if (num_sg == 2) {
  1947. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1948. 0);
  1949. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1950. 1);
  1951. } else {
  1952. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1953. 0);
  1954. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1955. 0);
  1956. }
  1957. sg = l_sg;
  1958. psgl++;
  1959. psgl++;
  1960. offset = 0;
  1961. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  1962. sg_len = sg_dma_len(sg);
  1963. addr = (u64) sg_dma_address(sg);
  1964. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1965. (addr & 0xFFFFFFFF));
  1966. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1967. (addr >> 32));
  1968. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  1969. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  1970. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  1971. offset += sg_len;
  1972. }
  1973. psgl--;
  1974. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  1975. }
  1976. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  1977. {
  1978. struct iscsi_sge *psgl;
  1979. unsigned long long addr;
  1980. struct beiscsi_io_task *io_task = task->dd_data;
  1981. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  1982. struct beiscsi_hba *phba = beiscsi_conn->phba;
  1983. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  1984. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1985. io_task->bhs_pa.u.a32.address_lo);
  1986. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1987. io_task->bhs_pa.u.a32.address_hi);
  1988. if (task->data) {
  1989. if (task->data_count) {
  1990. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  1991. addr = (u64) pci_map_single(phba->pcidev,
  1992. task->data,
  1993. task->data_count, 1);
  1994. } else {
  1995. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  1996. addr = 0;
  1997. }
  1998. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1999. ((u32)(addr & 0xFFFFFFFF)));
  2000. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2001. ((u32)(addr >> 32)));
  2002. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2003. task->data_count);
  2004. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2005. } else {
  2006. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2007. addr = 0;
  2008. }
  2009. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2010. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2011. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2012. io_task->bhs_pa.u.a32.address_hi);
  2013. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2014. io_task->bhs_pa.u.a32.address_lo);
  2015. if (task->data) {
  2016. psgl++;
  2017. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2018. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2019. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2020. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2021. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2022. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2023. psgl++;
  2024. if (task->data) {
  2025. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2026. ((u32)(addr & 0xFFFFFFFF)));
  2027. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2028. ((u32)(addr >> 32)));
  2029. }
  2030. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2031. }
  2032. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2033. }
  2034. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2035. {
  2036. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2037. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2038. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2039. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2040. sizeof(struct sol_cqe));
  2041. num_async_pdu_buf_pages =
  2042. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2043. phba->params.defpdu_hdr_sz);
  2044. num_async_pdu_buf_sgl_pages =
  2045. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2046. sizeof(struct phys_addr));
  2047. num_async_pdu_data_pages =
  2048. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2049. phba->params.defpdu_data_sz);
  2050. num_async_pdu_data_sgl_pages =
  2051. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2052. sizeof(struct phys_addr));
  2053. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2054. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2055. BE_ISCSI_PDU_HEADER_SIZE;
  2056. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2057. sizeof(struct hwi_context_memory);
  2058. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2059. * (phba->params.wrbs_per_cxn)
  2060. * phba->params.cxns_per_ctrl;
  2061. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2062. (phba->params.wrbs_per_cxn);
  2063. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2064. phba->params.cxns_per_ctrl);
  2065. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2066. phba->params.icds_per_ctrl;
  2067. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2068. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2069. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2070. num_async_pdu_buf_pages * PAGE_SIZE;
  2071. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2072. num_async_pdu_data_pages * PAGE_SIZE;
  2073. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2074. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2075. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2076. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2077. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2078. phba->params.asyncpdus_per_ctrl *
  2079. sizeof(struct async_pdu_handle);
  2080. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2081. phba->params.asyncpdus_per_ctrl *
  2082. sizeof(struct async_pdu_handle);
  2083. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2084. sizeof(struct hwi_async_pdu_context) +
  2085. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2086. }
  2087. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2088. {
  2089. struct be_mem_descriptor *mem_descr;
  2090. dma_addr_t bus_add;
  2091. struct mem_array *mem_arr, *mem_arr_orig;
  2092. unsigned int i, j, alloc_size, curr_alloc_size;
  2093. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2094. if (!phba->phwi_ctrlr)
  2095. return -ENOMEM;
  2096. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2097. GFP_KERNEL);
  2098. if (!phba->init_mem) {
  2099. kfree(phba->phwi_ctrlr);
  2100. return -ENOMEM;
  2101. }
  2102. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2103. GFP_KERNEL);
  2104. if (!mem_arr_orig) {
  2105. kfree(phba->init_mem);
  2106. kfree(phba->phwi_ctrlr);
  2107. return -ENOMEM;
  2108. }
  2109. mem_descr = phba->init_mem;
  2110. for (i = 0; i < SE_MEM_MAX; i++) {
  2111. j = 0;
  2112. mem_arr = mem_arr_orig;
  2113. alloc_size = phba->mem_req[i];
  2114. memset(mem_arr, 0, sizeof(struct mem_array) *
  2115. BEISCSI_MAX_FRAGS_INIT);
  2116. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2117. do {
  2118. mem_arr->virtual_address = pci_alloc_consistent(
  2119. phba->pcidev,
  2120. curr_alloc_size,
  2121. &bus_add);
  2122. if (!mem_arr->virtual_address) {
  2123. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2124. goto free_mem;
  2125. if (curr_alloc_size -
  2126. rounddown_pow_of_two(curr_alloc_size))
  2127. curr_alloc_size = rounddown_pow_of_two
  2128. (curr_alloc_size);
  2129. else
  2130. curr_alloc_size = curr_alloc_size / 2;
  2131. } else {
  2132. mem_arr->bus_address.u.
  2133. a64.address = (__u64) bus_add;
  2134. mem_arr->size = curr_alloc_size;
  2135. alloc_size -= curr_alloc_size;
  2136. curr_alloc_size = min(be_max_phys_size *
  2137. 1024, alloc_size);
  2138. j++;
  2139. mem_arr++;
  2140. }
  2141. } while (alloc_size);
  2142. mem_descr->num_elements = j;
  2143. mem_descr->size_in_bytes = phba->mem_req[i];
  2144. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2145. GFP_KERNEL);
  2146. if (!mem_descr->mem_array)
  2147. goto free_mem;
  2148. memcpy(mem_descr->mem_array, mem_arr_orig,
  2149. sizeof(struct mem_array) * j);
  2150. mem_descr++;
  2151. }
  2152. kfree(mem_arr_orig);
  2153. return 0;
  2154. free_mem:
  2155. mem_descr->num_elements = j;
  2156. while ((i) || (j)) {
  2157. for (j = mem_descr->num_elements; j > 0; j--) {
  2158. pci_free_consistent(phba->pcidev,
  2159. mem_descr->mem_array[j - 1].size,
  2160. mem_descr->mem_array[j - 1].
  2161. virtual_address,
  2162. (unsigned long)mem_descr->
  2163. mem_array[j - 1].
  2164. bus_address.u.a64.address);
  2165. }
  2166. if (i) {
  2167. i--;
  2168. kfree(mem_descr->mem_array);
  2169. mem_descr--;
  2170. }
  2171. }
  2172. kfree(mem_arr_orig);
  2173. kfree(phba->init_mem);
  2174. kfree(phba->phwi_ctrlr);
  2175. return -ENOMEM;
  2176. }
  2177. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2178. {
  2179. beiscsi_find_mem_req(phba);
  2180. return beiscsi_alloc_mem(phba);
  2181. }
  2182. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2183. {
  2184. struct pdu_data_out *pdata_out;
  2185. struct pdu_nop_out *pnop_out;
  2186. struct be_mem_descriptor *mem_descr;
  2187. mem_descr = phba->init_mem;
  2188. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2189. pdata_out =
  2190. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2191. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2192. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2193. IIOC_SCSI_DATA);
  2194. pnop_out =
  2195. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2196. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2197. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2198. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2199. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2200. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2201. }
  2202. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2203. {
  2204. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2205. struct wrb_handle *pwrb_handle = NULL;
  2206. struct hwi_controller *phwi_ctrlr;
  2207. struct hwi_wrb_context *pwrb_context;
  2208. struct iscsi_wrb *pwrb = NULL;
  2209. unsigned int num_cxn_wrbh = 0;
  2210. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2211. mem_descr_wrbh = phba->init_mem;
  2212. mem_descr_wrbh += HWI_MEM_WRBH;
  2213. mem_descr_wrb = phba->init_mem;
  2214. mem_descr_wrb += HWI_MEM_WRB;
  2215. phwi_ctrlr = phba->phwi_ctrlr;
  2216. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2217. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2218. pwrb_context->pwrb_handle_base =
  2219. kzalloc(sizeof(struct wrb_handle *) *
  2220. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2221. if (!pwrb_context->pwrb_handle_base) {
  2222. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2223. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2224. goto init_wrb_hndl_failed;
  2225. }
  2226. pwrb_context->pwrb_handle_basestd =
  2227. kzalloc(sizeof(struct wrb_handle *) *
  2228. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2229. if (!pwrb_context->pwrb_handle_basestd) {
  2230. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2231. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2232. goto init_wrb_hndl_failed;
  2233. }
  2234. if (!num_cxn_wrbh) {
  2235. pwrb_handle =
  2236. mem_descr_wrbh->mem_array[idx].virtual_address;
  2237. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2238. ((sizeof(struct wrb_handle)) *
  2239. phba->params.wrbs_per_cxn));
  2240. idx++;
  2241. }
  2242. pwrb_context->alloc_index = 0;
  2243. pwrb_context->wrb_handles_available = 0;
  2244. pwrb_context->free_index = 0;
  2245. if (num_cxn_wrbh) {
  2246. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2247. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2248. pwrb_context->pwrb_handle_basestd[j] =
  2249. pwrb_handle;
  2250. pwrb_context->wrb_handles_available++;
  2251. pwrb_handle->wrb_index = j;
  2252. pwrb_handle++;
  2253. }
  2254. num_cxn_wrbh--;
  2255. }
  2256. }
  2257. idx = 0;
  2258. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2259. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2260. if (!num_cxn_wrb) {
  2261. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2262. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2263. ((sizeof(struct iscsi_wrb) *
  2264. phba->params.wrbs_per_cxn));
  2265. idx++;
  2266. }
  2267. if (num_cxn_wrb) {
  2268. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2269. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2270. pwrb_handle->pwrb = pwrb;
  2271. pwrb++;
  2272. }
  2273. num_cxn_wrb--;
  2274. }
  2275. }
  2276. return 0;
  2277. init_wrb_hndl_failed:
  2278. for (j = index; j > 0; j--) {
  2279. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2280. kfree(pwrb_context->pwrb_handle_base);
  2281. kfree(pwrb_context->pwrb_handle_basestd);
  2282. }
  2283. return -ENOMEM;
  2284. }
  2285. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2286. {
  2287. struct hwi_controller *phwi_ctrlr;
  2288. struct hba_parameters *p = &phba->params;
  2289. struct hwi_async_pdu_context *pasync_ctx;
  2290. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2291. unsigned int index, idx, num_per_mem, num_async_data;
  2292. struct be_mem_descriptor *mem_descr;
  2293. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2294. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2295. phwi_ctrlr = phba->phwi_ctrlr;
  2296. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2297. mem_descr->mem_array[0].virtual_address;
  2298. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2299. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2300. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2301. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2302. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2303. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2304. if (mem_descr->mem_array[0].virtual_address) {
  2305. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2306. "BM_%d : hwi_init_async_pdu_ctx"
  2307. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2308. mem_descr->mem_array[0].virtual_address);
  2309. } else
  2310. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2311. "BM_%d : No Virtual address\n");
  2312. pasync_ctx->async_header.va_base =
  2313. mem_descr->mem_array[0].virtual_address;
  2314. pasync_ctx->async_header.pa_base.u.a64.address =
  2315. mem_descr->mem_array[0].bus_address.u.a64.address;
  2316. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2317. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2318. if (mem_descr->mem_array[0].virtual_address) {
  2319. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2320. "BM_%d : hwi_init_async_pdu_ctx"
  2321. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2322. mem_descr->mem_array[0].virtual_address);
  2323. } else
  2324. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2325. "BM_%d : No Virtual address\n");
  2326. pasync_ctx->async_header.ring_base =
  2327. mem_descr->mem_array[0].virtual_address;
  2328. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2329. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2330. if (mem_descr->mem_array[0].virtual_address) {
  2331. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2332. "BM_%d : hwi_init_async_pdu_ctx"
  2333. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2334. mem_descr->mem_array[0].virtual_address);
  2335. } else
  2336. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2337. "BM_%d : No Virtual address\n");
  2338. pasync_ctx->async_header.handle_base =
  2339. mem_descr->mem_array[0].virtual_address;
  2340. pasync_ctx->async_header.writables = 0;
  2341. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2342. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2343. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2344. if (mem_descr->mem_array[0].virtual_address) {
  2345. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2346. "BM_%d : hwi_init_async_pdu_ctx"
  2347. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2348. mem_descr->mem_array[0].virtual_address);
  2349. } else
  2350. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2351. "BM_%d : No Virtual address\n");
  2352. pasync_ctx->async_data.ring_base =
  2353. mem_descr->mem_array[0].virtual_address;
  2354. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2355. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2356. if (!mem_descr->mem_array[0].virtual_address)
  2357. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2358. "BM_%d : No Virtual address\n");
  2359. pasync_ctx->async_data.handle_base =
  2360. mem_descr->mem_array[0].virtual_address;
  2361. pasync_ctx->async_data.writables = 0;
  2362. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2363. pasync_header_h =
  2364. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2365. pasync_data_h =
  2366. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2367. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2368. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2369. if (mem_descr->mem_array[0].virtual_address) {
  2370. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2371. "BM_%d : hwi_init_async_pdu_ctx"
  2372. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2373. mem_descr->mem_array[0].virtual_address);
  2374. } else
  2375. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2376. "BM_%d : No Virtual address\n");
  2377. idx = 0;
  2378. pasync_ctx->async_data.va_base =
  2379. mem_descr->mem_array[idx].virtual_address;
  2380. pasync_ctx->async_data.pa_base.u.a64.address =
  2381. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2382. num_async_data = ((mem_descr->mem_array[idx].size) /
  2383. phba->params.defpdu_data_sz);
  2384. num_per_mem = 0;
  2385. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2386. pasync_header_h->cri = -1;
  2387. pasync_header_h->index = (char)index;
  2388. INIT_LIST_HEAD(&pasync_header_h->link);
  2389. pasync_header_h->pbuffer =
  2390. (void *)((unsigned long)
  2391. (pasync_ctx->async_header.va_base) +
  2392. (p->defpdu_hdr_sz * index));
  2393. pasync_header_h->pa.u.a64.address =
  2394. pasync_ctx->async_header.pa_base.u.a64.address +
  2395. (p->defpdu_hdr_sz * index);
  2396. list_add_tail(&pasync_header_h->link,
  2397. &pasync_ctx->async_header.free_list);
  2398. pasync_header_h++;
  2399. pasync_ctx->async_header.free_entries++;
  2400. pasync_ctx->async_header.writables++;
  2401. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2402. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2403. header_busy_list);
  2404. pasync_data_h->cri = -1;
  2405. pasync_data_h->index = (char)index;
  2406. INIT_LIST_HEAD(&pasync_data_h->link);
  2407. if (!num_async_data) {
  2408. num_per_mem = 0;
  2409. idx++;
  2410. pasync_ctx->async_data.va_base =
  2411. mem_descr->mem_array[idx].virtual_address;
  2412. pasync_ctx->async_data.pa_base.u.a64.address =
  2413. mem_descr->mem_array[idx].
  2414. bus_address.u.a64.address;
  2415. num_async_data = ((mem_descr->mem_array[idx].size) /
  2416. phba->params.defpdu_data_sz);
  2417. }
  2418. pasync_data_h->pbuffer =
  2419. (void *)((unsigned long)
  2420. (pasync_ctx->async_data.va_base) +
  2421. (p->defpdu_data_sz * num_per_mem));
  2422. pasync_data_h->pa.u.a64.address =
  2423. pasync_ctx->async_data.pa_base.u.a64.address +
  2424. (p->defpdu_data_sz * num_per_mem);
  2425. num_per_mem++;
  2426. num_async_data--;
  2427. list_add_tail(&pasync_data_h->link,
  2428. &pasync_ctx->async_data.free_list);
  2429. pasync_data_h++;
  2430. pasync_ctx->async_data.free_entries++;
  2431. pasync_ctx->async_data.writables++;
  2432. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2433. }
  2434. pasync_ctx->async_header.host_write_ptr = 0;
  2435. pasync_ctx->async_header.ep_read_ptr = -1;
  2436. pasync_ctx->async_data.host_write_ptr = 0;
  2437. pasync_ctx->async_data.ep_read_ptr = -1;
  2438. }
  2439. static int
  2440. be_sgl_create_contiguous(void *virtual_address,
  2441. u64 physical_address, u32 length,
  2442. struct be_dma_mem *sgl)
  2443. {
  2444. WARN_ON(!virtual_address);
  2445. WARN_ON(!physical_address);
  2446. WARN_ON(!length > 0);
  2447. WARN_ON(!sgl);
  2448. sgl->va = virtual_address;
  2449. sgl->dma = (unsigned long)physical_address;
  2450. sgl->size = length;
  2451. return 0;
  2452. }
  2453. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2454. {
  2455. memset(sgl, 0, sizeof(*sgl));
  2456. }
  2457. static void
  2458. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2459. struct mem_array *pmem, struct be_dma_mem *sgl)
  2460. {
  2461. if (sgl->va)
  2462. be_sgl_destroy_contiguous(sgl);
  2463. be_sgl_create_contiguous(pmem->virtual_address,
  2464. pmem->bus_address.u.a64.address,
  2465. pmem->size, sgl);
  2466. }
  2467. static void
  2468. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2469. struct mem_array *pmem, struct be_dma_mem *sgl)
  2470. {
  2471. if (sgl->va)
  2472. be_sgl_destroy_contiguous(sgl);
  2473. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2474. pmem->bus_address.u.a64.address,
  2475. pmem->size, sgl);
  2476. }
  2477. static int be_fill_queue(struct be_queue_info *q,
  2478. u16 len, u16 entry_size, void *vaddress)
  2479. {
  2480. struct be_dma_mem *mem = &q->dma_mem;
  2481. memset(q, 0, sizeof(*q));
  2482. q->len = len;
  2483. q->entry_size = entry_size;
  2484. mem->size = len * entry_size;
  2485. mem->va = vaddress;
  2486. if (!mem->va)
  2487. return -ENOMEM;
  2488. memset(mem->va, 0, mem->size);
  2489. return 0;
  2490. }
  2491. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2492. struct hwi_context_memory *phwi_context)
  2493. {
  2494. unsigned int i, num_eq_pages;
  2495. int ret = 0, eq_for_mcc;
  2496. struct be_queue_info *eq;
  2497. struct be_dma_mem *mem;
  2498. void *eq_vaddress;
  2499. dma_addr_t paddr;
  2500. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2501. sizeof(struct be_eq_entry));
  2502. if (phba->msix_enabled)
  2503. eq_for_mcc = 1;
  2504. else
  2505. eq_for_mcc = 0;
  2506. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2507. eq = &phwi_context->be_eq[i].q;
  2508. mem = &eq->dma_mem;
  2509. phwi_context->be_eq[i].phba = phba;
  2510. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2511. num_eq_pages * PAGE_SIZE,
  2512. &paddr);
  2513. if (!eq_vaddress)
  2514. goto create_eq_error;
  2515. mem->va = eq_vaddress;
  2516. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2517. sizeof(struct be_eq_entry), eq_vaddress);
  2518. if (ret) {
  2519. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2520. "BM_%d : be_fill_queue Failed for EQ\n");
  2521. goto create_eq_error;
  2522. }
  2523. mem->dma = paddr;
  2524. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2525. phwi_context->cur_eqd);
  2526. if (ret) {
  2527. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2528. "BM_%d : beiscsi_cmd_eq_create"
  2529. "Failed for EQ\n");
  2530. goto create_eq_error;
  2531. }
  2532. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2533. "BM_%d : eqid = %d\n",
  2534. phwi_context->be_eq[i].q.id);
  2535. }
  2536. return 0;
  2537. create_eq_error:
  2538. for (i = 0; i < (phba->num_cpus + 1); i++) {
  2539. eq = &phwi_context->be_eq[i].q;
  2540. mem = &eq->dma_mem;
  2541. if (mem->va)
  2542. pci_free_consistent(phba->pcidev, num_eq_pages
  2543. * PAGE_SIZE,
  2544. mem->va, mem->dma);
  2545. }
  2546. return ret;
  2547. }
  2548. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2549. struct hwi_context_memory *phwi_context)
  2550. {
  2551. unsigned int i, num_cq_pages;
  2552. int ret = 0;
  2553. struct be_queue_info *cq, *eq;
  2554. struct be_dma_mem *mem;
  2555. struct be_eq_obj *pbe_eq;
  2556. void *cq_vaddress;
  2557. dma_addr_t paddr;
  2558. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2559. sizeof(struct sol_cqe));
  2560. for (i = 0; i < phba->num_cpus; i++) {
  2561. cq = &phwi_context->be_cq[i];
  2562. eq = &phwi_context->be_eq[i].q;
  2563. pbe_eq = &phwi_context->be_eq[i];
  2564. pbe_eq->cq = cq;
  2565. pbe_eq->phba = phba;
  2566. mem = &cq->dma_mem;
  2567. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2568. num_cq_pages * PAGE_SIZE,
  2569. &paddr);
  2570. if (!cq_vaddress)
  2571. goto create_cq_error;
  2572. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2573. sizeof(struct sol_cqe), cq_vaddress);
  2574. if (ret) {
  2575. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2576. "BM_%d : be_fill_queue Failed "
  2577. "for ISCSI CQ\n");
  2578. goto create_cq_error;
  2579. }
  2580. mem->dma = paddr;
  2581. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2582. false, 0);
  2583. if (ret) {
  2584. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2585. "BM_%d : beiscsi_cmd_eq_create"
  2586. "Failed for ISCSI CQ\n");
  2587. goto create_cq_error;
  2588. }
  2589. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2590. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2591. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2592. }
  2593. return 0;
  2594. create_cq_error:
  2595. for (i = 0; i < phba->num_cpus; i++) {
  2596. cq = &phwi_context->be_cq[i];
  2597. mem = &cq->dma_mem;
  2598. if (mem->va)
  2599. pci_free_consistent(phba->pcidev, num_cq_pages
  2600. * PAGE_SIZE,
  2601. mem->va, mem->dma);
  2602. }
  2603. return ret;
  2604. }
  2605. static int
  2606. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2607. struct hwi_context_memory *phwi_context,
  2608. struct hwi_controller *phwi_ctrlr,
  2609. unsigned int def_pdu_ring_sz)
  2610. {
  2611. unsigned int idx;
  2612. int ret;
  2613. struct be_queue_info *dq, *cq;
  2614. struct be_dma_mem *mem;
  2615. struct be_mem_descriptor *mem_descr;
  2616. void *dq_vaddress;
  2617. idx = 0;
  2618. dq = &phwi_context->be_def_hdrq;
  2619. cq = &phwi_context->be_cq[0];
  2620. mem = &dq->dma_mem;
  2621. mem_descr = phba->init_mem;
  2622. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2623. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2624. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2625. sizeof(struct phys_addr),
  2626. sizeof(struct phys_addr), dq_vaddress);
  2627. if (ret) {
  2628. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2629. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2630. return ret;
  2631. }
  2632. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2633. bus_address.u.a64.address;
  2634. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2635. def_pdu_ring_sz,
  2636. phba->params.defpdu_hdr_sz);
  2637. if (ret) {
  2638. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2639. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2640. return ret;
  2641. }
  2642. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2643. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2644. "BM_%d : iscsi def pdu id is %d\n",
  2645. phwi_context->be_def_hdrq.id);
  2646. hwi_post_async_buffers(phba, 1);
  2647. return 0;
  2648. }
  2649. static int
  2650. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2651. struct hwi_context_memory *phwi_context,
  2652. struct hwi_controller *phwi_ctrlr,
  2653. unsigned int def_pdu_ring_sz)
  2654. {
  2655. unsigned int idx;
  2656. int ret;
  2657. struct be_queue_info *dataq, *cq;
  2658. struct be_dma_mem *mem;
  2659. struct be_mem_descriptor *mem_descr;
  2660. void *dq_vaddress;
  2661. idx = 0;
  2662. dataq = &phwi_context->be_def_dataq;
  2663. cq = &phwi_context->be_cq[0];
  2664. mem = &dataq->dma_mem;
  2665. mem_descr = phba->init_mem;
  2666. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2667. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2668. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2669. sizeof(struct phys_addr),
  2670. sizeof(struct phys_addr), dq_vaddress);
  2671. if (ret) {
  2672. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2673. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2674. return ret;
  2675. }
  2676. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2677. bus_address.u.a64.address;
  2678. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2679. def_pdu_ring_sz,
  2680. phba->params.defpdu_data_sz);
  2681. if (ret) {
  2682. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2683. "BM_%d be_cmd_create_default_pdu_queue"
  2684. " Failed for DEF PDU DATA\n");
  2685. return ret;
  2686. }
  2687. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2688. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2689. "BM_%d : iscsi def data id is %d\n",
  2690. phwi_context->be_def_dataq.id);
  2691. hwi_post_async_buffers(phba, 0);
  2692. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2693. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2694. return 0;
  2695. }
  2696. static int
  2697. beiscsi_post_pages(struct beiscsi_hba *phba)
  2698. {
  2699. struct be_mem_descriptor *mem_descr;
  2700. struct mem_array *pm_arr;
  2701. unsigned int page_offset, i;
  2702. struct be_dma_mem sgl;
  2703. int status;
  2704. mem_descr = phba->init_mem;
  2705. mem_descr += HWI_MEM_SGE;
  2706. pm_arr = mem_descr->mem_array;
  2707. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2708. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2709. for (i = 0; i < mem_descr->num_elements; i++) {
  2710. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2711. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2712. page_offset,
  2713. (pm_arr->size / PAGE_SIZE));
  2714. page_offset += pm_arr->size / PAGE_SIZE;
  2715. if (status != 0) {
  2716. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2717. "BM_%d : post sgl failed.\n");
  2718. return status;
  2719. }
  2720. pm_arr++;
  2721. }
  2722. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2723. "BM_%d : POSTED PAGES\n");
  2724. return 0;
  2725. }
  2726. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2727. {
  2728. struct be_dma_mem *mem = &q->dma_mem;
  2729. if (mem->va) {
  2730. pci_free_consistent(phba->pcidev, mem->size,
  2731. mem->va, mem->dma);
  2732. mem->va = NULL;
  2733. }
  2734. }
  2735. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2736. u16 len, u16 entry_size)
  2737. {
  2738. struct be_dma_mem *mem = &q->dma_mem;
  2739. memset(q, 0, sizeof(*q));
  2740. q->len = len;
  2741. q->entry_size = entry_size;
  2742. mem->size = len * entry_size;
  2743. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2744. if (!mem->va)
  2745. return -ENOMEM;
  2746. memset(mem->va, 0, mem->size);
  2747. return 0;
  2748. }
  2749. static int
  2750. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2751. struct hwi_context_memory *phwi_context,
  2752. struct hwi_controller *phwi_ctrlr)
  2753. {
  2754. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2755. u64 pa_addr_lo;
  2756. unsigned int idx, num, i;
  2757. struct mem_array *pwrb_arr;
  2758. void *wrb_vaddr;
  2759. struct be_dma_mem sgl;
  2760. struct be_mem_descriptor *mem_descr;
  2761. int status;
  2762. idx = 0;
  2763. mem_descr = phba->init_mem;
  2764. mem_descr += HWI_MEM_WRB;
  2765. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2766. GFP_KERNEL);
  2767. if (!pwrb_arr) {
  2768. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2769. "BM_%d : Memory alloc failed in create wrb ring.\n");
  2770. return -ENOMEM;
  2771. }
  2772. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2773. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2774. num_wrb_rings = mem_descr->mem_array[idx].size /
  2775. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2776. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2777. if (num_wrb_rings) {
  2778. pwrb_arr[num].virtual_address = wrb_vaddr;
  2779. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2780. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2781. sizeof(struct iscsi_wrb);
  2782. wrb_vaddr += pwrb_arr[num].size;
  2783. pa_addr_lo += pwrb_arr[num].size;
  2784. num_wrb_rings--;
  2785. } else {
  2786. idx++;
  2787. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2788. pa_addr_lo = mem_descr->mem_array[idx].\
  2789. bus_address.u.a64.address;
  2790. num_wrb_rings = mem_descr->mem_array[idx].size /
  2791. (phba->params.wrbs_per_cxn *
  2792. sizeof(struct iscsi_wrb));
  2793. pwrb_arr[num].virtual_address = wrb_vaddr;
  2794. pwrb_arr[num].bus_address.u.a64.address\
  2795. = pa_addr_lo;
  2796. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2797. sizeof(struct iscsi_wrb);
  2798. wrb_vaddr += pwrb_arr[num].size;
  2799. pa_addr_lo += pwrb_arr[num].size;
  2800. num_wrb_rings--;
  2801. }
  2802. }
  2803. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2804. wrb_mem_index = 0;
  2805. offset = 0;
  2806. size = 0;
  2807. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2808. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2809. &phwi_context->be_wrbq[i]);
  2810. if (status != 0) {
  2811. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2812. "BM_%d : wrbq create failed.");
  2813. kfree(pwrb_arr);
  2814. return status;
  2815. }
  2816. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  2817. id;
  2818. }
  2819. kfree(pwrb_arr);
  2820. return 0;
  2821. }
  2822. static void free_wrb_handles(struct beiscsi_hba *phba)
  2823. {
  2824. unsigned int index;
  2825. struct hwi_controller *phwi_ctrlr;
  2826. struct hwi_wrb_context *pwrb_context;
  2827. phwi_ctrlr = phba->phwi_ctrlr;
  2828. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2829. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2830. kfree(pwrb_context->pwrb_handle_base);
  2831. kfree(pwrb_context->pwrb_handle_basestd);
  2832. }
  2833. }
  2834. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  2835. {
  2836. struct be_queue_info *q;
  2837. struct be_ctrl_info *ctrl = &phba->ctrl;
  2838. q = &phba->ctrl.mcc_obj.q;
  2839. if (q->created)
  2840. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  2841. be_queue_free(phba, q);
  2842. q = &phba->ctrl.mcc_obj.cq;
  2843. if (q->created)
  2844. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2845. be_queue_free(phba, q);
  2846. }
  2847. static void hwi_cleanup(struct beiscsi_hba *phba)
  2848. {
  2849. struct be_queue_info *q;
  2850. struct be_ctrl_info *ctrl = &phba->ctrl;
  2851. struct hwi_controller *phwi_ctrlr;
  2852. struct hwi_context_memory *phwi_context;
  2853. int i, eq_num;
  2854. phwi_ctrlr = phba->phwi_ctrlr;
  2855. phwi_context = phwi_ctrlr->phwi_ctxt;
  2856. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2857. q = &phwi_context->be_wrbq[i];
  2858. if (q->created)
  2859. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  2860. }
  2861. free_wrb_handles(phba);
  2862. q = &phwi_context->be_def_hdrq;
  2863. if (q->created)
  2864. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2865. q = &phwi_context->be_def_dataq;
  2866. if (q->created)
  2867. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2868. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  2869. for (i = 0; i < (phba->num_cpus); i++) {
  2870. q = &phwi_context->be_cq[i];
  2871. if (q->created)
  2872. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2873. }
  2874. if (phba->msix_enabled)
  2875. eq_num = 1;
  2876. else
  2877. eq_num = 0;
  2878. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  2879. q = &phwi_context->be_eq[i].q;
  2880. if (q->created)
  2881. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  2882. }
  2883. be_mcc_queues_destroy(phba);
  2884. }
  2885. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  2886. struct hwi_context_memory *phwi_context)
  2887. {
  2888. struct be_queue_info *q, *cq;
  2889. struct be_ctrl_info *ctrl = &phba->ctrl;
  2890. /* Alloc MCC compl queue */
  2891. cq = &phba->ctrl.mcc_obj.cq;
  2892. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  2893. sizeof(struct be_mcc_compl)))
  2894. goto err;
  2895. /* Ask BE to create MCC compl queue; */
  2896. if (phba->msix_enabled) {
  2897. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  2898. [phba->num_cpus].q, false, true, 0))
  2899. goto mcc_cq_free;
  2900. } else {
  2901. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  2902. false, true, 0))
  2903. goto mcc_cq_free;
  2904. }
  2905. /* Alloc MCC queue */
  2906. q = &phba->ctrl.mcc_obj.q;
  2907. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  2908. goto mcc_cq_destroy;
  2909. /* Ask BE to create MCC queue */
  2910. if (beiscsi_cmd_mccq_create(phba, q, cq))
  2911. goto mcc_q_free;
  2912. return 0;
  2913. mcc_q_free:
  2914. be_queue_free(phba, q);
  2915. mcc_cq_destroy:
  2916. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  2917. mcc_cq_free:
  2918. be_queue_free(phba, cq);
  2919. err:
  2920. return -ENOMEM;
  2921. }
  2922. static int find_num_cpus(void)
  2923. {
  2924. int num_cpus = 0;
  2925. num_cpus = num_online_cpus();
  2926. if (num_cpus >= MAX_CPUS)
  2927. num_cpus = MAX_CPUS - 1;
  2928. return num_cpus;
  2929. }
  2930. static int hwi_init_port(struct beiscsi_hba *phba)
  2931. {
  2932. struct hwi_controller *phwi_ctrlr;
  2933. struct hwi_context_memory *phwi_context;
  2934. unsigned int def_pdu_ring_sz;
  2935. struct be_ctrl_info *ctrl = &phba->ctrl;
  2936. int status;
  2937. def_pdu_ring_sz =
  2938. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  2939. phwi_ctrlr = phba->phwi_ctrlr;
  2940. phwi_context = phwi_ctrlr->phwi_ctxt;
  2941. phwi_context->max_eqd = 0;
  2942. phwi_context->min_eqd = 0;
  2943. phwi_context->cur_eqd = 64;
  2944. be_cmd_fw_initialize(&phba->ctrl);
  2945. status = beiscsi_create_eqs(phba, phwi_context);
  2946. if (status != 0) {
  2947. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2948. "BM_%d : EQ not created\n");
  2949. goto error;
  2950. }
  2951. status = be_mcc_queues_create(phba, phwi_context);
  2952. if (status != 0)
  2953. goto error;
  2954. status = mgmt_check_supported_fw(ctrl, phba);
  2955. if (status != 0) {
  2956. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2957. "BM_%d : Unsupported fw version\n");
  2958. goto error;
  2959. }
  2960. status = beiscsi_create_cqs(phba, phwi_context);
  2961. if (status != 0) {
  2962. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2963. "BM_%d : CQ not created\n");
  2964. goto error;
  2965. }
  2966. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  2967. def_pdu_ring_sz);
  2968. if (status != 0) {
  2969. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2970. "BM_%d : Default Header not created\n");
  2971. goto error;
  2972. }
  2973. status = beiscsi_create_def_data(phba, phwi_context,
  2974. phwi_ctrlr, def_pdu_ring_sz);
  2975. if (status != 0) {
  2976. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2977. "BM_%d : Default Data not created\n");
  2978. goto error;
  2979. }
  2980. status = beiscsi_post_pages(phba);
  2981. if (status != 0) {
  2982. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2983. "BM_%d : Post SGL Pages Failed\n");
  2984. goto error;
  2985. }
  2986. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  2987. if (status != 0) {
  2988. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2989. "BM_%d : WRB Rings not created\n");
  2990. goto error;
  2991. }
  2992. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2993. "BM_%d : hwi_init_port success\n");
  2994. return 0;
  2995. error:
  2996. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2997. "BM_%d : hwi_init_port failed");
  2998. hwi_cleanup(phba);
  2999. return status;
  3000. }
  3001. static int hwi_init_controller(struct beiscsi_hba *phba)
  3002. {
  3003. struct hwi_controller *phwi_ctrlr;
  3004. phwi_ctrlr = phba->phwi_ctrlr;
  3005. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3006. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3007. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3008. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3009. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3010. phwi_ctrlr->phwi_ctxt);
  3011. } else {
  3012. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3013. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3014. "than one element.Failing to load\n");
  3015. return -ENOMEM;
  3016. }
  3017. iscsi_init_global_templates(phba);
  3018. if (beiscsi_init_wrb_handle(phba))
  3019. return -ENOMEM;
  3020. hwi_init_async_pdu_ctx(phba);
  3021. if (hwi_init_port(phba) != 0) {
  3022. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3023. "BM_%d : hwi_init_controller failed\n");
  3024. return -ENOMEM;
  3025. }
  3026. return 0;
  3027. }
  3028. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3029. {
  3030. struct be_mem_descriptor *mem_descr;
  3031. int i, j;
  3032. mem_descr = phba->init_mem;
  3033. i = 0;
  3034. j = 0;
  3035. for (i = 0; i < SE_MEM_MAX; i++) {
  3036. for (j = mem_descr->num_elements; j > 0; j--) {
  3037. pci_free_consistent(phba->pcidev,
  3038. mem_descr->mem_array[j - 1].size,
  3039. mem_descr->mem_array[j - 1].virtual_address,
  3040. (unsigned long)mem_descr->mem_array[j - 1].
  3041. bus_address.u.a64.address);
  3042. }
  3043. kfree(mem_descr->mem_array);
  3044. mem_descr++;
  3045. }
  3046. kfree(phba->init_mem);
  3047. kfree(phba->phwi_ctrlr);
  3048. }
  3049. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3050. {
  3051. int ret = -ENOMEM;
  3052. ret = beiscsi_get_memory(phba);
  3053. if (ret < 0) {
  3054. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3055. "BM_%d : beiscsi_dev_probe -"
  3056. "Failed in beiscsi_alloc_memory\n");
  3057. return ret;
  3058. }
  3059. ret = hwi_init_controller(phba);
  3060. if (ret)
  3061. goto free_init;
  3062. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3063. "BM_%d : Return success from beiscsi_init_controller");
  3064. return 0;
  3065. free_init:
  3066. beiscsi_free_mem(phba);
  3067. return ret;
  3068. }
  3069. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3070. {
  3071. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3072. struct sgl_handle *psgl_handle;
  3073. struct iscsi_sge *pfrag;
  3074. unsigned int arr_index, i, idx;
  3075. phba->io_sgl_hndl_avbl = 0;
  3076. phba->eh_sgl_hndl_avbl = 0;
  3077. mem_descr_sglh = phba->init_mem;
  3078. mem_descr_sglh += HWI_MEM_SGLH;
  3079. if (1 == mem_descr_sglh->num_elements) {
  3080. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3081. phba->params.ios_per_ctrl,
  3082. GFP_KERNEL);
  3083. if (!phba->io_sgl_hndl_base) {
  3084. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3085. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3086. return -ENOMEM;
  3087. }
  3088. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3089. (phba->params.icds_per_ctrl -
  3090. phba->params.ios_per_ctrl),
  3091. GFP_KERNEL);
  3092. if (!phba->eh_sgl_hndl_base) {
  3093. kfree(phba->io_sgl_hndl_base);
  3094. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3095. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3096. return -ENOMEM;
  3097. }
  3098. } else {
  3099. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3100. "BM_%d : HWI_MEM_SGLH is more than one element."
  3101. "Failing to load\n");
  3102. return -ENOMEM;
  3103. }
  3104. arr_index = 0;
  3105. idx = 0;
  3106. while (idx < mem_descr_sglh->num_elements) {
  3107. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3108. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3109. sizeof(struct sgl_handle)); i++) {
  3110. if (arr_index < phba->params.ios_per_ctrl) {
  3111. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3112. phba->io_sgl_hndl_avbl++;
  3113. arr_index++;
  3114. } else {
  3115. phba->eh_sgl_hndl_base[arr_index -
  3116. phba->params.ios_per_ctrl] =
  3117. psgl_handle;
  3118. arr_index++;
  3119. phba->eh_sgl_hndl_avbl++;
  3120. }
  3121. psgl_handle++;
  3122. }
  3123. idx++;
  3124. }
  3125. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3126. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3127. "phba->eh_sgl_hndl_avbl=%d\n",
  3128. phba->io_sgl_hndl_avbl,
  3129. phba->eh_sgl_hndl_avbl);
  3130. mem_descr_sg = phba->init_mem;
  3131. mem_descr_sg += HWI_MEM_SGE;
  3132. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3133. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3134. mem_descr_sg->num_elements);
  3135. arr_index = 0;
  3136. idx = 0;
  3137. while (idx < mem_descr_sg->num_elements) {
  3138. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3139. for (i = 0;
  3140. i < (mem_descr_sg->mem_array[idx].size) /
  3141. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3142. i++) {
  3143. if (arr_index < phba->params.ios_per_ctrl)
  3144. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3145. else
  3146. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3147. phba->params.ios_per_ctrl];
  3148. psgl_handle->pfrag = pfrag;
  3149. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3150. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3151. pfrag += phba->params.num_sge_per_io;
  3152. psgl_handle->sgl_index =
  3153. phba->fw_config.iscsi_icd_start + arr_index++;
  3154. }
  3155. idx++;
  3156. }
  3157. phba->io_sgl_free_index = 0;
  3158. phba->io_sgl_alloc_index = 0;
  3159. phba->eh_sgl_free_index = 0;
  3160. phba->eh_sgl_alloc_index = 0;
  3161. return 0;
  3162. }
  3163. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3164. {
  3165. int i, new_cid;
  3166. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3167. GFP_KERNEL);
  3168. if (!phba->cid_array) {
  3169. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3170. "BM_%d : Failed to allocate memory in "
  3171. "hba_setup_cid_tbls\n");
  3172. return -ENOMEM;
  3173. }
  3174. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3175. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3176. if (!phba->ep_array) {
  3177. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3178. "BM_%d : Failed to allocate memory in "
  3179. "hba_setup_cid_tbls\n");
  3180. kfree(phba->cid_array);
  3181. return -ENOMEM;
  3182. }
  3183. new_cid = phba->fw_config.iscsi_cid_start;
  3184. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3185. phba->cid_array[i] = new_cid;
  3186. new_cid += 2;
  3187. }
  3188. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3189. return 0;
  3190. }
  3191. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3192. {
  3193. struct be_ctrl_info *ctrl = &phba->ctrl;
  3194. struct hwi_controller *phwi_ctrlr;
  3195. struct hwi_context_memory *phwi_context;
  3196. struct be_queue_info *eq;
  3197. u8 __iomem *addr;
  3198. u32 reg, i;
  3199. u32 enabled;
  3200. phwi_ctrlr = phba->phwi_ctrlr;
  3201. phwi_context = phwi_ctrlr->phwi_ctxt;
  3202. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3203. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3204. reg = ioread32(addr);
  3205. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3206. if (!enabled) {
  3207. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3208. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3209. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3210. iowrite32(reg, addr);
  3211. }
  3212. if (!phba->msix_enabled) {
  3213. eq = &phwi_context->be_eq[0].q;
  3214. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3215. "BM_%d : eq->id=%d\n", eq->id);
  3216. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3217. } else {
  3218. for (i = 0; i <= phba->num_cpus; i++) {
  3219. eq = &phwi_context->be_eq[i].q;
  3220. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3221. "BM_%d : eq->id=%d\n", eq->id);
  3222. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3223. }
  3224. }
  3225. }
  3226. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3227. {
  3228. struct be_ctrl_info *ctrl = &phba->ctrl;
  3229. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3230. u32 reg = ioread32(addr);
  3231. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3232. if (enabled) {
  3233. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3234. iowrite32(reg, addr);
  3235. } else
  3236. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3237. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3238. }
  3239. /**
  3240. * beiscsi_get_boot_info()- Get the boot session info
  3241. * @phba: The device priv structure instance
  3242. *
  3243. * Get the boot target info and store in driver priv structure
  3244. *
  3245. * return values
  3246. * Success: 0
  3247. * Failure: Non-Zero Value
  3248. **/
  3249. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3250. {
  3251. struct be_cmd_get_session_resp *session_resp;
  3252. struct be_mcc_wrb *wrb;
  3253. struct be_dma_mem nonemb_cmd;
  3254. unsigned int tag, wrb_num;
  3255. unsigned short status, extd_status;
  3256. unsigned int s_handle;
  3257. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3258. int ret = -ENOMEM;
  3259. /* Get the session handle of the boot target */
  3260. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3261. if (ret) {
  3262. beiscsi_log(phba, KERN_ERR,
  3263. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3264. "BM_%d : No boot session\n");
  3265. return ret;
  3266. }
  3267. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3268. sizeof(*session_resp),
  3269. &nonemb_cmd.dma);
  3270. if (nonemb_cmd.va == NULL) {
  3271. beiscsi_log(phba, KERN_ERR,
  3272. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3273. "BM_%d : Failed to allocate memory for"
  3274. "beiscsi_get_session_info\n");
  3275. return -ENOMEM;
  3276. }
  3277. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3278. tag = mgmt_get_session_info(phba, s_handle,
  3279. &nonemb_cmd);
  3280. if (!tag) {
  3281. beiscsi_log(phba, KERN_ERR,
  3282. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3283. "BM_%d : beiscsi_get_session_info"
  3284. " Failed\n");
  3285. goto boot_freemem;
  3286. } else
  3287. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3288. phba->ctrl.mcc_numtag[tag]);
  3289. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3290. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3291. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3292. if (status || extd_status) {
  3293. beiscsi_log(phba, KERN_ERR,
  3294. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3295. "BM_%d : beiscsi_get_session_info Failed"
  3296. " status = %d extd_status = %d\n",
  3297. status, extd_status);
  3298. free_mcc_tag(&phba->ctrl, tag);
  3299. goto boot_freemem;
  3300. }
  3301. wrb = queue_get_wrb(mccq, wrb_num);
  3302. free_mcc_tag(&phba->ctrl, tag);
  3303. session_resp = nonemb_cmd.va ;
  3304. memcpy(&phba->boot_sess, &session_resp->session_info,
  3305. sizeof(struct mgmt_session_info));
  3306. ret = 0;
  3307. boot_freemem:
  3308. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3309. nonemb_cmd.va, nonemb_cmd.dma);
  3310. return ret;
  3311. }
  3312. static void beiscsi_boot_release(void *data)
  3313. {
  3314. struct beiscsi_hba *phba = data;
  3315. scsi_host_put(phba->shost);
  3316. }
  3317. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3318. {
  3319. struct iscsi_boot_kobj *boot_kobj;
  3320. /* get boot info using mgmt cmd */
  3321. if (beiscsi_get_boot_info(phba))
  3322. /* Try to see if we can carry on without this */
  3323. return 0;
  3324. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3325. if (!phba->boot_kset)
  3326. return -ENOMEM;
  3327. /* get a ref because the show function will ref the phba */
  3328. if (!scsi_host_get(phba->shost))
  3329. goto free_kset;
  3330. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3331. beiscsi_show_boot_tgt_info,
  3332. beiscsi_tgt_get_attr_visibility,
  3333. beiscsi_boot_release);
  3334. if (!boot_kobj)
  3335. goto put_shost;
  3336. if (!scsi_host_get(phba->shost))
  3337. goto free_kset;
  3338. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3339. beiscsi_show_boot_ini_info,
  3340. beiscsi_ini_get_attr_visibility,
  3341. beiscsi_boot_release);
  3342. if (!boot_kobj)
  3343. goto put_shost;
  3344. if (!scsi_host_get(phba->shost))
  3345. goto free_kset;
  3346. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3347. beiscsi_show_boot_eth_info,
  3348. beiscsi_eth_get_attr_visibility,
  3349. beiscsi_boot_release);
  3350. if (!boot_kobj)
  3351. goto put_shost;
  3352. return 0;
  3353. put_shost:
  3354. scsi_host_put(phba->shost);
  3355. free_kset:
  3356. iscsi_boot_destroy_kset(phba->boot_kset);
  3357. return -ENOMEM;
  3358. }
  3359. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3360. {
  3361. int ret;
  3362. ret = beiscsi_init_controller(phba);
  3363. if (ret < 0) {
  3364. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3365. "BM_%d : beiscsi_dev_probe - Failed in"
  3366. "beiscsi_init_controller\n");
  3367. return ret;
  3368. }
  3369. ret = beiscsi_init_sgl_handle(phba);
  3370. if (ret < 0) {
  3371. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3372. "BM_%d : beiscsi_dev_probe - Failed in"
  3373. "beiscsi_init_sgl_handle\n");
  3374. goto do_cleanup_ctrlr;
  3375. }
  3376. if (hba_setup_cid_tbls(phba)) {
  3377. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3378. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3379. kfree(phba->io_sgl_hndl_base);
  3380. kfree(phba->eh_sgl_hndl_base);
  3381. goto do_cleanup_ctrlr;
  3382. }
  3383. return ret;
  3384. do_cleanup_ctrlr:
  3385. hwi_cleanup(phba);
  3386. return ret;
  3387. }
  3388. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3389. {
  3390. struct hwi_controller *phwi_ctrlr;
  3391. struct hwi_context_memory *phwi_context;
  3392. struct be_queue_info *eq;
  3393. struct be_eq_entry *eqe = NULL;
  3394. int i, eq_msix;
  3395. unsigned int num_processed;
  3396. phwi_ctrlr = phba->phwi_ctrlr;
  3397. phwi_context = phwi_ctrlr->phwi_ctxt;
  3398. if (phba->msix_enabled)
  3399. eq_msix = 1;
  3400. else
  3401. eq_msix = 0;
  3402. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3403. eq = &phwi_context->be_eq[i].q;
  3404. eqe = queue_tail_node(eq);
  3405. num_processed = 0;
  3406. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3407. & EQE_VALID_MASK) {
  3408. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3409. queue_tail_inc(eq);
  3410. eqe = queue_tail_node(eq);
  3411. num_processed++;
  3412. }
  3413. if (num_processed)
  3414. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3415. }
  3416. }
  3417. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3418. {
  3419. int mgmt_status;
  3420. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3421. if (mgmt_status)
  3422. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3423. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3424. hwi_purge_eq(phba);
  3425. hwi_cleanup(phba);
  3426. kfree(phba->io_sgl_hndl_base);
  3427. kfree(phba->eh_sgl_hndl_base);
  3428. kfree(phba->cid_array);
  3429. kfree(phba->ep_array);
  3430. }
  3431. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3432. {
  3433. struct beiscsi_io_task *io_task = task->dd_data;
  3434. struct iscsi_conn *conn = task->conn;
  3435. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3436. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3437. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3438. struct hwi_wrb_context *pwrb_context;
  3439. struct hwi_controller *phwi_ctrlr;
  3440. phwi_ctrlr = phba->phwi_ctrlr;
  3441. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3442. - phba->fw_config.iscsi_cid_start];
  3443. if (io_task->cmd_bhs) {
  3444. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3445. io_task->bhs_pa.u.a64.address);
  3446. io_task->cmd_bhs = NULL;
  3447. }
  3448. if (task->sc) {
  3449. if (io_task->pwrb_handle) {
  3450. free_wrb_handle(phba, pwrb_context,
  3451. io_task->pwrb_handle);
  3452. io_task->pwrb_handle = NULL;
  3453. }
  3454. if (io_task->psgl_handle) {
  3455. spin_lock(&phba->io_sgl_lock);
  3456. free_io_sgl_handle(phba, io_task->psgl_handle);
  3457. spin_unlock(&phba->io_sgl_lock);
  3458. io_task->psgl_handle = NULL;
  3459. }
  3460. } else {
  3461. if (!beiscsi_conn->login_in_progress) {
  3462. if (io_task->pwrb_handle) {
  3463. free_wrb_handle(phba, pwrb_context,
  3464. io_task->pwrb_handle);
  3465. io_task->pwrb_handle = NULL;
  3466. }
  3467. if (io_task->psgl_handle) {
  3468. spin_lock(&phba->mgmt_sgl_lock);
  3469. free_mgmt_sgl_handle(phba,
  3470. io_task->psgl_handle);
  3471. spin_unlock(&phba->mgmt_sgl_lock);
  3472. io_task->psgl_handle = NULL;
  3473. }
  3474. }
  3475. }
  3476. }
  3477. void
  3478. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3479. struct beiscsi_offload_params *params)
  3480. {
  3481. struct wrb_handle *pwrb_handle;
  3482. struct iscsi_target_context_update_wrb *pwrb = NULL;
  3483. struct be_mem_descriptor *mem_descr;
  3484. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3485. struct iscsi_task *task = beiscsi_conn->task;
  3486. struct iscsi_session *session = task->conn->session;
  3487. u32 doorbell = 0;
  3488. /*
  3489. * We can always use 0 here because it is reserved by libiscsi for
  3490. * login/startup related tasks.
  3491. */
  3492. beiscsi_conn->login_in_progress = 0;
  3493. spin_lock_bh(&session->lock);
  3494. beiscsi_cleanup_task(task);
  3495. spin_unlock_bh(&session->lock);
  3496. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3497. phba->fw_config.iscsi_cid_start));
  3498. pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
  3499. memset(pwrb, 0, sizeof(*pwrb));
  3500. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3501. max_burst_length, pwrb, params->dw[offsetof
  3502. (struct amap_beiscsi_offload_params,
  3503. max_burst_length) / 32]);
  3504. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3505. max_send_data_segment_length, pwrb,
  3506. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3507. max_send_data_segment_length) / 32]);
  3508. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3509. first_burst_length,
  3510. pwrb,
  3511. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3512. first_burst_length) / 32]);
  3513. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
  3514. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3515. erl) / 32] & OFFLD_PARAMS_ERL));
  3516. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
  3517. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3518. dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
  3519. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
  3520. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3521. hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
  3522. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
  3523. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3524. ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
  3525. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
  3526. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3527. imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
  3528. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
  3529. pwrb,
  3530. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3531. exp_statsn) / 32] + 1));
  3532. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
  3533. 0x7);
  3534. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
  3535. pwrb, pwrb_handle->wrb_index);
  3536. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
  3537. pwrb, pwrb_handle->nxt_wrb_index);
  3538. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3539. session_state, pwrb, 0);
  3540. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
  3541. pwrb, 1);
  3542. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
  3543. pwrb, 0);
  3544. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
  3545. 0);
  3546. mem_descr = phba->init_mem;
  3547. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  3548. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3549. pad_buffer_addr_hi, pwrb,
  3550. mem_descr->mem_array[0].bus_address.u.a32.address_hi);
  3551. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3552. pad_buffer_addr_lo, pwrb,
  3553. mem_descr->mem_array[0].bus_address.u.a32.address_lo);
  3554. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
  3555. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3556. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3557. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3558. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3559. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3560. }
  3561. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3562. int *index, int *age)
  3563. {
  3564. *index = (int)itt;
  3565. if (age)
  3566. *age = conn->session->age;
  3567. }
  3568. /**
  3569. * beiscsi_alloc_pdu - allocates pdu and related resources
  3570. * @task: libiscsi task
  3571. * @opcode: opcode of pdu for task
  3572. *
  3573. * This is called with the session lock held. It will allocate
  3574. * the wrb and sgl if needed for the command. And it will prep
  3575. * the pdu's itt. beiscsi_parse_pdu will later translate
  3576. * the pdu itt to the libiscsi task itt.
  3577. */
  3578. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3579. {
  3580. struct beiscsi_io_task *io_task = task->dd_data;
  3581. struct iscsi_conn *conn = task->conn;
  3582. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3583. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3584. struct hwi_wrb_context *pwrb_context;
  3585. struct hwi_controller *phwi_ctrlr;
  3586. itt_t itt;
  3587. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3588. dma_addr_t paddr;
  3589. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3590. GFP_ATOMIC, &paddr);
  3591. if (!io_task->cmd_bhs)
  3592. return -ENOMEM;
  3593. io_task->bhs_pa.u.a64.address = paddr;
  3594. io_task->libiscsi_itt = (itt_t)task->itt;
  3595. io_task->conn = beiscsi_conn;
  3596. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3597. task->hdr_max = sizeof(struct be_cmd_bhs);
  3598. io_task->psgl_handle = NULL;
  3599. io_task->pwrb_handle = NULL;
  3600. if (task->sc) {
  3601. spin_lock(&phba->io_sgl_lock);
  3602. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3603. spin_unlock(&phba->io_sgl_lock);
  3604. if (!io_task->psgl_handle)
  3605. goto free_hndls;
  3606. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3607. beiscsi_conn->beiscsi_conn_cid -
  3608. phba->fw_config.iscsi_cid_start);
  3609. if (!io_task->pwrb_handle)
  3610. goto free_io_hndls;
  3611. } else {
  3612. io_task->scsi_cmnd = NULL;
  3613. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3614. if (!beiscsi_conn->login_in_progress) {
  3615. spin_lock(&phba->mgmt_sgl_lock);
  3616. io_task->psgl_handle = (struct sgl_handle *)
  3617. alloc_mgmt_sgl_handle(phba);
  3618. spin_unlock(&phba->mgmt_sgl_lock);
  3619. if (!io_task->psgl_handle)
  3620. goto free_hndls;
  3621. beiscsi_conn->login_in_progress = 1;
  3622. beiscsi_conn->plogin_sgl_handle =
  3623. io_task->psgl_handle;
  3624. io_task->pwrb_handle =
  3625. alloc_wrb_handle(phba,
  3626. beiscsi_conn->beiscsi_conn_cid -
  3627. phba->fw_config.iscsi_cid_start);
  3628. if (!io_task->pwrb_handle)
  3629. goto free_io_hndls;
  3630. beiscsi_conn->plogin_wrb_handle =
  3631. io_task->pwrb_handle;
  3632. } else {
  3633. io_task->psgl_handle =
  3634. beiscsi_conn->plogin_sgl_handle;
  3635. io_task->pwrb_handle =
  3636. beiscsi_conn->plogin_wrb_handle;
  3637. }
  3638. beiscsi_conn->task = task;
  3639. } else {
  3640. spin_lock(&phba->mgmt_sgl_lock);
  3641. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3642. spin_unlock(&phba->mgmt_sgl_lock);
  3643. if (!io_task->psgl_handle)
  3644. goto free_hndls;
  3645. io_task->pwrb_handle =
  3646. alloc_wrb_handle(phba,
  3647. beiscsi_conn->beiscsi_conn_cid -
  3648. phba->fw_config.iscsi_cid_start);
  3649. if (!io_task->pwrb_handle)
  3650. goto free_mgmt_hndls;
  3651. }
  3652. }
  3653. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3654. wrb_index << 16) | (unsigned int)
  3655. (io_task->psgl_handle->sgl_index));
  3656. io_task->pwrb_handle->pio_handle = task;
  3657. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3658. return 0;
  3659. free_io_hndls:
  3660. spin_lock(&phba->io_sgl_lock);
  3661. free_io_sgl_handle(phba, io_task->psgl_handle);
  3662. spin_unlock(&phba->io_sgl_lock);
  3663. goto free_hndls;
  3664. free_mgmt_hndls:
  3665. spin_lock(&phba->mgmt_sgl_lock);
  3666. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3667. spin_unlock(&phba->mgmt_sgl_lock);
  3668. free_hndls:
  3669. phwi_ctrlr = phba->phwi_ctrlr;
  3670. pwrb_context = &phwi_ctrlr->wrb_context[
  3671. beiscsi_conn->beiscsi_conn_cid -
  3672. phba->fw_config.iscsi_cid_start];
  3673. if (io_task->pwrb_handle)
  3674. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3675. io_task->pwrb_handle = NULL;
  3676. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3677. io_task->bhs_pa.u.a64.address);
  3678. io_task->cmd_bhs = NULL;
  3679. beiscsi_log(phba, KERN_ERR,
  3680. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3681. "BM_%d : Alloc of SGL_ICD Failed\n");
  3682. return -ENOMEM;
  3683. }
  3684. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3685. unsigned int num_sg, unsigned int xferlen,
  3686. unsigned int writedir)
  3687. {
  3688. struct beiscsi_io_task *io_task = task->dd_data;
  3689. struct iscsi_conn *conn = task->conn;
  3690. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3691. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3692. struct iscsi_wrb *pwrb = NULL;
  3693. unsigned int doorbell = 0;
  3694. pwrb = io_task->pwrb_handle->pwrb;
  3695. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3696. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3697. if (writedir) {
  3698. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3699. INI_WR_CMD);
  3700. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3701. } else {
  3702. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3703. INI_RD_CMD);
  3704. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3705. }
  3706. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3707. cpu_to_be16(*(unsigned short *)
  3708. &io_task->cmd_bhs->iscsi_hdr.lun));
  3709. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3710. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3711. io_task->pwrb_handle->wrb_index);
  3712. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3713. be32_to_cpu(task->cmdsn));
  3714. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3715. io_task->psgl_handle->sgl_index);
  3716. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3717. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3718. io_task->pwrb_handle->nxt_wrb_index);
  3719. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3720. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3721. doorbell |= (io_task->pwrb_handle->wrb_index &
  3722. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3723. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3724. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3725. return 0;
  3726. }
  3727. static int beiscsi_mtask(struct iscsi_task *task)
  3728. {
  3729. struct beiscsi_io_task *io_task = task->dd_data;
  3730. struct iscsi_conn *conn = task->conn;
  3731. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3732. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3733. struct iscsi_wrb *pwrb = NULL;
  3734. unsigned int doorbell = 0;
  3735. unsigned int cid;
  3736. cid = beiscsi_conn->beiscsi_conn_cid;
  3737. pwrb = io_task->pwrb_handle->pwrb;
  3738. memset(pwrb, 0, sizeof(*pwrb));
  3739. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3740. be32_to_cpu(task->cmdsn));
  3741. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3742. io_task->pwrb_handle->wrb_index);
  3743. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3744. io_task->psgl_handle->sgl_index);
  3745. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  3746. case ISCSI_OP_LOGIN:
  3747. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3748. TGT_DM_CMD);
  3749. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3750. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  3751. hwi_write_buffer(pwrb, task);
  3752. break;
  3753. case ISCSI_OP_NOOP_OUT:
  3754. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  3755. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3756. TGT_DM_CMD);
  3757. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
  3758. pwrb, 0);
  3759. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
  3760. } else {
  3761. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3762. INI_RD_CMD);
  3763. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3764. }
  3765. hwi_write_buffer(pwrb, task);
  3766. break;
  3767. case ISCSI_OP_TEXT:
  3768. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3769. TGT_DM_CMD);
  3770. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3771. hwi_write_buffer(pwrb, task);
  3772. break;
  3773. case ISCSI_OP_SCSI_TMFUNC:
  3774. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3775. INI_TMF_CMD);
  3776. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3777. hwi_write_buffer(pwrb, task);
  3778. break;
  3779. case ISCSI_OP_LOGOUT:
  3780. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3781. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3782. HWH_TYPE_LOGOUT);
  3783. hwi_write_buffer(pwrb, task);
  3784. break;
  3785. default:
  3786. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3787. "BM_%d : opcode =%d Not supported\n",
  3788. task->hdr->opcode & ISCSI_OPCODE_MASK);
  3789. return -EINVAL;
  3790. }
  3791. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  3792. task->data_count);
  3793. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3794. io_task->pwrb_handle->nxt_wrb_index);
  3795. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3796. doorbell |= cid & DB_WRB_POST_CID_MASK;
  3797. doorbell |= (io_task->pwrb_handle->wrb_index &
  3798. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3799. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3800. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3801. return 0;
  3802. }
  3803. static int beiscsi_task_xmit(struct iscsi_task *task)
  3804. {
  3805. struct beiscsi_io_task *io_task = task->dd_data;
  3806. struct scsi_cmnd *sc = task->sc;
  3807. struct scatterlist *sg;
  3808. int num_sg;
  3809. unsigned int writedir = 0, xferlen = 0;
  3810. if (!sc)
  3811. return beiscsi_mtask(task);
  3812. io_task->scsi_cmnd = sc;
  3813. num_sg = scsi_dma_map(sc);
  3814. if (num_sg < 0) {
  3815. struct iscsi_conn *conn = task->conn;
  3816. struct beiscsi_hba *phba = NULL;
  3817. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  3818. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  3819. "BM_%d : scsi_dma_map Failed\n");
  3820. return num_sg;
  3821. }
  3822. xferlen = scsi_bufflen(sc);
  3823. sg = scsi_sglist(sc);
  3824. if (sc->sc_data_direction == DMA_TO_DEVICE)
  3825. writedir = 1;
  3826. else
  3827. writedir = 0;
  3828. return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
  3829. }
  3830. /**
  3831. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  3832. * @job: job to handle
  3833. */
  3834. static int beiscsi_bsg_request(struct bsg_job *job)
  3835. {
  3836. struct Scsi_Host *shost;
  3837. struct beiscsi_hba *phba;
  3838. struct iscsi_bsg_request *bsg_req = job->request;
  3839. int rc = -EINVAL;
  3840. unsigned int tag;
  3841. struct be_dma_mem nonemb_cmd;
  3842. struct be_cmd_resp_hdr *resp;
  3843. struct iscsi_bsg_reply *bsg_reply = job->reply;
  3844. unsigned short status, extd_status;
  3845. shost = iscsi_job_to_shost(job);
  3846. phba = iscsi_host_priv(shost);
  3847. switch (bsg_req->msgcode) {
  3848. case ISCSI_BSG_HST_VENDOR:
  3849. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3850. job->request_payload.payload_len,
  3851. &nonemb_cmd.dma);
  3852. if (nonemb_cmd.va == NULL) {
  3853. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3854. "BM_%d : Failed to allocate memory for "
  3855. "beiscsi_bsg_request\n");
  3856. return -EIO;
  3857. }
  3858. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  3859. &nonemb_cmd);
  3860. if (!tag) {
  3861. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3862. "BM_%d : be_cmd_get_mac_addr Failed\n");
  3863. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3864. nonemb_cmd.va, nonemb_cmd.dma);
  3865. return -EAGAIN;
  3866. } else
  3867. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3868. phba->ctrl.mcc_numtag[tag]);
  3869. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3870. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3871. free_mcc_tag(&phba->ctrl, tag);
  3872. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  3873. sg_copy_from_buffer(job->reply_payload.sg_list,
  3874. job->reply_payload.sg_cnt,
  3875. nonemb_cmd.va, (resp->response_length
  3876. + sizeof(*resp)));
  3877. bsg_reply->reply_payload_rcv_len = resp->response_length;
  3878. bsg_reply->result = status;
  3879. bsg_job_done(job, bsg_reply->result,
  3880. bsg_reply->reply_payload_rcv_len);
  3881. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3882. nonemb_cmd.va, nonemb_cmd.dma);
  3883. if (status || extd_status) {
  3884. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3885. "BM_%d : be_cmd_get_mac_addr Failed"
  3886. " status = %d extd_status = %d\n",
  3887. status, extd_status);
  3888. return -EIO;
  3889. }
  3890. break;
  3891. default:
  3892. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3893. "BM_%d : Unsupported bsg command: 0x%x\n",
  3894. bsg_req->msgcode);
  3895. break;
  3896. }
  3897. return rc;
  3898. }
  3899. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  3900. {
  3901. /* Set the logging parameter */
  3902. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  3903. }
  3904. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  3905. {
  3906. struct hwi_controller *phwi_ctrlr;
  3907. struct hwi_context_memory *phwi_context;
  3908. struct be_eq_obj *pbe_eq;
  3909. unsigned int i, msix_vec;
  3910. u8 *real_offset = 0;
  3911. u32 value = 0;
  3912. phwi_ctrlr = phba->phwi_ctrlr;
  3913. phwi_context = phwi_ctrlr->phwi_ctxt;
  3914. hwi_disable_intr(phba);
  3915. if (phba->msix_enabled) {
  3916. for (i = 0; i <= phba->num_cpus; i++) {
  3917. msix_vec = phba->msix_entries[i].vector;
  3918. free_irq(msix_vec, &phwi_context->be_eq[i]);
  3919. kfree(phba->msi_name[i]);
  3920. }
  3921. } else
  3922. if (phba->pcidev->irq)
  3923. free_irq(phba->pcidev->irq, phba);
  3924. pci_disable_msix(phba->pcidev);
  3925. destroy_workqueue(phba->wq);
  3926. if (blk_iopoll_enabled)
  3927. for (i = 0; i < phba->num_cpus; i++) {
  3928. pbe_eq = &phwi_context->be_eq[i];
  3929. blk_iopoll_disable(&pbe_eq->iopoll);
  3930. }
  3931. beiscsi_clean_port(phba);
  3932. beiscsi_free_mem(phba);
  3933. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3934. value = readl((void *)real_offset);
  3935. if (value & 0x00010000) {
  3936. value &= 0xfffeffff;
  3937. writel(value, (void *)real_offset);
  3938. }
  3939. beiscsi_unmap_pci_function(phba);
  3940. pci_free_consistent(phba->pcidev,
  3941. phba->ctrl.mbox_mem_alloced.size,
  3942. phba->ctrl.mbox_mem_alloced.va,
  3943. phba->ctrl.mbox_mem_alloced.dma);
  3944. }
  3945. static void beiscsi_remove(struct pci_dev *pcidev)
  3946. {
  3947. struct beiscsi_hba *phba = NULL;
  3948. phba = pci_get_drvdata(pcidev);
  3949. if (!phba) {
  3950. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  3951. return;
  3952. }
  3953. beiscsi_destroy_def_ifaces(phba);
  3954. beiscsi_quiesce(phba);
  3955. iscsi_boot_destroy_kset(phba->boot_kset);
  3956. iscsi_host_remove(phba->shost);
  3957. pci_dev_put(phba->pcidev);
  3958. iscsi_host_free(phba->shost);
  3959. pci_disable_device(pcidev);
  3960. }
  3961. static void beiscsi_shutdown(struct pci_dev *pcidev)
  3962. {
  3963. struct beiscsi_hba *phba = NULL;
  3964. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  3965. if (!phba) {
  3966. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  3967. return;
  3968. }
  3969. beiscsi_quiesce(phba);
  3970. pci_disable_device(pcidev);
  3971. }
  3972. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  3973. {
  3974. int i, status;
  3975. for (i = 0; i <= phba->num_cpus; i++)
  3976. phba->msix_entries[i].entry = i;
  3977. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  3978. (phba->num_cpus + 1));
  3979. if (!status)
  3980. phba->msix_enabled = true;
  3981. return;
  3982. }
  3983. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  3984. const struct pci_device_id *id)
  3985. {
  3986. struct beiscsi_hba *phba = NULL;
  3987. struct hwi_controller *phwi_ctrlr;
  3988. struct hwi_context_memory *phwi_context;
  3989. struct be_eq_obj *pbe_eq;
  3990. int ret, num_cpus, i;
  3991. u8 *real_offset = 0;
  3992. u32 value = 0;
  3993. ret = beiscsi_enable_pci(pcidev);
  3994. if (ret < 0) {
  3995. dev_err(&pcidev->dev,
  3996. "beiscsi_dev_probe - Failed to enable pci device\n");
  3997. return ret;
  3998. }
  3999. phba = beiscsi_hba_alloc(pcidev);
  4000. if (!phba) {
  4001. dev_err(&pcidev->dev,
  4002. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4003. goto disable_pci;
  4004. }
  4005. /* Initialize Driver configuration Paramters */
  4006. beiscsi_hba_attrs_init(phba);
  4007. switch (pcidev->device) {
  4008. case BE_DEVICE_ID1:
  4009. case OC_DEVICE_ID1:
  4010. case OC_DEVICE_ID2:
  4011. phba->generation = BE_GEN2;
  4012. break;
  4013. case BE_DEVICE_ID2:
  4014. case OC_DEVICE_ID3:
  4015. phba->generation = BE_GEN3;
  4016. break;
  4017. default:
  4018. phba->generation = 0;
  4019. }
  4020. if (enable_msix)
  4021. num_cpus = find_num_cpus();
  4022. else
  4023. num_cpus = 1;
  4024. phba->num_cpus = num_cpus;
  4025. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4026. "BM_%d : num_cpus = %d\n",
  4027. phba->num_cpus);
  4028. if (enable_msix) {
  4029. beiscsi_msix_enable(phba);
  4030. if (!phba->msix_enabled)
  4031. phba->num_cpus = 1;
  4032. }
  4033. ret = be_ctrl_init(phba, pcidev);
  4034. if (ret) {
  4035. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4036. "BM_%d : beiscsi_dev_probe-"
  4037. "Failed in be_ctrl_init\n");
  4038. goto hba_free;
  4039. }
  4040. if (!num_hba) {
  4041. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  4042. value = readl((void *)real_offset);
  4043. if (value & 0x00010000) {
  4044. gcrashmode++;
  4045. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4046. "BM_%d : Loading Driver in crashdump mode\n");
  4047. ret = beiscsi_cmd_reset_function(phba);
  4048. if (ret) {
  4049. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4050. "BM_%d : Reset Failed. Aborting Crashdump\n");
  4051. goto hba_free;
  4052. }
  4053. ret = be_chk_reset_complete(phba);
  4054. if (ret) {
  4055. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4056. "BM_%d : Failed to get out of reset."
  4057. "Aborting Crashdump\n");
  4058. goto hba_free;
  4059. }
  4060. } else {
  4061. value |= 0x00010000;
  4062. writel(value, (void *)real_offset);
  4063. num_hba++;
  4064. }
  4065. }
  4066. spin_lock_init(&phba->io_sgl_lock);
  4067. spin_lock_init(&phba->mgmt_sgl_lock);
  4068. spin_lock_init(&phba->isr_lock);
  4069. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4070. if (ret != 0) {
  4071. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4072. "BM_%d : Error getting fw config\n");
  4073. goto free_port;
  4074. }
  4075. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  4076. beiscsi_get_params(phba);
  4077. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4078. ret = beiscsi_init_port(phba);
  4079. if (ret < 0) {
  4080. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4081. "BM_%d : beiscsi_dev_probe-"
  4082. "Failed in beiscsi_init_port\n");
  4083. goto free_port;
  4084. }
  4085. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4086. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4087. phba->ctrl.mcc_tag[i] = i + 1;
  4088. phba->ctrl.mcc_numtag[i + 1] = 0;
  4089. phba->ctrl.mcc_tag_available++;
  4090. }
  4091. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4092. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_q_irq%u",
  4093. phba->shost->host_no);
  4094. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  4095. if (!phba->wq) {
  4096. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4097. "BM_%d : beiscsi_dev_probe-"
  4098. "Failed to allocate work queue\n");
  4099. goto free_twq;
  4100. }
  4101. INIT_WORK(&phba->work_cqs, beiscsi_process_all_cqs);
  4102. phwi_ctrlr = phba->phwi_ctrlr;
  4103. phwi_context = phwi_ctrlr->phwi_ctxt;
  4104. if (blk_iopoll_enabled) {
  4105. for (i = 0; i < phba->num_cpus; i++) {
  4106. pbe_eq = &phwi_context->be_eq[i];
  4107. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4108. be_iopoll);
  4109. blk_iopoll_enable(&pbe_eq->iopoll);
  4110. }
  4111. }
  4112. ret = beiscsi_init_irqs(phba);
  4113. if (ret < 0) {
  4114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4115. "BM_%d : beiscsi_dev_probe-"
  4116. "Failed to beiscsi_init_irqs\n");
  4117. goto free_blkenbld;
  4118. }
  4119. hwi_enable_intr(phba);
  4120. if (beiscsi_setup_boot_info(phba))
  4121. /*
  4122. * log error but continue, because we may not be using
  4123. * iscsi boot.
  4124. */
  4125. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4126. "BM_%d : Could not set up "
  4127. "iSCSI boot info.\n");
  4128. beiscsi_create_def_ifaces(phba);
  4129. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4130. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4131. return 0;
  4132. free_blkenbld:
  4133. destroy_workqueue(phba->wq);
  4134. if (blk_iopoll_enabled)
  4135. for (i = 0; i < phba->num_cpus; i++) {
  4136. pbe_eq = &phwi_context->be_eq[i];
  4137. blk_iopoll_disable(&pbe_eq->iopoll);
  4138. }
  4139. free_twq:
  4140. beiscsi_clean_port(phba);
  4141. beiscsi_free_mem(phba);
  4142. free_port:
  4143. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  4144. value = readl((void *)real_offset);
  4145. if (value & 0x00010000) {
  4146. value &= 0xfffeffff;
  4147. writel(value, (void *)real_offset);
  4148. }
  4149. pci_free_consistent(phba->pcidev,
  4150. phba->ctrl.mbox_mem_alloced.size,
  4151. phba->ctrl.mbox_mem_alloced.va,
  4152. phba->ctrl.mbox_mem_alloced.dma);
  4153. beiscsi_unmap_pci_function(phba);
  4154. hba_free:
  4155. if (phba->msix_enabled)
  4156. pci_disable_msix(phba->pcidev);
  4157. iscsi_host_remove(phba->shost);
  4158. pci_dev_put(phba->pcidev);
  4159. iscsi_host_free(phba->shost);
  4160. disable_pci:
  4161. pci_disable_device(pcidev);
  4162. return ret;
  4163. }
  4164. struct iscsi_transport beiscsi_iscsi_transport = {
  4165. .owner = THIS_MODULE,
  4166. .name = DRV_NAME,
  4167. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4168. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4169. .create_session = beiscsi_session_create,
  4170. .destroy_session = beiscsi_session_destroy,
  4171. .create_conn = beiscsi_conn_create,
  4172. .bind_conn = beiscsi_conn_bind,
  4173. .destroy_conn = iscsi_conn_teardown,
  4174. .attr_is_visible = be2iscsi_attr_is_visible,
  4175. .set_iface_param = be2iscsi_iface_set_param,
  4176. .get_iface_param = be2iscsi_iface_get_param,
  4177. .set_param = beiscsi_set_param,
  4178. .get_conn_param = iscsi_conn_get_param,
  4179. .get_session_param = iscsi_session_get_param,
  4180. .get_host_param = beiscsi_get_host_param,
  4181. .start_conn = beiscsi_conn_start,
  4182. .stop_conn = iscsi_conn_stop,
  4183. .send_pdu = iscsi_conn_send_pdu,
  4184. .xmit_task = beiscsi_task_xmit,
  4185. .cleanup_task = beiscsi_cleanup_task,
  4186. .alloc_pdu = beiscsi_alloc_pdu,
  4187. .parse_pdu_itt = beiscsi_parse_pdu,
  4188. .get_stats = beiscsi_conn_get_stats,
  4189. .get_ep_param = beiscsi_ep_get_param,
  4190. .ep_connect = beiscsi_ep_connect,
  4191. .ep_poll = beiscsi_ep_poll,
  4192. .ep_disconnect = beiscsi_ep_disconnect,
  4193. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4194. .bsg_request = beiscsi_bsg_request,
  4195. };
  4196. static struct pci_driver beiscsi_pci_driver = {
  4197. .name = DRV_NAME,
  4198. .probe = beiscsi_dev_probe,
  4199. .remove = beiscsi_remove,
  4200. .shutdown = beiscsi_shutdown,
  4201. .id_table = beiscsi_pci_id_table
  4202. };
  4203. static int __init beiscsi_module_init(void)
  4204. {
  4205. int ret;
  4206. beiscsi_scsi_transport =
  4207. iscsi_register_transport(&beiscsi_iscsi_transport);
  4208. if (!beiscsi_scsi_transport) {
  4209. printk(KERN_ERR
  4210. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4211. return -ENOMEM;
  4212. }
  4213. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4214. &beiscsi_iscsi_transport);
  4215. ret = pci_register_driver(&beiscsi_pci_driver);
  4216. if (ret) {
  4217. printk(KERN_ERR
  4218. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4219. goto unregister_iscsi_transport;
  4220. }
  4221. return 0;
  4222. unregister_iscsi_transport:
  4223. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4224. return ret;
  4225. }
  4226. static void __exit beiscsi_module_exit(void)
  4227. {
  4228. pci_unregister_driver(&beiscsi_pci_driver);
  4229. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4230. }
  4231. module_init(beiscsi_module_init);
  4232. module_exit(beiscsi_module_exit);