bnx2x_stats.c 59 KB

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  1. /* bnx2x_stats.c: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. * UDP CSUM errata workaround by Arik Gendelman
  13. * Slowpath and fastpath rework by Vladislav Zolotarov
  14. * Statistics and Link management by Yitchak Gertner
  15. *
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include "bnx2x_stats.h"
  19. #include "bnx2x_cmn.h"
  20. /* Statistics */
  21. /*
  22. * General service functions
  23. */
  24. static inline long bnx2x_hilo(u32 *hiref)
  25. {
  26. u32 lo = *(hiref + 1);
  27. #if (BITS_PER_LONG == 64)
  28. u32 hi = *hiref;
  29. return HILO_U64(hi, lo);
  30. #else
  31. return lo;
  32. #endif
  33. }
  34. static inline u16 bnx2x_get_port_stats_dma_len(struct bnx2x *bp)
  35. {
  36. u16 res = 0;
  37. /* 'newest' convention - shmem2 cotains the size of the port stats */
  38. if (SHMEM2_HAS(bp, sizeof_port_stats)) {
  39. u32 size = SHMEM2_RD(bp, sizeof_port_stats);
  40. if (size)
  41. res = size;
  42. /* prevent newer BC from causing buffer overflow */
  43. if (res > sizeof(struct host_port_stats))
  44. res = sizeof(struct host_port_stats);
  45. }
  46. /* Older convention - all BCs support the port stats' fields up until
  47. * the 'not_used' field
  48. */
  49. if (!res) {
  50. res = offsetof(struct host_port_stats, not_used) + 4;
  51. /* if PFC stats are supported by the MFW, DMA them as well */
  52. if (bp->flags & BC_SUPPORTS_PFC_STATS) {
  53. res += offsetof(struct host_port_stats,
  54. pfc_frames_rx_lo) -
  55. offsetof(struct host_port_stats,
  56. pfc_frames_tx_hi) + 4 ;
  57. }
  58. }
  59. res >>= 2;
  60. WARN_ON(res > 2 * DMAE_LEN32_RD_MAX);
  61. return res;
  62. }
  63. /*
  64. * Init service functions
  65. */
  66. /* Post the next statistics ramrod. Protect it with the spin in
  67. * order to ensure the strict order between statistics ramrods
  68. * (each ramrod has a sequence number passed in a
  69. * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be
  70. * sent in order).
  71. */
  72. static void bnx2x_storm_stats_post(struct bnx2x *bp)
  73. {
  74. if (!bp->stats_pending) {
  75. int rc;
  76. spin_lock_bh(&bp->stats_lock);
  77. if (bp->stats_pending) {
  78. spin_unlock_bh(&bp->stats_lock);
  79. return;
  80. }
  81. bp->fw_stats_req->hdr.drv_stats_counter =
  82. cpu_to_le16(bp->stats_counter++);
  83. DP(BNX2X_MSG_STATS, "Sending statistics ramrod %d\n",
  84. bp->fw_stats_req->hdr.drv_stats_counter);
  85. /* send FW stats ramrod */
  86. rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
  87. U64_HI(bp->fw_stats_req_mapping),
  88. U64_LO(bp->fw_stats_req_mapping),
  89. NONE_CONNECTION_TYPE);
  90. if (rc == 0)
  91. bp->stats_pending = 1;
  92. spin_unlock_bh(&bp->stats_lock);
  93. }
  94. }
  95. static void bnx2x_hw_stats_post(struct bnx2x *bp)
  96. {
  97. struct dmae_command *dmae = &bp->stats_dmae;
  98. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  99. *stats_comp = DMAE_COMP_VAL;
  100. if (CHIP_REV_IS_SLOW(bp))
  101. return;
  102. /* Update MCP's statistics if possible */
  103. if (bp->func_stx)
  104. memcpy(bnx2x_sp(bp, func_stats), &bp->func_stats,
  105. sizeof(bp->func_stats));
  106. /* loader */
  107. if (bp->executer_idx) {
  108. int loader_idx = PMF_DMAE_C(bp);
  109. u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  110. true, DMAE_COMP_GRC);
  111. opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
  112. memset(dmae, 0, sizeof(struct dmae_command));
  113. dmae->opcode = opcode;
  114. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
  115. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
  116. dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
  117. sizeof(struct dmae_command) *
  118. (loader_idx + 1)) >> 2;
  119. dmae->dst_addr_hi = 0;
  120. dmae->len = sizeof(struct dmae_command) >> 2;
  121. if (CHIP_IS_E1(bp))
  122. dmae->len--;
  123. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
  124. dmae->comp_addr_hi = 0;
  125. dmae->comp_val = 1;
  126. *stats_comp = 0;
  127. bnx2x_post_dmae(bp, dmae, loader_idx);
  128. } else if (bp->func_stx) {
  129. *stats_comp = 0;
  130. bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
  131. }
  132. }
  133. static int bnx2x_stats_comp(struct bnx2x *bp)
  134. {
  135. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  136. int cnt = 10;
  137. might_sleep();
  138. while (*stats_comp != DMAE_COMP_VAL) {
  139. if (!cnt) {
  140. BNX2X_ERR("timeout waiting for stats finished\n");
  141. break;
  142. }
  143. cnt--;
  144. usleep_range(1000, 1000);
  145. }
  146. return 1;
  147. }
  148. /*
  149. * Statistics service functions
  150. */
  151. static void bnx2x_stats_pmf_update(struct bnx2x *bp)
  152. {
  153. struct dmae_command *dmae;
  154. u32 opcode;
  155. int loader_idx = PMF_DMAE_C(bp);
  156. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  157. /* sanity */
  158. if (!bp->port.pmf || !bp->port.port_stx) {
  159. BNX2X_ERR("BUG!\n");
  160. return;
  161. }
  162. bp->executer_idx = 0;
  163. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0);
  164. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  165. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
  166. dmae->src_addr_lo = bp->port.port_stx >> 2;
  167. dmae->src_addr_hi = 0;
  168. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  169. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  170. dmae->len = DMAE_LEN32_RD_MAX;
  171. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  172. dmae->comp_addr_hi = 0;
  173. dmae->comp_val = 1;
  174. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  175. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  176. dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
  177. dmae->src_addr_hi = 0;
  178. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
  179. DMAE_LEN32_RD_MAX * 4);
  180. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
  181. DMAE_LEN32_RD_MAX * 4);
  182. dmae->len = bnx2x_get_port_stats_dma_len(bp) - DMAE_LEN32_RD_MAX;
  183. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  184. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  185. dmae->comp_val = DMAE_COMP_VAL;
  186. *stats_comp = 0;
  187. bnx2x_hw_stats_post(bp);
  188. bnx2x_stats_comp(bp);
  189. }
  190. static void bnx2x_port_stats_init(struct bnx2x *bp)
  191. {
  192. struct dmae_command *dmae;
  193. int port = BP_PORT(bp);
  194. u32 opcode;
  195. int loader_idx = PMF_DMAE_C(bp);
  196. u32 mac_addr;
  197. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  198. /* sanity */
  199. if (!bp->link_vars.link_up || !bp->port.pmf) {
  200. BNX2X_ERR("BUG!\n");
  201. return;
  202. }
  203. bp->executer_idx = 0;
  204. /* MCP */
  205. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  206. true, DMAE_COMP_GRC);
  207. if (bp->port.port_stx) {
  208. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  209. dmae->opcode = opcode;
  210. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  211. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  212. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  213. dmae->dst_addr_hi = 0;
  214. dmae->len = bnx2x_get_port_stats_dma_len(bp);
  215. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  216. dmae->comp_addr_hi = 0;
  217. dmae->comp_val = 1;
  218. }
  219. if (bp->func_stx) {
  220. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  221. dmae->opcode = opcode;
  222. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  223. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  224. dmae->dst_addr_lo = bp->func_stx >> 2;
  225. dmae->dst_addr_hi = 0;
  226. dmae->len = sizeof(struct host_func_stats) >> 2;
  227. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  228. dmae->comp_addr_hi = 0;
  229. dmae->comp_val = 1;
  230. }
  231. /* MAC */
  232. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  233. true, DMAE_COMP_GRC);
  234. /* EMAC is special */
  235. if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
  236. mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
  237. /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
  238. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  239. dmae->opcode = opcode;
  240. dmae->src_addr_lo = (mac_addr +
  241. EMAC_REG_EMAC_RX_STAT_AC) >> 2;
  242. dmae->src_addr_hi = 0;
  243. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  244. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  245. dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
  246. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  247. dmae->comp_addr_hi = 0;
  248. dmae->comp_val = 1;
  249. /* EMAC_REG_EMAC_RX_STAT_AC_28 */
  250. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  251. dmae->opcode = opcode;
  252. dmae->src_addr_lo = (mac_addr +
  253. EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
  254. dmae->src_addr_hi = 0;
  255. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  256. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  257. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  258. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  259. dmae->len = 1;
  260. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  261. dmae->comp_addr_hi = 0;
  262. dmae->comp_val = 1;
  263. /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
  264. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  265. dmae->opcode = opcode;
  266. dmae->src_addr_lo = (mac_addr +
  267. EMAC_REG_EMAC_TX_STAT_AC) >> 2;
  268. dmae->src_addr_hi = 0;
  269. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  270. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  271. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  272. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  273. dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
  274. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  275. dmae->comp_addr_hi = 0;
  276. dmae->comp_val = 1;
  277. } else {
  278. u32 tx_src_addr_lo, rx_src_addr_lo;
  279. u16 rx_len, tx_len;
  280. /* configure the params according to MAC type */
  281. switch (bp->link_vars.mac_type) {
  282. case MAC_TYPE_BMAC:
  283. mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
  284. NIG_REG_INGRESS_BMAC0_MEM);
  285. /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
  286. BIGMAC_REGISTER_TX_STAT_GTBYT */
  287. if (CHIP_IS_E1x(bp)) {
  288. tx_src_addr_lo = (mac_addr +
  289. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  290. tx_len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
  291. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  292. rx_src_addr_lo = (mac_addr +
  293. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  294. rx_len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
  295. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  296. } else {
  297. tx_src_addr_lo = (mac_addr +
  298. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  299. tx_len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
  300. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  301. rx_src_addr_lo = (mac_addr +
  302. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  303. rx_len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
  304. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  305. }
  306. break;
  307. case MAC_TYPE_UMAC: /* handled by MSTAT */
  308. case MAC_TYPE_XMAC: /* handled by MSTAT */
  309. default:
  310. mac_addr = port ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
  311. tx_src_addr_lo = (mac_addr +
  312. MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2;
  313. rx_src_addr_lo = (mac_addr +
  314. MSTAT_REG_RX_STAT_GR64_LO) >> 2;
  315. tx_len = sizeof(bp->slowpath->
  316. mac_stats.mstat_stats.stats_tx) >> 2;
  317. rx_len = sizeof(bp->slowpath->
  318. mac_stats.mstat_stats.stats_rx) >> 2;
  319. break;
  320. }
  321. /* TX stats */
  322. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  323. dmae->opcode = opcode;
  324. dmae->src_addr_lo = tx_src_addr_lo;
  325. dmae->src_addr_hi = 0;
  326. dmae->len = tx_len;
  327. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  328. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  329. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  330. dmae->comp_addr_hi = 0;
  331. dmae->comp_val = 1;
  332. /* RX stats */
  333. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  334. dmae->opcode = opcode;
  335. dmae->src_addr_hi = 0;
  336. dmae->src_addr_lo = rx_src_addr_lo;
  337. dmae->dst_addr_lo =
  338. U64_LO(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  339. dmae->dst_addr_hi =
  340. U64_HI(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  341. dmae->len = rx_len;
  342. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  343. dmae->comp_addr_hi = 0;
  344. dmae->comp_val = 1;
  345. }
  346. /* NIG */
  347. if (!CHIP_IS_E3(bp)) {
  348. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  349. dmae->opcode = opcode;
  350. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
  351. NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
  352. dmae->src_addr_hi = 0;
  353. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  354. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  355. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  356. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  357. dmae->len = (2*sizeof(u32)) >> 2;
  358. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  359. dmae->comp_addr_hi = 0;
  360. dmae->comp_val = 1;
  361. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  362. dmae->opcode = opcode;
  363. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
  364. NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
  365. dmae->src_addr_hi = 0;
  366. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  367. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  368. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  369. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  370. dmae->len = (2*sizeof(u32)) >> 2;
  371. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  372. dmae->comp_addr_hi = 0;
  373. dmae->comp_val = 1;
  374. }
  375. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  376. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  377. true, DMAE_COMP_PCI);
  378. dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
  379. NIG_REG_STAT0_BRB_DISCARD) >> 2;
  380. dmae->src_addr_hi = 0;
  381. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
  382. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
  383. dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
  384. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  385. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  386. dmae->comp_val = DMAE_COMP_VAL;
  387. *stats_comp = 0;
  388. }
  389. static void bnx2x_func_stats_init(struct bnx2x *bp)
  390. {
  391. struct dmae_command *dmae = &bp->stats_dmae;
  392. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  393. /* sanity */
  394. if (!bp->func_stx) {
  395. BNX2X_ERR("BUG!\n");
  396. return;
  397. }
  398. bp->executer_idx = 0;
  399. memset(dmae, 0, sizeof(struct dmae_command));
  400. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  401. true, DMAE_COMP_PCI);
  402. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  403. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  404. dmae->dst_addr_lo = bp->func_stx >> 2;
  405. dmae->dst_addr_hi = 0;
  406. dmae->len = sizeof(struct host_func_stats) >> 2;
  407. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  408. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  409. dmae->comp_val = DMAE_COMP_VAL;
  410. *stats_comp = 0;
  411. }
  412. static void bnx2x_stats_start(struct bnx2x *bp)
  413. {
  414. if (bp->port.pmf)
  415. bnx2x_port_stats_init(bp);
  416. else if (bp->func_stx)
  417. bnx2x_func_stats_init(bp);
  418. bnx2x_hw_stats_post(bp);
  419. bnx2x_storm_stats_post(bp);
  420. }
  421. static void bnx2x_stats_pmf_start(struct bnx2x *bp)
  422. {
  423. bnx2x_stats_comp(bp);
  424. bnx2x_stats_pmf_update(bp);
  425. bnx2x_stats_start(bp);
  426. }
  427. static void bnx2x_stats_restart(struct bnx2x *bp)
  428. {
  429. bnx2x_stats_comp(bp);
  430. bnx2x_stats_start(bp);
  431. }
  432. static void bnx2x_bmac_stats_update(struct bnx2x *bp)
  433. {
  434. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  435. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  436. struct {
  437. u32 lo;
  438. u32 hi;
  439. } diff;
  440. if (CHIP_IS_E1x(bp)) {
  441. struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
  442. /* the macros below will use "bmac1_stats" type */
  443. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  444. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  445. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  446. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  447. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  448. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  449. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  450. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  451. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  452. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  453. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  454. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  455. UPDATE_STAT64(tx_stat_gt127,
  456. tx_stat_etherstatspkts65octetsto127octets);
  457. UPDATE_STAT64(tx_stat_gt255,
  458. tx_stat_etherstatspkts128octetsto255octets);
  459. UPDATE_STAT64(tx_stat_gt511,
  460. tx_stat_etherstatspkts256octetsto511octets);
  461. UPDATE_STAT64(tx_stat_gt1023,
  462. tx_stat_etherstatspkts512octetsto1023octets);
  463. UPDATE_STAT64(tx_stat_gt1518,
  464. tx_stat_etherstatspkts1024octetsto1522octets);
  465. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  466. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  467. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  468. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  469. UPDATE_STAT64(tx_stat_gterr,
  470. tx_stat_dot3statsinternalmactransmiterrors);
  471. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  472. } else {
  473. struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats);
  474. /* the macros below will use "bmac2_stats" type */
  475. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  476. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  477. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  478. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  479. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  480. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  481. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  482. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  483. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  484. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  485. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  486. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  487. UPDATE_STAT64(tx_stat_gt127,
  488. tx_stat_etherstatspkts65octetsto127octets);
  489. UPDATE_STAT64(tx_stat_gt255,
  490. tx_stat_etherstatspkts128octetsto255octets);
  491. UPDATE_STAT64(tx_stat_gt511,
  492. tx_stat_etherstatspkts256octetsto511octets);
  493. UPDATE_STAT64(tx_stat_gt1023,
  494. tx_stat_etherstatspkts512octetsto1023octets);
  495. UPDATE_STAT64(tx_stat_gt1518,
  496. tx_stat_etherstatspkts1024octetsto1522octets);
  497. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  498. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  499. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  500. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  501. UPDATE_STAT64(tx_stat_gterr,
  502. tx_stat_dot3statsinternalmactransmiterrors);
  503. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  504. /* collect PFC stats */
  505. pstats->pfc_frames_tx_hi = new->tx_stat_gtpp_hi;
  506. pstats->pfc_frames_tx_lo = new->tx_stat_gtpp_lo;
  507. pstats->pfc_frames_rx_hi = new->rx_stat_grpp_hi;
  508. pstats->pfc_frames_rx_lo = new->rx_stat_grpp_lo;
  509. }
  510. estats->pause_frames_received_hi =
  511. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  512. estats->pause_frames_received_lo =
  513. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  514. estats->pause_frames_sent_hi =
  515. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  516. estats->pause_frames_sent_lo =
  517. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  518. estats->pfc_frames_received_hi =
  519. pstats->pfc_frames_rx_hi;
  520. estats->pfc_frames_received_lo =
  521. pstats->pfc_frames_rx_lo;
  522. estats->pfc_frames_sent_hi =
  523. pstats->pfc_frames_tx_hi;
  524. estats->pfc_frames_sent_lo =
  525. pstats->pfc_frames_tx_lo;
  526. }
  527. static void bnx2x_mstat_stats_update(struct bnx2x *bp)
  528. {
  529. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  530. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  531. struct mstat_stats *new = bnx2x_sp(bp, mac_stats.mstat_stats);
  532. ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
  533. ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
  534. ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
  535. ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
  536. ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
  537. ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
  538. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
  539. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
  540. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
  541. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
  542. /* collect pfc stats */
  543. ADD_64(pstats->pfc_frames_tx_hi, new->stats_tx.tx_gtxpp_hi,
  544. pstats->pfc_frames_tx_lo, new->stats_tx.tx_gtxpp_lo);
  545. ADD_64(pstats->pfc_frames_rx_hi, new->stats_rx.rx_grxpp_hi,
  546. pstats->pfc_frames_rx_lo, new->stats_rx.rx_grxpp_lo);
  547. ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
  548. ADD_STAT64(stats_tx.tx_gt127,
  549. tx_stat_etherstatspkts65octetsto127octets);
  550. ADD_STAT64(stats_tx.tx_gt255,
  551. tx_stat_etherstatspkts128octetsto255octets);
  552. ADD_STAT64(stats_tx.tx_gt511,
  553. tx_stat_etherstatspkts256octetsto511octets);
  554. ADD_STAT64(stats_tx.tx_gt1023,
  555. tx_stat_etherstatspkts512octetsto1023octets);
  556. ADD_STAT64(stats_tx.tx_gt1518,
  557. tx_stat_etherstatspkts1024octetsto1522octets);
  558. ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
  559. ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
  560. ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
  561. ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
  562. ADD_STAT64(stats_tx.tx_gterr,
  563. tx_stat_dot3statsinternalmactransmiterrors);
  564. ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
  565. estats->etherstatspkts1024octetsto1522octets_hi =
  566. pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_hi;
  567. estats->etherstatspkts1024octetsto1522octets_lo =
  568. pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_lo;
  569. estats->etherstatspktsover1522octets_hi =
  570. pstats->mac_stx[1].tx_stat_mac_2047_hi;
  571. estats->etherstatspktsover1522octets_lo =
  572. pstats->mac_stx[1].tx_stat_mac_2047_lo;
  573. ADD_64(estats->etherstatspktsover1522octets_hi,
  574. pstats->mac_stx[1].tx_stat_mac_4095_hi,
  575. estats->etherstatspktsover1522octets_lo,
  576. pstats->mac_stx[1].tx_stat_mac_4095_lo);
  577. ADD_64(estats->etherstatspktsover1522octets_hi,
  578. pstats->mac_stx[1].tx_stat_mac_9216_hi,
  579. estats->etherstatspktsover1522octets_lo,
  580. pstats->mac_stx[1].tx_stat_mac_9216_lo);
  581. ADD_64(estats->etherstatspktsover1522octets_hi,
  582. pstats->mac_stx[1].tx_stat_mac_16383_hi,
  583. estats->etherstatspktsover1522octets_lo,
  584. pstats->mac_stx[1].tx_stat_mac_16383_lo);
  585. estats->pause_frames_received_hi =
  586. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  587. estats->pause_frames_received_lo =
  588. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  589. estats->pause_frames_sent_hi =
  590. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  591. estats->pause_frames_sent_lo =
  592. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  593. estats->pfc_frames_received_hi =
  594. pstats->pfc_frames_rx_hi;
  595. estats->pfc_frames_received_lo =
  596. pstats->pfc_frames_rx_lo;
  597. estats->pfc_frames_sent_hi =
  598. pstats->pfc_frames_tx_hi;
  599. estats->pfc_frames_sent_lo =
  600. pstats->pfc_frames_tx_lo;
  601. }
  602. static void bnx2x_emac_stats_update(struct bnx2x *bp)
  603. {
  604. struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
  605. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  606. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  607. UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
  608. UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
  609. UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
  610. UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
  611. UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
  612. UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
  613. UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
  614. UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
  615. UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
  616. UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
  617. UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
  618. UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
  619. UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
  620. UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
  621. UPDATE_EXTEND_STAT(tx_stat_outxonsent);
  622. UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
  623. UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
  624. UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
  625. UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
  626. UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
  627. UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
  628. UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
  629. UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
  630. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
  631. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
  632. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
  633. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
  634. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
  635. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
  636. UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
  637. UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
  638. estats->pause_frames_received_hi =
  639. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
  640. estats->pause_frames_received_lo =
  641. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
  642. ADD_64(estats->pause_frames_received_hi,
  643. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
  644. estats->pause_frames_received_lo,
  645. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
  646. estats->pause_frames_sent_hi =
  647. pstats->mac_stx[1].tx_stat_outxonsent_hi;
  648. estats->pause_frames_sent_lo =
  649. pstats->mac_stx[1].tx_stat_outxonsent_lo;
  650. ADD_64(estats->pause_frames_sent_hi,
  651. pstats->mac_stx[1].tx_stat_outxoffsent_hi,
  652. estats->pause_frames_sent_lo,
  653. pstats->mac_stx[1].tx_stat_outxoffsent_lo);
  654. }
  655. static int bnx2x_hw_stats_update(struct bnx2x *bp)
  656. {
  657. struct nig_stats *new = bnx2x_sp(bp, nig_stats);
  658. struct nig_stats *old = &(bp->port.old_nig_stats);
  659. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  660. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  661. struct {
  662. u32 lo;
  663. u32 hi;
  664. } diff;
  665. switch (bp->link_vars.mac_type) {
  666. case MAC_TYPE_BMAC:
  667. bnx2x_bmac_stats_update(bp);
  668. break;
  669. case MAC_TYPE_EMAC:
  670. bnx2x_emac_stats_update(bp);
  671. break;
  672. case MAC_TYPE_UMAC:
  673. case MAC_TYPE_XMAC:
  674. bnx2x_mstat_stats_update(bp);
  675. break;
  676. case MAC_TYPE_NONE: /* unreached */
  677. DP(BNX2X_MSG_STATS,
  678. "stats updated by DMAE but no MAC active\n");
  679. return -1;
  680. default: /* unreached */
  681. BNX2X_ERR("Unknown MAC type\n");
  682. }
  683. ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
  684. new->brb_discard - old->brb_discard);
  685. ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
  686. new->brb_truncate - old->brb_truncate);
  687. if (!CHIP_IS_E3(bp)) {
  688. UPDATE_STAT64_NIG(egress_mac_pkt0,
  689. etherstatspkts1024octetsto1522octets);
  690. UPDATE_STAT64_NIG(egress_mac_pkt1,
  691. etherstatspktsover1522octets);
  692. }
  693. memcpy(old, new, sizeof(struct nig_stats));
  694. memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
  695. sizeof(struct mac_stx));
  696. estats->brb_drop_hi = pstats->brb_drop_hi;
  697. estats->brb_drop_lo = pstats->brb_drop_lo;
  698. pstats->host_port_stats_counter++;
  699. if (CHIP_IS_E3(bp)) {
  700. u32 lpi_reg = BP_PORT(bp) ? MISC_REG_CPMU_LP_SM_ENT_CNT_P1
  701. : MISC_REG_CPMU_LP_SM_ENT_CNT_P0;
  702. estats->eee_tx_lpi += REG_RD(bp, lpi_reg);
  703. }
  704. if (!BP_NOMCP(bp)) {
  705. u32 nig_timer_max =
  706. SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
  707. if (nig_timer_max != estats->nig_timer_max) {
  708. estats->nig_timer_max = nig_timer_max;
  709. BNX2X_ERR("NIG timer max (%u)\n",
  710. estats->nig_timer_max);
  711. }
  712. }
  713. return 0;
  714. }
  715. static int bnx2x_storm_stats_update(struct bnx2x *bp)
  716. {
  717. struct tstorm_per_port_stats *tport =
  718. &bp->fw_stats_data->port.tstorm_port_statistics;
  719. struct tstorm_per_pf_stats *tfunc =
  720. &bp->fw_stats_data->pf.tstorm_pf_statistics;
  721. struct host_func_stats *fstats = &bp->func_stats;
  722. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  723. struct bnx2x_eth_stats_old *estats_old = &bp->eth_stats_old;
  724. struct stats_counter *counters = &bp->fw_stats_data->storm_counters;
  725. int i;
  726. u16 cur_stats_counter;
  727. /* Make sure we use the value of the counter
  728. * used for sending the last stats ramrod.
  729. */
  730. spin_lock_bh(&bp->stats_lock);
  731. cur_stats_counter = bp->stats_counter - 1;
  732. spin_unlock_bh(&bp->stats_lock);
  733. /* are storm stats valid? */
  734. if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
  735. DP(BNX2X_MSG_STATS,
  736. "stats not updated by xstorm xstorm counter (0x%x) != stats_counter (0x%x)\n",
  737. le16_to_cpu(counters->xstats_counter), bp->stats_counter);
  738. return -EAGAIN;
  739. }
  740. if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
  741. DP(BNX2X_MSG_STATS,
  742. "stats not updated by ustorm ustorm counter (0x%x) != stats_counter (0x%x)\n",
  743. le16_to_cpu(counters->ustats_counter), bp->stats_counter);
  744. return -EAGAIN;
  745. }
  746. if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
  747. DP(BNX2X_MSG_STATS,
  748. "stats not updated by cstorm cstorm counter (0x%x) != stats_counter (0x%x)\n",
  749. le16_to_cpu(counters->cstats_counter), bp->stats_counter);
  750. return -EAGAIN;
  751. }
  752. if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
  753. DP(BNX2X_MSG_STATS,
  754. "stats not updated by tstorm tstorm counter (0x%x) != stats_counter (0x%x)\n",
  755. le16_to_cpu(counters->tstats_counter), bp->stats_counter);
  756. return -EAGAIN;
  757. }
  758. estats->error_bytes_received_hi = 0;
  759. estats->error_bytes_received_lo = 0;
  760. for_each_eth_queue(bp, i) {
  761. struct bnx2x_fastpath *fp = &bp->fp[i];
  762. struct tstorm_per_queue_stats *tclient =
  763. &bp->fw_stats_data->queue_stats[i].
  764. tstorm_queue_statistics;
  765. struct tstorm_per_queue_stats *old_tclient =
  766. &bnx2x_fp_stats(bp, fp)->old_tclient;
  767. struct ustorm_per_queue_stats *uclient =
  768. &bp->fw_stats_data->queue_stats[i].
  769. ustorm_queue_statistics;
  770. struct ustorm_per_queue_stats *old_uclient =
  771. &bnx2x_fp_stats(bp, fp)->old_uclient;
  772. struct xstorm_per_queue_stats *xclient =
  773. &bp->fw_stats_data->queue_stats[i].
  774. xstorm_queue_statistics;
  775. struct xstorm_per_queue_stats *old_xclient =
  776. &bnx2x_fp_stats(bp, fp)->old_xclient;
  777. struct bnx2x_eth_q_stats *qstats =
  778. &bnx2x_fp_stats(bp, fp)->eth_q_stats;
  779. struct bnx2x_eth_q_stats_old *qstats_old =
  780. &bnx2x_fp_stats(bp, fp)->eth_q_stats_old;
  781. u32 diff;
  782. DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, bcast_sent 0x%x mcast_sent 0x%x\n",
  783. i, xclient->ucast_pkts_sent,
  784. xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
  785. DP(BNX2X_MSG_STATS, "---------------\n");
  786. UPDATE_QSTAT(tclient->rcv_bcast_bytes,
  787. total_broadcast_bytes_received);
  788. UPDATE_QSTAT(tclient->rcv_mcast_bytes,
  789. total_multicast_bytes_received);
  790. UPDATE_QSTAT(tclient->rcv_ucast_bytes,
  791. total_unicast_bytes_received);
  792. /*
  793. * sum to total_bytes_received all
  794. * unicast/multicast/broadcast
  795. */
  796. qstats->total_bytes_received_hi =
  797. qstats->total_broadcast_bytes_received_hi;
  798. qstats->total_bytes_received_lo =
  799. qstats->total_broadcast_bytes_received_lo;
  800. ADD_64(qstats->total_bytes_received_hi,
  801. qstats->total_multicast_bytes_received_hi,
  802. qstats->total_bytes_received_lo,
  803. qstats->total_multicast_bytes_received_lo);
  804. ADD_64(qstats->total_bytes_received_hi,
  805. qstats->total_unicast_bytes_received_hi,
  806. qstats->total_bytes_received_lo,
  807. qstats->total_unicast_bytes_received_lo);
  808. qstats->valid_bytes_received_hi =
  809. qstats->total_bytes_received_hi;
  810. qstats->valid_bytes_received_lo =
  811. qstats->total_bytes_received_lo;
  812. UPDATE_EXTEND_TSTAT(rcv_ucast_pkts,
  813. total_unicast_packets_received);
  814. UPDATE_EXTEND_TSTAT(rcv_mcast_pkts,
  815. total_multicast_packets_received);
  816. UPDATE_EXTEND_TSTAT(rcv_bcast_pkts,
  817. total_broadcast_packets_received);
  818. UPDATE_EXTEND_E_TSTAT(pkts_too_big_discard,
  819. etherstatsoverrsizepkts);
  820. UPDATE_EXTEND_E_TSTAT(no_buff_discard, no_buff_discard);
  821. SUB_EXTEND_USTAT(ucast_no_buff_pkts,
  822. total_unicast_packets_received);
  823. SUB_EXTEND_USTAT(mcast_no_buff_pkts,
  824. total_multicast_packets_received);
  825. SUB_EXTEND_USTAT(bcast_no_buff_pkts,
  826. total_broadcast_packets_received);
  827. UPDATE_EXTEND_E_USTAT(ucast_no_buff_pkts, no_buff_discard);
  828. UPDATE_EXTEND_E_USTAT(mcast_no_buff_pkts, no_buff_discard);
  829. UPDATE_EXTEND_E_USTAT(bcast_no_buff_pkts, no_buff_discard);
  830. UPDATE_QSTAT(xclient->bcast_bytes_sent,
  831. total_broadcast_bytes_transmitted);
  832. UPDATE_QSTAT(xclient->mcast_bytes_sent,
  833. total_multicast_bytes_transmitted);
  834. UPDATE_QSTAT(xclient->ucast_bytes_sent,
  835. total_unicast_bytes_transmitted);
  836. /*
  837. * sum to total_bytes_transmitted all
  838. * unicast/multicast/broadcast
  839. */
  840. qstats->total_bytes_transmitted_hi =
  841. qstats->total_unicast_bytes_transmitted_hi;
  842. qstats->total_bytes_transmitted_lo =
  843. qstats->total_unicast_bytes_transmitted_lo;
  844. ADD_64(qstats->total_bytes_transmitted_hi,
  845. qstats->total_broadcast_bytes_transmitted_hi,
  846. qstats->total_bytes_transmitted_lo,
  847. qstats->total_broadcast_bytes_transmitted_lo);
  848. ADD_64(qstats->total_bytes_transmitted_hi,
  849. qstats->total_multicast_bytes_transmitted_hi,
  850. qstats->total_bytes_transmitted_lo,
  851. qstats->total_multicast_bytes_transmitted_lo);
  852. UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
  853. total_unicast_packets_transmitted);
  854. UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
  855. total_multicast_packets_transmitted);
  856. UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
  857. total_broadcast_packets_transmitted);
  858. UPDATE_EXTEND_TSTAT(checksum_discard,
  859. total_packets_received_checksum_discarded);
  860. UPDATE_EXTEND_TSTAT(ttl0_discard,
  861. total_packets_received_ttl0_discarded);
  862. UPDATE_EXTEND_XSTAT(error_drop_pkts,
  863. total_transmitted_dropped_packets_error);
  864. /* TPA aggregations completed */
  865. UPDATE_EXTEND_E_USTAT(coalesced_events, total_tpa_aggregations);
  866. /* Number of network frames aggregated by TPA */
  867. UPDATE_EXTEND_E_USTAT(coalesced_pkts,
  868. total_tpa_aggregated_frames);
  869. /* Total number of bytes in completed TPA aggregations */
  870. UPDATE_QSTAT(uclient->coalesced_bytes, total_tpa_bytes);
  871. UPDATE_ESTAT_QSTAT_64(total_tpa_bytes);
  872. UPDATE_FSTAT_QSTAT(total_bytes_received);
  873. UPDATE_FSTAT_QSTAT(total_bytes_transmitted);
  874. UPDATE_FSTAT_QSTAT(total_unicast_packets_received);
  875. UPDATE_FSTAT_QSTAT(total_multicast_packets_received);
  876. UPDATE_FSTAT_QSTAT(total_broadcast_packets_received);
  877. UPDATE_FSTAT_QSTAT(total_unicast_packets_transmitted);
  878. UPDATE_FSTAT_QSTAT(total_multicast_packets_transmitted);
  879. UPDATE_FSTAT_QSTAT(total_broadcast_packets_transmitted);
  880. UPDATE_FSTAT_QSTAT(valid_bytes_received);
  881. }
  882. ADD_64(estats->total_bytes_received_hi,
  883. estats->rx_stat_ifhcinbadoctets_hi,
  884. estats->total_bytes_received_lo,
  885. estats->rx_stat_ifhcinbadoctets_lo);
  886. ADD_64(estats->total_bytes_received_hi,
  887. le32_to_cpu(tfunc->rcv_error_bytes.hi),
  888. estats->total_bytes_received_lo,
  889. le32_to_cpu(tfunc->rcv_error_bytes.lo));
  890. ADD_64(estats->error_bytes_received_hi,
  891. le32_to_cpu(tfunc->rcv_error_bytes.hi),
  892. estats->error_bytes_received_lo,
  893. le32_to_cpu(tfunc->rcv_error_bytes.lo));
  894. UPDATE_ESTAT(etherstatsoverrsizepkts, rx_stat_dot3statsframestoolong);
  895. ADD_64(estats->error_bytes_received_hi,
  896. estats->rx_stat_ifhcinbadoctets_hi,
  897. estats->error_bytes_received_lo,
  898. estats->rx_stat_ifhcinbadoctets_lo);
  899. if (bp->port.pmf) {
  900. struct bnx2x_fw_port_stats_old *fwstats = &bp->fw_stats_old;
  901. UPDATE_FW_STAT(mac_filter_discard);
  902. UPDATE_FW_STAT(mf_tag_discard);
  903. UPDATE_FW_STAT(brb_truncate_discard);
  904. UPDATE_FW_STAT(mac_discard);
  905. }
  906. fstats->host_func_stats_start = ++fstats->host_func_stats_end;
  907. bp->stats_pending = 0;
  908. return 0;
  909. }
  910. static void bnx2x_net_stats_update(struct bnx2x *bp)
  911. {
  912. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  913. struct net_device_stats *nstats = &bp->dev->stats;
  914. unsigned long tmp;
  915. int i;
  916. nstats->rx_packets =
  917. bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
  918. bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
  919. bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
  920. nstats->tx_packets =
  921. bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
  922. bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
  923. bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
  924. nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
  925. nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
  926. tmp = estats->mac_discard;
  927. for_each_rx_queue(bp, i) {
  928. struct tstorm_per_queue_stats *old_tclient =
  929. &bp->fp_stats[i].old_tclient;
  930. tmp += le32_to_cpu(old_tclient->checksum_discard);
  931. }
  932. nstats->rx_dropped = tmp + bp->net_stats_old.rx_dropped;
  933. nstats->tx_dropped = 0;
  934. nstats->multicast =
  935. bnx2x_hilo(&estats->total_multicast_packets_received_hi);
  936. nstats->collisions =
  937. bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
  938. nstats->rx_length_errors =
  939. bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
  940. bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
  941. nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
  942. bnx2x_hilo(&estats->brb_truncate_hi);
  943. nstats->rx_crc_errors =
  944. bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
  945. nstats->rx_frame_errors =
  946. bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
  947. nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
  948. nstats->rx_missed_errors = 0;
  949. nstats->rx_errors = nstats->rx_length_errors +
  950. nstats->rx_over_errors +
  951. nstats->rx_crc_errors +
  952. nstats->rx_frame_errors +
  953. nstats->rx_fifo_errors +
  954. nstats->rx_missed_errors;
  955. nstats->tx_aborted_errors =
  956. bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
  957. bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
  958. nstats->tx_carrier_errors =
  959. bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
  960. nstats->tx_fifo_errors = 0;
  961. nstats->tx_heartbeat_errors = 0;
  962. nstats->tx_window_errors = 0;
  963. nstats->tx_errors = nstats->tx_aborted_errors +
  964. nstats->tx_carrier_errors +
  965. bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
  966. }
  967. static void bnx2x_drv_stats_update(struct bnx2x *bp)
  968. {
  969. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  970. int i;
  971. for_each_queue(bp, i) {
  972. struct bnx2x_eth_q_stats *qstats = &bp->fp_stats[i].eth_q_stats;
  973. struct bnx2x_eth_q_stats_old *qstats_old =
  974. &bp->fp_stats[i].eth_q_stats_old;
  975. UPDATE_ESTAT_QSTAT(driver_xoff);
  976. UPDATE_ESTAT_QSTAT(rx_err_discard_pkt);
  977. UPDATE_ESTAT_QSTAT(rx_skb_alloc_failed);
  978. UPDATE_ESTAT_QSTAT(hw_csum_err);
  979. }
  980. }
  981. static bool bnx2x_edebug_stats_stopped(struct bnx2x *bp)
  982. {
  983. u32 val;
  984. if (SHMEM2_HAS(bp, edebug_driver_if[1])) {
  985. val = SHMEM2_RD(bp, edebug_driver_if[1]);
  986. if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT)
  987. return true;
  988. }
  989. return false;
  990. }
  991. static void bnx2x_stats_update(struct bnx2x *bp)
  992. {
  993. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  994. if (bnx2x_edebug_stats_stopped(bp))
  995. return;
  996. if (*stats_comp != DMAE_COMP_VAL)
  997. return;
  998. if (bp->port.pmf)
  999. bnx2x_hw_stats_update(bp);
  1000. if (bnx2x_storm_stats_update(bp)) {
  1001. if (bp->stats_pending++ == 3) {
  1002. BNX2X_ERR("storm stats were not updated for 3 times\n");
  1003. bnx2x_panic();
  1004. }
  1005. return;
  1006. }
  1007. bnx2x_net_stats_update(bp);
  1008. bnx2x_drv_stats_update(bp);
  1009. if (netif_msg_timer(bp)) {
  1010. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  1011. netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
  1012. estats->brb_drop_lo, estats->brb_truncate_lo);
  1013. }
  1014. bnx2x_hw_stats_post(bp);
  1015. bnx2x_storm_stats_post(bp);
  1016. }
  1017. static void bnx2x_port_stats_stop(struct bnx2x *bp)
  1018. {
  1019. struct dmae_command *dmae;
  1020. u32 opcode;
  1021. int loader_idx = PMF_DMAE_C(bp);
  1022. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1023. bp->executer_idx = 0;
  1024. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0);
  1025. if (bp->port.port_stx) {
  1026. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1027. if (bp->func_stx)
  1028. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  1029. opcode, DMAE_COMP_GRC);
  1030. else
  1031. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  1032. opcode, DMAE_COMP_PCI);
  1033. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  1034. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  1035. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  1036. dmae->dst_addr_hi = 0;
  1037. dmae->len = bnx2x_get_port_stats_dma_len(bp);
  1038. if (bp->func_stx) {
  1039. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  1040. dmae->comp_addr_hi = 0;
  1041. dmae->comp_val = 1;
  1042. } else {
  1043. dmae->comp_addr_lo =
  1044. U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1045. dmae->comp_addr_hi =
  1046. U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1047. dmae->comp_val = DMAE_COMP_VAL;
  1048. *stats_comp = 0;
  1049. }
  1050. }
  1051. if (bp->func_stx) {
  1052. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1053. dmae->opcode =
  1054. bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  1055. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  1056. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  1057. dmae->dst_addr_lo = bp->func_stx >> 2;
  1058. dmae->dst_addr_hi = 0;
  1059. dmae->len = sizeof(struct host_func_stats) >> 2;
  1060. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1061. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1062. dmae->comp_val = DMAE_COMP_VAL;
  1063. *stats_comp = 0;
  1064. }
  1065. }
  1066. static void bnx2x_stats_stop(struct bnx2x *bp)
  1067. {
  1068. int update = 0;
  1069. bnx2x_stats_comp(bp);
  1070. if (bp->port.pmf)
  1071. update = (bnx2x_hw_stats_update(bp) == 0);
  1072. update |= (bnx2x_storm_stats_update(bp) == 0);
  1073. if (update) {
  1074. bnx2x_net_stats_update(bp);
  1075. if (bp->port.pmf)
  1076. bnx2x_port_stats_stop(bp);
  1077. bnx2x_hw_stats_post(bp);
  1078. bnx2x_stats_comp(bp);
  1079. }
  1080. }
  1081. static void bnx2x_stats_do_nothing(struct bnx2x *bp)
  1082. {
  1083. }
  1084. static const struct {
  1085. void (*action)(struct bnx2x *bp);
  1086. enum bnx2x_stats_state next_state;
  1087. } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
  1088. /* state event */
  1089. {
  1090. /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
  1091. /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
  1092. /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
  1093. /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
  1094. },
  1095. {
  1096. /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
  1097. /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
  1098. /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
  1099. /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
  1100. }
  1101. };
  1102. void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
  1103. {
  1104. enum bnx2x_stats_state state;
  1105. if (unlikely(bp->panic))
  1106. return;
  1107. spin_lock_bh(&bp->stats_lock);
  1108. state = bp->stats_state;
  1109. bp->stats_state = bnx2x_stats_stm[state][event].next_state;
  1110. spin_unlock_bh(&bp->stats_lock);
  1111. bnx2x_stats_stm[state][event].action(bp);
  1112. if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
  1113. DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
  1114. state, event, bp->stats_state);
  1115. }
  1116. static void bnx2x_port_stats_base_init(struct bnx2x *bp)
  1117. {
  1118. struct dmae_command *dmae;
  1119. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1120. /* sanity */
  1121. if (!bp->port.pmf || !bp->port.port_stx) {
  1122. BNX2X_ERR("BUG!\n");
  1123. return;
  1124. }
  1125. bp->executer_idx = 0;
  1126. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1127. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  1128. true, DMAE_COMP_PCI);
  1129. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  1130. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  1131. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  1132. dmae->dst_addr_hi = 0;
  1133. dmae->len = bnx2x_get_port_stats_dma_len(bp);
  1134. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1135. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1136. dmae->comp_val = DMAE_COMP_VAL;
  1137. *stats_comp = 0;
  1138. bnx2x_hw_stats_post(bp);
  1139. bnx2x_stats_comp(bp);
  1140. }
  1141. /* This function will prepare the statistics ramrod data the way
  1142. * we will only have to increment the statistics counter and
  1143. * send the ramrod each time we have to.
  1144. */
  1145. static void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
  1146. {
  1147. int i;
  1148. int first_queue_query_index;
  1149. struct stats_query_header *stats_hdr = &bp->fw_stats_req->hdr;
  1150. dma_addr_t cur_data_offset;
  1151. struct stats_query_entry *cur_query_entry;
  1152. stats_hdr->cmd_num = bp->fw_stats_num;
  1153. stats_hdr->drv_stats_counter = 0;
  1154. /* storm_counters struct contains the counters of completed
  1155. * statistics requests per storm which are incremented by FW
  1156. * each time it completes hadning a statistics ramrod. We will
  1157. * check these counters in the timer handler and discard a
  1158. * (statistics) ramrod completion.
  1159. */
  1160. cur_data_offset = bp->fw_stats_data_mapping +
  1161. offsetof(struct bnx2x_fw_stats_data, storm_counters);
  1162. stats_hdr->stats_counters_addrs.hi =
  1163. cpu_to_le32(U64_HI(cur_data_offset));
  1164. stats_hdr->stats_counters_addrs.lo =
  1165. cpu_to_le32(U64_LO(cur_data_offset));
  1166. /* prepare to the first stats ramrod (will be completed with
  1167. * the counters equal to zero) - init counters to somethig different.
  1168. */
  1169. memset(&bp->fw_stats_data->storm_counters, 0xff,
  1170. sizeof(struct stats_counter));
  1171. /**** Port FW statistics data ****/
  1172. cur_data_offset = bp->fw_stats_data_mapping +
  1173. offsetof(struct bnx2x_fw_stats_data, port);
  1174. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
  1175. cur_query_entry->kind = STATS_TYPE_PORT;
  1176. /* For port query index is a DONT CARE */
  1177. cur_query_entry->index = BP_PORT(bp);
  1178. /* For port query funcID is a DONT CARE */
  1179. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1180. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1181. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1182. /**** PF FW statistics data ****/
  1183. cur_data_offset = bp->fw_stats_data_mapping +
  1184. offsetof(struct bnx2x_fw_stats_data, pf);
  1185. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
  1186. cur_query_entry->kind = STATS_TYPE_PF;
  1187. /* For PF query index is a DONT CARE */
  1188. cur_query_entry->index = BP_PORT(bp);
  1189. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1190. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1191. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1192. /**** FCoE FW statistics data ****/
  1193. if (!NO_FCOE(bp)) {
  1194. cur_data_offset = bp->fw_stats_data_mapping +
  1195. offsetof(struct bnx2x_fw_stats_data, fcoe);
  1196. cur_query_entry =
  1197. &bp->fw_stats_req->query[BNX2X_FCOE_QUERY_IDX];
  1198. cur_query_entry->kind = STATS_TYPE_FCOE;
  1199. /* For FCoE query index is a DONT CARE */
  1200. cur_query_entry->index = BP_PORT(bp);
  1201. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1202. cur_query_entry->address.hi =
  1203. cpu_to_le32(U64_HI(cur_data_offset));
  1204. cur_query_entry->address.lo =
  1205. cpu_to_le32(U64_LO(cur_data_offset));
  1206. }
  1207. /**** Clients' queries ****/
  1208. cur_data_offset = bp->fw_stats_data_mapping +
  1209. offsetof(struct bnx2x_fw_stats_data, queue_stats);
  1210. /* first queue query index depends whether FCoE offloaded request will
  1211. * be included in the ramrod
  1212. */
  1213. if (!NO_FCOE(bp))
  1214. first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX;
  1215. else
  1216. first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1;
  1217. for_each_eth_queue(bp, i) {
  1218. cur_query_entry =
  1219. &bp->fw_stats_req->
  1220. query[first_queue_query_index + i];
  1221. cur_query_entry->kind = STATS_TYPE_QUEUE;
  1222. cur_query_entry->index = bnx2x_stats_id(&bp->fp[i]);
  1223. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1224. cur_query_entry->address.hi =
  1225. cpu_to_le32(U64_HI(cur_data_offset));
  1226. cur_query_entry->address.lo =
  1227. cpu_to_le32(U64_LO(cur_data_offset));
  1228. cur_data_offset += sizeof(struct per_queue_stats);
  1229. }
  1230. /* add FCoE queue query if needed */
  1231. if (!NO_FCOE(bp)) {
  1232. cur_query_entry =
  1233. &bp->fw_stats_req->
  1234. query[first_queue_query_index + i];
  1235. cur_query_entry->kind = STATS_TYPE_QUEUE;
  1236. cur_query_entry->index = bnx2x_stats_id(&bp->fp[FCOE_IDX(bp)]);
  1237. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1238. cur_query_entry->address.hi =
  1239. cpu_to_le32(U64_HI(cur_data_offset));
  1240. cur_query_entry->address.lo =
  1241. cpu_to_le32(U64_LO(cur_data_offset));
  1242. }
  1243. }
  1244. void bnx2x_stats_init(struct bnx2x *bp)
  1245. {
  1246. int /*abs*/port = BP_PORT(bp);
  1247. int mb_idx = BP_FW_MB_IDX(bp);
  1248. int i;
  1249. bp->stats_pending = 0;
  1250. bp->executer_idx = 0;
  1251. bp->stats_counter = 0;
  1252. /* port and func stats for management */
  1253. if (!BP_NOMCP(bp)) {
  1254. bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
  1255. bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
  1256. } else {
  1257. bp->port.port_stx = 0;
  1258. bp->func_stx = 0;
  1259. }
  1260. DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
  1261. bp->port.port_stx, bp->func_stx);
  1262. /* pmf should retrieve port statistics from SP on a non-init*/
  1263. if (!bp->stats_init && bp->port.pmf && bp->port.port_stx)
  1264. bnx2x_stats_handle(bp, STATS_EVENT_PMF);
  1265. port = BP_PORT(bp);
  1266. /* port stats */
  1267. memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
  1268. bp->port.old_nig_stats.brb_discard =
  1269. REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
  1270. bp->port.old_nig_stats.brb_truncate =
  1271. REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
  1272. if (!CHIP_IS_E3(bp)) {
  1273. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
  1274. &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
  1275. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
  1276. &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
  1277. }
  1278. /* function stats */
  1279. for_each_queue(bp, i) {
  1280. struct bnx2x_fp_stats *fp_stats = &bp->fp_stats[i];
  1281. memset(&fp_stats->old_tclient, 0,
  1282. sizeof(fp_stats->old_tclient));
  1283. memset(&fp_stats->old_uclient, 0,
  1284. sizeof(fp_stats->old_uclient));
  1285. memset(&fp_stats->old_xclient, 0,
  1286. sizeof(fp_stats->old_xclient));
  1287. if (bp->stats_init) {
  1288. memset(&fp_stats->eth_q_stats, 0,
  1289. sizeof(fp_stats->eth_q_stats));
  1290. memset(&fp_stats->eth_q_stats_old, 0,
  1291. sizeof(fp_stats->eth_q_stats_old));
  1292. }
  1293. }
  1294. /* Prepare statistics ramrod data */
  1295. bnx2x_prep_fw_stats_req(bp);
  1296. memset(&bp->dev->stats, 0, sizeof(bp->dev->stats));
  1297. if (bp->stats_init) {
  1298. memset(&bp->net_stats_old, 0, sizeof(bp->net_stats_old));
  1299. memset(&bp->fw_stats_old, 0, sizeof(bp->fw_stats_old));
  1300. memset(&bp->eth_stats_old, 0, sizeof(bp->eth_stats_old));
  1301. memset(&bp->eth_stats, 0, sizeof(bp->eth_stats));
  1302. memset(&bp->func_stats, 0, sizeof(bp->func_stats));
  1303. /* Clean SP from previous statistics */
  1304. if (bp->func_stx) {
  1305. memset(bnx2x_sp(bp, func_stats), 0,
  1306. sizeof(struct host_func_stats));
  1307. bnx2x_func_stats_init(bp);
  1308. bnx2x_hw_stats_post(bp);
  1309. bnx2x_stats_comp(bp);
  1310. }
  1311. }
  1312. bp->stats_state = STATS_STATE_DISABLED;
  1313. if (bp->port.pmf && bp->port.port_stx)
  1314. bnx2x_port_stats_base_init(bp);
  1315. /* mark the end of statistics initializiation */
  1316. bp->stats_init = false;
  1317. }
  1318. void bnx2x_save_statistics(struct bnx2x *bp)
  1319. {
  1320. int i;
  1321. struct net_device_stats *nstats = &bp->dev->stats;
  1322. /* save queue statistics */
  1323. for_each_eth_queue(bp, i) {
  1324. struct bnx2x_fastpath *fp = &bp->fp[i];
  1325. struct bnx2x_eth_q_stats *qstats =
  1326. &bnx2x_fp_stats(bp, fp)->eth_q_stats;
  1327. struct bnx2x_eth_q_stats_old *qstats_old =
  1328. &bnx2x_fp_stats(bp, fp)->eth_q_stats_old;
  1329. UPDATE_QSTAT_OLD(total_unicast_bytes_received_hi);
  1330. UPDATE_QSTAT_OLD(total_unicast_bytes_received_lo);
  1331. UPDATE_QSTAT_OLD(total_broadcast_bytes_received_hi);
  1332. UPDATE_QSTAT_OLD(total_broadcast_bytes_received_lo);
  1333. UPDATE_QSTAT_OLD(total_multicast_bytes_received_hi);
  1334. UPDATE_QSTAT_OLD(total_multicast_bytes_received_lo);
  1335. UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_hi);
  1336. UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_lo);
  1337. UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_hi);
  1338. UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_lo);
  1339. UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_hi);
  1340. UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_lo);
  1341. UPDATE_QSTAT_OLD(total_tpa_bytes_hi);
  1342. UPDATE_QSTAT_OLD(total_tpa_bytes_lo);
  1343. }
  1344. /* save net_device_stats statistics */
  1345. bp->net_stats_old.rx_dropped = nstats->rx_dropped;
  1346. /* store port firmware statistics */
  1347. if (bp->port.pmf && IS_MF(bp)) {
  1348. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  1349. struct bnx2x_fw_port_stats_old *fwstats = &bp->fw_stats_old;
  1350. UPDATE_FW_STAT_OLD(mac_filter_discard);
  1351. UPDATE_FW_STAT_OLD(mf_tag_discard);
  1352. UPDATE_FW_STAT_OLD(brb_truncate_discard);
  1353. UPDATE_FW_STAT_OLD(mac_discard);
  1354. }
  1355. }
  1356. void bnx2x_afex_collect_stats(struct bnx2x *bp, void *void_afex_stats,
  1357. u32 stats_type)
  1358. {
  1359. int i;
  1360. struct afex_stats *afex_stats = (struct afex_stats *)void_afex_stats;
  1361. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  1362. struct per_queue_stats *fcoe_q_stats =
  1363. &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)];
  1364. struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
  1365. &fcoe_q_stats->tstorm_queue_statistics;
  1366. struct ustorm_per_queue_stats *fcoe_q_ustorm_stats =
  1367. &fcoe_q_stats->ustorm_queue_statistics;
  1368. struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
  1369. &fcoe_q_stats->xstorm_queue_statistics;
  1370. struct fcoe_statistics_params *fw_fcoe_stat =
  1371. &bp->fw_stats_data->fcoe;
  1372. memset(afex_stats, 0, sizeof(struct afex_stats));
  1373. for_each_eth_queue(bp, i) {
  1374. struct bnx2x_eth_q_stats *qstats = &bp->fp_stats[i].eth_q_stats;
  1375. ADD_64(afex_stats->rx_unicast_bytes_hi,
  1376. qstats->total_unicast_bytes_received_hi,
  1377. afex_stats->rx_unicast_bytes_lo,
  1378. qstats->total_unicast_bytes_received_lo);
  1379. ADD_64(afex_stats->rx_broadcast_bytes_hi,
  1380. qstats->total_broadcast_bytes_received_hi,
  1381. afex_stats->rx_broadcast_bytes_lo,
  1382. qstats->total_broadcast_bytes_received_lo);
  1383. ADD_64(afex_stats->rx_multicast_bytes_hi,
  1384. qstats->total_multicast_bytes_received_hi,
  1385. afex_stats->rx_multicast_bytes_lo,
  1386. qstats->total_multicast_bytes_received_lo);
  1387. ADD_64(afex_stats->rx_unicast_frames_hi,
  1388. qstats->total_unicast_packets_received_hi,
  1389. afex_stats->rx_unicast_frames_lo,
  1390. qstats->total_unicast_packets_received_lo);
  1391. ADD_64(afex_stats->rx_broadcast_frames_hi,
  1392. qstats->total_broadcast_packets_received_hi,
  1393. afex_stats->rx_broadcast_frames_lo,
  1394. qstats->total_broadcast_packets_received_lo);
  1395. ADD_64(afex_stats->rx_multicast_frames_hi,
  1396. qstats->total_multicast_packets_received_hi,
  1397. afex_stats->rx_multicast_frames_lo,
  1398. qstats->total_multicast_packets_received_lo);
  1399. /* sum to rx_frames_discarded all discraded
  1400. * packets due to size, ttl0 and checksum
  1401. */
  1402. ADD_64(afex_stats->rx_frames_discarded_hi,
  1403. qstats->total_packets_received_checksum_discarded_hi,
  1404. afex_stats->rx_frames_discarded_lo,
  1405. qstats->total_packets_received_checksum_discarded_lo);
  1406. ADD_64(afex_stats->rx_frames_discarded_hi,
  1407. qstats->total_packets_received_ttl0_discarded_hi,
  1408. afex_stats->rx_frames_discarded_lo,
  1409. qstats->total_packets_received_ttl0_discarded_lo);
  1410. ADD_64(afex_stats->rx_frames_discarded_hi,
  1411. qstats->etherstatsoverrsizepkts_hi,
  1412. afex_stats->rx_frames_discarded_lo,
  1413. qstats->etherstatsoverrsizepkts_lo);
  1414. ADD_64(afex_stats->rx_frames_dropped_hi,
  1415. qstats->no_buff_discard_hi,
  1416. afex_stats->rx_frames_dropped_lo,
  1417. qstats->no_buff_discard_lo);
  1418. ADD_64(afex_stats->tx_unicast_bytes_hi,
  1419. qstats->total_unicast_bytes_transmitted_hi,
  1420. afex_stats->tx_unicast_bytes_lo,
  1421. qstats->total_unicast_bytes_transmitted_lo);
  1422. ADD_64(afex_stats->tx_broadcast_bytes_hi,
  1423. qstats->total_broadcast_bytes_transmitted_hi,
  1424. afex_stats->tx_broadcast_bytes_lo,
  1425. qstats->total_broadcast_bytes_transmitted_lo);
  1426. ADD_64(afex_stats->tx_multicast_bytes_hi,
  1427. qstats->total_multicast_bytes_transmitted_hi,
  1428. afex_stats->tx_multicast_bytes_lo,
  1429. qstats->total_multicast_bytes_transmitted_lo);
  1430. ADD_64(afex_stats->tx_unicast_frames_hi,
  1431. qstats->total_unicast_packets_transmitted_hi,
  1432. afex_stats->tx_unicast_frames_lo,
  1433. qstats->total_unicast_packets_transmitted_lo);
  1434. ADD_64(afex_stats->tx_broadcast_frames_hi,
  1435. qstats->total_broadcast_packets_transmitted_hi,
  1436. afex_stats->tx_broadcast_frames_lo,
  1437. qstats->total_broadcast_packets_transmitted_lo);
  1438. ADD_64(afex_stats->tx_multicast_frames_hi,
  1439. qstats->total_multicast_packets_transmitted_hi,
  1440. afex_stats->tx_multicast_frames_lo,
  1441. qstats->total_multicast_packets_transmitted_lo);
  1442. ADD_64(afex_stats->tx_frames_dropped_hi,
  1443. qstats->total_transmitted_dropped_packets_error_hi,
  1444. afex_stats->tx_frames_dropped_lo,
  1445. qstats->total_transmitted_dropped_packets_error_lo);
  1446. }
  1447. /* now add FCoE statistics which are collected separately
  1448. * (both offloaded and non offloaded)
  1449. */
  1450. if (!NO_FCOE(bp)) {
  1451. ADD_64_LE(afex_stats->rx_unicast_bytes_hi,
  1452. LE32_0,
  1453. afex_stats->rx_unicast_bytes_lo,
  1454. fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
  1455. ADD_64_LE(afex_stats->rx_unicast_bytes_hi,
  1456. fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
  1457. afex_stats->rx_unicast_bytes_lo,
  1458. fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
  1459. ADD_64_LE(afex_stats->rx_broadcast_bytes_hi,
  1460. fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
  1461. afex_stats->rx_broadcast_bytes_lo,
  1462. fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
  1463. ADD_64_LE(afex_stats->rx_multicast_bytes_hi,
  1464. fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
  1465. afex_stats->rx_multicast_bytes_lo,
  1466. fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
  1467. ADD_64_LE(afex_stats->rx_unicast_frames_hi,
  1468. LE32_0,
  1469. afex_stats->rx_unicast_frames_lo,
  1470. fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
  1471. ADD_64_LE(afex_stats->rx_unicast_frames_hi,
  1472. LE32_0,
  1473. afex_stats->rx_unicast_frames_lo,
  1474. fcoe_q_tstorm_stats->rcv_ucast_pkts);
  1475. ADD_64_LE(afex_stats->rx_broadcast_frames_hi,
  1476. LE32_0,
  1477. afex_stats->rx_broadcast_frames_lo,
  1478. fcoe_q_tstorm_stats->rcv_bcast_pkts);
  1479. ADD_64_LE(afex_stats->rx_multicast_frames_hi,
  1480. LE32_0,
  1481. afex_stats->rx_multicast_frames_lo,
  1482. fcoe_q_tstorm_stats->rcv_ucast_pkts);
  1483. ADD_64_LE(afex_stats->rx_frames_discarded_hi,
  1484. LE32_0,
  1485. afex_stats->rx_frames_discarded_lo,
  1486. fcoe_q_tstorm_stats->checksum_discard);
  1487. ADD_64_LE(afex_stats->rx_frames_discarded_hi,
  1488. LE32_0,
  1489. afex_stats->rx_frames_discarded_lo,
  1490. fcoe_q_tstorm_stats->pkts_too_big_discard);
  1491. ADD_64_LE(afex_stats->rx_frames_discarded_hi,
  1492. LE32_0,
  1493. afex_stats->rx_frames_discarded_lo,
  1494. fcoe_q_tstorm_stats->ttl0_discard);
  1495. ADD_64_LE16(afex_stats->rx_frames_dropped_hi,
  1496. LE16_0,
  1497. afex_stats->rx_frames_dropped_lo,
  1498. fcoe_q_tstorm_stats->no_buff_discard);
  1499. ADD_64_LE(afex_stats->rx_frames_dropped_hi,
  1500. LE32_0,
  1501. afex_stats->rx_frames_dropped_lo,
  1502. fcoe_q_ustorm_stats->ucast_no_buff_pkts);
  1503. ADD_64_LE(afex_stats->rx_frames_dropped_hi,
  1504. LE32_0,
  1505. afex_stats->rx_frames_dropped_lo,
  1506. fcoe_q_ustorm_stats->mcast_no_buff_pkts);
  1507. ADD_64_LE(afex_stats->rx_frames_dropped_hi,
  1508. LE32_0,
  1509. afex_stats->rx_frames_dropped_lo,
  1510. fcoe_q_ustorm_stats->bcast_no_buff_pkts);
  1511. ADD_64_LE(afex_stats->rx_frames_dropped_hi,
  1512. LE32_0,
  1513. afex_stats->rx_frames_dropped_lo,
  1514. fw_fcoe_stat->rx_stat1.fcoe_rx_drop_pkt_cnt);
  1515. ADD_64_LE(afex_stats->rx_frames_dropped_hi,
  1516. LE32_0,
  1517. afex_stats->rx_frames_dropped_lo,
  1518. fw_fcoe_stat->rx_stat2.fcoe_rx_drop_pkt_cnt);
  1519. ADD_64_LE(afex_stats->tx_unicast_bytes_hi,
  1520. LE32_0,
  1521. afex_stats->tx_unicast_bytes_lo,
  1522. fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
  1523. ADD_64_LE(afex_stats->tx_unicast_bytes_hi,
  1524. fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
  1525. afex_stats->tx_unicast_bytes_lo,
  1526. fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
  1527. ADD_64_LE(afex_stats->tx_broadcast_bytes_hi,
  1528. fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
  1529. afex_stats->tx_broadcast_bytes_lo,
  1530. fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
  1531. ADD_64_LE(afex_stats->tx_multicast_bytes_hi,
  1532. fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
  1533. afex_stats->tx_multicast_bytes_lo,
  1534. fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
  1535. ADD_64_LE(afex_stats->tx_unicast_frames_hi,
  1536. LE32_0,
  1537. afex_stats->tx_unicast_frames_lo,
  1538. fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
  1539. ADD_64_LE(afex_stats->tx_unicast_frames_hi,
  1540. LE32_0,
  1541. afex_stats->tx_unicast_frames_lo,
  1542. fcoe_q_xstorm_stats->ucast_pkts_sent);
  1543. ADD_64_LE(afex_stats->tx_broadcast_frames_hi,
  1544. LE32_0,
  1545. afex_stats->tx_broadcast_frames_lo,
  1546. fcoe_q_xstorm_stats->bcast_pkts_sent);
  1547. ADD_64_LE(afex_stats->tx_multicast_frames_hi,
  1548. LE32_0,
  1549. afex_stats->tx_multicast_frames_lo,
  1550. fcoe_q_xstorm_stats->mcast_pkts_sent);
  1551. ADD_64_LE(afex_stats->tx_frames_dropped_hi,
  1552. LE32_0,
  1553. afex_stats->tx_frames_dropped_lo,
  1554. fcoe_q_xstorm_stats->error_drop_pkts);
  1555. }
  1556. /* if port stats are requested, add them to the PMF
  1557. * stats, as anyway they will be accumulated by the
  1558. * MCP before sent to the switch
  1559. */
  1560. if ((bp->port.pmf) && (stats_type == VICSTATST_UIF_INDEX)) {
  1561. ADD_64(afex_stats->rx_frames_dropped_hi,
  1562. 0,
  1563. afex_stats->rx_frames_dropped_lo,
  1564. estats->mac_filter_discard);
  1565. ADD_64(afex_stats->rx_frames_dropped_hi,
  1566. 0,
  1567. afex_stats->rx_frames_dropped_lo,
  1568. estats->brb_truncate_discard);
  1569. ADD_64(afex_stats->rx_frames_discarded_hi,
  1570. 0,
  1571. afex_stats->rx_frames_discarded_lo,
  1572. estats->mac_discard);
  1573. }
  1574. }