ints-priority.c 40 KB

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  1. /*
  2. * Set up the interrupt priorities
  3. *
  4. * Copyright 2004-2009 Analog Devices Inc.
  5. * 2003 Bas Vermeulen <bas@buyways.nl>
  6. * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
  7. * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
  8. * 1999 D. Jeff Dionne <jeff@uclinux.org>
  9. * 1996 Roman Zippel
  10. *
  11. * Licensed under the GPL-2
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel_stat.h>
  15. #include <linux/seq_file.h>
  16. #include <linux/irq.h>
  17. #include <linux/sched.h>
  18. #include <linux/syscore_ops.h>
  19. #include <asm/delay.h>
  20. #ifdef CONFIG_IPIPE
  21. #include <linux/ipipe.h>
  22. #endif
  23. #include <asm/traps.h>
  24. #include <asm/blackfin.h>
  25. #include <asm/gpio.h>
  26. #include <asm/irq_handler.h>
  27. #include <asm/dpmc.h>
  28. #include <asm/traps.h>
  29. #ifndef SEC_GCTL
  30. # define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  31. #else
  32. # define SIC_SYSIRQ(irq) ((irq) - IVG15)
  33. #endif
  34. /*
  35. * NOTES:
  36. * - we have separated the physical Hardware interrupt from the
  37. * levels that the LINUX kernel sees (see the description in irq.h)
  38. * -
  39. */
  40. #ifndef CONFIG_SMP
  41. /* Initialize this to an actual value to force it into the .data
  42. * section so that we know it is properly initialized at entry into
  43. * the kernel but before bss is initialized to zero (which is where
  44. * it would live otherwise). The 0x1f magic represents the IRQs we
  45. * cannot actually mask out in hardware.
  46. */
  47. unsigned long bfin_irq_flags = 0x1f;
  48. EXPORT_SYMBOL(bfin_irq_flags);
  49. #endif
  50. #ifdef CONFIG_PM
  51. unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
  52. unsigned vr_wakeup;
  53. #endif
  54. #ifndef SEC_GCTL
  55. static struct ivgx {
  56. /* irq number for request_irq, available in mach-bf5xx/irq.h */
  57. unsigned int irqno;
  58. /* corresponding bit in the SIC_ISR register */
  59. unsigned int isrflag;
  60. } ivg_table[NR_PERI_INTS];
  61. static struct ivg_slice {
  62. /* position of first irq in ivg_table for given ivg */
  63. struct ivgx *ifirst;
  64. struct ivgx *istop;
  65. } ivg7_13[IVG13 - IVG7 + 1];
  66. /*
  67. * Search SIC_IAR and fill tables with the irqvalues
  68. * and their positions in the SIC_ISR register.
  69. */
  70. static void __init search_IAR(void)
  71. {
  72. unsigned ivg, irq_pos = 0;
  73. for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  74. int irqN;
  75. ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  76. for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
  77. int irqn;
  78. u32 iar =
  79. bfin_read32((unsigned long *)SIC_IAR0 +
  80. #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
  81. defined(CONFIG_BF538) || defined(CONFIG_BF539)
  82. ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
  83. #else
  84. (irqN >> 3)
  85. #endif
  86. );
  87. for (irqn = irqN; irqn < irqN + 4; ++irqn) {
  88. int iar_shift = (irqn & 7) * 4;
  89. if (ivg == (0xf & (iar >> iar_shift))) {
  90. ivg_table[irq_pos].irqno = IVG7 + irqn;
  91. ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
  92. ivg7_13[ivg].istop++;
  93. irq_pos++;
  94. }
  95. }
  96. }
  97. }
  98. }
  99. #endif
  100. /*
  101. * This is for core internal IRQs
  102. */
  103. void bfin_ack_noop(struct irq_data *d)
  104. {
  105. /* Dummy function. */
  106. }
  107. static void bfin_core_mask_irq(struct irq_data *d)
  108. {
  109. bfin_irq_flags &= ~(1 << d->irq);
  110. if (!hard_irqs_disabled())
  111. hard_local_irq_enable();
  112. }
  113. static void bfin_core_unmask_irq(struct irq_data *d)
  114. {
  115. bfin_irq_flags |= 1 << d->irq;
  116. /*
  117. * If interrupts are enabled, IMASK must contain the same value
  118. * as bfin_irq_flags. Make sure that invariant holds. If interrupts
  119. * are currently disabled we need not do anything; one of the
  120. * callers will take care of setting IMASK to the proper value
  121. * when reenabling interrupts.
  122. * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
  123. * what we need.
  124. */
  125. if (!hard_irqs_disabled())
  126. hard_local_irq_enable();
  127. return;
  128. }
  129. void bfin_internal_mask_irq(unsigned int irq)
  130. {
  131. unsigned long flags = hard_local_irq_save();
  132. #ifndef SEC_GCTL
  133. #ifdef SIC_IMASK0
  134. unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
  135. unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
  136. bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
  137. ~(1 << mask_bit));
  138. # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
  139. bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
  140. ~(1 << mask_bit));
  141. # endif
  142. #else
  143. bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
  144. ~(1 << SIC_SYSIRQ(irq)));
  145. #endif /* end of SIC_IMASK0 */
  146. #endif
  147. hard_local_irq_restore(flags);
  148. }
  149. static void bfin_internal_mask_irq_chip(struct irq_data *d)
  150. {
  151. bfin_internal_mask_irq(d->irq);
  152. }
  153. #ifdef CONFIG_SMP
  154. void bfin_internal_unmask_irq_affinity(unsigned int irq,
  155. const struct cpumask *affinity)
  156. #else
  157. void bfin_internal_unmask_irq(unsigned int irq)
  158. #endif
  159. {
  160. unsigned long flags = hard_local_irq_save();
  161. #ifndef SEC_GCTL
  162. #ifdef SIC_IMASK0
  163. unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
  164. unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
  165. # ifdef CONFIG_SMP
  166. if (cpumask_test_cpu(0, affinity))
  167. # endif
  168. bfin_write_SIC_IMASK(mask_bank,
  169. bfin_read_SIC_IMASK(mask_bank) |
  170. (1 << mask_bit));
  171. # ifdef CONFIG_SMP
  172. if (cpumask_test_cpu(1, affinity))
  173. bfin_write_SICB_IMASK(mask_bank,
  174. bfin_read_SICB_IMASK(mask_bank) |
  175. (1 << mask_bit));
  176. # endif
  177. #else
  178. bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
  179. (1 << SIC_SYSIRQ(irq)));
  180. #endif
  181. #endif
  182. hard_local_irq_restore(flags);
  183. }
  184. #ifdef SEC_GCTL
  185. static void bfin_sec_preflow_handler(struct irq_data *d)
  186. {
  187. unsigned long flags = hard_local_irq_save();
  188. unsigned int sid = SIC_SYSIRQ(d->irq);
  189. bfin_write_SEC_SCI(0, SEC_CSID, sid);
  190. hard_local_irq_restore(flags);
  191. }
  192. static void bfin_sec_mask_ack_irq(struct irq_data *d)
  193. {
  194. unsigned long flags = hard_local_irq_save();
  195. unsigned int sid = SIC_SYSIRQ(d->irq);
  196. bfin_write_SEC_SCI(0, SEC_CSID, sid);
  197. hard_local_irq_restore(flags);
  198. }
  199. static void bfin_sec_unmask_irq(struct irq_data *d)
  200. {
  201. unsigned long flags = hard_local_irq_save();
  202. unsigned int sid = SIC_SYSIRQ(d->irq);
  203. bfin_write32(SEC_END, sid);
  204. hard_local_irq_restore(flags);
  205. }
  206. static void bfin_sec_enable_ssi(unsigned int sid)
  207. {
  208. unsigned long flags = hard_local_irq_save();
  209. uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
  210. reg_sctl |= SEC_SCTL_SRC_EN;
  211. bfin_write_SEC_SCTL(sid, reg_sctl);
  212. hard_local_irq_restore(flags);
  213. }
  214. static void bfin_sec_disable_ssi(unsigned int sid)
  215. {
  216. unsigned long flags = hard_local_irq_save();
  217. uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
  218. reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
  219. bfin_write_SEC_SCTL(sid, reg_sctl);
  220. hard_local_irq_restore(flags);
  221. }
  222. static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
  223. {
  224. unsigned long flags = hard_local_irq_save();
  225. uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
  226. reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
  227. bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
  228. hard_local_irq_restore(flags);
  229. }
  230. static void bfin_sec_enable_sci(unsigned int sid)
  231. {
  232. unsigned long flags = hard_local_irq_save();
  233. uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
  234. if (sid == SIC_SYSIRQ(IRQ_WATCH0))
  235. reg_sctl |= SEC_SCTL_FAULT_EN;
  236. else
  237. reg_sctl |= SEC_SCTL_INT_EN;
  238. bfin_write_SEC_SCTL(sid, reg_sctl);
  239. hard_local_irq_restore(flags);
  240. }
  241. static void bfin_sec_disable_sci(unsigned int sid)
  242. {
  243. unsigned long flags = hard_local_irq_save();
  244. uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
  245. reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
  246. bfin_write_SEC_SCTL(sid, reg_sctl);
  247. hard_local_irq_restore(flags);
  248. }
  249. static void bfin_sec_enable(struct irq_data *d)
  250. {
  251. unsigned long flags = hard_local_irq_save();
  252. unsigned int sid = SIC_SYSIRQ(d->irq);
  253. bfin_sec_enable_sci(sid);
  254. bfin_sec_enable_ssi(sid);
  255. hard_local_irq_restore(flags);
  256. }
  257. static void bfin_sec_disable(struct irq_data *d)
  258. {
  259. unsigned long flags = hard_local_irq_save();
  260. unsigned int sid = SIC_SYSIRQ(d->irq);
  261. bfin_sec_disable_sci(sid);
  262. bfin_sec_disable_ssi(sid);
  263. hard_local_irq_restore(flags);
  264. }
  265. static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
  266. {
  267. unsigned long flags = hard_local_irq_save();
  268. uint32_t reg_sctl;
  269. int i;
  270. bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
  271. for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
  272. reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
  273. reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
  274. bfin_write_SEC_SCTL(i, reg_sctl);
  275. }
  276. hard_local_irq_restore(flags);
  277. }
  278. void bfin_sec_raise_irq(unsigned int sid)
  279. {
  280. unsigned long flags = hard_local_irq_save();
  281. bfin_write32(SEC_RAISE, sid);
  282. hard_local_irq_restore(flags);
  283. }
  284. static void init_software_driven_irq(void)
  285. {
  286. bfin_sec_set_ssi_coreid(34, 0);
  287. bfin_sec_set_ssi_coreid(35, 1);
  288. bfin_sec_set_ssi_coreid(36, 0);
  289. bfin_sec_set_ssi_coreid(37, 1);
  290. }
  291. void bfin_sec_resume(void)
  292. {
  293. bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
  294. udelay(100);
  295. bfin_write_SEC_GCTL(SEC_GCTL_EN);
  296. bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
  297. }
  298. void handle_sec_sfi_fault(uint32_t gstat)
  299. {
  300. }
  301. void handle_sec_sci_fault(uint32_t gstat)
  302. {
  303. uint32_t core_id;
  304. uint32_t cstat;
  305. core_id = gstat & SEC_GSTAT_SCI;
  306. cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
  307. if (cstat & SEC_CSTAT_ERR) {
  308. switch (cstat & SEC_CSTAT_ERRC) {
  309. case SEC_CSTAT_ACKERR:
  310. printk(KERN_DEBUG "sec ack err\n");
  311. break;
  312. default:
  313. printk(KERN_DEBUG "sec sci unknow err\n");
  314. }
  315. }
  316. }
  317. void handle_sec_ssi_fault(uint32_t gstat)
  318. {
  319. uint32_t sid;
  320. uint32_t sstat;
  321. sid = gstat & SEC_GSTAT_SID;
  322. sstat = bfin_read_SEC_SSTAT(sid);
  323. }
  324. void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
  325. {
  326. uint32_t sec_gstat;
  327. raw_spin_lock(&desc->lock);
  328. sec_gstat = bfin_read32(SEC_GSTAT);
  329. if (sec_gstat & SEC_GSTAT_ERR) {
  330. switch (sec_gstat & SEC_GSTAT_ERRC) {
  331. case 0:
  332. handle_sec_sfi_fault(sec_gstat);
  333. break;
  334. case SEC_GSTAT_SCIERR:
  335. handle_sec_sci_fault(sec_gstat);
  336. break;
  337. case SEC_GSTAT_SSIERR:
  338. handle_sec_ssi_fault(sec_gstat);
  339. break;
  340. }
  341. }
  342. raw_spin_unlock(&desc->lock);
  343. }
  344. void handle_core_fault(unsigned int irq, struct irq_desc *desc)
  345. {
  346. struct pt_regs *fp = get_irq_regs();
  347. raw_spin_lock(&desc->lock);
  348. switch (irq) {
  349. case IRQ_C0_DBL_FAULT:
  350. double_fault_c(fp);
  351. break;
  352. case IRQ_C0_HW_ERR:
  353. dump_bfin_process(fp);
  354. dump_bfin_mem(fp);
  355. show_regs(fp);
  356. printk(KERN_NOTICE "Kernel Stack\n");
  357. show_stack(current, NULL);
  358. print_modules();
  359. panic("Kernel core hardware error");
  360. break;
  361. case IRQ_C0_NMI_L1_PARITY_ERR:
  362. panic("NMI occurs unexpectedly");
  363. break;
  364. default:
  365. panic("Core 1 fault occurs unexpectedly");
  366. }
  367. raw_spin_unlock(&desc->lock);
  368. }
  369. #endif
  370. #ifdef CONFIG_SMP
  371. static void bfin_internal_unmask_irq_chip(struct irq_data *d)
  372. {
  373. bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
  374. }
  375. static int bfin_internal_set_affinity(struct irq_data *d,
  376. const struct cpumask *mask, bool force)
  377. {
  378. bfin_internal_mask_irq(d->irq);
  379. bfin_internal_unmask_irq_affinity(d->irq, mask);
  380. return 0;
  381. }
  382. #else
  383. static void bfin_internal_unmask_irq_chip(struct irq_data *d)
  384. {
  385. bfin_internal_unmask_irq(d->irq);
  386. }
  387. #endif
  388. #if defined(CONFIG_PM) && !defined(SEC_GCTL)
  389. int bfin_internal_set_wake(unsigned int irq, unsigned int state)
  390. {
  391. u32 bank, bit, wakeup = 0;
  392. unsigned long flags;
  393. bank = SIC_SYSIRQ(irq) / 32;
  394. bit = SIC_SYSIRQ(irq) % 32;
  395. switch (irq) {
  396. #ifdef IRQ_RTC
  397. case IRQ_RTC:
  398. wakeup |= WAKE;
  399. break;
  400. #endif
  401. #ifdef IRQ_CAN0_RX
  402. case IRQ_CAN0_RX:
  403. wakeup |= CANWE;
  404. break;
  405. #endif
  406. #ifdef IRQ_CAN1_RX
  407. case IRQ_CAN1_RX:
  408. wakeup |= CANWE;
  409. break;
  410. #endif
  411. #ifdef IRQ_USB_INT0
  412. case IRQ_USB_INT0:
  413. wakeup |= USBWE;
  414. break;
  415. #endif
  416. #ifdef CONFIG_BF54x
  417. case IRQ_CNT:
  418. wakeup |= ROTWE;
  419. break;
  420. #endif
  421. default:
  422. break;
  423. }
  424. flags = hard_local_irq_save();
  425. if (state) {
  426. bfin_sic_iwr[bank] |= (1 << bit);
  427. vr_wakeup |= wakeup;
  428. } else {
  429. bfin_sic_iwr[bank] &= ~(1 << bit);
  430. vr_wakeup &= ~wakeup;
  431. }
  432. hard_local_irq_restore(flags);
  433. return 0;
  434. }
  435. static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
  436. {
  437. return bfin_internal_set_wake(d->irq, state);
  438. }
  439. #else
  440. inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
  441. {
  442. return 0;
  443. }
  444. # define bfin_internal_set_wake_chip NULL
  445. #endif
  446. static struct irq_chip bfin_core_irqchip = {
  447. .name = "CORE",
  448. .irq_mask = bfin_core_mask_irq,
  449. .irq_unmask = bfin_core_unmask_irq,
  450. };
  451. static struct irq_chip bfin_internal_irqchip = {
  452. .name = "INTN",
  453. .irq_mask = bfin_internal_mask_irq_chip,
  454. .irq_unmask = bfin_internal_unmask_irq_chip,
  455. .irq_disable = bfin_internal_mask_irq_chip,
  456. .irq_enable = bfin_internal_unmask_irq_chip,
  457. #ifdef CONFIG_SMP
  458. .irq_set_affinity = bfin_internal_set_affinity,
  459. #endif
  460. .irq_set_wake = bfin_internal_set_wake_chip,
  461. };
  462. #ifdef SEC_GCTL
  463. static struct irq_chip bfin_sec_irqchip = {
  464. .name = "SEC",
  465. .irq_mask_ack = bfin_sec_mask_ack_irq,
  466. .irq_mask = bfin_sec_mask_ack_irq,
  467. .irq_unmask = bfin_sec_unmask_irq,
  468. .irq_eoi = bfin_sec_unmask_irq,
  469. .irq_disable = bfin_sec_disable,
  470. .irq_enable = bfin_sec_enable,
  471. };
  472. #endif
  473. void bfin_handle_irq(unsigned irq)
  474. {
  475. #ifdef CONFIG_IPIPE
  476. struct pt_regs regs; /* Contents not used. */
  477. ipipe_trace_irq_entry(irq);
  478. __ipipe_handle_irq(irq, &regs);
  479. ipipe_trace_irq_exit(irq);
  480. #else /* !CONFIG_IPIPE */
  481. generic_handle_irq(irq);
  482. #endif /* !CONFIG_IPIPE */
  483. }
  484. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  485. static int mac_stat_int_mask;
  486. static void bfin_mac_status_ack_irq(unsigned int irq)
  487. {
  488. switch (irq) {
  489. case IRQ_MAC_MMCINT:
  490. bfin_write_EMAC_MMC_TIRQS(
  491. bfin_read_EMAC_MMC_TIRQE() &
  492. bfin_read_EMAC_MMC_TIRQS());
  493. bfin_write_EMAC_MMC_RIRQS(
  494. bfin_read_EMAC_MMC_RIRQE() &
  495. bfin_read_EMAC_MMC_RIRQS());
  496. break;
  497. case IRQ_MAC_RXFSINT:
  498. bfin_write_EMAC_RX_STKY(
  499. bfin_read_EMAC_RX_IRQE() &
  500. bfin_read_EMAC_RX_STKY());
  501. break;
  502. case IRQ_MAC_TXFSINT:
  503. bfin_write_EMAC_TX_STKY(
  504. bfin_read_EMAC_TX_IRQE() &
  505. bfin_read_EMAC_TX_STKY());
  506. break;
  507. case IRQ_MAC_WAKEDET:
  508. bfin_write_EMAC_WKUP_CTL(
  509. bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
  510. break;
  511. default:
  512. /* These bits are W1C */
  513. bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
  514. break;
  515. }
  516. }
  517. static void bfin_mac_status_mask_irq(struct irq_data *d)
  518. {
  519. unsigned int irq = d->irq;
  520. mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
  521. #ifdef BF537_FAMILY
  522. switch (irq) {
  523. case IRQ_MAC_PHYINT:
  524. bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
  525. break;
  526. default:
  527. break;
  528. }
  529. #else
  530. if (!mac_stat_int_mask)
  531. bfin_internal_mask_irq(IRQ_MAC_ERROR);
  532. #endif
  533. bfin_mac_status_ack_irq(irq);
  534. }
  535. static void bfin_mac_status_unmask_irq(struct irq_data *d)
  536. {
  537. unsigned int irq = d->irq;
  538. #ifdef BF537_FAMILY
  539. switch (irq) {
  540. case IRQ_MAC_PHYINT:
  541. bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
  542. break;
  543. default:
  544. break;
  545. }
  546. #else
  547. if (!mac_stat_int_mask)
  548. bfin_internal_unmask_irq(IRQ_MAC_ERROR);
  549. #endif
  550. mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
  551. }
  552. #ifdef CONFIG_PM
  553. int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
  554. {
  555. #ifdef BF537_FAMILY
  556. return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
  557. #else
  558. return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
  559. #endif
  560. }
  561. #else
  562. # define bfin_mac_status_set_wake NULL
  563. #endif
  564. static struct irq_chip bfin_mac_status_irqchip = {
  565. .name = "MACST",
  566. .irq_mask = bfin_mac_status_mask_irq,
  567. .irq_unmask = bfin_mac_status_unmask_irq,
  568. .irq_set_wake = bfin_mac_status_set_wake,
  569. };
  570. void bfin_demux_mac_status_irq(unsigned int int_err_irq,
  571. struct irq_desc *inta_desc)
  572. {
  573. int i, irq = 0;
  574. u32 status = bfin_read_EMAC_SYSTAT();
  575. for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
  576. if (status & (1L << i)) {
  577. irq = IRQ_MAC_PHYINT + i;
  578. break;
  579. }
  580. if (irq) {
  581. if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
  582. bfin_handle_irq(irq);
  583. } else {
  584. bfin_mac_status_ack_irq(irq);
  585. pr_debug("IRQ %d:"
  586. " MASKED MAC ERROR INTERRUPT ASSERTED\n",
  587. irq);
  588. }
  589. } else
  590. printk(KERN_ERR
  591. "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
  592. " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
  593. "(EMAC_SYSTAT=0x%X)\n",
  594. __func__, __FILE__, __LINE__, status);
  595. }
  596. #endif
  597. static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
  598. {
  599. #ifdef CONFIG_IPIPE
  600. handle = handle_level_irq;
  601. #endif
  602. __irq_set_handler_locked(irq, handle);
  603. }
  604. static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
  605. extern void bfin_gpio_irq_prepare(unsigned gpio);
  606. #if !BFIN_GPIO_PINT
  607. static void bfin_gpio_ack_irq(struct irq_data *d)
  608. {
  609. /* AFAIK ack_irq in case mask_ack is provided
  610. * get's only called for edge sense irqs
  611. */
  612. set_gpio_data(irq_to_gpio(d->irq), 0);
  613. }
  614. static void bfin_gpio_mask_ack_irq(struct irq_data *d)
  615. {
  616. unsigned int irq = d->irq;
  617. u32 gpionr = irq_to_gpio(irq);
  618. if (!irqd_is_level_type(d))
  619. set_gpio_data(gpionr, 0);
  620. set_gpio_maska(gpionr, 0);
  621. }
  622. static void bfin_gpio_mask_irq(struct irq_data *d)
  623. {
  624. set_gpio_maska(irq_to_gpio(d->irq), 0);
  625. }
  626. static void bfin_gpio_unmask_irq(struct irq_data *d)
  627. {
  628. set_gpio_maska(irq_to_gpio(d->irq), 1);
  629. }
  630. static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
  631. {
  632. u32 gpionr = irq_to_gpio(d->irq);
  633. if (__test_and_set_bit(gpionr, gpio_enabled))
  634. bfin_gpio_irq_prepare(gpionr);
  635. bfin_gpio_unmask_irq(d);
  636. return 0;
  637. }
  638. static void bfin_gpio_irq_shutdown(struct irq_data *d)
  639. {
  640. u32 gpionr = irq_to_gpio(d->irq);
  641. bfin_gpio_mask_irq(d);
  642. __clear_bit(gpionr, gpio_enabled);
  643. bfin_gpio_irq_free(gpionr);
  644. }
  645. static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
  646. {
  647. unsigned int irq = d->irq;
  648. int ret;
  649. char buf[16];
  650. u32 gpionr = irq_to_gpio(irq);
  651. if (type == IRQ_TYPE_PROBE) {
  652. /* only probe unenabled GPIO interrupt lines */
  653. if (test_bit(gpionr, gpio_enabled))
  654. return 0;
  655. type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  656. }
  657. if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
  658. IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
  659. snprintf(buf, 16, "gpio-irq%d", irq);
  660. ret = bfin_gpio_irq_request(gpionr, buf);
  661. if (ret)
  662. return ret;
  663. if (__test_and_set_bit(gpionr, gpio_enabled))
  664. bfin_gpio_irq_prepare(gpionr);
  665. } else {
  666. __clear_bit(gpionr, gpio_enabled);
  667. return 0;
  668. }
  669. set_gpio_inen(gpionr, 0);
  670. set_gpio_dir(gpionr, 0);
  671. if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
  672. == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
  673. set_gpio_both(gpionr, 1);
  674. else
  675. set_gpio_both(gpionr, 0);
  676. if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
  677. set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
  678. else
  679. set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
  680. if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
  681. set_gpio_edge(gpionr, 1);
  682. set_gpio_inen(gpionr, 1);
  683. set_gpio_data(gpionr, 0);
  684. } else {
  685. set_gpio_edge(gpionr, 0);
  686. set_gpio_inen(gpionr, 1);
  687. }
  688. if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
  689. bfin_set_irq_handler(irq, handle_edge_irq);
  690. else
  691. bfin_set_irq_handler(irq, handle_level_irq);
  692. return 0;
  693. }
  694. #ifdef CONFIG_PM
  695. static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
  696. {
  697. return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
  698. }
  699. #else
  700. # define bfin_gpio_set_wake NULL
  701. #endif
  702. static void bfin_demux_gpio_block(unsigned int irq)
  703. {
  704. unsigned int gpio, mask;
  705. gpio = irq_to_gpio(irq);
  706. mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
  707. while (mask) {
  708. if (mask & 1)
  709. bfin_handle_irq(irq);
  710. irq++;
  711. mask >>= 1;
  712. }
  713. }
  714. void bfin_demux_gpio_irq(unsigned int inta_irq,
  715. struct irq_desc *desc)
  716. {
  717. unsigned int irq;
  718. switch (inta_irq) {
  719. #if defined(BF537_FAMILY)
  720. case IRQ_PF_INTA_PG_INTA:
  721. bfin_demux_gpio_block(IRQ_PF0);
  722. irq = IRQ_PG0;
  723. break;
  724. case IRQ_PH_INTA_MAC_RX:
  725. irq = IRQ_PH0;
  726. break;
  727. #elif defined(BF533_FAMILY)
  728. case IRQ_PROG_INTA:
  729. irq = IRQ_PF0;
  730. break;
  731. #elif defined(BF538_FAMILY)
  732. case IRQ_PORTF_INTA:
  733. irq = IRQ_PF0;
  734. break;
  735. #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
  736. case IRQ_PORTF_INTA:
  737. irq = IRQ_PF0;
  738. break;
  739. case IRQ_PORTG_INTA:
  740. irq = IRQ_PG0;
  741. break;
  742. case IRQ_PORTH_INTA:
  743. irq = IRQ_PH0;
  744. break;
  745. #elif defined(CONFIG_BF561)
  746. case IRQ_PROG0_INTA:
  747. irq = IRQ_PF0;
  748. break;
  749. case IRQ_PROG1_INTA:
  750. irq = IRQ_PF16;
  751. break;
  752. case IRQ_PROG2_INTA:
  753. irq = IRQ_PF32;
  754. break;
  755. #endif
  756. default:
  757. BUG();
  758. return;
  759. }
  760. bfin_demux_gpio_block(irq);
  761. }
  762. #else
  763. #define NR_PINT_BITS 32
  764. #define IRQ_NOT_AVAIL 0xFF
  765. #define PINT_2_BANK(x) ((x) >> 5)
  766. #define PINT_2_BIT(x) ((x) & 0x1F)
  767. #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
  768. static unsigned char irq2pint_lut[NR_PINTS];
  769. static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
  770. static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
  771. (struct bfin_pint_regs *)PINT0_MASK_SET,
  772. (struct bfin_pint_regs *)PINT1_MASK_SET,
  773. (struct bfin_pint_regs *)PINT2_MASK_SET,
  774. (struct bfin_pint_regs *)PINT3_MASK_SET,
  775. #ifdef CONFIG_BF60x
  776. (struct bfin_pint_regs *)PINT4_MASK_SET,
  777. (struct bfin_pint_regs *)PINT5_MASK_SET,
  778. #endif
  779. };
  780. inline unsigned int get_irq_base(u32 bank, u8 bmap)
  781. {
  782. unsigned int irq_base;
  783. #ifndef CONFIG_BF60x
  784. if (bank < 2) { /*PA-PB */
  785. irq_base = IRQ_PA0 + bmap * 16;
  786. } else { /*PC-PJ */
  787. irq_base = IRQ_PC0 + bmap * 16;
  788. }
  789. #else
  790. irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
  791. #endif
  792. return irq_base;
  793. }
  794. /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
  795. void init_pint_lut(void)
  796. {
  797. u16 bank, bit, irq_base, bit_pos;
  798. u32 pint_assign;
  799. u8 bmap;
  800. memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
  801. for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
  802. pint_assign = pint[bank]->assign;
  803. for (bit = 0; bit < NR_PINT_BITS; bit++) {
  804. bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
  805. irq_base = get_irq_base(bank, bmap);
  806. irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
  807. bit_pos = bit + bank * NR_PINT_BITS;
  808. pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
  809. irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
  810. }
  811. }
  812. }
  813. static void bfin_gpio_ack_irq(struct irq_data *d)
  814. {
  815. u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
  816. u32 pintbit = PINT_BIT(pint_val);
  817. u32 bank = PINT_2_BANK(pint_val);
  818. if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
  819. if (pint[bank]->invert_set & pintbit)
  820. pint[bank]->invert_clear = pintbit;
  821. else
  822. pint[bank]->invert_set = pintbit;
  823. }
  824. pint[bank]->request = pintbit;
  825. }
  826. static void bfin_gpio_mask_ack_irq(struct irq_data *d)
  827. {
  828. u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
  829. u32 pintbit = PINT_BIT(pint_val);
  830. u32 bank = PINT_2_BANK(pint_val);
  831. if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
  832. if (pint[bank]->invert_set & pintbit)
  833. pint[bank]->invert_clear = pintbit;
  834. else
  835. pint[bank]->invert_set = pintbit;
  836. }
  837. pint[bank]->request = pintbit;
  838. pint[bank]->mask_clear = pintbit;
  839. }
  840. static void bfin_gpio_mask_irq(struct irq_data *d)
  841. {
  842. u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
  843. pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
  844. }
  845. static void bfin_gpio_unmask_irq(struct irq_data *d)
  846. {
  847. u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
  848. u32 pintbit = PINT_BIT(pint_val);
  849. u32 bank = PINT_2_BANK(pint_val);
  850. pint[bank]->mask_set = pintbit;
  851. }
  852. static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
  853. {
  854. unsigned int irq = d->irq;
  855. u32 gpionr = irq_to_gpio(irq);
  856. u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
  857. if (pint_val == IRQ_NOT_AVAIL) {
  858. printk(KERN_ERR
  859. "GPIO IRQ %d :Not in PINT Assign table "
  860. "Reconfigure Interrupt to Port Assignemt\n", irq);
  861. return -ENODEV;
  862. }
  863. if (__test_and_set_bit(gpionr, gpio_enabled))
  864. bfin_gpio_irq_prepare(gpionr);
  865. bfin_gpio_unmask_irq(d);
  866. return 0;
  867. }
  868. static void bfin_gpio_irq_shutdown(struct irq_data *d)
  869. {
  870. u32 gpionr = irq_to_gpio(d->irq);
  871. bfin_gpio_mask_irq(d);
  872. __clear_bit(gpionr, gpio_enabled);
  873. bfin_gpio_irq_free(gpionr);
  874. }
  875. static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
  876. {
  877. unsigned int irq = d->irq;
  878. int ret;
  879. char buf[16];
  880. u32 gpionr = irq_to_gpio(irq);
  881. u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
  882. u32 pintbit = PINT_BIT(pint_val);
  883. u32 bank = PINT_2_BANK(pint_val);
  884. if (pint_val == IRQ_NOT_AVAIL)
  885. return -ENODEV;
  886. if (type == IRQ_TYPE_PROBE) {
  887. /* only probe unenabled GPIO interrupt lines */
  888. if (test_bit(gpionr, gpio_enabled))
  889. return 0;
  890. type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  891. }
  892. if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
  893. IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
  894. snprintf(buf, 16, "gpio-irq%d", irq);
  895. ret = bfin_gpio_irq_request(gpionr, buf);
  896. if (ret)
  897. return ret;
  898. if (__test_and_set_bit(gpionr, gpio_enabled))
  899. bfin_gpio_irq_prepare(gpionr);
  900. } else {
  901. __clear_bit(gpionr, gpio_enabled);
  902. return 0;
  903. }
  904. if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
  905. pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
  906. else
  907. pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
  908. if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
  909. == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
  910. if (gpio_get_value(gpionr))
  911. pint[bank]->invert_set = pintbit;
  912. else
  913. pint[bank]->invert_clear = pintbit;
  914. }
  915. if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
  916. pint[bank]->edge_set = pintbit;
  917. bfin_set_irq_handler(irq, handle_edge_irq);
  918. } else {
  919. pint[bank]->edge_clear = pintbit;
  920. bfin_set_irq_handler(irq, handle_level_irq);
  921. }
  922. return 0;
  923. }
  924. #ifdef CONFIG_PM
  925. static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
  926. static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
  927. static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
  928. {
  929. u32 pint_irq;
  930. u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
  931. u32 bank = PINT_2_BANK(pint_val);
  932. switch (bank) {
  933. case 0:
  934. pint_irq = IRQ_PINT0;
  935. break;
  936. case 2:
  937. pint_irq = IRQ_PINT2;
  938. break;
  939. case 3:
  940. pint_irq = IRQ_PINT3;
  941. break;
  942. case 1:
  943. pint_irq = IRQ_PINT1;
  944. break;
  945. #ifdef CONFIG_BF60x
  946. case 4:
  947. pint_irq = IRQ_PINT4;
  948. break;
  949. case 5:
  950. pint_irq = IRQ_PINT5;
  951. break;
  952. #endif
  953. default:
  954. return -EINVAL;
  955. }
  956. bfin_internal_set_wake(pint_irq, state);
  957. return 0;
  958. }
  959. void bfin_pint_suspend(void)
  960. {
  961. u32 bank;
  962. for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
  963. save_pint_reg[bank].mask_set = pint[bank]->mask_set;
  964. save_pint_reg[bank].assign = pint[bank]->assign;
  965. save_pint_reg[bank].edge_set = pint[bank]->edge_set;
  966. save_pint_reg[bank].invert_set = pint[bank]->invert_set;
  967. }
  968. }
  969. void bfin_pint_resume(void)
  970. {
  971. u32 bank;
  972. for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
  973. pint[bank]->mask_set = save_pint_reg[bank].mask_set;
  974. pint[bank]->assign = save_pint_reg[bank].assign;
  975. pint[bank]->edge_set = save_pint_reg[bank].edge_set;
  976. pint[bank]->invert_set = save_pint_reg[bank].invert_set;
  977. }
  978. }
  979. #ifdef SEC_GCTL
  980. static int sec_suspend(void)
  981. {
  982. u32 bank;
  983. for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
  984. save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0));
  985. return 0;
  986. }
  987. static void sec_resume(void)
  988. {
  989. u32 bank;
  990. bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
  991. udelay(100);
  992. bfin_write_SEC_GCTL(SEC_GCTL_EN);
  993. bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
  994. for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
  995. bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
  996. }
  997. static struct syscore_ops sec_pm_syscore_ops = {
  998. .suspend = sec_suspend,
  999. .resume = sec_resume,
  1000. };
  1001. #endif
  1002. #else
  1003. # define bfin_gpio_set_wake NULL
  1004. #endif
  1005. void bfin_demux_gpio_irq(unsigned int inta_irq,
  1006. struct irq_desc *desc)
  1007. {
  1008. u32 bank, pint_val;
  1009. u32 request, irq;
  1010. u32 level_mask;
  1011. int umask = 0;
  1012. struct irq_chip *chip = irq_desc_get_chip(desc);
  1013. if (chip->irq_mask_ack) {
  1014. chip->irq_mask_ack(&desc->irq_data);
  1015. } else {
  1016. chip->irq_mask(&desc->irq_data);
  1017. if (chip->irq_ack)
  1018. chip->irq_ack(&desc->irq_data);
  1019. }
  1020. switch (inta_irq) {
  1021. case IRQ_PINT0:
  1022. bank = 0;
  1023. break;
  1024. case IRQ_PINT2:
  1025. bank = 2;
  1026. break;
  1027. case IRQ_PINT3:
  1028. bank = 3;
  1029. break;
  1030. case IRQ_PINT1:
  1031. bank = 1;
  1032. break;
  1033. #ifdef CONFIG_BF60x
  1034. case IRQ_PINT4:
  1035. bank = 4;
  1036. break;
  1037. case IRQ_PINT5:
  1038. bank = 5;
  1039. break;
  1040. #endif
  1041. default:
  1042. return;
  1043. }
  1044. pint_val = bank * NR_PINT_BITS;
  1045. request = pint[bank]->request;
  1046. level_mask = pint[bank]->edge_set & request;
  1047. while (request) {
  1048. if (request & 1) {
  1049. irq = pint2irq_lut[pint_val] + SYS_IRQS;
  1050. if (level_mask & PINT_BIT(pint_val)) {
  1051. umask = 1;
  1052. chip->irq_unmask(&desc->irq_data);
  1053. }
  1054. bfin_handle_irq(irq);
  1055. }
  1056. pint_val++;
  1057. request >>= 1;
  1058. }
  1059. if (!umask)
  1060. chip->irq_unmask(&desc->irq_data);
  1061. }
  1062. #endif
  1063. static struct irq_chip bfin_gpio_irqchip = {
  1064. .name = "GPIO",
  1065. .irq_ack = bfin_gpio_ack_irq,
  1066. .irq_mask = bfin_gpio_mask_irq,
  1067. .irq_mask_ack = bfin_gpio_mask_ack_irq,
  1068. .irq_unmask = bfin_gpio_unmask_irq,
  1069. .irq_disable = bfin_gpio_mask_irq,
  1070. .irq_enable = bfin_gpio_unmask_irq,
  1071. .irq_set_type = bfin_gpio_irq_type,
  1072. .irq_startup = bfin_gpio_irq_startup,
  1073. .irq_shutdown = bfin_gpio_irq_shutdown,
  1074. .irq_set_wake = bfin_gpio_set_wake,
  1075. };
  1076. void __cpuinit init_exception_vectors(void)
  1077. {
  1078. /* cannot program in software:
  1079. * evt0 - emulation (jtag)
  1080. * evt1 - reset
  1081. */
  1082. bfin_write_EVT2(evt_nmi);
  1083. bfin_write_EVT3(trap);
  1084. bfin_write_EVT5(evt_ivhw);
  1085. bfin_write_EVT6(evt_timer);
  1086. bfin_write_EVT7(evt_evt7);
  1087. bfin_write_EVT8(evt_evt8);
  1088. bfin_write_EVT9(evt_evt9);
  1089. bfin_write_EVT10(evt_evt10);
  1090. bfin_write_EVT11(evt_evt11);
  1091. bfin_write_EVT12(evt_evt12);
  1092. bfin_write_EVT13(evt_evt13);
  1093. bfin_write_EVT14(evt_evt14);
  1094. bfin_write_EVT15(evt_system_call);
  1095. CSYNC();
  1096. }
  1097. #ifndef SEC_GCTL
  1098. /*
  1099. * This function should be called during kernel startup to initialize
  1100. * the BFin IRQ handling routines.
  1101. */
  1102. int __init init_arch_irq(void)
  1103. {
  1104. int irq;
  1105. unsigned long ilat = 0;
  1106. /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
  1107. #ifdef SIC_IMASK0
  1108. bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
  1109. bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
  1110. # ifdef SIC_IMASK2
  1111. bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
  1112. # endif
  1113. # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
  1114. bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
  1115. bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
  1116. # endif
  1117. #else
  1118. bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
  1119. #endif
  1120. local_irq_disable();
  1121. #if BFIN_GPIO_PINT
  1122. # ifdef CONFIG_PINTx_REASSIGN
  1123. pint[0]->assign = CONFIG_PINT0_ASSIGN;
  1124. pint[1]->assign = CONFIG_PINT1_ASSIGN;
  1125. pint[2]->assign = CONFIG_PINT2_ASSIGN;
  1126. pint[3]->assign = CONFIG_PINT3_ASSIGN;
  1127. # endif
  1128. /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
  1129. init_pint_lut();
  1130. #endif
  1131. for (irq = 0; irq <= SYS_IRQS; irq++) {
  1132. if (irq <= IRQ_CORETMR)
  1133. irq_set_chip(irq, &bfin_core_irqchip);
  1134. else
  1135. irq_set_chip(irq, &bfin_internal_irqchip);
  1136. switch (irq) {
  1137. #if BFIN_GPIO_PINT
  1138. case IRQ_PINT0:
  1139. case IRQ_PINT1:
  1140. case IRQ_PINT2:
  1141. case IRQ_PINT3:
  1142. #elif defined(BF537_FAMILY)
  1143. case IRQ_PH_INTA_MAC_RX:
  1144. case IRQ_PF_INTA_PG_INTA:
  1145. #elif defined(BF533_FAMILY)
  1146. case IRQ_PROG_INTA:
  1147. #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
  1148. case IRQ_PORTF_INTA:
  1149. case IRQ_PORTG_INTA:
  1150. case IRQ_PORTH_INTA:
  1151. #elif defined(CONFIG_BF561)
  1152. case IRQ_PROG0_INTA:
  1153. case IRQ_PROG1_INTA:
  1154. case IRQ_PROG2_INTA:
  1155. #elif defined(BF538_FAMILY)
  1156. case IRQ_PORTF_INTA:
  1157. #endif
  1158. irq_set_chained_handler(irq, bfin_demux_gpio_irq);
  1159. break;
  1160. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  1161. case IRQ_MAC_ERROR:
  1162. irq_set_chained_handler(irq,
  1163. bfin_demux_mac_status_irq);
  1164. break;
  1165. #endif
  1166. #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
  1167. case IRQ_SUPPLE_0:
  1168. case IRQ_SUPPLE_1:
  1169. irq_set_handler(irq, handle_percpu_irq);
  1170. break;
  1171. #endif
  1172. #ifdef CONFIG_TICKSOURCE_CORETMR
  1173. case IRQ_CORETMR:
  1174. # ifdef CONFIG_SMP
  1175. irq_set_handler(irq, handle_percpu_irq);
  1176. # else
  1177. irq_set_handler(irq, handle_simple_irq);
  1178. # endif
  1179. break;
  1180. #endif
  1181. #ifdef CONFIG_TICKSOURCE_GPTMR0
  1182. case IRQ_TIMER0:
  1183. irq_set_handler(irq, handle_simple_irq);
  1184. break;
  1185. #endif
  1186. default:
  1187. #ifdef CONFIG_IPIPE
  1188. irq_set_handler(irq, handle_level_irq);
  1189. #else
  1190. irq_set_handler(irq, handle_simple_irq);
  1191. #endif
  1192. break;
  1193. }
  1194. }
  1195. init_mach_irq();
  1196. #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
  1197. for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
  1198. irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
  1199. handle_level_irq);
  1200. #endif
  1201. /* if configured as edge, then will be changed to do_edge_IRQ */
  1202. for (irq = GPIO_IRQ_BASE;
  1203. irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
  1204. irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
  1205. handle_level_irq);
  1206. bfin_write_IMASK(0);
  1207. CSYNC();
  1208. ilat = bfin_read_ILAT();
  1209. CSYNC();
  1210. bfin_write_ILAT(ilat);
  1211. CSYNC();
  1212. printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
  1213. /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
  1214. * local_irq_enable()
  1215. */
  1216. program_IAR();
  1217. /* Therefore it's better to setup IARs before interrupts enabled */
  1218. search_IAR();
  1219. /* Enable interrupts IVG7-15 */
  1220. bfin_irq_flags |= IMASK_IVG15 |
  1221. IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
  1222. IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
  1223. /* This implicitly covers ANOMALY_05000171
  1224. * Boot-ROM code modifies SICA_IWRx wakeup registers
  1225. */
  1226. #ifdef SIC_IWR0
  1227. bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
  1228. # ifdef SIC_IWR1
  1229. /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
  1230. * will screw up the bootrom as it relies on MDMA0/1 waking it
  1231. * up from IDLE instructions. See this report for more info:
  1232. * http://blackfin.uclinux.org/gf/tracker/4323
  1233. */
  1234. if (ANOMALY_05000435)
  1235. bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
  1236. else
  1237. bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
  1238. # endif
  1239. # ifdef SIC_IWR2
  1240. bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
  1241. # endif
  1242. #else
  1243. bfin_write_SIC_IWR(IWR_DISABLE_ALL);
  1244. #endif
  1245. return 0;
  1246. }
  1247. #ifdef CONFIG_DO_IRQ_L1
  1248. __attribute__((l1_text))
  1249. #endif
  1250. static int vec_to_irq(int vec)
  1251. {
  1252. struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
  1253. struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
  1254. unsigned long sic_status[3];
  1255. if (likely(vec == EVT_IVTMR_P))
  1256. return IRQ_CORETMR;
  1257. #ifdef SIC_ISR
  1258. sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
  1259. #else
  1260. if (smp_processor_id()) {
  1261. # ifdef SICB_ISR0
  1262. /* This will be optimized out in UP mode. */
  1263. sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
  1264. sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
  1265. # endif
  1266. } else {
  1267. sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
  1268. sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
  1269. }
  1270. #endif
  1271. #ifdef SIC_ISR2
  1272. sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
  1273. #endif
  1274. for (;; ivg++) {
  1275. if (ivg >= ivg_stop)
  1276. return -1;
  1277. #ifdef SIC_ISR
  1278. if (sic_status[0] & ivg->isrflag)
  1279. #else
  1280. if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
  1281. #endif
  1282. return ivg->irqno;
  1283. }
  1284. }
  1285. #else /* SEC_GCTL */
  1286. /*
  1287. * This function should be called during kernel startup to initialize
  1288. * the BFin IRQ handling routines.
  1289. */
  1290. int __init init_arch_irq(void)
  1291. {
  1292. int irq;
  1293. unsigned long ilat = 0;
  1294. bfin_write_SEC_GCTL(SEC_GCTL_RESET);
  1295. local_irq_disable();
  1296. #if BFIN_GPIO_PINT
  1297. # ifdef CONFIG_PINTx_REASSIGN
  1298. pint[0]->assign = CONFIG_PINT0_ASSIGN;
  1299. pint[1]->assign = CONFIG_PINT1_ASSIGN;
  1300. pint[2]->assign = CONFIG_PINT2_ASSIGN;
  1301. pint[3]->assign = CONFIG_PINT3_ASSIGN;
  1302. pint[4]->assign = CONFIG_PINT4_ASSIGN;
  1303. pint[5]->assign = CONFIG_PINT5_ASSIGN;
  1304. # endif
  1305. /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
  1306. init_pint_lut();
  1307. #endif
  1308. for (irq = 0; irq <= SYS_IRQS; irq++) {
  1309. if (irq <= IRQ_CORETMR) {
  1310. irq_set_chip(irq, &bfin_core_irqchip);
  1311. #ifdef CONFIG_TICKSOURCE_CORETMR
  1312. if (irq == IRQ_CORETMR)
  1313. # ifdef CONFIG_SMP
  1314. irq_set_handler(irq, handle_percpu_irq);
  1315. # else
  1316. irq_set_handler(irq, handle_simple_irq);
  1317. # endif
  1318. #endif
  1319. } else if (irq < BFIN_IRQ(0)) {
  1320. irq_set_chip_and_handler(irq, &bfin_internal_irqchip,
  1321. handle_simple_irq);
  1322. } else if (irq == IRQ_SEC_ERR) {
  1323. irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
  1324. handle_sec_fault);
  1325. } else if (irq < CORE_IRQS && irq >= IRQ_C0_DBL_FAULT) {
  1326. irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
  1327. handle_core_fault);
  1328. } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
  1329. irq_set_chip(irq, &bfin_sec_irqchip);
  1330. irq_set_chained_handler(irq, bfin_demux_gpio_irq);
  1331. } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
  1332. irq_set_chip(irq, &bfin_sec_irqchip);
  1333. irq_set_handler(irq, handle_percpu_irq);
  1334. } else {
  1335. irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
  1336. handle_fasteoi_irq);
  1337. __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
  1338. }
  1339. }
  1340. for (irq = GPIO_IRQ_BASE;
  1341. irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
  1342. irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
  1343. handle_level_irq);
  1344. bfin_write_IMASK(0);
  1345. CSYNC();
  1346. ilat = bfin_read_ILAT();
  1347. CSYNC();
  1348. bfin_write_ILAT(ilat);
  1349. CSYNC();
  1350. printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
  1351. bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
  1352. bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
  1353. /* Enable interrupts IVG7-15 */
  1354. bfin_irq_flags |= IMASK_IVG15 |
  1355. IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
  1356. IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
  1357. bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
  1358. bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
  1359. bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
  1360. bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
  1361. udelay(100);
  1362. bfin_write_SEC_GCTL(SEC_GCTL_EN);
  1363. bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
  1364. bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
  1365. init_software_driven_irq();
  1366. register_syscore_ops(&sec_pm_syscore_ops);
  1367. return 0;
  1368. }
  1369. #ifdef CONFIG_DO_IRQ_L1
  1370. __attribute__((l1_text))
  1371. #endif
  1372. static int vec_to_irq(int vec)
  1373. {
  1374. if (likely(vec == EVT_IVTMR_P))
  1375. return IRQ_CORETMR;
  1376. return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
  1377. }
  1378. #endif /* SEC_GCTL */
  1379. #ifdef CONFIG_DO_IRQ_L1
  1380. __attribute__((l1_text))
  1381. #endif
  1382. void do_irq(int vec, struct pt_regs *fp)
  1383. {
  1384. int irq = vec_to_irq(vec);
  1385. if (irq == -1)
  1386. return;
  1387. asm_do_IRQ(irq, fp);
  1388. }
  1389. #ifdef CONFIG_IPIPE
  1390. int __ipipe_get_irq_priority(unsigned irq)
  1391. {
  1392. int ient, prio;
  1393. if (irq <= IRQ_CORETMR)
  1394. return irq;
  1395. #ifdef SEC_GCTL
  1396. if (irq >= BFIN_IRQ(0))
  1397. return IVG11;
  1398. #else
  1399. for (ient = 0; ient < NR_PERI_INTS; ient++) {
  1400. struct ivgx *ivg = ivg_table + ient;
  1401. if (ivg->irqno == irq) {
  1402. for (prio = 0; prio <= IVG13-IVG7; prio++) {
  1403. if (ivg7_13[prio].ifirst <= ivg &&
  1404. ivg7_13[prio].istop > ivg)
  1405. return IVG7 + prio;
  1406. }
  1407. }
  1408. }
  1409. #endif
  1410. return IVG15;
  1411. }
  1412. /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
  1413. #ifdef CONFIG_DO_IRQ_L1
  1414. __attribute__((l1_text))
  1415. #endif
  1416. asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
  1417. {
  1418. struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
  1419. struct ipipe_domain *this_domain = __ipipe_current_domain;
  1420. int irq, s = 0;
  1421. irq = vec_to_irq(vec);
  1422. if (irq == -1)
  1423. return 0;
  1424. if (irq == IRQ_SYSTMR) {
  1425. #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
  1426. bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
  1427. #endif
  1428. /* This is basically what we need from the register frame. */
  1429. __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
  1430. __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
  1431. if (this_domain != ipipe_root_domain)
  1432. __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
  1433. else
  1434. __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
  1435. }
  1436. /*
  1437. * We don't want Linux interrupt handlers to run at the
  1438. * current core priority level (i.e. < EVT15), since this
  1439. * might delay other interrupts handled by a high priority
  1440. * domain. Here is what we do instead:
  1441. *
  1442. * - we raise the SYNCDEFER bit to prevent
  1443. * __ipipe_handle_irq() to sync the pipeline for the root
  1444. * stage for the incoming interrupt. Upon return, that IRQ is
  1445. * pending in the interrupt log.
  1446. *
  1447. * - we raise the TIF_IRQ_SYNC bit for the current thread, so
  1448. * that _schedule_and_signal_from_int will eventually sync the
  1449. * pipeline from EVT15.
  1450. */
  1451. if (this_domain == ipipe_root_domain) {
  1452. s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
  1453. barrier();
  1454. }
  1455. ipipe_trace_irq_entry(irq);
  1456. __ipipe_handle_irq(irq, regs);
  1457. ipipe_trace_irq_exit(irq);
  1458. if (user_mode(regs) &&
  1459. !ipipe_test_foreign_stack() &&
  1460. (current->ipipe_flags & PF_EVTRET) != 0) {
  1461. /*
  1462. * Testing for user_regs() does NOT fully eliminate
  1463. * foreign stack contexts, because of the forged
  1464. * interrupt returns we do through
  1465. * __ipipe_call_irqtail. In that case, we might have
  1466. * preempted a foreign stack context in a high
  1467. * priority domain, with a single interrupt level now
  1468. * pending after the irqtail unwinding is done. In
  1469. * which case user_mode() is now true, and the event
  1470. * gets dispatched spuriously.
  1471. */
  1472. current->ipipe_flags &= ~PF_EVTRET;
  1473. __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
  1474. }
  1475. if (this_domain == ipipe_root_domain) {
  1476. set_thread_flag(TIF_IRQ_SYNC);
  1477. if (!s) {
  1478. __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
  1479. return !test_bit(IPIPE_STALL_FLAG, &p->status);
  1480. }
  1481. }
  1482. return 0;
  1483. }
  1484. #endif /* CONFIG_IPIPE */