mmu.c 33 KB

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  1. /*
  2. * linux/arch/arm/mm/mmu.c
  3. *
  4. * Copyright (C) 1995-2005 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/errno.h>
  13. #include <linux/init.h>
  14. #include <linux/mman.h>
  15. #include <linux/nodemask.h>
  16. #include <linux/memblock.h>
  17. #include <linux/fs.h>
  18. #include <linux/vmalloc.h>
  19. #include <linux/sizes.h>
  20. #include <asm/cp15.h>
  21. #include <asm/cputype.h>
  22. #include <asm/sections.h>
  23. #include <asm/cachetype.h>
  24. #include <asm/setup.h>
  25. #include <asm/smp_plat.h>
  26. #include <asm/tlb.h>
  27. #include <asm/highmem.h>
  28. #include <asm/system_info.h>
  29. #include <asm/traps.h>
  30. #include <asm/mach/arch.h>
  31. #include <asm/mach/map.h>
  32. #include <asm/mach/pci.h>
  33. #include "mm.h"
  34. /*
  35. * empty_zero_page is a special page that is used for
  36. * zero-initialized data and COW.
  37. */
  38. struct page *empty_zero_page;
  39. EXPORT_SYMBOL(empty_zero_page);
  40. /*
  41. * The pmd table for the upper-most set of pages.
  42. */
  43. pmd_t *top_pmd;
  44. #define CPOLICY_UNCACHED 0
  45. #define CPOLICY_BUFFERED 1
  46. #define CPOLICY_WRITETHROUGH 2
  47. #define CPOLICY_WRITEBACK 3
  48. #define CPOLICY_WRITEALLOC 4
  49. static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  50. static unsigned int ecc_mask __initdata = 0;
  51. pgprot_t pgprot_user;
  52. pgprot_t pgprot_kernel;
  53. EXPORT_SYMBOL(pgprot_user);
  54. EXPORT_SYMBOL(pgprot_kernel);
  55. struct cachepolicy {
  56. const char policy[16];
  57. unsigned int cr_mask;
  58. pmdval_t pmd;
  59. pteval_t pte;
  60. };
  61. static struct cachepolicy cache_policies[] __initdata = {
  62. {
  63. .policy = "uncached",
  64. .cr_mask = CR_W|CR_C,
  65. .pmd = PMD_SECT_UNCACHED,
  66. .pte = L_PTE_MT_UNCACHED,
  67. }, {
  68. .policy = "buffered",
  69. .cr_mask = CR_C,
  70. .pmd = PMD_SECT_BUFFERED,
  71. .pte = L_PTE_MT_BUFFERABLE,
  72. }, {
  73. .policy = "writethrough",
  74. .cr_mask = 0,
  75. .pmd = PMD_SECT_WT,
  76. .pte = L_PTE_MT_WRITETHROUGH,
  77. }, {
  78. .policy = "writeback",
  79. .cr_mask = 0,
  80. .pmd = PMD_SECT_WB,
  81. .pte = L_PTE_MT_WRITEBACK,
  82. }, {
  83. .policy = "writealloc",
  84. .cr_mask = 0,
  85. .pmd = PMD_SECT_WBWA,
  86. .pte = L_PTE_MT_WRITEALLOC,
  87. }
  88. };
  89. /*
  90. * These are useful for identifying cache coherency
  91. * problems by allowing the cache or the cache and
  92. * writebuffer to be turned off. (Note: the write
  93. * buffer should not be on and the cache off).
  94. */
  95. static int __init early_cachepolicy(char *p)
  96. {
  97. int i;
  98. for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
  99. int len = strlen(cache_policies[i].policy);
  100. if (memcmp(p, cache_policies[i].policy, len) == 0) {
  101. cachepolicy = i;
  102. cr_alignment &= ~cache_policies[i].cr_mask;
  103. cr_no_alignment &= ~cache_policies[i].cr_mask;
  104. break;
  105. }
  106. }
  107. if (i == ARRAY_SIZE(cache_policies))
  108. printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
  109. /*
  110. * This restriction is partly to do with the way we boot; it is
  111. * unpredictable to have memory mapped using two different sets of
  112. * memory attributes (shared, type, and cache attribs). We can not
  113. * change these attributes once the initial assembly has setup the
  114. * page tables.
  115. */
  116. if (cpu_architecture() >= CPU_ARCH_ARMv6) {
  117. printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
  118. cachepolicy = CPOLICY_WRITEBACK;
  119. }
  120. flush_cache_all();
  121. set_cr(cr_alignment);
  122. return 0;
  123. }
  124. early_param("cachepolicy", early_cachepolicy);
  125. static int __init early_nocache(char *__unused)
  126. {
  127. char *p = "buffered";
  128. printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
  129. early_cachepolicy(p);
  130. return 0;
  131. }
  132. early_param("nocache", early_nocache);
  133. static int __init early_nowrite(char *__unused)
  134. {
  135. char *p = "uncached";
  136. printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
  137. early_cachepolicy(p);
  138. return 0;
  139. }
  140. early_param("nowb", early_nowrite);
  141. #ifndef CONFIG_ARM_LPAE
  142. static int __init early_ecc(char *p)
  143. {
  144. if (memcmp(p, "on", 2) == 0)
  145. ecc_mask = PMD_PROTECTION;
  146. else if (memcmp(p, "off", 3) == 0)
  147. ecc_mask = 0;
  148. return 0;
  149. }
  150. early_param("ecc", early_ecc);
  151. #endif
  152. static int __init noalign_setup(char *__unused)
  153. {
  154. cr_alignment &= ~CR_A;
  155. cr_no_alignment &= ~CR_A;
  156. set_cr(cr_alignment);
  157. return 1;
  158. }
  159. __setup("noalign", noalign_setup);
  160. #ifndef CONFIG_SMP
  161. void adjust_cr(unsigned long mask, unsigned long set)
  162. {
  163. unsigned long flags;
  164. mask &= ~CR_A;
  165. set &= mask;
  166. local_irq_save(flags);
  167. cr_no_alignment = (cr_no_alignment & ~mask) | set;
  168. cr_alignment = (cr_alignment & ~mask) | set;
  169. set_cr((get_cr() & ~mask) | set);
  170. local_irq_restore(flags);
  171. }
  172. #endif
  173. #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
  174. #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
  175. static struct mem_type mem_types[] = {
  176. [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
  177. .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
  178. L_PTE_SHARED,
  179. .prot_l1 = PMD_TYPE_TABLE,
  180. .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
  181. .domain = DOMAIN_IO,
  182. },
  183. [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
  184. .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
  185. .prot_l1 = PMD_TYPE_TABLE,
  186. .prot_sect = PROT_SECT_DEVICE,
  187. .domain = DOMAIN_IO,
  188. },
  189. [MT_DEVICE_CACHED] = { /* ioremap_cached */
  190. .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
  191. .prot_l1 = PMD_TYPE_TABLE,
  192. .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
  193. .domain = DOMAIN_IO,
  194. },
  195. [MT_DEVICE_WC] = { /* ioremap_wc */
  196. .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
  197. .prot_l1 = PMD_TYPE_TABLE,
  198. .prot_sect = PROT_SECT_DEVICE,
  199. .domain = DOMAIN_IO,
  200. },
  201. [MT_UNCACHED] = {
  202. .prot_pte = PROT_PTE_DEVICE,
  203. .prot_l1 = PMD_TYPE_TABLE,
  204. .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
  205. .domain = DOMAIN_IO,
  206. },
  207. [MT_CACHECLEAN] = {
  208. .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
  209. .domain = DOMAIN_KERNEL,
  210. },
  211. #ifndef CONFIG_ARM_LPAE
  212. [MT_MINICLEAN] = {
  213. .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
  214. .domain = DOMAIN_KERNEL,
  215. },
  216. #endif
  217. [MT_LOW_VECTORS] = {
  218. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
  219. L_PTE_RDONLY,
  220. .prot_l1 = PMD_TYPE_TABLE,
  221. .domain = DOMAIN_USER,
  222. },
  223. [MT_HIGH_VECTORS] = {
  224. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
  225. L_PTE_USER | L_PTE_RDONLY,
  226. .prot_l1 = PMD_TYPE_TABLE,
  227. .domain = DOMAIN_USER,
  228. },
  229. [MT_MEMORY] = {
  230. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
  231. .prot_l1 = PMD_TYPE_TABLE,
  232. .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
  233. .domain = DOMAIN_KERNEL,
  234. },
  235. [MT_ROM] = {
  236. .prot_sect = PMD_TYPE_SECT,
  237. .domain = DOMAIN_KERNEL,
  238. },
  239. [MT_MEMORY_NONCACHED] = {
  240. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
  241. L_PTE_MT_BUFFERABLE,
  242. .prot_l1 = PMD_TYPE_TABLE,
  243. .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
  244. .domain = DOMAIN_KERNEL,
  245. },
  246. [MT_MEMORY_DTCM] = {
  247. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
  248. L_PTE_XN,
  249. .prot_l1 = PMD_TYPE_TABLE,
  250. .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
  251. .domain = DOMAIN_KERNEL,
  252. },
  253. [MT_MEMORY_ITCM] = {
  254. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
  255. .prot_l1 = PMD_TYPE_TABLE,
  256. .domain = DOMAIN_KERNEL,
  257. },
  258. [MT_MEMORY_SO] = {
  259. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
  260. L_PTE_MT_UNCACHED,
  261. .prot_l1 = PMD_TYPE_TABLE,
  262. .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
  263. PMD_SECT_UNCACHED | PMD_SECT_XN,
  264. .domain = DOMAIN_KERNEL,
  265. },
  266. [MT_MEMORY_DMA_READY] = {
  267. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
  268. .prot_l1 = PMD_TYPE_TABLE,
  269. .domain = DOMAIN_KERNEL,
  270. },
  271. };
  272. const struct mem_type *get_mem_type(unsigned int type)
  273. {
  274. return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
  275. }
  276. EXPORT_SYMBOL(get_mem_type);
  277. /*
  278. * Adjust the PMD section entries according to the CPU in use.
  279. */
  280. static void __init build_mem_type_table(void)
  281. {
  282. struct cachepolicy *cp;
  283. unsigned int cr = get_cr();
  284. pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
  285. int cpu_arch = cpu_architecture();
  286. int i;
  287. if (cpu_arch < CPU_ARCH_ARMv6) {
  288. #if defined(CONFIG_CPU_DCACHE_DISABLE)
  289. if (cachepolicy > CPOLICY_BUFFERED)
  290. cachepolicy = CPOLICY_BUFFERED;
  291. #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
  292. if (cachepolicy > CPOLICY_WRITETHROUGH)
  293. cachepolicy = CPOLICY_WRITETHROUGH;
  294. #endif
  295. }
  296. if (cpu_arch < CPU_ARCH_ARMv5) {
  297. if (cachepolicy >= CPOLICY_WRITEALLOC)
  298. cachepolicy = CPOLICY_WRITEBACK;
  299. ecc_mask = 0;
  300. }
  301. if (is_smp())
  302. cachepolicy = CPOLICY_WRITEALLOC;
  303. /*
  304. * Strip out features not present on earlier architectures.
  305. * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
  306. * without extended page tables don't have the 'Shared' bit.
  307. */
  308. if (cpu_arch < CPU_ARCH_ARMv5)
  309. for (i = 0; i < ARRAY_SIZE(mem_types); i++)
  310. mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
  311. if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
  312. for (i = 0; i < ARRAY_SIZE(mem_types); i++)
  313. mem_types[i].prot_sect &= ~PMD_SECT_S;
  314. /*
  315. * ARMv5 and lower, bit 4 must be set for page tables (was: cache
  316. * "update-able on write" bit on ARM610). However, Xscale and
  317. * Xscale3 require this bit to be cleared.
  318. */
  319. if (cpu_is_xscale() || cpu_is_xsc3()) {
  320. for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
  321. mem_types[i].prot_sect &= ~PMD_BIT4;
  322. mem_types[i].prot_l1 &= ~PMD_BIT4;
  323. }
  324. } else if (cpu_arch < CPU_ARCH_ARMv6) {
  325. for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
  326. if (mem_types[i].prot_l1)
  327. mem_types[i].prot_l1 |= PMD_BIT4;
  328. if (mem_types[i].prot_sect)
  329. mem_types[i].prot_sect |= PMD_BIT4;
  330. }
  331. }
  332. /*
  333. * Mark the device areas according to the CPU/architecture.
  334. */
  335. if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
  336. if (!cpu_is_xsc3()) {
  337. /*
  338. * Mark device regions on ARMv6+ as execute-never
  339. * to prevent speculative instruction fetches.
  340. */
  341. mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
  342. mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
  343. mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
  344. mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
  345. }
  346. if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
  347. /*
  348. * For ARMv7 with TEX remapping,
  349. * - shared device is SXCB=1100
  350. * - nonshared device is SXCB=0100
  351. * - write combine device mem is SXCB=0001
  352. * (Uncached Normal memory)
  353. */
  354. mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
  355. mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
  356. mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
  357. } else if (cpu_is_xsc3()) {
  358. /*
  359. * For Xscale3,
  360. * - shared device is TEXCB=00101
  361. * - nonshared device is TEXCB=01000
  362. * - write combine device mem is TEXCB=00100
  363. * (Inner/Outer Uncacheable in xsc3 parlance)
  364. */
  365. mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
  366. mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
  367. mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
  368. } else {
  369. /*
  370. * For ARMv6 and ARMv7 without TEX remapping,
  371. * - shared device is TEXCB=00001
  372. * - nonshared device is TEXCB=01000
  373. * - write combine device mem is TEXCB=00100
  374. * (Uncached Normal in ARMv6 parlance).
  375. */
  376. mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
  377. mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
  378. mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
  379. }
  380. } else {
  381. /*
  382. * On others, write combining is "Uncached/Buffered"
  383. */
  384. mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
  385. }
  386. /*
  387. * Now deal with the memory-type mappings
  388. */
  389. cp = &cache_policies[cachepolicy];
  390. vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
  391. /*
  392. * ARMv6 and above have extended page tables.
  393. */
  394. if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
  395. #ifndef CONFIG_ARM_LPAE
  396. /*
  397. * Mark cache clean areas and XIP ROM read only
  398. * from SVC mode and no access from userspace.
  399. */
  400. mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
  401. mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
  402. mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
  403. #endif
  404. if (is_smp()) {
  405. /*
  406. * Mark memory with the "shared" attribute
  407. * for SMP systems
  408. */
  409. user_pgprot |= L_PTE_SHARED;
  410. kern_pgprot |= L_PTE_SHARED;
  411. vecs_pgprot |= L_PTE_SHARED;
  412. mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
  413. mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
  414. mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
  415. mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
  416. mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
  417. mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
  418. mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
  419. mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
  420. mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
  421. }
  422. }
  423. /*
  424. * Non-cacheable Normal - intended for memory areas that must
  425. * not cause dirty cache line writebacks when used
  426. */
  427. if (cpu_arch >= CPU_ARCH_ARMv6) {
  428. if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
  429. /* Non-cacheable Normal is XCB = 001 */
  430. mem_types[MT_MEMORY_NONCACHED].prot_sect |=
  431. PMD_SECT_BUFFERED;
  432. } else {
  433. /* For both ARMv6 and non-TEX-remapping ARMv7 */
  434. mem_types[MT_MEMORY_NONCACHED].prot_sect |=
  435. PMD_SECT_TEX(1);
  436. }
  437. } else {
  438. mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
  439. }
  440. #ifdef CONFIG_ARM_LPAE
  441. /*
  442. * Do not generate access flag faults for the kernel mappings.
  443. */
  444. for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
  445. mem_types[i].prot_pte |= PTE_EXT_AF;
  446. if (mem_types[i].prot_sect)
  447. mem_types[i].prot_sect |= PMD_SECT_AF;
  448. }
  449. kern_pgprot |= PTE_EXT_AF;
  450. vecs_pgprot |= PTE_EXT_AF;
  451. #endif
  452. for (i = 0; i < 16; i++) {
  453. unsigned long v = pgprot_val(protection_map[i]);
  454. protection_map[i] = __pgprot(v | user_pgprot);
  455. }
  456. mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
  457. mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
  458. pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
  459. pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
  460. L_PTE_DIRTY | kern_pgprot);
  461. mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
  462. mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
  463. mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
  464. mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
  465. mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
  466. mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
  467. mem_types[MT_ROM].prot_sect |= cp->pmd;
  468. switch (cp->pmd) {
  469. case PMD_SECT_WT:
  470. mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
  471. break;
  472. case PMD_SECT_WB:
  473. case PMD_SECT_WBWA:
  474. mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
  475. break;
  476. }
  477. printk("Memory policy: ECC %sabled, Data cache %s\n",
  478. ecc_mask ? "en" : "dis", cp->policy);
  479. for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
  480. struct mem_type *t = &mem_types[i];
  481. if (t->prot_l1)
  482. t->prot_l1 |= PMD_DOMAIN(t->domain);
  483. if (t->prot_sect)
  484. t->prot_sect |= PMD_DOMAIN(t->domain);
  485. }
  486. }
  487. #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
  488. pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
  489. unsigned long size, pgprot_t vma_prot)
  490. {
  491. if (!pfn_valid(pfn))
  492. return pgprot_noncached(vma_prot);
  493. else if (file->f_flags & O_SYNC)
  494. return pgprot_writecombine(vma_prot);
  495. return vma_prot;
  496. }
  497. EXPORT_SYMBOL(phys_mem_access_prot);
  498. #endif
  499. #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
  500. static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
  501. {
  502. void *ptr = __va(memblock_alloc(sz, align));
  503. memset(ptr, 0, sz);
  504. return ptr;
  505. }
  506. static void __init *early_alloc(unsigned long sz)
  507. {
  508. return early_alloc_aligned(sz, sz);
  509. }
  510. static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
  511. {
  512. if (pmd_none(*pmd)) {
  513. pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
  514. __pmd_populate(pmd, __pa(pte), prot);
  515. }
  516. BUG_ON(pmd_bad(*pmd));
  517. return pte_offset_kernel(pmd, addr);
  518. }
  519. static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
  520. unsigned long end, unsigned long pfn,
  521. const struct mem_type *type)
  522. {
  523. pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
  524. do {
  525. set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
  526. pfn++;
  527. } while (pte++, addr += PAGE_SIZE, addr != end);
  528. }
  529. static void __init alloc_init_section(pud_t *pud, unsigned long addr,
  530. unsigned long end, phys_addr_t phys,
  531. const struct mem_type *type)
  532. {
  533. pmd_t *pmd = pmd_offset(pud, addr);
  534. /*
  535. * Try a section mapping - end, addr and phys must all be aligned
  536. * to a section boundary. Note that PMDs refer to the individual
  537. * L1 entries, whereas PGDs refer to a group of L1 entries making
  538. * up one logical pointer to an L2 table.
  539. */
  540. if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
  541. pmd_t *p = pmd;
  542. #ifndef CONFIG_ARM_LPAE
  543. if (addr & SECTION_SIZE)
  544. pmd++;
  545. #endif
  546. do {
  547. *pmd = __pmd(phys | type->prot_sect);
  548. phys += SECTION_SIZE;
  549. } while (pmd++, addr += SECTION_SIZE, addr != end);
  550. flush_pmd_entry(p);
  551. } else {
  552. /*
  553. * No need to loop; pte's aren't interested in the
  554. * individual L1 entries.
  555. */
  556. alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
  557. }
  558. }
  559. static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
  560. unsigned long end, unsigned long phys, const struct mem_type *type)
  561. {
  562. pud_t *pud = pud_offset(pgd, addr);
  563. unsigned long next;
  564. do {
  565. next = pud_addr_end(addr, end);
  566. alloc_init_section(pud, addr, next, phys, type);
  567. phys += next - addr;
  568. } while (pud++, addr = next, addr != end);
  569. }
  570. #ifndef CONFIG_ARM_LPAE
  571. static void __init create_36bit_mapping(struct map_desc *md,
  572. const struct mem_type *type)
  573. {
  574. unsigned long addr, length, end;
  575. phys_addr_t phys;
  576. pgd_t *pgd;
  577. addr = md->virtual;
  578. phys = __pfn_to_phys(md->pfn);
  579. length = PAGE_ALIGN(md->length);
  580. if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
  581. printk(KERN_ERR "MM: CPU does not support supersection "
  582. "mapping for 0x%08llx at 0x%08lx\n",
  583. (long long)__pfn_to_phys((u64)md->pfn), addr);
  584. return;
  585. }
  586. /* N.B. ARMv6 supersections are only defined to work with domain 0.
  587. * Since domain assignments can in fact be arbitrary, the
  588. * 'domain == 0' check below is required to insure that ARMv6
  589. * supersections are only allocated for domain 0 regardless
  590. * of the actual domain assignments in use.
  591. */
  592. if (type->domain) {
  593. printk(KERN_ERR "MM: invalid domain in supersection "
  594. "mapping for 0x%08llx at 0x%08lx\n",
  595. (long long)__pfn_to_phys((u64)md->pfn), addr);
  596. return;
  597. }
  598. if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
  599. printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
  600. " at 0x%08lx invalid alignment\n",
  601. (long long)__pfn_to_phys((u64)md->pfn), addr);
  602. return;
  603. }
  604. /*
  605. * Shift bits [35:32] of address into bits [23:20] of PMD
  606. * (See ARMv6 spec).
  607. */
  608. phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
  609. pgd = pgd_offset_k(addr);
  610. end = addr + length;
  611. do {
  612. pud_t *pud = pud_offset(pgd, addr);
  613. pmd_t *pmd = pmd_offset(pud, addr);
  614. int i;
  615. for (i = 0; i < 16; i++)
  616. *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
  617. addr += SUPERSECTION_SIZE;
  618. phys += SUPERSECTION_SIZE;
  619. pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
  620. } while (addr != end);
  621. }
  622. #endif /* !CONFIG_ARM_LPAE */
  623. /*
  624. * Create the page directory entries and any necessary
  625. * page tables for the mapping specified by `md'. We
  626. * are able to cope here with varying sizes and address
  627. * offsets, and we take full advantage of sections and
  628. * supersections.
  629. */
  630. static void __init create_mapping(struct map_desc *md)
  631. {
  632. unsigned long addr, length, end;
  633. phys_addr_t phys;
  634. const struct mem_type *type;
  635. pgd_t *pgd;
  636. if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
  637. printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
  638. " at 0x%08lx in user region\n",
  639. (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
  640. return;
  641. }
  642. if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
  643. md->virtual >= PAGE_OFFSET &&
  644. (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
  645. printk(KERN_WARNING "BUG: mapping for 0x%08llx"
  646. " at 0x%08lx out of vmalloc space\n",
  647. (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
  648. }
  649. type = &mem_types[md->type];
  650. #ifndef CONFIG_ARM_LPAE
  651. /*
  652. * Catch 36-bit addresses
  653. */
  654. if (md->pfn >= 0x100000) {
  655. create_36bit_mapping(md, type);
  656. return;
  657. }
  658. #endif
  659. addr = md->virtual & PAGE_MASK;
  660. phys = __pfn_to_phys(md->pfn);
  661. length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
  662. if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
  663. printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
  664. "be mapped using pages, ignoring.\n",
  665. (long long)__pfn_to_phys(md->pfn), addr);
  666. return;
  667. }
  668. pgd = pgd_offset_k(addr);
  669. end = addr + length;
  670. do {
  671. unsigned long next = pgd_addr_end(addr, end);
  672. alloc_init_pud(pgd, addr, next, phys, type);
  673. phys += next - addr;
  674. addr = next;
  675. } while (pgd++, addr != end);
  676. }
  677. /*
  678. * Create the architecture specific mappings
  679. */
  680. void __init iotable_init(struct map_desc *io_desc, int nr)
  681. {
  682. struct map_desc *md;
  683. struct vm_struct *vm;
  684. if (!nr)
  685. return;
  686. vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
  687. for (md = io_desc; nr; md++, nr--) {
  688. create_mapping(md);
  689. vm->addr = (void *)(md->virtual & PAGE_MASK);
  690. vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
  691. vm->phys_addr = __pfn_to_phys(md->pfn);
  692. vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
  693. vm->flags |= VM_ARM_MTYPE(md->type);
  694. vm->caller = iotable_init;
  695. vm_area_add_early(vm++);
  696. }
  697. }
  698. void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
  699. void *caller)
  700. {
  701. struct vm_struct *vm;
  702. vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
  703. vm->addr = (void *)addr;
  704. vm->size = size;
  705. vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
  706. vm->caller = caller;
  707. vm_area_add_early(vm);
  708. }
  709. #ifndef CONFIG_ARM_LPAE
  710. /*
  711. * The Linux PMD is made of two consecutive section entries covering 2MB
  712. * (see definition in include/asm/pgtable-2level.h). However a call to
  713. * create_mapping() may optimize static mappings by using individual
  714. * 1MB section mappings. This leaves the actual PMD potentially half
  715. * initialized if the top or bottom section entry isn't used, leaving it
  716. * open to problems if a subsequent ioremap() or vmalloc() tries to use
  717. * the virtual space left free by that unused section entry.
  718. *
  719. * Let's avoid the issue by inserting dummy vm entries covering the unused
  720. * PMD halves once the static mappings are in place.
  721. */
  722. static void __init pmd_empty_section_gap(unsigned long addr)
  723. {
  724. vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
  725. }
  726. static void __init fill_pmd_gaps(void)
  727. {
  728. struct vm_struct *vm;
  729. unsigned long addr, next = 0;
  730. pmd_t *pmd;
  731. /* we're still single threaded hence no lock needed here */
  732. for (vm = vmlist; vm; vm = vm->next) {
  733. if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING)))
  734. continue;
  735. addr = (unsigned long)vm->addr;
  736. if (addr < next)
  737. continue;
  738. /*
  739. * Check if this vm starts on an odd section boundary.
  740. * If so and the first section entry for this PMD is free
  741. * then we block the corresponding virtual address.
  742. */
  743. if ((addr & ~PMD_MASK) == SECTION_SIZE) {
  744. pmd = pmd_off_k(addr);
  745. if (pmd_none(*pmd))
  746. pmd_empty_section_gap(addr & PMD_MASK);
  747. }
  748. /*
  749. * Then check if this vm ends on an odd section boundary.
  750. * If so and the second section entry for this PMD is empty
  751. * then we block the corresponding virtual address.
  752. */
  753. addr += vm->size;
  754. if ((addr & ~PMD_MASK) == SECTION_SIZE) {
  755. pmd = pmd_off_k(addr) + 1;
  756. if (pmd_none(*pmd))
  757. pmd_empty_section_gap(addr);
  758. }
  759. /* no need to look at any vm entry until we hit the next PMD */
  760. next = (addr + PMD_SIZE - 1) & PMD_MASK;
  761. }
  762. }
  763. #else
  764. #define fill_pmd_gaps() do { } while (0)
  765. #endif
  766. #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
  767. static void __init pci_reserve_io(void)
  768. {
  769. struct vm_struct *vm;
  770. unsigned long addr;
  771. /* we're still single threaded hence no lock needed here */
  772. for (vm = vmlist; vm; vm = vm->next) {
  773. if (!(vm->flags & VM_ARM_STATIC_MAPPING))
  774. continue;
  775. addr = (unsigned long)vm->addr;
  776. addr &= ~(SZ_2M - 1);
  777. if (addr == PCI_IO_VIRT_BASE)
  778. return;
  779. }
  780. vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
  781. }
  782. #else
  783. #define pci_reserve_io() do { } while (0)
  784. #endif
  785. static void * __initdata vmalloc_min =
  786. (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
  787. /*
  788. * vmalloc=size forces the vmalloc area to be exactly 'size'
  789. * bytes. This can be used to increase (or decrease) the vmalloc
  790. * area - the default is 240m.
  791. */
  792. static int __init early_vmalloc(char *arg)
  793. {
  794. unsigned long vmalloc_reserve = memparse(arg, NULL);
  795. if (vmalloc_reserve < SZ_16M) {
  796. vmalloc_reserve = SZ_16M;
  797. printk(KERN_WARNING
  798. "vmalloc area too small, limiting to %luMB\n",
  799. vmalloc_reserve >> 20);
  800. }
  801. if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
  802. vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
  803. printk(KERN_WARNING
  804. "vmalloc area is too big, limiting to %luMB\n",
  805. vmalloc_reserve >> 20);
  806. }
  807. vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
  808. return 0;
  809. }
  810. early_param("vmalloc", early_vmalloc);
  811. phys_addr_t arm_lowmem_limit __initdata = 0;
  812. void __init sanity_check_meminfo(void)
  813. {
  814. int i, j, highmem = 0;
  815. for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
  816. struct membank *bank = &meminfo.bank[j];
  817. *bank = meminfo.bank[i];
  818. if (bank->start > ULONG_MAX)
  819. highmem = 1;
  820. #ifdef CONFIG_HIGHMEM
  821. if (__va(bank->start) >= vmalloc_min ||
  822. __va(bank->start) < (void *)PAGE_OFFSET)
  823. highmem = 1;
  824. bank->highmem = highmem;
  825. /*
  826. * Split those memory banks which are partially overlapping
  827. * the vmalloc area greatly simplifying things later.
  828. */
  829. if (!highmem && __va(bank->start) < vmalloc_min &&
  830. bank->size > vmalloc_min - __va(bank->start)) {
  831. if (meminfo.nr_banks >= NR_BANKS) {
  832. printk(KERN_CRIT "NR_BANKS too low, "
  833. "ignoring high memory\n");
  834. } else {
  835. memmove(bank + 1, bank,
  836. (meminfo.nr_banks - i) * sizeof(*bank));
  837. meminfo.nr_banks++;
  838. i++;
  839. bank[1].size -= vmalloc_min - __va(bank->start);
  840. bank[1].start = __pa(vmalloc_min - 1) + 1;
  841. bank[1].highmem = highmem = 1;
  842. j++;
  843. }
  844. bank->size = vmalloc_min - __va(bank->start);
  845. }
  846. #else
  847. bank->highmem = highmem;
  848. /*
  849. * Highmem banks not allowed with !CONFIG_HIGHMEM.
  850. */
  851. if (highmem) {
  852. printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
  853. "(!CONFIG_HIGHMEM).\n",
  854. (unsigned long long)bank->start,
  855. (unsigned long long)bank->start + bank->size - 1);
  856. continue;
  857. }
  858. /*
  859. * Check whether this memory bank would entirely overlap
  860. * the vmalloc area.
  861. */
  862. if (__va(bank->start) >= vmalloc_min ||
  863. __va(bank->start) < (void *)PAGE_OFFSET) {
  864. printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
  865. "(vmalloc region overlap).\n",
  866. (unsigned long long)bank->start,
  867. (unsigned long long)bank->start + bank->size - 1);
  868. continue;
  869. }
  870. /*
  871. * Check whether this memory bank would partially overlap
  872. * the vmalloc area.
  873. */
  874. if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
  875. __va(bank->start + bank->size - 1) <= __va(bank->start)) {
  876. unsigned long newsize = vmalloc_min - __va(bank->start);
  877. printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
  878. "to -%.8llx (vmalloc region overlap).\n",
  879. (unsigned long long)bank->start,
  880. (unsigned long long)bank->start + bank->size - 1,
  881. (unsigned long long)bank->start + newsize - 1);
  882. bank->size = newsize;
  883. }
  884. #endif
  885. if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
  886. arm_lowmem_limit = bank->start + bank->size;
  887. j++;
  888. }
  889. #ifdef CONFIG_HIGHMEM
  890. if (highmem) {
  891. const char *reason = NULL;
  892. if (cache_is_vipt_aliasing()) {
  893. /*
  894. * Interactions between kmap and other mappings
  895. * make highmem support with aliasing VIPT caches
  896. * rather difficult.
  897. */
  898. reason = "with VIPT aliasing cache";
  899. }
  900. if (reason) {
  901. printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
  902. reason);
  903. while (j > 0 && meminfo.bank[j - 1].highmem)
  904. j--;
  905. }
  906. }
  907. #endif
  908. meminfo.nr_banks = j;
  909. high_memory = __va(arm_lowmem_limit - 1) + 1;
  910. memblock_set_current_limit(arm_lowmem_limit);
  911. }
  912. static inline void prepare_page_table(void)
  913. {
  914. unsigned long addr;
  915. phys_addr_t end;
  916. /*
  917. * Clear out all the mappings below the kernel image.
  918. */
  919. for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
  920. pmd_clear(pmd_off_k(addr));
  921. #ifdef CONFIG_XIP_KERNEL
  922. /* The XIP kernel is mapped in the module area -- skip over it */
  923. addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
  924. #endif
  925. for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
  926. pmd_clear(pmd_off_k(addr));
  927. /*
  928. * Find the end of the first block of lowmem.
  929. */
  930. end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
  931. if (end >= arm_lowmem_limit)
  932. end = arm_lowmem_limit;
  933. /*
  934. * Clear out all the kernel space mappings, except for the first
  935. * memory bank, up to the vmalloc region.
  936. */
  937. for (addr = __phys_to_virt(end);
  938. addr < VMALLOC_START; addr += PMD_SIZE)
  939. pmd_clear(pmd_off_k(addr));
  940. }
  941. #ifdef CONFIG_ARM_LPAE
  942. /* the first page is reserved for pgd */
  943. #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
  944. PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
  945. #else
  946. #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
  947. #endif
  948. /*
  949. * Reserve the special regions of memory
  950. */
  951. void __init arm_mm_memblock_reserve(void)
  952. {
  953. /*
  954. * Reserve the page tables. These are already in use,
  955. * and can only be in node 0.
  956. */
  957. memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
  958. #ifdef CONFIG_SA1111
  959. /*
  960. * Because of the SA1111 DMA bug, we want to preserve our
  961. * precious DMA-able memory...
  962. */
  963. memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
  964. #endif
  965. }
  966. /*
  967. * Set up the device mappings. Since we clear out the page tables for all
  968. * mappings above VMALLOC_START, we will remove any debug device mappings.
  969. * This means you have to be careful how you debug this function, or any
  970. * called function. This means you can't use any function or debugging
  971. * method which may touch any device, otherwise the kernel _will_ crash.
  972. */
  973. static void __init devicemaps_init(struct machine_desc *mdesc)
  974. {
  975. struct map_desc map;
  976. unsigned long addr;
  977. void *vectors;
  978. /*
  979. * Allocate the vector page early.
  980. */
  981. vectors = early_alloc(PAGE_SIZE);
  982. early_trap_init(vectors);
  983. for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
  984. pmd_clear(pmd_off_k(addr));
  985. /*
  986. * Map the kernel if it is XIP.
  987. * It is always first in the modulearea.
  988. */
  989. #ifdef CONFIG_XIP_KERNEL
  990. map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
  991. map.virtual = MODULES_VADDR;
  992. map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
  993. map.type = MT_ROM;
  994. create_mapping(&map);
  995. #endif
  996. /*
  997. * Map the cache flushing regions.
  998. */
  999. #ifdef FLUSH_BASE
  1000. map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
  1001. map.virtual = FLUSH_BASE;
  1002. map.length = SZ_1M;
  1003. map.type = MT_CACHECLEAN;
  1004. create_mapping(&map);
  1005. #endif
  1006. #ifdef FLUSH_BASE_MINICACHE
  1007. map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
  1008. map.virtual = FLUSH_BASE_MINICACHE;
  1009. map.length = SZ_1M;
  1010. map.type = MT_MINICLEAN;
  1011. create_mapping(&map);
  1012. #endif
  1013. /*
  1014. * Create a mapping for the machine vectors at the high-vectors
  1015. * location (0xffff0000). If we aren't using high-vectors, also
  1016. * create a mapping at the low-vectors virtual address.
  1017. */
  1018. map.pfn = __phys_to_pfn(virt_to_phys(vectors));
  1019. map.virtual = 0xffff0000;
  1020. map.length = PAGE_SIZE;
  1021. map.type = MT_HIGH_VECTORS;
  1022. create_mapping(&map);
  1023. if (!vectors_high()) {
  1024. map.virtual = 0;
  1025. map.type = MT_LOW_VECTORS;
  1026. create_mapping(&map);
  1027. }
  1028. /*
  1029. * Ask the machine support to map in the statically mapped devices.
  1030. */
  1031. if (mdesc->map_io)
  1032. mdesc->map_io();
  1033. fill_pmd_gaps();
  1034. /* Reserve fixed i/o space in VMALLOC region */
  1035. pci_reserve_io();
  1036. /*
  1037. * Finally flush the caches and tlb to ensure that we're in a
  1038. * consistent state wrt the writebuffer. This also ensures that
  1039. * any write-allocated cache lines in the vector page are written
  1040. * back. After this point, we can start to touch devices again.
  1041. */
  1042. local_flush_tlb_all();
  1043. flush_cache_all();
  1044. }
  1045. static void __init kmap_init(void)
  1046. {
  1047. #ifdef CONFIG_HIGHMEM
  1048. pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
  1049. PKMAP_BASE, _PAGE_KERNEL_TABLE);
  1050. #endif
  1051. }
  1052. static void __init map_lowmem(void)
  1053. {
  1054. struct memblock_region *reg;
  1055. /* Map all the lowmem memory banks. */
  1056. for_each_memblock(memory, reg) {
  1057. phys_addr_t start = reg->base;
  1058. phys_addr_t end = start + reg->size;
  1059. struct map_desc map;
  1060. if (end > arm_lowmem_limit)
  1061. end = arm_lowmem_limit;
  1062. if (start >= end)
  1063. break;
  1064. map.pfn = __phys_to_pfn(start);
  1065. map.virtual = __phys_to_virt(start);
  1066. map.length = end - start;
  1067. map.type = MT_MEMORY;
  1068. create_mapping(&map);
  1069. }
  1070. }
  1071. /*
  1072. * paging_init() sets up the page tables, initialises the zone memory
  1073. * maps, and sets up the zero page, bad page and bad page tables.
  1074. */
  1075. void __init paging_init(struct machine_desc *mdesc)
  1076. {
  1077. void *zero_page;
  1078. memblock_set_current_limit(arm_lowmem_limit);
  1079. build_mem_type_table();
  1080. prepare_page_table();
  1081. map_lowmem();
  1082. dma_contiguous_remap();
  1083. devicemaps_init(mdesc);
  1084. kmap_init();
  1085. top_pmd = pmd_off_k(0xffff0000);
  1086. /* allocate the zero page. */
  1087. zero_page = early_alloc(PAGE_SIZE);
  1088. bootmem_init();
  1089. empty_zero_page = virt_to_page(zero_page);
  1090. __flush_dcache_page(NULL, empty_zero_page);
  1091. }