platsmp.c 4.2 KB

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  1. /*
  2. * linux/arch/arm/mach-tegra/platsmp.c
  3. *
  4. * Copyright (C) 2002 ARM Ltd.
  5. * All Rights Reserved
  6. *
  7. * Copyright (C) 2009 Palm
  8. * All Rights Reserved
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/errno.h>
  16. #include <linux/delay.h>
  17. #include <linux/device.h>
  18. #include <linux/jiffies.h>
  19. #include <linux/smp.h>
  20. #include <linux/io.h>
  21. #include <asm/cacheflush.h>
  22. #include <asm/hardware/gic.h>
  23. #include <asm/mach-types.h>
  24. #include <asm/smp_scu.h>
  25. #include <mach/clk.h>
  26. #include <mach/iomap.h>
  27. #include <mach/powergate.h>
  28. #include "fuse.h"
  29. #include "flowctrl.h"
  30. #include "reset.h"
  31. #include "tegra_cpu_car.h"
  32. #include "common.h"
  33. extern void tegra_secondary_startup(void);
  34. static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
  35. #define EVP_CPU_RESET_VECTOR \
  36. (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
  37. static void __cpuinit tegra_secondary_init(unsigned int cpu)
  38. {
  39. /*
  40. * if any interrupts are already enabled for the primary
  41. * core (e.g. timer irq), then they will not have been enabled
  42. * for us: do so
  43. */
  44. gic_secondary_init(0);
  45. }
  46. static int tegra20_power_up_cpu(unsigned int cpu)
  47. {
  48. /* Enable the CPU clock. */
  49. tegra_enable_cpu_clock(cpu);
  50. /* Clear flow controller CSR. */
  51. flowctrl_write_cpu_csr(cpu, 0);
  52. return 0;
  53. }
  54. static int tegra30_power_up_cpu(unsigned int cpu)
  55. {
  56. int ret, pwrgateid;
  57. unsigned long timeout;
  58. pwrgateid = tegra_cpu_powergate_id(cpu);
  59. if (pwrgateid < 0)
  60. return pwrgateid;
  61. /* If this is the first boot, toggle powergates directly. */
  62. if (!tegra_powergate_is_powered(pwrgateid)) {
  63. ret = tegra_powergate_power_on(pwrgateid);
  64. if (ret)
  65. return ret;
  66. /* Wait for the power to come up. */
  67. timeout = jiffies + 10*HZ;
  68. while (tegra_powergate_is_powered(pwrgateid)) {
  69. if (time_after(jiffies, timeout))
  70. return -ETIMEDOUT;
  71. udelay(10);
  72. }
  73. }
  74. /* CPU partition is powered. Enable the CPU clock. */
  75. tegra_enable_cpu_clock(cpu);
  76. udelay(10);
  77. /* Remove I/O clamps. */
  78. ret = tegra_powergate_remove_clamping(pwrgateid);
  79. udelay(10);
  80. /* Clear flow controller CSR. */
  81. flowctrl_write_cpu_csr(cpu, 0);
  82. return 0;
  83. }
  84. static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)
  85. {
  86. int status;
  87. /*
  88. * Force the CPU into reset. The CPU must remain in reset when the
  89. * flow controller state is cleared (which will cause the flow
  90. * controller to stop driving reset if the CPU has been power-gated
  91. * via the flow controller). This will have no effect on first boot
  92. * of the CPU since it should already be in reset.
  93. */
  94. tegra_put_cpu_in_reset(cpu);
  95. /*
  96. * Unhalt the CPU. If the flow controller was used to power-gate the
  97. * CPU this will cause the flow controller to stop driving reset.
  98. * The CPU will remain in reset because the clock and reset block
  99. * is now driving reset.
  100. */
  101. flowctrl_write_cpu_halt(cpu, 0);
  102. switch (tegra_chip_id) {
  103. case TEGRA20:
  104. status = tegra20_power_up_cpu(cpu);
  105. break;
  106. case TEGRA30:
  107. status = tegra30_power_up_cpu(cpu);
  108. break;
  109. default:
  110. status = -EINVAL;
  111. break;
  112. }
  113. if (status)
  114. goto done;
  115. /* Take the CPU out of reset. */
  116. tegra_cpu_out_of_reset(cpu);
  117. done:
  118. return status;
  119. }
  120. /*
  121. * Initialise the CPU possible map early - this describes the CPUs
  122. * which may be present or become present in the system.
  123. */
  124. static void __init tegra_smp_init_cpus(void)
  125. {
  126. unsigned int i, ncores = scu_get_core_count(scu_base);
  127. if (ncores > nr_cpu_ids) {
  128. pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
  129. ncores, nr_cpu_ids);
  130. ncores = nr_cpu_ids;
  131. }
  132. for (i = 0; i < ncores; i++)
  133. set_cpu_possible(i, true);
  134. set_smp_cross_call(gic_raise_softirq);
  135. }
  136. static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
  137. {
  138. tegra_cpu_reset_handler_init();
  139. scu_enable(scu_base);
  140. }
  141. struct smp_operations tegra_smp_ops __initdata = {
  142. .smp_init_cpus = tegra_smp_init_cpus,
  143. .smp_prepare_cpus = tegra_smp_prepare_cpus,
  144. .smp_secondary_init = tegra_secondary_init,
  145. .smp_boot_secondary = tegra_boot_secondary,
  146. #ifdef CONFIG_HOTPLUG_CPU
  147. .cpu_die = tegra_cpu_die,
  148. .cpu_disable = tegra_cpu_disable,
  149. #endif
  150. };