cpu-tegra.c 6.6 KB

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  1. /*
  2. * arch/arm/mach-tegra/cpu-tegra.c
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. *
  6. * Author:
  7. * Colin Cross <ccross@google.com>
  8. * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
  9. *
  10. * This software is licensed under the terms of the GNU General Public
  11. * License version 2, as published by the Free Software Foundation, and
  12. * may be copied, distributed, and modified under those terms.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/types.h>
  23. #include <linux/sched.h>
  24. #include <linux/cpufreq.h>
  25. #include <linux/delay.h>
  26. #include <linux/init.h>
  27. #include <linux/err.h>
  28. #include <linux/clk.h>
  29. #include <linux/io.h>
  30. #include <linux/suspend.h>
  31. #include <mach/clk.h>
  32. /* Frequency table index must be sequential starting at 0 */
  33. static struct cpufreq_frequency_table freq_table[] = {
  34. { 0, 216000 },
  35. { 1, 312000 },
  36. { 2, 456000 },
  37. { 3, 608000 },
  38. { 4, 760000 },
  39. { 5, 816000 },
  40. { 6, 912000 },
  41. { 7, 1000000 },
  42. { 8, CPUFREQ_TABLE_END },
  43. };
  44. #define NUM_CPUS 2
  45. static struct clk *cpu_clk;
  46. static struct clk *pll_x_clk;
  47. static struct clk *pll_p_clk;
  48. static struct clk *emc_clk;
  49. static unsigned long target_cpu_speed[NUM_CPUS];
  50. static DEFINE_MUTEX(tegra_cpu_lock);
  51. static bool is_suspended;
  52. static int tegra_verify_speed(struct cpufreq_policy *policy)
  53. {
  54. return cpufreq_frequency_table_verify(policy, freq_table);
  55. }
  56. static unsigned int tegra_getspeed(unsigned int cpu)
  57. {
  58. unsigned long rate;
  59. if (cpu >= NUM_CPUS)
  60. return 0;
  61. rate = clk_get_rate(cpu_clk) / 1000;
  62. return rate;
  63. }
  64. static int tegra_cpu_clk_set_rate(unsigned long rate)
  65. {
  66. int ret;
  67. /*
  68. * Take an extra reference to the main pll so it doesn't turn
  69. * off when we move the cpu off of it
  70. */
  71. clk_prepare_enable(pll_x_clk);
  72. ret = clk_set_parent(cpu_clk, pll_p_clk);
  73. if (ret) {
  74. pr_err("Failed to switch cpu to clock pll_p\n");
  75. goto out;
  76. }
  77. if (rate == clk_get_rate(pll_p_clk))
  78. goto out;
  79. ret = clk_set_rate(pll_x_clk, rate);
  80. if (ret) {
  81. pr_err("Failed to change pll_x to %lu\n", rate);
  82. goto out;
  83. }
  84. ret = clk_set_parent(cpu_clk, pll_x_clk);
  85. if (ret) {
  86. pr_err("Failed to switch cpu to clock pll_x\n");
  87. goto out;
  88. }
  89. out:
  90. clk_disable_unprepare(pll_x_clk);
  91. return ret;
  92. }
  93. static int tegra_update_cpu_speed(unsigned long rate)
  94. {
  95. int ret = 0;
  96. struct cpufreq_freqs freqs;
  97. freqs.old = tegra_getspeed(0);
  98. freqs.new = rate;
  99. if (freqs.old == freqs.new)
  100. return ret;
  101. /*
  102. * Vote on memory bus frequency based on cpu frequency
  103. * This sets the minimum frequency, display or avp may request higher
  104. */
  105. if (rate >= 816000)
  106. clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
  107. else if (rate >= 456000)
  108. clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
  109. else
  110. clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
  111. for_each_online_cpu(freqs.cpu)
  112. cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  113. #ifdef CONFIG_CPU_FREQ_DEBUG
  114. printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
  115. freqs.old, freqs.new);
  116. #endif
  117. ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
  118. if (ret) {
  119. pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
  120. freqs.new);
  121. return ret;
  122. }
  123. for_each_online_cpu(freqs.cpu)
  124. cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
  125. return 0;
  126. }
  127. static unsigned long tegra_cpu_highest_speed(void)
  128. {
  129. unsigned long rate = 0;
  130. int i;
  131. for_each_online_cpu(i)
  132. rate = max(rate, target_cpu_speed[i]);
  133. return rate;
  134. }
  135. static int tegra_target(struct cpufreq_policy *policy,
  136. unsigned int target_freq,
  137. unsigned int relation)
  138. {
  139. unsigned int idx;
  140. unsigned int freq;
  141. int ret = 0;
  142. mutex_lock(&tegra_cpu_lock);
  143. if (is_suspended) {
  144. ret = -EBUSY;
  145. goto out;
  146. }
  147. cpufreq_frequency_table_target(policy, freq_table, target_freq,
  148. relation, &idx);
  149. freq = freq_table[idx].frequency;
  150. target_cpu_speed[policy->cpu] = freq;
  151. ret = tegra_update_cpu_speed(tegra_cpu_highest_speed());
  152. out:
  153. mutex_unlock(&tegra_cpu_lock);
  154. return ret;
  155. }
  156. static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
  157. void *dummy)
  158. {
  159. mutex_lock(&tegra_cpu_lock);
  160. if (event == PM_SUSPEND_PREPARE) {
  161. is_suspended = true;
  162. pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
  163. freq_table[0].frequency);
  164. tegra_update_cpu_speed(freq_table[0].frequency);
  165. } else if (event == PM_POST_SUSPEND) {
  166. is_suspended = false;
  167. }
  168. mutex_unlock(&tegra_cpu_lock);
  169. return NOTIFY_OK;
  170. }
  171. static struct notifier_block tegra_cpu_pm_notifier = {
  172. .notifier_call = tegra_pm_notify,
  173. };
  174. static int tegra_cpu_init(struct cpufreq_policy *policy)
  175. {
  176. if (policy->cpu >= NUM_CPUS)
  177. return -EINVAL;
  178. cpu_clk = clk_get_sys(NULL, "cpu");
  179. if (IS_ERR(cpu_clk))
  180. return PTR_ERR(cpu_clk);
  181. pll_x_clk = clk_get_sys(NULL, "pll_x");
  182. if (IS_ERR(pll_x_clk))
  183. return PTR_ERR(pll_x_clk);
  184. pll_p_clk = clk_get_sys(NULL, "pll_p");
  185. if (IS_ERR(pll_p_clk))
  186. return PTR_ERR(pll_p_clk);
  187. emc_clk = clk_get_sys("cpu", "emc");
  188. if (IS_ERR(emc_clk)) {
  189. clk_put(cpu_clk);
  190. return PTR_ERR(emc_clk);
  191. }
  192. clk_prepare_enable(emc_clk);
  193. clk_prepare_enable(cpu_clk);
  194. cpufreq_frequency_table_cpuinfo(policy, freq_table);
  195. cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
  196. policy->cur = tegra_getspeed(policy->cpu);
  197. target_cpu_speed[policy->cpu] = policy->cur;
  198. /* FIXME: what's the actual transition time? */
  199. policy->cpuinfo.transition_latency = 300 * 1000;
  200. policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
  201. cpumask_copy(policy->related_cpus, cpu_possible_mask);
  202. if (policy->cpu == 0)
  203. register_pm_notifier(&tegra_cpu_pm_notifier);
  204. return 0;
  205. }
  206. static int tegra_cpu_exit(struct cpufreq_policy *policy)
  207. {
  208. cpufreq_frequency_table_cpuinfo(policy, freq_table);
  209. clk_disable_unprepare(emc_clk);
  210. clk_put(emc_clk);
  211. clk_put(cpu_clk);
  212. return 0;
  213. }
  214. static struct freq_attr *tegra_cpufreq_attr[] = {
  215. &cpufreq_freq_attr_scaling_available_freqs,
  216. NULL,
  217. };
  218. static struct cpufreq_driver tegra_cpufreq_driver = {
  219. .verify = tegra_verify_speed,
  220. .target = tegra_target,
  221. .get = tegra_getspeed,
  222. .init = tegra_cpu_init,
  223. .exit = tegra_cpu_exit,
  224. .name = "tegra",
  225. .attr = tegra_cpufreq_attr,
  226. };
  227. static int __init tegra_cpufreq_init(void)
  228. {
  229. return cpufreq_register_driver(&tegra_cpufreq_driver);
  230. }
  231. static void __exit tegra_cpufreq_exit(void)
  232. {
  233. cpufreq_unregister_driver(&tegra_cpufreq_driver);
  234. }
  235. MODULE_AUTHOR("Colin Cross <ccross@android.com>");
  236. MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
  237. MODULE_LICENSE("GPL");
  238. module_init(tegra_cpufreq_init);
  239. module_exit(tegra_cpufreq_exit);