omap_phy_internal.c 4.0 KB

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  1. /*
  2. * This file configures the internal USB PHY in OMAP4430. Used
  3. * with TWL6030 transceiver and MUSB on OMAP4430.
  4. *
  5. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * Author: Hema HK <hemahk@ti.com>
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. */
  23. #include <linux/types.h>
  24. #include <linux/delay.h>
  25. #include <linux/clk.h>
  26. #include <linux/io.h>
  27. #include <linux/err.h>
  28. #include <linux/usb.h>
  29. #include <plat/usb.h>
  30. #include "soc.h"
  31. #include "control.h"
  32. void am35x_musb_reset(void)
  33. {
  34. u32 regval;
  35. /* Reset the musb interface */
  36. regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
  37. regval |= AM35XX_USBOTGSS_SW_RST;
  38. omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
  39. regval &= ~AM35XX_USBOTGSS_SW_RST;
  40. omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
  41. regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
  42. }
  43. void am35x_musb_phy_power(u8 on)
  44. {
  45. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  46. u32 devconf2;
  47. if (on) {
  48. /*
  49. * Start the on-chip PHY and its PLL.
  50. */
  51. devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
  52. devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
  53. devconf2 |= CONF2_PHY_PLLON;
  54. omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
  55. pr_info(KERN_INFO "Waiting for PHY clock good...\n");
  56. while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
  57. & CONF2_PHYCLKGD)) {
  58. cpu_relax();
  59. if (time_after(jiffies, timeout)) {
  60. pr_err(KERN_ERR "musb PHY clock good timed out\n");
  61. break;
  62. }
  63. }
  64. } else {
  65. /*
  66. * Power down the on-chip PHY.
  67. */
  68. devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
  69. devconf2 &= ~CONF2_PHY_PLLON;
  70. devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
  71. omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
  72. }
  73. }
  74. void am35x_musb_clear_irq(void)
  75. {
  76. u32 regval;
  77. regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
  78. regval |= AM35XX_USBOTGSS_INT_CLR;
  79. omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
  80. regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
  81. }
  82. void am35x_set_mode(u8 musb_mode)
  83. {
  84. u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
  85. devconf2 &= ~CONF2_OTGMODE;
  86. switch (musb_mode) {
  87. case MUSB_HOST: /* Force VBUS valid, ID = 0 */
  88. devconf2 |= CONF2_FORCE_HOST;
  89. break;
  90. case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
  91. devconf2 |= CONF2_FORCE_DEVICE;
  92. break;
  93. case MUSB_OTG: /* Don't override the VBUS/ID comparators */
  94. devconf2 |= CONF2_NO_OVERRIDE;
  95. break;
  96. default:
  97. pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
  98. }
  99. omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
  100. }
  101. void ti81xx_musb_phy_power(u8 on)
  102. {
  103. void __iomem *scm_base = NULL;
  104. u32 usbphycfg;
  105. scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
  106. if (!scm_base) {
  107. pr_err("system control module ioremap failed\n");
  108. return;
  109. }
  110. usbphycfg = __raw_readl(scm_base + USBCTRL0);
  111. if (on) {
  112. if (cpu_is_ti816x()) {
  113. usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
  114. usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
  115. } else if (cpu_is_ti814x()) {
  116. usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
  117. | USBPHY_DPINPUT | USBPHY_DMINPUT);
  118. usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
  119. | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
  120. }
  121. } else {
  122. if (cpu_is_ti816x())
  123. usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
  124. else if (cpu_is_ti814x())
  125. usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
  126. }
  127. __raw_writel(usbphycfg, scm_base + USBCTRL0);
  128. iounmap(scm_base);
  129. }