omap4-common.c 6.4 KB

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  1. /*
  2. * OMAP4 specific common source file.
  3. *
  4. * Copyright (C) 2010 Texas Instruments, Inc.
  5. * Author:
  6. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  7. *
  8. *
  9. * This program is free software,you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/memblock.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/export.h>
  21. #include <asm/hardware/gic.h>
  22. #include <asm/hardware/cache-l2x0.h>
  23. #include <asm/mach/map.h>
  24. #include <asm/memblock.h>
  25. #include <plat/sram.h>
  26. #include <plat/omap-secure.h>
  27. #include <plat/mmc.h>
  28. #include "omap-wakeupgen.h"
  29. #include "soc.h"
  30. #include "common.h"
  31. #include "hsmmc.h"
  32. #include "omap4-sar-layout.h"
  33. #ifdef CONFIG_CACHE_L2X0
  34. static void __iomem *l2cache_base;
  35. #endif
  36. static void __iomem *sar_ram_base;
  37. #ifdef CONFIG_OMAP4_ERRATA_I688
  38. /* Used to implement memory barrier on DRAM path */
  39. #define OMAP4_DRAM_BARRIER_VA 0xfe600000
  40. void __iomem *dram_sync, *sram_sync;
  41. static phys_addr_t paddr;
  42. static u32 size;
  43. void omap_bus_sync(void)
  44. {
  45. if (dram_sync && sram_sync) {
  46. writel_relaxed(readl_relaxed(dram_sync), dram_sync);
  47. writel_relaxed(readl_relaxed(sram_sync), sram_sync);
  48. isb();
  49. }
  50. }
  51. EXPORT_SYMBOL(omap_bus_sync);
  52. /* Steal one page physical memory for barrier implementation */
  53. int __init omap_barrier_reserve_memblock(void)
  54. {
  55. size = ALIGN(PAGE_SIZE, SZ_1M);
  56. paddr = arm_memblock_steal(size, SZ_1M);
  57. return 0;
  58. }
  59. void __init omap_barriers_init(void)
  60. {
  61. struct map_desc dram_io_desc[1];
  62. dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
  63. dram_io_desc[0].pfn = __phys_to_pfn(paddr);
  64. dram_io_desc[0].length = size;
  65. dram_io_desc[0].type = MT_MEMORY_SO;
  66. iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
  67. dram_sync = (void __iomem *) dram_io_desc[0].virtual;
  68. sram_sync = (void __iomem *) OMAP4_SRAM_VA;
  69. pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
  70. (long long) paddr, dram_io_desc[0].virtual);
  71. }
  72. #else
  73. void __init omap_barriers_init(void)
  74. {}
  75. #endif
  76. void __init gic_init_irq(void)
  77. {
  78. void __iomem *omap_irq_base;
  79. void __iomem *gic_dist_base_addr;
  80. /* Static mapping, never released */
  81. gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
  82. BUG_ON(!gic_dist_base_addr);
  83. /* Static mapping, never released */
  84. omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
  85. BUG_ON(!omap_irq_base);
  86. omap_wakeupgen_init();
  87. gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
  88. }
  89. #ifdef CONFIG_CACHE_L2X0
  90. void __iomem *omap4_get_l2cache_base(void)
  91. {
  92. return l2cache_base;
  93. }
  94. static void omap4_l2x0_disable(void)
  95. {
  96. /* Disable PL310 L2 Cache controller */
  97. omap_smc1(0x102, 0x0);
  98. }
  99. static void omap4_l2x0_set_debug(unsigned long val)
  100. {
  101. /* Program PL310 L2 Cache controller debug register */
  102. omap_smc1(0x100, val);
  103. }
  104. static int __init omap_l2_cache_init(void)
  105. {
  106. u32 aux_ctrl = 0;
  107. /*
  108. * To avoid code running on other OMAPs in
  109. * multi-omap builds
  110. */
  111. if (!cpu_is_omap44xx())
  112. return -ENODEV;
  113. /* Static mapping, never released */
  114. l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
  115. if (WARN_ON(!l2cache_base))
  116. return -ENOMEM;
  117. /*
  118. * 16-way associativity, parity disabled
  119. * Way size - 32KB (es1.0)
  120. * Way size - 64KB (es2.0 +)
  121. */
  122. aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
  123. (0x1 << 25) |
  124. (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
  125. (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
  126. if (omap_rev() == OMAP4430_REV_ES1_0) {
  127. aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
  128. } else {
  129. aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
  130. (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
  131. (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  132. (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  133. (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
  134. }
  135. if (omap_rev() != OMAP4430_REV_ES1_0)
  136. omap_smc1(0x109, aux_ctrl);
  137. /* Enable PL310 L2 Cache controller */
  138. omap_smc1(0x102, 0x1);
  139. if (of_have_populated_dt())
  140. l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
  141. else
  142. l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
  143. /*
  144. * Override default outer_cache.disable with a OMAP4
  145. * specific one
  146. */
  147. outer_cache.disable = omap4_l2x0_disable;
  148. outer_cache.set_debug = omap4_l2x0_set_debug;
  149. return 0;
  150. }
  151. early_initcall(omap_l2_cache_init);
  152. #endif
  153. void __iomem *omap4_get_sar_ram_base(void)
  154. {
  155. return sar_ram_base;
  156. }
  157. /*
  158. * SAR RAM used to save and restore the HW
  159. * context in low power modes
  160. */
  161. static int __init omap4_sar_ram_init(void)
  162. {
  163. /*
  164. * To avoid code running on other OMAPs in
  165. * multi-omap builds
  166. */
  167. if (!cpu_is_omap44xx())
  168. return -ENOMEM;
  169. /* Static mapping, never released */
  170. sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
  171. if (WARN_ON(!sar_ram_base))
  172. return -ENOMEM;
  173. return 0;
  174. }
  175. early_initcall(omap4_sar_ram_init);
  176. static struct of_device_id irq_match[] __initdata = {
  177. { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
  178. { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
  179. { }
  180. };
  181. void __init omap_gic_of_init(void)
  182. {
  183. omap_wakeupgen_init();
  184. of_irq_init(irq_match);
  185. }
  186. #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  187. static int omap4_twl6030_hsmmc_late_init(struct device *dev)
  188. {
  189. int irq = 0;
  190. struct platform_device *pdev = container_of(dev,
  191. struct platform_device, dev);
  192. struct omap_mmc_platform_data *pdata = dev->platform_data;
  193. /* Setting MMC1 Card detect Irq */
  194. if (pdev->id == 0) {
  195. irq = twl6030_mmc_card_detect_config();
  196. if (irq < 0) {
  197. dev_err(dev, "%s: Error card detect config(%d)\n",
  198. __func__, irq);
  199. return irq;
  200. }
  201. pdata->slots[0].card_detect_irq = irq;
  202. pdata->slots[0].card_detect = twl6030_mmc_card_detect;
  203. }
  204. return 0;
  205. }
  206. static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
  207. {
  208. struct omap_mmc_platform_data *pdata;
  209. /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
  210. if (!dev) {
  211. pr_err("Failed %s\n", __func__);
  212. return;
  213. }
  214. pdata = dev->platform_data;
  215. pdata->init = omap4_twl6030_hsmmc_late_init;
  216. }
  217. int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  218. {
  219. struct omap2_hsmmc_info *c;
  220. omap_hsmmc_init(controllers);
  221. for (c = controllers; c->mmc; c++) {
  222. /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
  223. if (!c->pdev)
  224. continue;
  225. omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
  226. }
  227. return 0;
  228. }
  229. #else
  230. int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
  231. {
  232. return 0;
  233. }
  234. #endif