gpmc.c 33 KB

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  1. /*
  2. * GPMC support functions
  3. *
  4. * Copyright (C) 2005-2006 Nokia Corporation
  5. *
  6. * Author: Juha Yrjola
  7. *
  8. * Copyright (C) 2009 Texas Instruments
  9. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #undef DEBUG
  16. #include <linux/irq.h>
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/err.h>
  20. #include <linux/clk.h>
  21. #include <linux/ioport.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/io.h>
  24. #include <linux/module.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/platform_device.h>
  27. #include <asm/mach-types.h>
  28. #include <plat/gpmc.h>
  29. #include <plat/cpu.h>
  30. #include <plat/gpmc.h>
  31. #include <plat/sdrc.h>
  32. #include <plat/omap_device.h>
  33. #include "soc.h"
  34. #include "common.h"
  35. #define DEVICE_NAME "omap-gpmc"
  36. /* GPMC register offsets */
  37. #define GPMC_REVISION 0x00
  38. #define GPMC_SYSCONFIG 0x10
  39. #define GPMC_SYSSTATUS 0x14
  40. #define GPMC_IRQSTATUS 0x18
  41. #define GPMC_IRQENABLE 0x1c
  42. #define GPMC_TIMEOUT_CONTROL 0x40
  43. #define GPMC_ERR_ADDRESS 0x44
  44. #define GPMC_ERR_TYPE 0x48
  45. #define GPMC_CONFIG 0x50
  46. #define GPMC_STATUS 0x54
  47. #define GPMC_PREFETCH_CONFIG1 0x1e0
  48. #define GPMC_PREFETCH_CONFIG2 0x1e4
  49. #define GPMC_PREFETCH_CONTROL 0x1ec
  50. #define GPMC_PREFETCH_STATUS 0x1f0
  51. #define GPMC_ECC_CONFIG 0x1f4
  52. #define GPMC_ECC_CONTROL 0x1f8
  53. #define GPMC_ECC_SIZE_CONFIG 0x1fc
  54. #define GPMC_ECC1_RESULT 0x200
  55. #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
  56. /* GPMC ECC control settings */
  57. #define GPMC_ECC_CTRL_ECCCLEAR 0x100
  58. #define GPMC_ECC_CTRL_ECCDISABLE 0x000
  59. #define GPMC_ECC_CTRL_ECCREG1 0x001
  60. #define GPMC_ECC_CTRL_ECCREG2 0x002
  61. #define GPMC_ECC_CTRL_ECCREG3 0x003
  62. #define GPMC_ECC_CTRL_ECCREG4 0x004
  63. #define GPMC_ECC_CTRL_ECCREG5 0x005
  64. #define GPMC_ECC_CTRL_ECCREG6 0x006
  65. #define GPMC_ECC_CTRL_ECCREG7 0x007
  66. #define GPMC_ECC_CTRL_ECCREG8 0x008
  67. #define GPMC_ECC_CTRL_ECCREG9 0x009
  68. #define GPMC_CS0_OFFSET 0x60
  69. #define GPMC_CS_SIZE 0x30
  70. #define GPMC_MEM_START 0x00000000
  71. #define GPMC_MEM_END 0x3FFFFFFF
  72. #define BOOT_ROM_SPACE 0x100000 /* 1MB */
  73. #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
  74. #define GPMC_SECTION_SHIFT 28 /* 128 MB */
  75. #define CS_NUM_SHIFT 24
  76. #define ENABLE_PREFETCH (0x1 << 7)
  77. #define DMA_MPU_MODE 2
  78. #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
  79. #define GPMC_REVISION_MINOR(l) (l & 0xf)
  80. #define GPMC_HAS_WR_ACCESS 0x1
  81. #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
  82. /* XXX: Only NAND irq has been considered,currently these are the only ones used
  83. */
  84. #define GPMC_NR_IRQ 2
  85. struct gpmc_client_irq {
  86. unsigned irq;
  87. u32 bitmask;
  88. };
  89. /* Structure to save gpmc cs context */
  90. struct gpmc_cs_config {
  91. u32 config1;
  92. u32 config2;
  93. u32 config3;
  94. u32 config4;
  95. u32 config5;
  96. u32 config6;
  97. u32 config7;
  98. int is_valid;
  99. };
  100. /*
  101. * Structure to save/restore gpmc context
  102. * to support core off on OMAP3
  103. */
  104. struct omap3_gpmc_regs {
  105. u32 sysconfig;
  106. u32 irqenable;
  107. u32 timeout_ctrl;
  108. u32 config;
  109. u32 prefetch_config1;
  110. u32 prefetch_config2;
  111. u32 prefetch_control;
  112. struct gpmc_cs_config cs_context[GPMC_CS_NUM];
  113. };
  114. static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
  115. static struct irq_chip gpmc_irq_chip;
  116. static unsigned gpmc_irq_start;
  117. static struct resource gpmc_mem_root;
  118. static struct resource gpmc_cs_mem[GPMC_CS_NUM];
  119. static DEFINE_SPINLOCK(gpmc_mem_lock);
  120. static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
  121. static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
  122. static struct device *gpmc_dev;
  123. static int gpmc_irq;
  124. static resource_size_t phys_base, mem_size;
  125. static unsigned gpmc_capability;
  126. static void __iomem *gpmc_base;
  127. static struct clk *gpmc_l3_clk;
  128. static irqreturn_t gpmc_handle_irq(int irq, void *dev);
  129. static void gpmc_write_reg(int idx, u32 val)
  130. {
  131. __raw_writel(val, gpmc_base + idx);
  132. }
  133. static u32 gpmc_read_reg(int idx)
  134. {
  135. return __raw_readl(gpmc_base + idx);
  136. }
  137. static void gpmc_cs_write_byte(int cs, int idx, u8 val)
  138. {
  139. void __iomem *reg_addr;
  140. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  141. __raw_writeb(val, reg_addr);
  142. }
  143. static u8 gpmc_cs_read_byte(int cs, int idx)
  144. {
  145. void __iomem *reg_addr;
  146. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  147. return __raw_readb(reg_addr);
  148. }
  149. void gpmc_cs_write_reg(int cs, int idx, u32 val)
  150. {
  151. void __iomem *reg_addr;
  152. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  153. __raw_writel(val, reg_addr);
  154. }
  155. u32 gpmc_cs_read_reg(int cs, int idx)
  156. {
  157. void __iomem *reg_addr;
  158. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  159. return __raw_readl(reg_addr);
  160. }
  161. /* TODO: Add support for gpmc_fck to clock framework and use it */
  162. unsigned long gpmc_get_fclk_period(void)
  163. {
  164. unsigned long rate = clk_get_rate(gpmc_l3_clk);
  165. if (rate == 0) {
  166. printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
  167. return 0;
  168. }
  169. rate /= 1000;
  170. rate = 1000000000 / rate; /* In picoseconds */
  171. return rate;
  172. }
  173. unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
  174. {
  175. unsigned long tick_ps;
  176. /* Calculate in picosecs to yield more exact results */
  177. tick_ps = gpmc_get_fclk_period();
  178. return (time_ns * 1000 + tick_ps - 1) / tick_ps;
  179. }
  180. unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
  181. {
  182. unsigned long tick_ps;
  183. /* Calculate in picosecs to yield more exact results */
  184. tick_ps = gpmc_get_fclk_period();
  185. return (time_ps + tick_ps - 1) / tick_ps;
  186. }
  187. unsigned int gpmc_ticks_to_ns(unsigned int ticks)
  188. {
  189. return ticks * gpmc_get_fclk_period() / 1000;
  190. }
  191. unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
  192. {
  193. unsigned long ticks = gpmc_ns_to_ticks(time_ns);
  194. return ticks * gpmc_get_fclk_period() / 1000;
  195. }
  196. #ifdef DEBUG
  197. static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
  198. int time, const char *name)
  199. #else
  200. static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
  201. int time)
  202. #endif
  203. {
  204. u32 l;
  205. int ticks, mask, nr_bits;
  206. if (time == 0)
  207. ticks = 0;
  208. else
  209. ticks = gpmc_ns_to_ticks(time);
  210. nr_bits = end_bit - st_bit + 1;
  211. if (ticks >= 1 << nr_bits) {
  212. #ifdef DEBUG
  213. printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
  214. cs, name, time, ticks, 1 << nr_bits);
  215. #endif
  216. return -1;
  217. }
  218. mask = (1 << nr_bits) - 1;
  219. l = gpmc_cs_read_reg(cs, reg);
  220. #ifdef DEBUG
  221. printk(KERN_INFO
  222. "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
  223. cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
  224. (l >> st_bit) & mask, time);
  225. #endif
  226. l &= ~(mask << st_bit);
  227. l |= ticks << st_bit;
  228. gpmc_cs_write_reg(cs, reg, l);
  229. return 0;
  230. }
  231. #ifdef DEBUG
  232. #define GPMC_SET_ONE(reg, st, end, field) \
  233. if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
  234. t->field, #field) < 0) \
  235. return -1
  236. #else
  237. #define GPMC_SET_ONE(reg, st, end, field) \
  238. if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
  239. return -1
  240. #endif
  241. int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
  242. {
  243. int div;
  244. u32 l;
  245. l = sync_clk + (gpmc_get_fclk_period() - 1);
  246. div = l / gpmc_get_fclk_period();
  247. if (div > 4)
  248. return -1;
  249. if (div <= 0)
  250. div = 1;
  251. return div;
  252. }
  253. int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
  254. {
  255. int div;
  256. u32 l;
  257. div = gpmc_cs_calc_divider(cs, t->sync_clk);
  258. if (div < 0)
  259. return div;
  260. GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
  261. GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
  262. GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
  263. GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
  264. GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
  265. GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
  266. GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
  267. GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
  268. GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
  269. GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
  270. GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
  271. GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
  272. GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
  273. GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
  274. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
  275. GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
  276. if (gpmc_capability & GPMC_HAS_WR_ACCESS)
  277. GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
  278. /* caller is expected to have initialized CONFIG1 to cover
  279. * at least sync vs async
  280. */
  281. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  282. if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
  283. #ifdef DEBUG
  284. printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
  285. cs, (div * gpmc_get_fclk_period()) / 1000, div);
  286. #endif
  287. l &= ~0x03;
  288. l |= (div - 1);
  289. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
  290. }
  291. return 0;
  292. }
  293. static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
  294. {
  295. u32 l;
  296. u32 mask;
  297. mask = (1 << GPMC_SECTION_SHIFT) - size;
  298. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  299. l &= ~0x3f;
  300. l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
  301. l &= ~(0x0f << 8);
  302. l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
  303. l |= GPMC_CONFIG7_CSVALID;
  304. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  305. }
  306. static void gpmc_cs_disable_mem(int cs)
  307. {
  308. u32 l;
  309. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  310. l &= ~GPMC_CONFIG7_CSVALID;
  311. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  312. }
  313. static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
  314. {
  315. u32 l;
  316. u32 mask;
  317. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  318. *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
  319. mask = (l >> 8) & 0x0f;
  320. *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
  321. }
  322. static int gpmc_cs_mem_enabled(int cs)
  323. {
  324. u32 l;
  325. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  326. return l & GPMC_CONFIG7_CSVALID;
  327. }
  328. int gpmc_cs_set_reserved(int cs, int reserved)
  329. {
  330. if (cs > GPMC_CS_NUM)
  331. return -ENODEV;
  332. gpmc_cs_map &= ~(1 << cs);
  333. gpmc_cs_map |= (reserved ? 1 : 0) << cs;
  334. return 0;
  335. }
  336. int gpmc_cs_reserved(int cs)
  337. {
  338. if (cs > GPMC_CS_NUM)
  339. return -ENODEV;
  340. return gpmc_cs_map & (1 << cs);
  341. }
  342. static unsigned long gpmc_mem_align(unsigned long size)
  343. {
  344. int order;
  345. size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
  346. order = GPMC_CHUNK_SHIFT - 1;
  347. do {
  348. size >>= 1;
  349. order++;
  350. } while (size);
  351. size = 1 << order;
  352. return size;
  353. }
  354. static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
  355. {
  356. struct resource *res = &gpmc_cs_mem[cs];
  357. int r;
  358. size = gpmc_mem_align(size);
  359. spin_lock(&gpmc_mem_lock);
  360. res->start = base;
  361. res->end = base + size - 1;
  362. r = request_resource(&gpmc_mem_root, res);
  363. spin_unlock(&gpmc_mem_lock);
  364. return r;
  365. }
  366. static int gpmc_cs_delete_mem(int cs)
  367. {
  368. struct resource *res = &gpmc_cs_mem[cs];
  369. int r;
  370. spin_lock(&gpmc_mem_lock);
  371. r = release_resource(&gpmc_cs_mem[cs]);
  372. res->start = 0;
  373. res->end = 0;
  374. spin_unlock(&gpmc_mem_lock);
  375. return r;
  376. }
  377. int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
  378. {
  379. struct resource *res = &gpmc_cs_mem[cs];
  380. int r = -1;
  381. if (cs > GPMC_CS_NUM)
  382. return -ENODEV;
  383. size = gpmc_mem_align(size);
  384. if (size > (1 << GPMC_SECTION_SHIFT))
  385. return -ENOMEM;
  386. spin_lock(&gpmc_mem_lock);
  387. if (gpmc_cs_reserved(cs)) {
  388. r = -EBUSY;
  389. goto out;
  390. }
  391. if (gpmc_cs_mem_enabled(cs))
  392. r = adjust_resource(res, res->start & ~(size - 1), size);
  393. if (r < 0)
  394. r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
  395. size, NULL, NULL);
  396. if (r < 0)
  397. goto out;
  398. gpmc_cs_enable_mem(cs, res->start, resource_size(res));
  399. *base = res->start;
  400. gpmc_cs_set_reserved(cs, 1);
  401. out:
  402. spin_unlock(&gpmc_mem_lock);
  403. return r;
  404. }
  405. EXPORT_SYMBOL(gpmc_cs_request);
  406. void gpmc_cs_free(int cs)
  407. {
  408. spin_lock(&gpmc_mem_lock);
  409. if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
  410. printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
  411. BUG();
  412. spin_unlock(&gpmc_mem_lock);
  413. return;
  414. }
  415. gpmc_cs_disable_mem(cs);
  416. release_resource(&gpmc_cs_mem[cs]);
  417. gpmc_cs_set_reserved(cs, 0);
  418. spin_unlock(&gpmc_mem_lock);
  419. }
  420. EXPORT_SYMBOL(gpmc_cs_free);
  421. /**
  422. * gpmc_read_status - read access request to get the different gpmc status
  423. * @cmd: command type
  424. * @return status
  425. */
  426. int gpmc_read_status(int cmd)
  427. {
  428. int status = -EINVAL;
  429. u32 regval = 0;
  430. switch (cmd) {
  431. case GPMC_GET_IRQ_STATUS:
  432. status = gpmc_read_reg(GPMC_IRQSTATUS);
  433. break;
  434. case GPMC_PREFETCH_FIFO_CNT:
  435. regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
  436. status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
  437. break;
  438. case GPMC_PREFETCH_COUNT:
  439. regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
  440. status = GPMC_PREFETCH_STATUS_COUNT(regval);
  441. break;
  442. case GPMC_STATUS_BUFFER:
  443. regval = gpmc_read_reg(GPMC_STATUS);
  444. /* 1 : buffer is available to write */
  445. status = regval & GPMC_STATUS_BUFF_EMPTY;
  446. break;
  447. default:
  448. printk(KERN_ERR "gpmc_read_status: Not supported\n");
  449. }
  450. return status;
  451. }
  452. EXPORT_SYMBOL(gpmc_read_status);
  453. /**
  454. * gpmc_cs_configure - write request to configure gpmc
  455. * @cs: chip select number
  456. * @cmd: command type
  457. * @wval: value to write
  458. * @return status of the operation
  459. */
  460. int gpmc_cs_configure(int cs, int cmd, int wval)
  461. {
  462. int err = 0;
  463. u32 regval = 0;
  464. switch (cmd) {
  465. case GPMC_ENABLE_IRQ:
  466. gpmc_write_reg(GPMC_IRQENABLE, wval);
  467. break;
  468. case GPMC_SET_IRQ_STATUS:
  469. gpmc_write_reg(GPMC_IRQSTATUS, wval);
  470. break;
  471. case GPMC_CONFIG_WP:
  472. regval = gpmc_read_reg(GPMC_CONFIG);
  473. if (wval)
  474. regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
  475. else
  476. regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
  477. gpmc_write_reg(GPMC_CONFIG, regval);
  478. break;
  479. case GPMC_CONFIG_RDY_BSY:
  480. regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  481. if (wval)
  482. regval |= WR_RD_PIN_MONITORING;
  483. else
  484. regval &= ~WR_RD_PIN_MONITORING;
  485. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
  486. break;
  487. case GPMC_CONFIG_DEV_SIZE:
  488. regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  489. /* clear 2 target bits */
  490. regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
  491. /* set the proper value */
  492. regval |= GPMC_CONFIG1_DEVICESIZE(wval);
  493. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
  494. break;
  495. case GPMC_CONFIG_DEV_TYPE:
  496. regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  497. regval |= GPMC_CONFIG1_DEVICETYPE(wval);
  498. if (wval == GPMC_DEVICETYPE_NOR)
  499. regval |= GPMC_CONFIG1_MUXADDDATA;
  500. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
  501. break;
  502. default:
  503. printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
  504. err = -EINVAL;
  505. }
  506. return err;
  507. }
  508. EXPORT_SYMBOL(gpmc_cs_configure);
  509. /**
  510. * gpmc_nand_read - nand specific read access request
  511. * @cs: chip select number
  512. * @cmd: command type
  513. */
  514. int gpmc_nand_read(int cs, int cmd)
  515. {
  516. int rval = -EINVAL;
  517. switch (cmd) {
  518. case GPMC_NAND_DATA:
  519. rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
  520. break;
  521. default:
  522. printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
  523. }
  524. return rval;
  525. }
  526. EXPORT_SYMBOL(gpmc_nand_read);
  527. /**
  528. * gpmc_nand_write - nand specific write request
  529. * @cs: chip select number
  530. * @cmd: command type
  531. * @wval: value to write
  532. */
  533. int gpmc_nand_write(int cs, int cmd, int wval)
  534. {
  535. int err = 0;
  536. switch (cmd) {
  537. case GPMC_NAND_COMMAND:
  538. gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
  539. break;
  540. case GPMC_NAND_ADDRESS:
  541. gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
  542. break;
  543. case GPMC_NAND_DATA:
  544. gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
  545. default:
  546. printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
  547. err = -EINVAL;
  548. }
  549. return err;
  550. }
  551. EXPORT_SYMBOL(gpmc_nand_write);
  552. /**
  553. * gpmc_prefetch_enable - configures and starts prefetch transfer
  554. * @cs: cs (chip select) number
  555. * @fifo_th: fifo threshold to be used for read/ write
  556. * @dma_mode: dma mode enable (1) or disable (0)
  557. * @u32_count: number of bytes to be transferred
  558. * @is_write: prefetch read(0) or write post(1) mode
  559. */
  560. int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
  561. unsigned int u32_count, int is_write)
  562. {
  563. if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
  564. pr_err("gpmc: fifo threshold is not supported\n");
  565. return -1;
  566. } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
  567. /* Set the amount of bytes to be prefetched */
  568. gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
  569. /* Set dma/mpu mode, the prefetch read / post write and
  570. * enable the engine. Set which cs is has requested for.
  571. */
  572. gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
  573. PREFETCH_FIFOTHRESHOLD(fifo_th) |
  574. ENABLE_PREFETCH |
  575. (dma_mode << DMA_MPU_MODE) |
  576. (0x1 & is_write)));
  577. /* Start the prefetch engine */
  578. gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
  579. } else {
  580. return -EBUSY;
  581. }
  582. return 0;
  583. }
  584. EXPORT_SYMBOL(gpmc_prefetch_enable);
  585. /**
  586. * gpmc_prefetch_reset - disables and stops the prefetch engine
  587. */
  588. int gpmc_prefetch_reset(int cs)
  589. {
  590. u32 config1;
  591. /* check if the same module/cs is trying to reset */
  592. config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
  593. if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
  594. return -EINVAL;
  595. /* Stop the PFPW engine */
  596. gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
  597. /* Reset/disable the PFPW engine */
  598. gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
  599. return 0;
  600. }
  601. EXPORT_SYMBOL(gpmc_prefetch_reset);
  602. void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
  603. {
  604. reg->gpmc_status = gpmc_base + GPMC_STATUS;
  605. reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
  606. GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
  607. reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
  608. GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
  609. reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
  610. GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
  611. reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
  612. reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
  613. reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
  614. reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
  615. reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
  616. reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
  617. reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
  618. reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
  619. reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0;
  620. }
  621. int gpmc_get_client_irq(unsigned irq_config)
  622. {
  623. int i;
  624. if (hweight32(irq_config) > 1)
  625. return 0;
  626. for (i = 0; i < GPMC_NR_IRQ; i++)
  627. if (gpmc_client_irq[i].bitmask & irq_config)
  628. return gpmc_client_irq[i].irq;
  629. return 0;
  630. }
  631. static int gpmc_irq_endis(unsigned irq, bool endis)
  632. {
  633. int i;
  634. u32 regval;
  635. for (i = 0; i < GPMC_NR_IRQ; i++)
  636. if (irq == gpmc_client_irq[i].irq) {
  637. regval = gpmc_read_reg(GPMC_IRQENABLE);
  638. if (endis)
  639. regval |= gpmc_client_irq[i].bitmask;
  640. else
  641. regval &= ~gpmc_client_irq[i].bitmask;
  642. gpmc_write_reg(GPMC_IRQENABLE, regval);
  643. break;
  644. }
  645. return 0;
  646. }
  647. static void gpmc_irq_disable(struct irq_data *p)
  648. {
  649. gpmc_irq_endis(p->irq, false);
  650. }
  651. static void gpmc_irq_enable(struct irq_data *p)
  652. {
  653. gpmc_irq_endis(p->irq, true);
  654. }
  655. static void gpmc_irq_noop(struct irq_data *data) { }
  656. static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
  657. static int gpmc_setup_irq(void)
  658. {
  659. int i;
  660. u32 regval;
  661. if (!gpmc_irq)
  662. return -EINVAL;
  663. gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
  664. if (IS_ERR_VALUE(gpmc_irq_start)) {
  665. pr_err("irq_alloc_descs failed\n");
  666. return gpmc_irq_start;
  667. }
  668. gpmc_irq_chip.name = "gpmc";
  669. gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
  670. gpmc_irq_chip.irq_enable = gpmc_irq_enable;
  671. gpmc_irq_chip.irq_disable = gpmc_irq_disable;
  672. gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
  673. gpmc_irq_chip.irq_ack = gpmc_irq_noop;
  674. gpmc_irq_chip.irq_mask = gpmc_irq_noop;
  675. gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
  676. gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
  677. gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
  678. for (i = 0; i < GPMC_NR_IRQ; i++) {
  679. gpmc_client_irq[i].irq = gpmc_irq_start + i;
  680. irq_set_chip_and_handler(gpmc_client_irq[i].irq,
  681. &gpmc_irq_chip, handle_simple_irq);
  682. set_irq_flags(gpmc_client_irq[i].irq,
  683. IRQF_VALID | IRQF_NOAUTOEN);
  684. }
  685. /* Disable interrupts */
  686. gpmc_write_reg(GPMC_IRQENABLE, 0);
  687. /* clear interrupts */
  688. regval = gpmc_read_reg(GPMC_IRQSTATUS);
  689. gpmc_write_reg(GPMC_IRQSTATUS, regval);
  690. return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
  691. }
  692. static __devexit int gpmc_free_irq(void)
  693. {
  694. int i;
  695. if (gpmc_irq)
  696. free_irq(gpmc_irq, NULL);
  697. for (i = 0; i < GPMC_NR_IRQ; i++) {
  698. irq_set_handler(gpmc_client_irq[i].irq, NULL);
  699. irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
  700. irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
  701. }
  702. irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
  703. return 0;
  704. }
  705. static void __devexit gpmc_mem_exit(void)
  706. {
  707. int cs;
  708. for (cs = 0; cs < GPMC_CS_NUM; cs++) {
  709. if (!gpmc_cs_mem_enabled(cs))
  710. continue;
  711. gpmc_cs_delete_mem(cs);
  712. }
  713. }
  714. static void __devinit gpmc_mem_init(void)
  715. {
  716. int cs;
  717. unsigned long boot_rom_space = 0;
  718. /* never allocate the first page, to facilitate bug detection;
  719. * even if we didn't boot from ROM.
  720. */
  721. boot_rom_space = BOOT_ROM_SPACE;
  722. /* In apollon the CS0 is mapped as 0x0000 0000 */
  723. if (machine_is_omap_apollon())
  724. boot_rom_space = 0;
  725. gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
  726. gpmc_mem_root.end = GPMC_MEM_END;
  727. /* Reserve all regions that has been set up by bootloader */
  728. for (cs = 0; cs < GPMC_CS_NUM; cs++) {
  729. u32 base, size;
  730. if (!gpmc_cs_mem_enabled(cs))
  731. continue;
  732. gpmc_cs_get_memconf(cs, &base, &size);
  733. if (gpmc_cs_insert_mem(cs, base, size) < 0)
  734. BUG();
  735. }
  736. }
  737. static __devinit int gpmc_probe(struct platform_device *pdev)
  738. {
  739. u32 l;
  740. struct resource *res;
  741. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  742. if (res == NULL)
  743. return -ENOENT;
  744. phys_base = res->start;
  745. mem_size = resource_size(res);
  746. gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
  747. if (!gpmc_base) {
  748. dev_err(&pdev->dev, "error: request memory / ioremap\n");
  749. return -EADDRNOTAVAIL;
  750. }
  751. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  752. if (res == NULL)
  753. dev_warn(&pdev->dev, "Failed to get resource: irq\n");
  754. else
  755. gpmc_irq = res->start;
  756. gpmc_l3_clk = clk_get(&pdev->dev, "fck");
  757. if (IS_ERR(gpmc_l3_clk)) {
  758. dev_err(&pdev->dev, "error: clk_get\n");
  759. gpmc_irq = 0;
  760. return PTR_ERR(gpmc_l3_clk);
  761. }
  762. clk_prepare_enable(gpmc_l3_clk);
  763. gpmc_dev = &pdev->dev;
  764. l = gpmc_read_reg(GPMC_REVISION);
  765. if (GPMC_REVISION_MAJOR(l) > 0x4)
  766. gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
  767. dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
  768. GPMC_REVISION_MINOR(l));
  769. gpmc_mem_init();
  770. if (IS_ERR_VALUE(gpmc_setup_irq()))
  771. dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
  772. return 0;
  773. }
  774. static __devexit int gpmc_remove(struct platform_device *pdev)
  775. {
  776. gpmc_free_irq();
  777. gpmc_mem_exit();
  778. gpmc_dev = NULL;
  779. return 0;
  780. }
  781. static struct platform_driver gpmc_driver = {
  782. .probe = gpmc_probe,
  783. .remove = __devexit_p(gpmc_remove),
  784. .driver = {
  785. .name = DEVICE_NAME,
  786. .owner = THIS_MODULE,
  787. },
  788. };
  789. static __init int gpmc_init(void)
  790. {
  791. return platform_driver_register(&gpmc_driver);
  792. }
  793. static __exit void gpmc_exit(void)
  794. {
  795. platform_driver_unregister(&gpmc_driver);
  796. }
  797. postcore_initcall(gpmc_init);
  798. module_exit(gpmc_exit);
  799. static int __init omap_gpmc_init(void)
  800. {
  801. struct omap_hwmod *oh;
  802. struct platform_device *pdev;
  803. char *oh_name = "gpmc";
  804. oh = omap_hwmod_lookup(oh_name);
  805. if (!oh) {
  806. pr_err("Could not look up %s\n", oh_name);
  807. return -ENODEV;
  808. }
  809. pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
  810. WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
  811. return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
  812. }
  813. postcore_initcall(omap_gpmc_init);
  814. static irqreturn_t gpmc_handle_irq(int irq, void *dev)
  815. {
  816. int i;
  817. u32 regval;
  818. regval = gpmc_read_reg(GPMC_IRQSTATUS);
  819. if (!regval)
  820. return IRQ_NONE;
  821. for (i = 0; i < GPMC_NR_IRQ; i++)
  822. if (regval & gpmc_client_irq[i].bitmask)
  823. generic_handle_irq(gpmc_client_irq[i].irq);
  824. gpmc_write_reg(GPMC_IRQSTATUS, regval);
  825. return IRQ_HANDLED;
  826. }
  827. #ifdef CONFIG_ARCH_OMAP3
  828. static struct omap3_gpmc_regs gpmc_context;
  829. void omap3_gpmc_save_context(void)
  830. {
  831. int i;
  832. gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
  833. gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
  834. gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
  835. gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
  836. gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
  837. gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
  838. gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
  839. for (i = 0; i < GPMC_CS_NUM; i++) {
  840. gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
  841. if (gpmc_context.cs_context[i].is_valid) {
  842. gpmc_context.cs_context[i].config1 =
  843. gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
  844. gpmc_context.cs_context[i].config2 =
  845. gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
  846. gpmc_context.cs_context[i].config3 =
  847. gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
  848. gpmc_context.cs_context[i].config4 =
  849. gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
  850. gpmc_context.cs_context[i].config5 =
  851. gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
  852. gpmc_context.cs_context[i].config6 =
  853. gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
  854. gpmc_context.cs_context[i].config7 =
  855. gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
  856. }
  857. }
  858. }
  859. void omap3_gpmc_restore_context(void)
  860. {
  861. int i;
  862. gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
  863. gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
  864. gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
  865. gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
  866. gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
  867. gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
  868. gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
  869. for (i = 0; i < GPMC_CS_NUM; i++) {
  870. if (gpmc_context.cs_context[i].is_valid) {
  871. gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
  872. gpmc_context.cs_context[i].config1);
  873. gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
  874. gpmc_context.cs_context[i].config2);
  875. gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
  876. gpmc_context.cs_context[i].config3);
  877. gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
  878. gpmc_context.cs_context[i].config4);
  879. gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
  880. gpmc_context.cs_context[i].config5);
  881. gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
  882. gpmc_context.cs_context[i].config6);
  883. gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
  884. gpmc_context.cs_context[i].config7);
  885. }
  886. }
  887. }
  888. #endif /* CONFIG_ARCH_OMAP3 */
  889. /**
  890. * gpmc_enable_hwecc - enable hardware ecc functionality
  891. * @cs: chip select number
  892. * @mode: read/write mode
  893. * @dev_width: device bus width(1 for x16, 0 for x8)
  894. * @ecc_size: bytes for which ECC will be generated
  895. */
  896. int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
  897. {
  898. unsigned int val;
  899. /* check if ecc module is in used */
  900. if (gpmc_ecc_used != -EINVAL)
  901. return -EINVAL;
  902. gpmc_ecc_used = cs;
  903. /* clear ecc and enable bits */
  904. gpmc_write_reg(GPMC_ECC_CONTROL,
  905. GPMC_ECC_CTRL_ECCCLEAR |
  906. GPMC_ECC_CTRL_ECCREG1);
  907. /* program ecc and result sizes */
  908. val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
  909. gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
  910. switch (mode) {
  911. case GPMC_ECC_READ:
  912. case GPMC_ECC_WRITE:
  913. gpmc_write_reg(GPMC_ECC_CONTROL,
  914. GPMC_ECC_CTRL_ECCCLEAR |
  915. GPMC_ECC_CTRL_ECCREG1);
  916. break;
  917. case GPMC_ECC_READSYN:
  918. gpmc_write_reg(GPMC_ECC_CONTROL,
  919. GPMC_ECC_CTRL_ECCCLEAR |
  920. GPMC_ECC_CTRL_ECCDISABLE);
  921. break;
  922. default:
  923. printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
  924. break;
  925. }
  926. /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
  927. val = (dev_width << 7) | (cs << 1) | (0x1);
  928. gpmc_write_reg(GPMC_ECC_CONFIG, val);
  929. return 0;
  930. }
  931. EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
  932. /**
  933. * gpmc_calculate_ecc - generate non-inverted ecc bytes
  934. * @cs: chip select number
  935. * @dat: data pointer over which ecc is computed
  936. * @ecc_code: ecc code buffer
  937. *
  938. * Using non-inverted ECC is considered ugly since writing a blank
  939. * page (padding) will clear the ECC bytes. This is not a problem as long
  940. * no one is trying to write data on the seemingly unused page. Reading
  941. * an erased page will produce an ECC mismatch between generated and read
  942. * ECC bytes that has to be dealt with separately.
  943. */
  944. int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
  945. {
  946. unsigned int val = 0x0;
  947. if (gpmc_ecc_used != cs)
  948. return -EINVAL;
  949. /* read ecc result */
  950. val = gpmc_read_reg(GPMC_ECC1_RESULT);
  951. *ecc_code++ = val; /* P128e, ..., P1e */
  952. *ecc_code++ = val >> 16; /* P128o, ..., P1o */
  953. /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
  954. *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
  955. gpmc_ecc_used = -EINVAL;
  956. return 0;
  957. }
  958. EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
  959. #ifdef CONFIG_ARCH_OMAP3
  960. /**
  961. * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
  962. * @cs: chip select number
  963. * @nsectors: how many 512-byte sectors to process
  964. * @nerrors: how many errors to correct per sector (4 or 8)
  965. *
  966. * This function must be executed before any call to gpmc_enable_hwecc_bch.
  967. */
  968. int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
  969. {
  970. /* check if ecc module is in use */
  971. if (gpmc_ecc_used != -EINVAL)
  972. return -EINVAL;
  973. /* support only OMAP3 class */
  974. if (!cpu_is_omap34xx()) {
  975. printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
  976. return -EINVAL;
  977. }
  978. /*
  979. * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
  980. * Other chips may be added if confirmed to work.
  981. */
  982. if ((nerrors == 4) &&
  983. (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
  984. printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
  985. return -EINVAL;
  986. }
  987. /* sanity check */
  988. if (nsectors > 8) {
  989. printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
  990. nsectors);
  991. return -EINVAL;
  992. }
  993. return 0;
  994. }
  995. EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
  996. /**
  997. * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
  998. * @cs: chip select number
  999. * @mode: read/write mode
  1000. * @dev_width: device bus width(1 for x16, 0 for x8)
  1001. * @nsectors: how many 512-byte sectors to process
  1002. * @nerrors: how many errors to correct per sector (4 or 8)
  1003. */
  1004. int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
  1005. int nerrors)
  1006. {
  1007. unsigned int val;
  1008. /* check if ecc module is in use */
  1009. if (gpmc_ecc_used != -EINVAL)
  1010. return -EINVAL;
  1011. gpmc_ecc_used = cs;
  1012. /* clear ecc and enable bits */
  1013. gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
  1014. /*
  1015. * When using BCH, sector size is hardcoded to 512 bytes.
  1016. * Here we are using wrapping mode 6 both for reading and writing, with:
  1017. * size0 = 0 (no additional protected byte in spare area)
  1018. * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
  1019. */
  1020. gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
  1021. /* BCH configuration */
  1022. val = ((1 << 16) | /* enable BCH */
  1023. (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
  1024. (0x06 << 8) | /* wrap mode = 6 */
  1025. (dev_width << 7) | /* bus width */
  1026. (((nsectors-1) & 0x7) << 4) | /* number of sectors */
  1027. (cs << 1) | /* ECC CS */
  1028. (0x1)); /* enable ECC */
  1029. gpmc_write_reg(GPMC_ECC_CONFIG, val);
  1030. gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
  1031. return 0;
  1032. }
  1033. EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
  1034. /**
  1035. * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
  1036. * @cs: chip select number
  1037. * @dat: The pointer to data on which ecc is computed
  1038. * @ecc: The ecc output buffer
  1039. */
  1040. int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
  1041. {
  1042. int i;
  1043. unsigned long nsectors, reg, val1, val2;
  1044. if (gpmc_ecc_used != cs)
  1045. return -EINVAL;
  1046. nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
  1047. for (i = 0; i < nsectors; i++) {
  1048. reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
  1049. /* Read hw-computed remainder */
  1050. val1 = gpmc_read_reg(reg + 0);
  1051. val2 = gpmc_read_reg(reg + 4);
  1052. /*
  1053. * Add constant polynomial to remainder, in order to get an ecc
  1054. * sequence of 0xFFs for a buffer filled with 0xFFs; and
  1055. * left-justify the resulting polynomial.
  1056. */
  1057. *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
  1058. *ecc++ = 0x13 ^ ((val2 >> 4) & 0xFF);
  1059. *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
  1060. *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
  1061. *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
  1062. *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
  1063. *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
  1064. }
  1065. gpmc_ecc_used = -EINVAL;
  1066. return 0;
  1067. }
  1068. EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
  1069. /**
  1070. * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
  1071. * @cs: chip select number
  1072. * @dat: The pointer to data on which ecc is computed
  1073. * @ecc: The ecc output buffer
  1074. */
  1075. int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
  1076. {
  1077. int i;
  1078. unsigned long nsectors, reg, val1, val2, val3, val4;
  1079. if (gpmc_ecc_used != cs)
  1080. return -EINVAL;
  1081. nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
  1082. for (i = 0; i < nsectors; i++) {
  1083. reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
  1084. /* Read hw-computed remainder */
  1085. val1 = gpmc_read_reg(reg + 0);
  1086. val2 = gpmc_read_reg(reg + 4);
  1087. val3 = gpmc_read_reg(reg + 8);
  1088. val4 = gpmc_read_reg(reg + 12);
  1089. /*
  1090. * Add constant polynomial to remainder, in order to get an ecc
  1091. * sequence of 0xFFs for a buffer filled with 0xFFs.
  1092. */
  1093. *ecc++ = 0xef ^ (val4 & 0xFF);
  1094. *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
  1095. *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
  1096. *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
  1097. *ecc++ = 0xed ^ (val3 & 0xFF);
  1098. *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
  1099. *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
  1100. *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
  1101. *ecc++ = 0x97 ^ (val2 & 0xFF);
  1102. *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
  1103. *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
  1104. *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
  1105. *ecc++ = 0xb5 ^ (val1 & 0xFF);
  1106. }
  1107. gpmc_ecc_used = -EINVAL;
  1108. return 0;
  1109. }
  1110. EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
  1111. #endif /* CONFIG_ARCH_OMAP3 */