board-3430sdp.c 15 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/board-3430sdp.c
  3. *
  4. * Copyright (C) 2007 Texas Instruments
  5. *
  6. * Modified from mach-omap2/board-generic.c
  7. *
  8. * Initial code: Syed Mohammed Khasim
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/delay.h>
  18. #include <linux/input.h>
  19. #include <linux/input/matrix_keypad.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/i2c/twl.h>
  22. #include <linux/regulator/machine.h>
  23. #include <linux/io.h>
  24. #include <linux/gpio.h>
  25. #include <linux/mmc/host.h>
  26. #include <linux/platform_data/spi-omap2-mcspi.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/mach/arch.h>
  29. #include <asm/mach/map.h>
  30. #include <plat/usb.h>
  31. #include "common.h"
  32. #include <plat/dma.h>
  33. #include <plat/gpmc.h>
  34. #include <video/omapdss.h>
  35. #include <video/omap-panel-tfp410.h>
  36. #include "gpmc-smc91x.h"
  37. #include "board-flash.h"
  38. #include "mux.h"
  39. #include "sdram-qimonda-hyb18m512160af-6.h"
  40. #include "hsmmc.h"
  41. #include "pm.h"
  42. #include "control.h"
  43. #include "common-board-devices.h"
  44. #define CONFIG_DISABLE_HFCLK 1
  45. #define SDP3430_TS_GPIO_IRQ_SDPV1 3
  46. #define SDP3430_TS_GPIO_IRQ_SDPV2 2
  47. #define ENABLE_VAUX3_DEDICATED 0x03
  48. #define ENABLE_VAUX3_DEV_GRP 0x20
  49. #define TWL4030_MSECURE_GPIO 22
  50. static uint32_t board_keymap[] = {
  51. KEY(0, 0, KEY_LEFT),
  52. KEY(0, 1, KEY_RIGHT),
  53. KEY(0, 2, KEY_A),
  54. KEY(0, 3, KEY_B),
  55. KEY(0, 4, KEY_C),
  56. KEY(1, 0, KEY_DOWN),
  57. KEY(1, 1, KEY_UP),
  58. KEY(1, 2, KEY_E),
  59. KEY(1, 3, KEY_F),
  60. KEY(1, 4, KEY_G),
  61. KEY(2, 0, KEY_ENTER),
  62. KEY(2, 1, KEY_I),
  63. KEY(2, 2, KEY_J),
  64. KEY(2, 3, KEY_K),
  65. KEY(2, 4, KEY_3),
  66. KEY(3, 0, KEY_M),
  67. KEY(3, 1, KEY_N),
  68. KEY(3, 2, KEY_O),
  69. KEY(3, 3, KEY_P),
  70. KEY(3, 4, KEY_Q),
  71. KEY(4, 0, KEY_R),
  72. KEY(4, 1, KEY_4),
  73. KEY(4, 2, KEY_T),
  74. KEY(4, 3, KEY_U),
  75. KEY(4, 4, KEY_D),
  76. KEY(5, 0, KEY_V),
  77. KEY(5, 1, KEY_W),
  78. KEY(5, 2, KEY_L),
  79. KEY(5, 3, KEY_S),
  80. KEY(5, 4, KEY_H),
  81. 0
  82. };
  83. static struct matrix_keymap_data board_map_data = {
  84. .keymap = board_keymap,
  85. .keymap_size = ARRAY_SIZE(board_keymap),
  86. };
  87. static struct twl4030_keypad_data sdp3430_kp_data = {
  88. .keymap_data = &board_map_data,
  89. .rows = 5,
  90. .cols = 6,
  91. .rep = 1,
  92. };
  93. #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
  94. #define SDP3430_LCD_PANEL_ENABLE_GPIO 5
  95. static struct gpio sdp3430_dss_gpios[] __initdata = {
  96. {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" },
  97. {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
  98. };
  99. static void __init sdp3430_display_init(void)
  100. {
  101. int r;
  102. r = gpio_request_array(sdp3430_dss_gpios,
  103. ARRAY_SIZE(sdp3430_dss_gpios));
  104. if (r)
  105. printk(KERN_ERR "failed to get LCD control GPIOs\n");
  106. }
  107. static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
  108. {
  109. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
  110. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
  111. return 0;
  112. }
  113. static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
  114. {
  115. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
  116. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
  117. }
  118. static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
  119. {
  120. return 0;
  121. }
  122. static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
  123. {
  124. }
  125. static struct omap_dss_device sdp3430_lcd_device = {
  126. .name = "lcd",
  127. .driver_name = "sharp_ls_panel",
  128. .type = OMAP_DISPLAY_TYPE_DPI,
  129. .phy.dpi.data_lines = 16,
  130. .platform_enable = sdp3430_panel_enable_lcd,
  131. .platform_disable = sdp3430_panel_disable_lcd,
  132. };
  133. static struct tfp410_platform_data dvi_panel = {
  134. .power_down_gpio = -1,
  135. };
  136. static struct omap_dss_device sdp3430_dvi_device = {
  137. .name = "dvi",
  138. .type = OMAP_DISPLAY_TYPE_DPI,
  139. .driver_name = "tfp410",
  140. .data = &dvi_panel,
  141. .phy.dpi.data_lines = 24,
  142. };
  143. static struct omap_dss_device sdp3430_tv_device = {
  144. .name = "tv",
  145. .driver_name = "venc",
  146. .type = OMAP_DISPLAY_TYPE_VENC,
  147. .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
  148. .platform_enable = sdp3430_panel_enable_tv,
  149. .platform_disable = sdp3430_panel_disable_tv,
  150. };
  151. static struct omap_dss_device *sdp3430_dss_devices[] = {
  152. &sdp3430_lcd_device,
  153. &sdp3430_dvi_device,
  154. &sdp3430_tv_device,
  155. };
  156. static struct omap_dss_board_info sdp3430_dss_data = {
  157. .num_devices = ARRAY_SIZE(sdp3430_dss_devices),
  158. .devices = sdp3430_dss_devices,
  159. .default_device = &sdp3430_lcd_device,
  160. };
  161. static struct omap2_hsmmc_info mmc[] = {
  162. {
  163. .mmc = 1,
  164. /* 8 bits (default) requires S6.3 == ON,
  165. * so the SIM card isn't used; else 4 bits.
  166. */
  167. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  168. .gpio_wp = 4,
  169. .deferred = true,
  170. },
  171. {
  172. .mmc = 2,
  173. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  174. .gpio_wp = 7,
  175. .deferred = true,
  176. },
  177. {} /* Terminator */
  178. };
  179. static int sdp3430_twl_gpio_setup(struct device *dev,
  180. unsigned gpio, unsigned ngpio)
  181. {
  182. /* gpio + 0 is "mmc0_cd" (input/IRQ),
  183. * gpio + 1 is "mmc1_cd" (input/IRQ)
  184. */
  185. mmc[0].gpio_cd = gpio + 0;
  186. mmc[1].gpio_cd = gpio + 1;
  187. omap_hsmmc_late_init(mmc);
  188. /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
  189. gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
  190. /* gpio + 15 is "sub_lcd_nRST" (output) */
  191. gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
  192. return 0;
  193. }
  194. static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
  195. .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
  196. | BIT(16) | BIT(17),
  197. .setup = sdp3430_twl_gpio_setup,
  198. };
  199. /* regulator consumer mappings */
  200. /* ads7846 on SPI */
  201. static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
  202. REGULATOR_SUPPLY("vcc", "spi1.0"),
  203. };
  204. static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
  205. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
  206. };
  207. static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
  208. REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
  209. };
  210. static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
  211. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
  212. };
  213. /*
  214. * Apply all the fixed voltages since most versions of U-Boot
  215. * don't bother with that initialization.
  216. */
  217. /* VAUX1 for mainboard (irda and sub-lcd) */
  218. static struct regulator_init_data sdp3430_vaux1 = {
  219. .constraints = {
  220. .min_uV = 2800000,
  221. .max_uV = 2800000,
  222. .apply_uV = true,
  223. .valid_modes_mask = REGULATOR_MODE_NORMAL
  224. | REGULATOR_MODE_STANDBY,
  225. .valid_ops_mask = REGULATOR_CHANGE_MODE
  226. | REGULATOR_CHANGE_STATUS,
  227. },
  228. };
  229. /* VAUX2 for camera module */
  230. static struct regulator_init_data sdp3430_vaux2 = {
  231. .constraints = {
  232. .min_uV = 2800000,
  233. .max_uV = 2800000,
  234. .apply_uV = true,
  235. .valid_modes_mask = REGULATOR_MODE_NORMAL
  236. | REGULATOR_MODE_STANDBY,
  237. .valid_ops_mask = REGULATOR_CHANGE_MODE
  238. | REGULATOR_CHANGE_STATUS,
  239. },
  240. };
  241. /* VAUX3 for LCD board */
  242. static struct regulator_init_data sdp3430_vaux3 = {
  243. .constraints = {
  244. .min_uV = 2800000,
  245. .max_uV = 2800000,
  246. .apply_uV = true,
  247. .valid_modes_mask = REGULATOR_MODE_NORMAL
  248. | REGULATOR_MODE_STANDBY,
  249. .valid_ops_mask = REGULATOR_CHANGE_MODE
  250. | REGULATOR_CHANGE_STATUS,
  251. },
  252. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
  253. .consumer_supplies = sdp3430_vaux3_supplies,
  254. };
  255. /* VAUX4 for OMAP VDD_CSI2 (camera) */
  256. static struct regulator_init_data sdp3430_vaux4 = {
  257. .constraints = {
  258. .min_uV = 1800000,
  259. .max_uV = 1800000,
  260. .apply_uV = true,
  261. .valid_modes_mask = REGULATOR_MODE_NORMAL
  262. | REGULATOR_MODE_STANDBY,
  263. .valid_ops_mask = REGULATOR_CHANGE_MODE
  264. | REGULATOR_CHANGE_STATUS,
  265. },
  266. };
  267. /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
  268. static struct regulator_init_data sdp3430_vmmc1 = {
  269. .constraints = {
  270. .min_uV = 1850000,
  271. .max_uV = 3150000,
  272. .valid_modes_mask = REGULATOR_MODE_NORMAL
  273. | REGULATOR_MODE_STANDBY,
  274. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  275. | REGULATOR_CHANGE_MODE
  276. | REGULATOR_CHANGE_STATUS,
  277. },
  278. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
  279. .consumer_supplies = sdp3430_vmmc1_supplies,
  280. };
  281. /* VMMC2 for MMC2 card */
  282. static struct regulator_init_data sdp3430_vmmc2 = {
  283. .constraints = {
  284. .min_uV = 1850000,
  285. .max_uV = 1850000,
  286. .apply_uV = true,
  287. .valid_modes_mask = REGULATOR_MODE_NORMAL
  288. | REGULATOR_MODE_STANDBY,
  289. .valid_ops_mask = REGULATOR_CHANGE_MODE
  290. | REGULATOR_CHANGE_STATUS,
  291. },
  292. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
  293. .consumer_supplies = sdp3430_vmmc2_supplies,
  294. };
  295. /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
  296. static struct regulator_init_data sdp3430_vsim = {
  297. .constraints = {
  298. .min_uV = 1800000,
  299. .max_uV = 3000000,
  300. .valid_modes_mask = REGULATOR_MODE_NORMAL
  301. | REGULATOR_MODE_STANDBY,
  302. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  303. | REGULATOR_CHANGE_MODE
  304. | REGULATOR_CHANGE_STATUS,
  305. },
  306. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
  307. .consumer_supplies = sdp3430_vsim_supplies,
  308. };
  309. static struct twl4030_platform_data sdp3430_twldata = {
  310. /* platform_data for children goes here */
  311. .gpio = &sdp3430_gpio_data,
  312. .keypad = &sdp3430_kp_data,
  313. .vaux1 = &sdp3430_vaux1,
  314. .vaux2 = &sdp3430_vaux2,
  315. .vaux3 = &sdp3430_vaux3,
  316. .vaux4 = &sdp3430_vaux4,
  317. .vmmc1 = &sdp3430_vmmc1,
  318. .vmmc2 = &sdp3430_vmmc2,
  319. .vsim = &sdp3430_vsim,
  320. };
  321. static int __init omap3430_i2c_init(void)
  322. {
  323. /* i2c1 for PMIC only */
  324. omap3_pmic_get_config(&sdp3430_twldata,
  325. TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
  326. TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
  327. TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
  328. sdp3430_twldata.vdac->constraints.apply_uV = true;
  329. sdp3430_twldata.vpll2->constraints.apply_uV = true;
  330. sdp3430_twldata.vpll2->constraints.name = "VDVI";
  331. omap3_pmic_init("twl4030", &sdp3430_twldata);
  332. /* i2c2 on camera connector (for sensor control) and optional isp1301 */
  333. omap_register_i2c_bus(2, 400, NULL, 0);
  334. /* i2c3 on display connector (for DVI, tfp410) */
  335. omap_register_i2c_bus(3, 400, NULL, 0);
  336. return 0;
  337. }
  338. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  339. static struct omap_smc91x_platform_data board_smc91x_data = {
  340. .cs = 3,
  341. .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
  342. IORESOURCE_IRQ_LOWLEVEL,
  343. };
  344. static void __init board_smc91x_init(void)
  345. {
  346. if (omap_rev() > OMAP3430_REV_ES1_0)
  347. board_smc91x_data.gpio_irq = 6;
  348. else
  349. board_smc91x_data.gpio_irq = 29;
  350. gpmc_smc91x_init(&board_smc91x_data);
  351. }
  352. #else
  353. static inline void board_smc91x_init(void)
  354. {
  355. }
  356. #endif
  357. static void enable_board_wakeup_source(void)
  358. {
  359. /* T2 interrupt line (keypad) */
  360. omap_mux_init_signal("sys_nirq",
  361. OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
  362. }
  363. static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
  364. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  365. .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  366. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  367. .phy_reset = true,
  368. .reset_gpio_port[0] = 57,
  369. .reset_gpio_port[1] = 61,
  370. .reset_gpio_port[2] = -EINVAL
  371. };
  372. #ifdef CONFIG_OMAP_MUX
  373. static struct omap_board_mux board_mux[] __initdata = {
  374. { .reg_offset = OMAP_MUX_TERMINATOR },
  375. };
  376. #else
  377. #define board_mux NULL
  378. #endif
  379. /*
  380. * SDP3430 V2 Board CS organization
  381. * Different from SDP3430 V1. Now 4 switches used to specify CS
  382. *
  383. * See also the Switch S8 settings in the comments.
  384. */
  385. static char chip_sel_3430[][GPMC_CS_NUM] = {
  386. {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
  387. {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
  388. {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
  389. };
  390. static struct mtd_partition sdp_nor_partitions[] = {
  391. /* bootloader (U-Boot, etc) in first sector */
  392. {
  393. .name = "Bootloader-NOR",
  394. .offset = 0,
  395. .size = SZ_256K,
  396. .mask_flags = MTD_WRITEABLE, /* force read-only */
  397. },
  398. /* bootloader params in the next sector */
  399. {
  400. .name = "Params-NOR",
  401. .offset = MTDPART_OFS_APPEND,
  402. .size = SZ_256K,
  403. .mask_flags = 0,
  404. },
  405. /* kernel */
  406. {
  407. .name = "Kernel-NOR",
  408. .offset = MTDPART_OFS_APPEND,
  409. .size = SZ_2M,
  410. .mask_flags = 0
  411. },
  412. /* file system */
  413. {
  414. .name = "Filesystem-NOR",
  415. .offset = MTDPART_OFS_APPEND,
  416. .size = MTDPART_SIZ_FULL,
  417. .mask_flags = 0
  418. }
  419. };
  420. static struct mtd_partition sdp_onenand_partitions[] = {
  421. {
  422. .name = "X-Loader-OneNAND",
  423. .offset = 0,
  424. .size = 4 * (64 * 2048),
  425. .mask_flags = MTD_WRITEABLE /* force read-only */
  426. },
  427. {
  428. .name = "U-Boot-OneNAND",
  429. .offset = MTDPART_OFS_APPEND,
  430. .size = 2 * (64 * 2048),
  431. .mask_flags = MTD_WRITEABLE /* force read-only */
  432. },
  433. {
  434. .name = "U-Boot Environment-OneNAND",
  435. .offset = MTDPART_OFS_APPEND,
  436. .size = 1 * (64 * 2048),
  437. },
  438. {
  439. .name = "Kernel-OneNAND",
  440. .offset = MTDPART_OFS_APPEND,
  441. .size = 16 * (64 * 2048),
  442. },
  443. {
  444. .name = "File System-OneNAND",
  445. .offset = MTDPART_OFS_APPEND,
  446. .size = MTDPART_SIZ_FULL,
  447. },
  448. };
  449. static struct mtd_partition sdp_nand_partitions[] = {
  450. /* All the partition sizes are listed in terms of NAND block size */
  451. {
  452. .name = "X-Loader-NAND",
  453. .offset = 0,
  454. .size = 4 * (64 * 2048),
  455. .mask_flags = MTD_WRITEABLE, /* force read-only */
  456. },
  457. {
  458. .name = "U-Boot-NAND",
  459. .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
  460. .size = 10 * (64 * 2048),
  461. .mask_flags = MTD_WRITEABLE, /* force read-only */
  462. },
  463. {
  464. .name = "Boot Env-NAND",
  465. .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
  466. .size = 6 * (64 * 2048),
  467. },
  468. {
  469. .name = "Kernel-NAND",
  470. .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
  471. .size = 40 * (64 * 2048),
  472. },
  473. {
  474. .name = "File System - NAND",
  475. .size = MTDPART_SIZ_FULL,
  476. .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
  477. },
  478. };
  479. static struct flash_partitions sdp_flash_partitions[] = {
  480. {
  481. .parts = sdp_nor_partitions,
  482. .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
  483. },
  484. {
  485. .parts = sdp_onenand_partitions,
  486. .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
  487. },
  488. {
  489. .parts = sdp_nand_partitions,
  490. .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
  491. },
  492. };
  493. static void __init omap_3430sdp_init(void)
  494. {
  495. int gpio_pendown;
  496. omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
  497. omap_hsmmc_init(mmc);
  498. omap3430_i2c_init();
  499. omap_display_init(&sdp3430_dss_data);
  500. if (omap_rev() > OMAP3430_REV_ES1_0)
  501. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
  502. else
  503. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
  504. omap_ads7846_init(1, gpio_pendown, 310, NULL);
  505. omap_serial_init();
  506. omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
  507. usb_musb_init(NULL);
  508. board_smc91x_init();
  509. board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
  510. sdp3430_display_init();
  511. enable_board_wakeup_source();
  512. usbhs_init(&usbhs_bdata);
  513. }
  514. MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
  515. /* Maintainer: Syed Khasim - Texas Instruments Inc */
  516. .atag_offset = 0x100,
  517. .reserve = omap_reserve,
  518. .map_io = omap3_map_io,
  519. .init_early = omap3430_init_early,
  520. .init_irq = omap3_init_irq,
  521. .handle_irq = omap3_intc_handle_irq,
  522. .init_machine = omap_3430sdp_init,
  523. .init_late = omap3430_init_late,
  524. .timer = &omap3_timer,
  525. .restart = omap_prcm_restart,
  526. MACHINE_END