platsmp.c 4.9 KB

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  1. /* linux/arch/arm/mach-exynos4/platsmp.c
  2. *
  3. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
  7. *
  8. * Copyright (C) 2002 ARM Ltd.
  9. * All Rights Reserved
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/errno.h>
  17. #include <linux/delay.h>
  18. #include <linux/device.h>
  19. #include <linux/jiffies.h>
  20. #include <linux/smp.h>
  21. #include <linux/io.h>
  22. #include <asm/cacheflush.h>
  23. #include <asm/hardware/gic.h>
  24. #include <asm/smp_plat.h>
  25. #include <asm/smp_scu.h>
  26. #include <mach/hardware.h>
  27. #include <mach/regs-clock.h>
  28. #include <mach/regs-pmu.h>
  29. #include <plat/cpu.h>
  30. #include "common.h"
  31. extern void exynos4_secondary_startup(void);
  32. #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
  33. S5P_INFORM5 : S5P_VA_SYSRAM)
  34. /*
  35. * Write pen_release in a way that is guaranteed to be visible to all
  36. * observers, irrespective of whether they're taking part in coherency
  37. * or not. This is necessary for the hotplug code to work reliably.
  38. */
  39. static void write_pen_release(int val)
  40. {
  41. pen_release = val;
  42. smp_wmb();
  43. __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  44. outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  45. }
  46. static void __iomem *scu_base_addr(void)
  47. {
  48. return (void __iomem *)(S5P_VA_SCU);
  49. }
  50. static DEFINE_SPINLOCK(boot_lock);
  51. static void __cpuinit exynos_secondary_init(unsigned int cpu)
  52. {
  53. /*
  54. * if any interrupts are already enabled for the primary
  55. * core (e.g. timer irq), then they will not have been enabled
  56. * for us: do so
  57. */
  58. gic_secondary_init(0);
  59. /*
  60. * let the primary processor know we're out of the
  61. * pen, then head off into the C entry point
  62. */
  63. write_pen_release(-1);
  64. /*
  65. * Synchronise with the boot thread.
  66. */
  67. spin_lock(&boot_lock);
  68. spin_unlock(&boot_lock);
  69. }
  70. static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
  71. {
  72. unsigned long timeout;
  73. /*
  74. * Set synchronisation state between this boot processor
  75. * and the secondary one
  76. */
  77. spin_lock(&boot_lock);
  78. /*
  79. * The secondary processor is waiting to be released from
  80. * the holding pen - release it, then wait for it to flag
  81. * that it has been released by resetting pen_release.
  82. *
  83. * Note that "pen_release" is the hardware CPU ID, whereas
  84. * "cpu" is Linux's internal ID.
  85. */
  86. write_pen_release(cpu_logical_map(cpu));
  87. if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
  88. __raw_writel(S5P_CORE_LOCAL_PWR_EN,
  89. S5P_ARM_CORE1_CONFIGURATION);
  90. timeout = 10;
  91. /* wait max 10 ms until cpu1 is on */
  92. while ((__raw_readl(S5P_ARM_CORE1_STATUS)
  93. & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
  94. if (timeout-- == 0)
  95. break;
  96. mdelay(1);
  97. }
  98. if (timeout == 0) {
  99. printk(KERN_ERR "cpu1 power enable failed");
  100. spin_unlock(&boot_lock);
  101. return -ETIMEDOUT;
  102. }
  103. }
  104. /*
  105. * Send the secondary CPU a soft interrupt, thereby causing
  106. * the boot monitor to read the system wide flags register,
  107. * and branch to the address found there.
  108. */
  109. timeout = jiffies + (1 * HZ);
  110. while (time_before(jiffies, timeout)) {
  111. smp_rmb();
  112. __raw_writel(virt_to_phys(exynos4_secondary_startup),
  113. CPU1_BOOT_REG);
  114. gic_raise_softirq(cpumask_of(cpu), 0);
  115. if (pen_release == -1)
  116. break;
  117. udelay(10);
  118. }
  119. /*
  120. * now the secondary core is starting up let it run its
  121. * calibrations, then wait for it to finish
  122. */
  123. spin_unlock(&boot_lock);
  124. return pen_release != -1 ? -ENOSYS : 0;
  125. }
  126. /*
  127. * Initialise the CPU possible map early - this describes the CPUs
  128. * which may be present or become present in the system.
  129. */
  130. static void __init exynos_smp_init_cpus(void)
  131. {
  132. void __iomem *scu_base = scu_base_addr();
  133. unsigned int i, ncores;
  134. if (soc_is_exynos5250())
  135. ncores = 2;
  136. else
  137. ncores = scu_base ? scu_get_core_count(scu_base) : 1;
  138. /* sanity check */
  139. if (ncores > nr_cpu_ids) {
  140. pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
  141. ncores, nr_cpu_ids);
  142. ncores = nr_cpu_ids;
  143. }
  144. for (i = 0; i < ncores; i++)
  145. set_cpu_possible(i, true);
  146. set_smp_cross_call(gic_raise_softirq);
  147. }
  148. static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
  149. {
  150. if (!soc_is_exynos5250())
  151. scu_enable(scu_base_addr());
  152. /*
  153. * Write the address of secondary startup into the
  154. * system-wide flags register. The boot monitor waits
  155. * until it receives a soft interrupt, and then the
  156. * secondary CPU branches to this address.
  157. */
  158. __raw_writel(virt_to_phys(exynos4_secondary_startup),
  159. CPU1_BOOT_REG);
  160. }
  161. struct smp_operations exynos_smp_ops __initdata = {
  162. .smp_init_cpus = exynos_smp_init_cpus,
  163. .smp_prepare_cpus = exynos_smp_prepare_cpus,
  164. .smp_secondary_init = exynos_secondary_init,
  165. .smp_boot_secondary = exynos_boot_secondary,
  166. #ifdef CONFIG_HOTPLUG_CPU
  167. .cpu_die = exynos_cpu_die,
  168. #endif
  169. };