common.c 25 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Common Codes for EXYNOS
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irq.h>
  14. #include <linux/io.h>
  15. #include <linux/device.h>
  16. #include <linux/gpio.h>
  17. #include <linux/sched.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/of.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/export.h>
  22. #include <linux/irqdomain.h>
  23. #include <linux/of_address.h>
  24. #include <asm/proc-fns.h>
  25. #include <asm/exception.h>
  26. #include <asm/hardware/cache-l2x0.h>
  27. #include <asm/hardware/gic.h>
  28. #include <asm/mach/map.h>
  29. #include <asm/mach/irq.h>
  30. #include <asm/cacheflush.h>
  31. #include <mach/regs-irq.h>
  32. #include <mach/regs-pmu.h>
  33. #include <mach/regs-gpio.h>
  34. #include <mach/pmu.h>
  35. #include <plat/cpu.h>
  36. #include <plat/clock.h>
  37. #include <plat/devs.h>
  38. #include <plat/pm.h>
  39. #include <plat/sdhci.h>
  40. #include <plat/gpio-cfg.h>
  41. #include <plat/adc-core.h>
  42. #include <plat/fb-core.h>
  43. #include <plat/fimc-core.h>
  44. #include <plat/iic-core.h>
  45. #include <plat/tv-core.h>
  46. #include <plat/regs-serial.h>
  47. #include "common.h"
  48. #define L2_AUX_VAL 0x7C470001
  49. #define L2_AUX_MASK 0xC200ffff
  50. static const char name_exynos4210[] = "EXYNOS4210";
  51. static const char name_exynos4212[] = "EXYNOS4212";
  52. static const char name_exynos4412[] = "EXYNOS4412";
  53. static const char name_exynos5250[] = "EXYNOS5250";
  54. static void exynos4_map_io(void);
  55. static void exynos5_map_io(void);
  56. static void exynos4_init_clocks(int xtal);
  57. static void exynos5_init_clocks(int xtal);
  58. static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  59. static int exynos_init(void);
  60. static struct cpu_table cpu_ids[] __initdata = {
  61. {
  62. .idcode = EXYNOS4210_CPU_ID,
  63. .idmask = EXYNOS4_CPU_MASK,
  64. .map_io = exynos4_map_io,
  65. .init_clocks = exynos4_init_clocks,
  66. .init_uarts = exynos_init_uarts,
  67. .init = exynos_init,
  68. .name = name_exynos4210,
  69. }, {
  70. .idcode = EXYNOS4212_CPU_ID,
  71. .idmask = EXYNOS4_CPU_MASK,
  72. .map_io = exynos4_map_io,
  73. .init_clocks = exynos4_init_clocks,
  74. .init_uarts = exynos_init_uarts,
  75. .init = exynos_init,
  76. .name = name_exynos4212,
  77. }, {
  78. .idcode = EXYNOS4412_CPU_ID,
  79. .idmask = EXYNOS4_CPU_MASK,
  80. .map_io = exynos4_map_io,
  81. .init_clocks = exynos4_init_clocks,
  82. .init_uarts = exynos_init_uarts,
  83. .init = exynos_init,
  84. .name = name_exynos4412,
  85. }, {
  86. .idcode = EXYNOS5250_SOC_ID,
  87. .idmask = EXYNOS5_SOC_MASK,
  88. .map_io = exynos5_map_io,
  89. .init_clocks = exynos5_init_clocks,
  90. .init_uarts = exynos_init_uarts,
  91. .init = exynos_init,
  92. .name = name_exynos5250,
  93. },
  94. };
  95. /* Initial IO mappings */
  96. static struct map_desc exynos_iodesc[] __initdata = {
  97. {
  98. .virtual = (unsigned long)S5P_VA_CHIPID,
  99. .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
  100. .length = SZ_4K,
  101. .type = MT_DEVICE,
  102. },
  103. };
  104. static struct map_desc exynos4_iodesc[] __initdata = {
  105. {
  106. .virtual = (unsigned long)S3C_VA_SYS,
  107. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  108. .length = SZ_64K,
  109. .type = MT_DEVICE,
  110. }, {
  111. .virtual = (unsigned long)S3C_VA_TIMER,
  112. .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
  113. .length = SZ_16K,
  114. .type = MT_DEVICE,
  115. }, {
  116. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  117. .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
  118. .length = SZ_4K,
  119. .type = MT_DEVICE,
  120. }, {
  121. .virtual = (unsigned long)S5P_VA_SROMC,
  122. .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
  123. .length = SZ_4K,
  124. .type = MT_DEVICE,
  125. }, {
  126. .virtual = (unsigned long)S5P_VA_SYSTIMER,
  127. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  128. .length = SZ_4K,
  129. .type = MT_DEVICE,
  130. }, {
  131. .virtual = (unsigned long)S5P_VA_PMU,
  132. .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
  133. .length = SZ_64K,
  134. .type = MT_DEVICE,
  135. }, {
  136. .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
  137. .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  138. .length = SZ_4K,
  139. .type = MT_DEVICE,
  140. }, {
  141. .virtual = (unsigned long)S5P_VA_GIC_CPU,
  142. .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
  143. .length = SZ_64K,
  144. .type = MT_DEVICE,
  145. }, {
  146. .virtual = (unsigned long)S5P_VA_GIC_DIST,
  147. .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
  148. .length = SZ_64K,
  149. .type = MT_DEVICE,
  150. }, {
  151. .virtual = (unsigned long)S3C_VA_UART,
  152. .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
  153. .length = SZ_512K,
  154. .type = MT_DEVICE,
  155. }, {
  156. .virtual = (unsigned long)S5P_VA_CMU,
  157. .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
  158. .length = SZ_128K,
  159. .type = MT_DEVICE,
  160. }, {
  161. .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
  162. .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  163. .length = SZ_8K,
  164. .type = MT_DEVICE,
  165. }, {
  166. .virtual = (unsigned long)S5P_VA_L2CC,
  167. .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
  168. .length = SZ_4K,
  169. .type = MT_DEVICE,
  170. }, {
  171. .virtual = (unsigned long)S5P_VA_DMC0,
  172. .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
  173. .length = SZ_64K,
  174. .type = MT_DEVICE,
  175. }, {
  176. .virtual = (unsigned long)S5P_VA_DMC1,
  177. .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
  178. .length = SZ_64K,
  179. .type = MT_DEVICE,
  180. }, {
  181. .virtual = (unsigned long)S3C_VA_USB_HSPHY,
  182. .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
  183. .length = SZ_4K,
  184. .type = MT_DEVICE,
  185. },
  186. };
  187. static struct map_desc exynos4_iodesc0[] __initdata = {
  188. {
  189. .virtual = (unsigned long)S5P_VA_SYSRAM,
  190. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
  191. .length = SZ_4K,
  192. .type = MT_DEVICE,
  193. },
  194. };
  195. static struct map_desc exynos4_iodesc1[] __initdata = {
  196. {
  197. .virtual = (unsigned long)S5P_VA_SYSRAM,
  198. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
  199. .length = SZ_4K,
  200. .type = MT_DEVICE,
  201. },
  202. };
  203. static struct map_desc exynos5_iodesc[] __initdata = {
  204. {
  205. .virtual = (unsigned long)S3C_VA_SYS,
  206. .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
  207. .length = SZ_64K,
  208. .type = MT_DEVICE,
  209. }, {
  210. .virtual = (unsigned long)S3C_VA_TIMER,
  211. .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
  212. .length = SZ_16K,
  213. .type = MT_DEVICE,
  214. }, {
  215. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  216. .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
  217. .length = SZ_4K,
  218. .type = MT_DEVICE,
  219. }, {
  220. .virtual = (unsigned long)S5P_VA_SROMC,
  221. .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
  222. .length = SZ_4K,
  223. .type = MT_DEVICE,
  224. }, {
  225. .virtual = (unsigned long)S5P_VA_SYSTIMER,
  226. .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
  227. .length = SZ_4K,
  228. .type = MT_DEVICE,
  229. }, {
  230. .virtual = (unsigned long)S5P_VA_SYSRAM,
  231. .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
  232. .length = SZ_4K,
  233. .type = MT_DEVICE,
  234. }, {
  235. .virtual = (unsigned long)S5P_VA_CMU,
  236. .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
  237. .length = 144 * SZ_1K,
  238. .type = MT_DEVICE,
  239. }, {
  240. .virtual = (unsigned long)S5P_VA_PMU,
  241. .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
  242. .length = SZ_64K,
  243. .type = MT_DEVICE,
  244. }, {
  245. .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
  246. .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
  247. .length = SZ_4K,
  248. .type = MT_DEVICE,
  249. }, {
  250. .virtual = (unsigned long)S3C_VA_UART,
  251. .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
  252. .length = SZ_512K,
  253. .type = MT_DEVICE,
  254. }, {
  255. .virtual = (unsigned long)S5P_VA_GIC_CPU,
  256. .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
  257. .length = SZ_8K,
  258. .type = MT_DEVICE,
  259. }, {
  260. .virtual = (unsigned long)S5P_VA_GIC_DIST,
  261. .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
  262. .length = SZ_4K,
  263. .type = MT_DEVICE,
  264. },
  265. };
  266. void exynos4_restart(char mode, const char *cmd)
  267. {
  268. __raw_writel(0x1, S5P_SWRESET);
  269. }
  270. void exynos5_restart(char mode, const char *cmd)
  271. {
  272. __raw_writel(0x1, EXYNOS_SWRESET);
  273. }
  274. void __init exynos_init_late(void)
  275. {
  276. exynos_pm_late_initcall();
  277. }
  278. /*
  279. * exynos_map_io
  280. *
  281. * register the standard cpu IO areas
  282. */
  283. void __init exynos_init_io(struct map_desc *mach_desc, int size)
  284. {
  285. /* initialize the io descriptors we need for initialization */
  286. iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
  287. if (mach_desc)
  288. iotable_init(mach_desc, size);
  289. /* detect cpu id and rev. */
  290. s5p_init_cpu(S5P_VA_CHIPID);
  291. s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
  292. }
  293. static void __init exynos4_map_io(void)
  294. {
  295. iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
  296. if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
  297. iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
  298. else
  299. iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
  300. /* initialize device information early */
  301. exynos4_default_sdhci0();
  302. exynos4_default_sdhci1();
  303. exynos4_default_sdhci2();
  304. exynos4_default_sdhci3();
  305. s3c_adc_setname("samsung-adc-v3");
  306. s3c_fimc_setname(0, "exynos4-fimc");
  307. s3c_fimc_setname(1, "exynos4-fimc");
  308. s3c_fimc_setname(2, "exynos4-fimc");
  309. s3c_fimc_setname(3, "exynos4-fimc");
  310. s3c_sdhci_setname(0, "exynos4-sdhci");
  311. s3c_sdhci_setname(1, "exynos4-sdhci");
  312. s3c_sdhci_setname(2, "exynos4-sdhci");
  313. s3c_sdhci_setname(3, "exynos4-sdhci");
  314. /* The I2C bus controllers are directly compatible with s3c2440 */
  315. s3c_i2c0_setname("s3c2440-i2c");
  316. s3c_i2c1_setname("s3c2440-i2c");
  317. s3c_i2c2_setname("s3c2440-i2c");
  318. s5p_fb_setname(0, "exynos4-fb");
  319. s5p_hdmi_setname("exynos4-hdmi");
  320. }
  321. static void __init exynos5_map_io(void)
  322. {
  323. iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
  324. s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
  325. s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
  326. s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
  327. s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
  328. s3c_sdhci_setname(0, "exynos4-sdhci");
  329. s3c_sdhci_setname(1, "exynos4-sdhci");
  330. s3c_sdhci_setname(2, "exynos4-sdhci");
  331. s3c_sdhci_setname(3, "exynos4-sdhci");
  332. /* The I2C bus controllers are directly compatible with s3c2440 */
  333. s3c_i2c0_setname("s3c2440-i2c");
  334. s3c_i2c1_setname("s3c2440-i2c");
  335. s3c_i2c2_setname("s3c2440-i2c");
  336. }
  337. static void __init exynos4_init_clocks(int xtal)
  338. {
  339. printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
  340. s3c24xx_register_baseclocks(xtal);
  341. s5p_register_clocks(xtal);
  342. if (soc_is_exynos4210())
  343. exynos4210_register_clocks();
  344. else if (soc_is_exynos4212() || soc_is_exynos4412())
  345. exynos4212_register_clocks();
  346. exynos4_register_clocks();
  347. exynos4_setup_clocks();
  348. }
  349. static void __init exynos5_init_clocks(int xtal)
  350. {
  351. printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
  352. s3c24xx_register_baseclocks(xtal);
  353. s5p_register_clocks(xtal);
  354. exynos5_register_clocks();
  355. exynos5_setup_clocks();
  356. }
  357. #define COMBINER_ENABLE_SET 0x0
  358. #define COMBINER_ENABLE_CLEAR 0x4
  359. #define COMBINER_INT_STATUS 0xC
  360. static DEFINE_SPINLOCK(irq_controller_lock);
  361. struct combiner_chip_data {
  362. unsigned int irq_offset;
  363. unsigned int irq_mask;
  364. void __iomem *base;
  365. };
  366. static struct irq_domain *combiner_irq_domain;
  367. static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
  368. static inline void __iomem *combiner_base(struct irq_data *data)
  369. {
  370. struct combiner_chip_data *combiner_data =
  371. irq_data_get_irq_chip_data(data);
  372. return combiner_data->base;
  373. }
  374. static void combiner_mask_irq(struct irq_data *data)
  375. {
  376. u32 mask = 1 << (data->hwirq % 32);
  377. __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
  378. }
  379. static void combiner_unmask_irq(struct irq_data *data)
  380. {
  381. u32 mask = 1 << (data->hwirq % 32);
  382. __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
  383. }
  384. static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
  385. {
  386. struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
  387. struct irq_chip *chip = irq_get_chip(irq);
  388. unsigned int cascade_irq, combiner_irq;
  389. unsigned long status;
  390. chained_irq_enter(chip, desc);
  391. spin_lock(&irq_controller_lock);
  392. status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
  393. spin_unlock(&irq_controller_lock);
  394. status &= chip_data->irq_mask;
  395. if (status == 0)
  396. goto out;
  397. combiner_irq = __ffs(status);
  398. cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
  399. if (unlikely(cascade_irq >= NR_IRQS))
  400. do_bad_IRQ(cascade_irq, desc);
  401. else
  402. generic_handle_irq(cascade_irq);
  403. out:
  404. chained_irq_exit(chip, desc);
  405. }
  406. static struct irq_chip combiner_chip = {
  407. .name = "COMBINER",
  408. .irq_mask = combiner_mask_irq,
  409. .irq_unmask = combiner_unmask_irq,
  410. };
  411. static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
  412. {
  413. unsigned int max_nr;
  414. if (soc_is_exynos5250())
  415. max_nr = EXYNOS5_MAX_COMBINER_NR;
  416. else
  417. max_nr = EXYNOS4_MAX_COMBINER_NR;
  418. if (combiner_nr >= max_nr)
  419. BUG();
  420. if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
  421. BUG();
  422. irq_set_chained_handler(irq, combiner_handle_cascade_irq);
  423. }
  424. static void __init combiner_init_one(unsigned int combiner_nr,
  425. void __iomem *base)
  426. {
  427. combiner_data[combiner_nr].base = base;
  428. combiner_data[combiner_nr].irq_offset = irq_find_mapping(
  429. combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
  430. combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
  431. /* Disable all interrupts */
  432. __raw_writel(combiner_data[combiner_nr].irq_mask,
  433. base + COMBINER_ENABLE_CLEAR);
  434. }
  435. #ifdef CONFIG_OF
  436. static int combiner_irq_domain_xlate(struct irq_domain *d,
  437. struct device_node *controller,
  438. const u32 *intspec, unsigned int intsize,
  439. unsigned long *out_hwirq,
  440. unsigned int *out_type)
  441. {
  442. if (d->of_node != controller)
  443. return -EINVAL;
  444. if (intsize < 2)
  445. return -EINVAL;
  446. *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
  447. *out_type = 0;
  448. return 0;
  449. }
  450. #else
  451. static int combiner_irq_domain_xlate(struct irq_domain *d,
  452. struct device_node *controller,
  453. const u32 *intspec, unsigned int intsize,
  454. unsigned long *out_hwirq,
  455. unsigned int *out_type)
  456. {
  457. return -EINVAL;
  458. }
  459. #endif
  460. static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
  461. irq_hw_number_t hw)
  462. {
  463. irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
  464. irq_set_chip_data(irq, &combiner_data[hw >> 3]);
  465. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  466. return 0;
  467. }
  468. static struct irq_domain_ops combiner_irq_domain_ops = {
  469. .xlate = combiner_irq_domain_xlate,
  470. .map = combiner_irq_domain_map,
  471. };
  472. static void __init combiner_init(void __iomem *combiner_base,
  473. struct device_node *np)
  474. {
  475. int i, irq, irq_base;
  476. unsigned int max_nr, nr_irq;
  477. if (np) {
  478. if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
  479. pr_warning("%s: number of combiners not specified, "
  480. "setting default as %d.\n",
  481. __func__, EXYNOS4_MAX_COMBINER_NR);
  482. max_nr = EXYNOS4_MAX_COMBINER_NR;
  483. }
  484. } else {
  485. max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
  486. EXYNOS4_MAX_COMBINER_NR;
  487. }
  488. nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
  489. irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
  490. if (IS_ERR_VALUE(irq_base)) {
  491. irq_base = COMBINER_IRQ(0, 0);
  492. pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
  493. }
  494. combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
  495. &combiner_irq_domain_ops, &combiner_data);
  496. if (WARN_ON(!combiner_irq_domain)) {
  497. pr_warning("%s: irq domain init failed\n", __func__);
  498. return;
  499. }
  500. for (i = 0; i < max_nr; i++) {
  501. combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
  502. irq = IRQ_SPI(i);
  503. #ifdef CONFIG_OF
  504. if (np)
  505. irq = irq_of_parse_and_map(np, i);
  506. #endif
  507. combiner_cascade_irq(i, irq);
  508. }
  509. }
  510. #ifdef CONFIG_OF
  511. int __init combiner_of_init(struct device_node *np, struct device_node *parent)
  512. {
  513. void __iomem *combiner_base;
  514. combiner_base = of_iomap(np, 0);
  515. if (!combiner_base) {
  516. pr_err("%s: failed to map combiner registers\n", __func__);
  517. return -ENXIO;
  518. }
  519. combiner_init(combiner_base, np);
  520. return 0;
  521. }
  522. static const struct of_device_id exynos4_dt_irq_match[] = {
  523. { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
  524. { .compatible = "samsung,exynos4210-combiner",
  525. .data = combiner_of_init, },
  526. {},
  527. };
  528. #endif
  529. void __init exynos4_init_irq(void)
  530. {
  531. unsigned int gic_bank_offset;
  532. gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
  533. if (!of_have_populated_dt())
  534. gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
  535. #ifdef CONFIG_OF
  536. else
  537. of_irq_init(exynos4_dt_irq_match);
  538. #endif
  539. if (!of_have_populated_dt())
  540. combiner_init(S5P_VA_COMBINER_BASE, NULL);
  541. /*
  542. * The parameters of s5p_init_irq() are for VIC init.
  543. * Theses parameters should be NULL and 0 because EXYNOS4
  544. * uses GIC instead of VIC.
  545. */
  546. s5p_init_irq(NULL, 0);
  547. }
  548. void __init exynos5_init_irq(void)
  549. {
  550. #ifdef CONFIG_OF
  551. of_irq_init(exynos4_dt_irq_match);
  552. #endif
  553. /*
  554. * The parameters of s5p_init_irq() are for VIC init.
  555. * Theses parameters should be NULL and 0 because EXYNOS4
  556. * uses GIC instead of VIC.
  557. */
  558. s5p_init_irq(NULL, 0);
  559. }
  560. struct bus_type exynos_subsys = {
  561. .name = "exynos-core",
  562. .dev_name = "exynos-core",
  563. };
  564. static struct device exynos4_dev = {
  565. .bus = &exynos_subsys,
  566. };
  567. static int __init exynos_core_init(void)
  568. {
  569. return subsys_system_register(&exynos_subsys, NULL);
  570. }
  571. core_initcall(exynos_core_init);
  572. #ifdef CONFIG_CACHE_L2X0
  573. static int __init exynos4_l2x0_cache_init(void)
  574. {
  575. int ret;
  576. if (soc_is_exynos5250())
  577. return 0;
  578. ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
  579. if (!ret) {
  580. l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
  581. clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
  582. return 0;
  583. }
  584. if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
  585. l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
  586. /* TAG, Data Latency Control: 2 cycles */
  587. l2x0_saved_regs.tag_latency = 0x110;
  588. if (soc_is_exynos4212() || soc_is_exynos4412())
  589. l2x0_saved_regs.data_latency = 0x120;
  590. else
  591. l2x0_saved_regs.data_latency = 0x110;
  592. l2x0_saved_regs.prefetch_ctrl = 0x30000007;
  593. l2x0_saved_regs.pwr_ctrl =
  594. (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
  595. l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
  596. __raw_writel(l2x0_saved_regs.tag_latency,
  597. S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
  598. __raw_writel(l2x0_saved_regs.data_latency,
  599. S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
  600. /* L2X0 Prefetch Control */
  601. __raw_writel(l2x0_saved_regs.prefetch_ctrl,
  602. S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
  603. /* L2X0 Power Control */
  604. __raw_writel(l2x0_saved_regs.pwr_ctrl,
  605. S5P_VA_L2CC + L2X0_POWER_CTRL);
  606. clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
  607. clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
  608. }
  609. l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
  610. return 0;
  611. }
  612. early_initcall(exynos4_l2x0_cache_init);
  613. #endif
  614. static int __init exynos_init(void)
  615. {
  616. printk(KERN_INFO "EXYNOS: Initializing architecture\n");
  617. return device_register(&exynos4_dev);
  618. }
  619. /* uart registration process */
  620. static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  621. {
  622. struct s3c2410_uartcfg *tcfg = cfg;
  623. u32 ucnt;
  624. for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
  625. tcfg->has_fracval = 1;
  626. if (soc_is_exynos5250())
  627. s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
  628. else
  629. s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
  630. }
  631. static void __iomem *exynos_eint_base;
  632. static DEFINE_SPINLOCK(eint_lock);
  633. static unsigned int eint0_15_data[16];
  634. static inline int exynos4_irq_to_gpio(unsigned int irq)
  635. {
  636. if (irq < IRQ_EINT(0))
  637. return -EINVAL;
  638. irq -= IRQ_EINT(0);
  639. if (irq < 8)
  640. return EXYNOS4_GPX0(irq);
  641. irq -= 8;
  642. if (irq < 8)
  643. return EXYNOS4_GPX1(irq);
  644. irq -= 8;
  645. if (irq < 8)
  646. return EXYNOS4_GPX2(irq);
  647. irq -= 8;
  648. if (irq < 8)
  649. return EXYNOS4_GPX3(irq);
  650. return -EINVAL;
  651. }
  652. static inline int exynos5_irq_to_gpio(unsigned int irq)
  653. {
  654. if (irq < IRQ_EINT(0))
  655. return -EINVAL;
  656. irq -= IRQ_EINT(0);
  657. if (irq < 8)
  658. return EXYNOS5_GPX0(irq);
  659. irq -= 8;
  660. if (irq < 8)
  661. return EXYNOS5_GPX1(irq);
  662. irq -= 8;
  663. if (irq < 8)
  664. return EXYNOS5_GPX2(irq);
  665. irq -= 8;
  666. if (irq < 8)
  667. return EXYNOS5_GPX3(irq);
  668. return -EINVAL;
  669. }
  670. static unsigned int exynos4_eint0_15_src_int[16] = {
  671. EXYNOS4_IRQ_EINT0,
  672. EXYNOS4_IRQ_EINT1,
  673. EXYNOS4_IRQ_EINT2,
  674. EXYNOS4_IRQ_EINT3,
  675. EXYNOS4_IRQ_EINT4,
  676. EXYNOS4_IRQ_EINT5,
  677. EXYNOS4_IRQ_EINT6,
  678. EXYNOS4_IRQ_EINT7,
  679. EXYNOS4_IRQ_EINT8,
  680. EXYNOS4_IRQ_EINT9,
  681. EXYNOS4_IRQ_EINT10,
  682. EXYNOS4_IRQ_EINT11,
  683. EXYNOS4_IRQ_EINT12,
  684. EXYNOS4_IRQ_EINT13,
  685. EXYNOS4_IRQ_EINT14,
  686. EXYNOS4_IRQ_EINT15,
  687. };
  688. static unsigned int exynos5_eint0_15_src_int[16] = {
  689. EXYNOS5_IRQ_EINT0,
  690. EXYNOS5_IRQ_EINT1,
  691. EXYNOS5_IRQ_EINT2,
  692. EXYNOS5_IRQ_EINT3,
  693. EXYNOS5_IRQ_EINT4,
  694. EXYNOS5_IRQ_EINT5,
  695. EXYNOS5_IRQ_EINT6,
  696. EXYNOS5_IRQ_EINT7,
  697. EXYNOS5_IRQ_EINT8,
  698. EXYNOS5_IRQ_EINT9,
  699. EXYNOS5_IRQ_EINT10,
  700. EXYNOS5_IRQ_EINT11,
  701. EXYNOS5_IRQ_EINT12,
  702. EXYNOS5_IRQ_EINT13,
  703. EXYNOS5_IRQ_EINT14,
  704. EXYNOS5_IRQ_EINT15,
  705. };
  706. static inline void exynos_irq_eint_mask(struct irq_data *data)
  707. {
  708. u32 mask;
  709. spin_lock(&eint_lock);
  710. mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
  711. mask |= EINT_OFFSET_BIT(data->irq);
  712. __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
  713. spin_unlock(&eint_lock);
  714. }
  715. static void exynos_irq_eint_unmask(struct irq_data *data)
  716. {
  717. u32 mask;
  718. spin_lock(&eint_lock);
  719. mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
  720. mask &= ~(EINT_OFFSET_BIT(data->irq));
  721. __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
  722. spin_unlock(&eint_lock);
  723. }
  724. static inline void exynos_irq_eint_ack(struct irq_data *data)
  725. {
  726. __raw_writel(EINT_OFFSET_BIT(data->irq),
  727. EINT_PEND(exynos_eint_base, data->irq));
  728. }
  729. static void exynos_irq_eint_maskack(struct irq_data *data)
  730. {
  731. exynos_irq_eint_mask(data);
  732. exynos_irq_eint_ack(data);
  733. }
  734. static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
  735. {
  736. int offs = EINT_OFFSET(data->irq);
  737. int shift;
  738. u32 ctrl, mask;
  739. u32 newvalue = 0;
  740. switch (type) {
  741. case IRQ_TYPE_EDGE_RISING:
  742. newvalue = S5P_IRQ_TYPE_EDGE_RISING;
  743. break;
  744. case IRQ_TYPE_EDGE_FALLING:
  745. newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
  746. break;
  747. case IRQ_TYPE_EDGE_BOTH:
  748. newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
  749. break;
  750. case IRQ_TYPE_LEVEL_LOW:
  751. newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
  752. break;
  753. case IRQ_TYPE_LEVEL_HIGH:
  754. newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
  755. break;
  756. default:
  757. printk(KERN_ERR "No such irq type %d", type);
  758. return -EINVAL;
  759. }
  760. shift = (offs & 0x7) * 4;
  761. mask = 0x7 << shift;
  762. spin_lock(&eint_lock);
  763. ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
  764. ctrl &= ~mask;
  765. ctrl |= newvalue << shift;
  766. __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
  767. spin_unlock(&eint_lock);
  768. if (soc_is_exynos5250())
  769. s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
  770. else
  771. s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
  772. return 0;
  773. }
  774. static struct irq_chip exynos_irq_eint = {
  775. .name = "exynos-eint",
  776. .irq_mask = exynos_irq_eint_mask,
  777. .irq_unmask = exynos_irq_eint_unmask,
  778. .irq_mask_ack = exynos_irq_eint_maskack,
  779. .irq_ack = exynos_irq_eint_ack,
  780. .irq_set_type = exynos_irq_eint_set_type,
  781. #ifdef CONFIG_PM
  782. .irq_set_wake = s3c_irqext_wake,
  783. #endif
  784. };
  785. /*
  786. * exynos4_irq_demux_eint
  787. *
  788. * This function demuxes the IRQ from from EINTs 16 to 31.
  789. * It is designed to be inlined into the specific handler
  790. * s5p_irq_demux_eintX_Y.
  791. *
  792. * Each EINT pend/mask registers handle eight of them.
  793. */
  794. static inline void exynos_irq_demux_eint(unsigned int start)
  795. {
  796. unsigned int irq;
  797. u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
  798. u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
  799. status &= ~mask;
  800. status &= 0xff;
  801. while (status) {
  802. irq = fls(status) - 1;
  803. generic_handle_irq(irq + start);
  804. status &= ~(1 << irq);
  805. }
  806. }
  807. static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
  808. {
  809. struct irq_chip *chip = irq_get_chip(irq);
  810. chained_irq_enter(chip, desc);
  811. exynos_irq_demux_eint(IRQ_EINT(16));
  812. exynos_irq_demux_eint(IRQ_EINT(24));
  813. chained_irq_exit(chip, desc);
  814. }
  815. static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
  816. {
  817. u32 *irq_data = irq_get_handler_data(irq);
  818. struct irq_chip *chip = irq_get_chip(irq);
  819. chained_irq_enter(chip, desc);
  820. chip->irq_mask(&desc->irq_data);
  821. if (chip->irq_ack)
  822. chip->irq_ack(&desc->irq_data);
  823. generic_handle_irq(*irq_data);
  824. chip->irq_unmask(&desc->irq_data);
  825. chained_irq_exit(chip, desc);
  826. }
  827. static int __init exynos_init_irq_eint(void)
  828. {
  829. int irq;
  830. #ifdef CONFIG_PINCTRL_SAMSUNG
  831. /*
  832. * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
  833. * functionality along with support for external gpio and wakeup
  834. * interrupts. If the samsung pinctrl driver is enabled and includes
  835. * the wakeup interrupt support, then the setting up external wakeup
  836. * interrupts here can be skipped. This check here is temporary to
  837. * allow exynos4 platforms that do not use Samsung pinctrl driver to
  838. * co-exist with platforms that do. When all of the Samsung Exynos4
  839. * platforms switch over to using the pinctrl driver, the wakeup
  840. * interrupt support code here can be completely removed.
  841. */
  842. struct device_node *pctrl_np, *wkup_np;
  843. const char *pctrl_compat = "samsung,pinctrl-exynos4210";
  844. const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
  845. for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
  846. if (of_device_is_available(pctrl_np)) {
  847. wkup_np = of_find_compatible_node(pctrl_np, NULL,
  848. wkup_compat);
  849. if (wkup_np)
  850. return -ENODEV;
  851. }
  852. }
  853. #endif
  854. if (soc_is_exynos5250())
  855. exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
  856. else
  857. exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
  858. if (exynos_eint_base == NULL) {
  859. pr_err("unable to ioremap for EINT base address\n");
  860. return -ENOMEM;
  861. }
  862. for (irq = 0 ; irq <= 31 ; irq++) {
  863. irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
  864. handle_level_irq);
  865. set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
  866. }
  867. irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
  868. for (irq = 0 ; irq <= 15 ; irq++) {
  869. eint0_15_data[irq] = IRQ_EINT(irq);
  870. if (soc_is_exynos5250()) {
  871. irq_set_handler_data(exynos5_eint0_15_src_int[irq],
  872. &eint0_15_data[irq]);
  873. irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
  874. exynos_irq_eint0_15);
  875. } else {
  876. irq_set_handler_data(exynos4_eint0_15_src_int[irq],
  877. &eint0_15_data[irq]);
  878. irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
  879. exynos_irq_eint0_15);
  880. }
  881. }
  882. return 0;
  883. }
  884. arch_initcall(exynos_init_irq_eint);