irq.c 2.6 KB

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  1. /*
  2. * arch/arm/mach-dove/irq.c
  3. *
  4. * Dove IRQ handling.
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/irq.h>
  13. #include <linux/gpio.h>
  14. #include <linux/io.h>
  15. #include <asm/mach/arch.h>
  16. #include <plat/irq.h>
  17. #include <asm/mach/irq.h>
  18. #include <mach/pm.h>
  19. #include <mach/bridge-regs.h>
  20. #include <plat/orion-gpio.h>
  21. #include "common.h"
  22. static void pmu_irq_mask(struct irq_data *d)
  23. {
  24. int pin = irq_to_pmu(d->irq);
  25. u32 u;
  26. u = readl(PMU_INTERRUPT_MASK);
  27. u &= ~(1 << (pin & 31));
  28. writel(u, PMU_INTERRUPT_MASK);
  29. }
  30. static void pmu_irq_unmask(struct irq_data *d)
  31. {
  32. int pin = irq_to_pmu(d->irq);
  33. u32 u;
  34. u = readl(PMU_INTERRUPT_MASK);
  35. u |= 1 << (pin & 31);
  36. writel(u, PMU_INTERRUPT_MASK);
  37. }
  38. static void pmu_irq_ack(struct irq_data *d)
  39. {
  40. int pin = irq_to_pmu(d->irq);
  41. u32 u;
  42. u = ~(1 << (pin & 31));
  43. writel(u, PMU_INTERRUPT_CAUSE);
  44. }
  45. static struct irq_chip pmu_irq_chip = {
  46. .name = "pmu_irq",
  47. .irq_mask = pmu_irq_mask,
  48. .irq_unmask = pmu_irq_unmask,
  49. .irq_ack = pmu_irq_ack,
  50. };
  51. static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
  52. {
  53. unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
  54. cause &= readl(PMU_INTERRUPT_MASK);
  55. if (cause == 0) {
  56. do_bad_IRQ(irq, desc);
  57. return;
  58. }
  59. for (irq = 0; irq < NR_PMU_IRQS; irq++) {
  60. if (!(cause & (1 << irq)))
  61. continue;
  62. irq = pmu_to_irq(irq);
  63. generic_handle_irq(irq);
  64. }
  65. }
  66. static int __initdata gpio0_irqs[4] = {
  67. IRQ_DOVE_GPIO_0_7,
  68. IRQ_DOVE_GPIO_8_15,
  69. IRQ_DOVE_GPIO_16_23,
  70. IRQ_DOVE_GPIO_24_31,
  71. };
  72. static int __initdata gpio1_irqs[4] = {
  73. IRQ_DOVE_HIGH_GPIO,
  74. 0,
  75. 0,
  76. 0,
  77. };
  78. static int __initdata gpio2_irqs[4] = {
  79. 0,
  80. 0,
  81. 0,
  82. 0,
  83. };
  84. void __init dove_init_irq(void)
  85. {
  86. int i;
  87. orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
  88. orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
  89. /*
  90. * Initialize gpiolib for GPIOs 0-71.
  91. */
  92. orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
  93. IRQ_DOVE_GPIO_START, gpio0_irqs);
  94. orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
  95. IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
  96. orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
  97. IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
  98. /*
  99. * Mask and clear PMU interrupts
  100. */
  101. writel(0, PMU_INTERRUPT_MASK);
  102. writel(0, PMU_INTERRUPT_CAUSE);
  103. for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
  104. irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
  105. irq_set_status_flags(i, IRQ_LEVEL);
  106. set_irq_flags(i, IRQF_VALID);
  107. }
  108. irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
  109. }