common.c 13 KB

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  1. /*
  2. * arch/arm/mach-dove/common.c
  3. *
  4. * Core functions for Marvell Dove 88AP510 System On Chip
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/delay.h>
  12. #include <linux/init.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pci.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/ata_platform.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of.h>
  19. #include <linux/of_platform.h>
  20. #include <asm/page.h>
  21. #include <asm/setup.h>
  22. #include <asm/timex.h>
  23. #include <asm/hardware/cache-tauros2.h>
  24. #include <asm/mach/map.h>
  25. #include <asm/mach/time.h>
  26. #include <asm/mach/pci.h>
  27. #include <mach/dove.h>
  28. #include <mach/pm.h>
  29. #include <mach/bridge-regs.h>
  30. #include <asm/mach/arch.h>
  31. #include <linux/irq.h>
  32. #include <plat/time.h>
  33. #include <linux/platform_data/usb-ehci-orion.h>
  34. #include <plat/common.h>
  35. #include <plat/addr-map.h>
  36. #include "common.h"
  37. /*****************************************************************************
  38. * I/O Address Mapping
  39. ****************************************************************************/
  40. static struct map_desc dove_io_desc[] __initdata = {
  41. {
  42. .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
  43. .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
  44. .length = DOVE_SB_REGS_SIZE,
  45. .type = MT_DEVICE,
  46. }, {
  47. .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
  48. .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
  49. .length = DOVE_NB_REGS_SIZE,
  50. .type = MT_DEVICE,
  51. },
  52. };
  53. void __init dove_map_io(void)
  54. {
  55. iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
  56. }
  57. /*****************************************************************************
  58. * CLK tree
  59. ****************************************************************************/
  60. static int dove_tclk;
  61. static DEFINE_SPINLOCK(gating_lock);
  62. static struct clk *tclk;
  63. static struct clk __init *dove_register_gate(const char *name,
  64. const char *parent, u8 bit_idx)
  65. {
  66. return clk_register_gate(NULL, name, parent, 0,
  67. (void __iomem *)CLOCK_GATING_CONTROL,
  68. bit_idx, 0, &gating_lock);
  69. }
  70. static void __init dove_clk_init(void)
  71. {
  72. struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
  73. struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
  74. struct clk *xor0, *xor1, *ge, *gephy;
  75. tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
  76. dove_tclk);
  77. usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
  78. usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
  79. sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
  80. pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
  81. pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
  82. sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
  83. sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
  84. nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
  85. camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
  86. i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
  87. i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
  88. crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
  89. ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
  90. pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
  91. xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
  92. xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
  93. gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
  94. ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
  95. orion_clkdev_add(NULL, "orion_spi.0", tclk);
  96. orion_clkdev_add(NULL, "orion_spi.1", tclk);
  97. orion_clkdev_add(NULL, "orion_wdt", tclk);
  98. orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
  99. orion_clkdev_add(NULL, "orion-ehci.0", usb0);
  100. orion_clkdev_add(NULL, "orion-ehci.1", usb1);
  101. orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
  102. orion_clkdev_add("0", "sata_mv.0", sata);
  103. orion_clkdev_add("0", "pcie", pex0);
  104. orion_clkdev_add("1", "pcie", pex1);
  105. orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
  106. orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
  107. orion_clkdev_add(NULL, "orion_nand", nand);
  108. orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
  109. orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
  110. orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
  111. orion_clkdev_add(NULL, "mv_crypto", crypto);
  112. orion_clkdev_add(NULL, "dove-ac97", ac97);
  113. orion_clkdev_add(NULL, "dove-pdma", pdma);
  114. orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
  115. orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
  116. }
  117. /*****************************************************************************
  118. * EHCI0
  119. ****************************************************************************/
  120. void __init dove_ehci0_init(void)
  121. {
  122. orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
  123. }
  124. /*****************************************************************************
  125. * EHCI1
  126. ****************************************************************************/
  127. void __init dove_ehci1_init(void)
  128. {
  129. orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
  130. }
  131. /*****************************************************************************
  132. * GE00
  133. ****************************************************************************/
  134. void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
  135. {
  136. orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
  137. IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
  138. 1600);
  139. }
  140. /*****************************************************************************
  141. * SoC RTC
  142. ****************************************************************************/
  143. void __init dove_rtc_init(void)
  144. {
  145. orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
  146. }
  147. /*****************************************************************************
  148. * SATA
  149. ****************************************************************************/
  150. void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
  151. {
  152. orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
  153. }
  154. /*****************************************************************************
  155. * UART0
  156. ****************************************************************************/
  157. void __init dove_uart0_init(void)
  158. {
  159. orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
  160. IRQ_DOVE_UART_0, tclk);
  161. }
  162. /*****************************************************************************
  163. * UART1
  164. ****************************************************************************/
  165. void __init dove_uart1_init(void)
  166. {
  167. orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
  168. IRQ_DOVE_UART_1, tclk);
  169. }
  170. /*****************************************************************************
  171. * UART2
  172. ****************************************************************************/
  173. void __init dove_uart2_init(void)
  174. {
  175. orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
  176. IRQ_DOVE_UART_2, tclk);
  177. }
  178. /*****************************************************************************
  179. * UART3
  180. ****************************************************************************/
  181. void __init dove_uart3_init(void)
  182. {
  183. orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
  184. IRQ_DOVE_UART_3, tclk);
  185. }
  186. /*****************************************************************************
  187. * SPI
  188. ****************************************************************************/
  189. void __init dove_spi0_init(void)
  190. {
  191. orion_spi_init(DOVE_SPI0_PHYS_BASE);
  192. }
  193. void __init dove_spi1_init(void)
  194. {
  195. orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
  196. }
  197. /*****************************************************************************
  198. * I2C
  199. ****************************************************************************/
  200. void __init dove_i2c_init(void)
  201. {
  202. orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
  203. }
  204. /*****************************************************************************
  205. * Time handling
  206. ****************************************************************************/
  207. void __init dove_init_early(void)
  208. {
  209. orion_time_set_base(TIMER_VIRT_BASE);
  210. }
  211. static int __init dove_find_tclk(void)
  212. {
  213. return 166666667;
  214. }
  215. static void __init dove_timer_init(void)
  216. {
  217. dove_tclk = dove_find_tclk();
  218. orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
  219. IRQ_DOVE_BRIDGE, dove_tclk);
  220. }
  221. struct sys_timer dove_timer = {
  222. .init = dove_timer_init,
  223. };
  224. /*****************************************************************************
  225. * Cryptographic Engines and Security Accelerator (CESA)
  226. ****************************************************************************/
  227. void __init dove_crypto_init(void)
  228. {
  229. orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
  230. DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
  231. }
  232. /*****************************************************************************
  233. * XOR 0
  234. ****************************************************************************/
  235. void __init dove_xor0_init(void)
  236. {
  237. orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
  238. IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
  239. }
  240. /*****************************************************************************
  241. * XOR 1
  242. ****************************************************************************/
  243. void __init dove_xor1_init(void)
  244. {
  245. orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
  246. IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
  247. }
  248. /*****************************************************************************
  249. * SDIO
  250. ****************************************************************************/
  251. static u64 sdio_dmamask = DMA_BIT_MASK(32);
  252. static struct resource dove_sdio0_resources[] = {
  253. {
  254. .start = DOVE_SDIO0_PHYS_BASE,
  255. .end = DOVE_SDIO0_PHYS_BASE + 0xff,
  256. .flags = IORESOURCE_MEM,
  257. }, {
  258. .start = IRQ_DOVE_SDIO0,
  259. .end = IRQ_DOVE_SDIO0,
  260. .flags = IORESOURCE_IRQ,
  261. },
  262. };
  263. static struct platform_device dove_sdio0 = {
  264. .name = "sdhci-dove",
  265. .id = 0,
  266. .dev = {
  267. .dma_mask = &sdio_dmamask,
  268. .coherent_dma_mask = DMA_BIT_MASK(32),
  269. },
  270. .resource = dove_sdio0_resources,
  271. .num_resources = ARRAY_SIZE(dove_sdio0_resources),
  272. };
  273. void __init dove_sdio0_init(void)
  274. {
  275. platform_device_register(&dove_sdio0);
  276. }
  277. static struct resource dove_sdio1_resources[] = {
  278. {
  279. .start = DOVE_SDIO1_PHYS_BASE,
  280. .end = DOVE_SDIO1_PHYS_BASE + 0xff,
  281. .flags = IORESOURCE_MEM,
  282. }, {
  283. .start = IRQ_DOVE_SDIO1,
  284. .end = IRQ_DOVE_SDIO1,
  285. .flags = IORESOURCE_IRQ,
  286. },
  287. };
  288. static struct platform_device dove_sdio1 = {
  289. .name = "sdhci-dove",
  290. .id = 1,
  291. .dev = {
  292. .dma_mask = &sdio_dmamask,
  293. .coherent_dma_mask = DMA_BIT_MASK(32),
  294. },
  295. .resource = dove_sdio1_resources,
  296. .num_resources = ARRAY_SIZE(dove_sdio1_resources),
  297. };
  298. void __init dove_sdio1_init(void)
  299. {
  300. platform_device_register(&dove_sdio1);
  301. }
  302. void __init dove_init(void)
  303. {
  304. pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
  305. (dove_tclk + 499999) / 1000000);
  306. #ifdef CONFIG_CACHE_TAUROS2
  307. tauros2_init(0);
  308. #endif
  309. dove_setup_cpu_mbus();
  310. /* Setup root of clk tree */
  311. dove_clk_init();
  312. /* internal devices that every board has */
  313. dove_rtc_init();
  314. dove_xor0_init();
  315. dove_xor1_init();
  316. }
  317. void dove_restart(char mode, const char *cmd)
  318. {
  319. /*
  320. * Enable soft reset to assert RSTOUTn.
  321. */
  322. writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
  323. /*
  324. * Assert soft reset.
  325. */
  326. writel(SOFT_RESET, SYSTEM_SOFT_RESET);
  327. while (1)
  328. ;
  329. }
  330. #if defined(CONFIG_MACH_DOVE_DT)
  331. /*
  332. * Auxdata required until real OF clock provider
  333. */
  334. struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
  335. OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
  336. OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
  337. OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
  338. OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
  339. NULL),
  340. OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
  341. OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
  342. OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
  343. {},
  344. };
  345. static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
  346. .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
  347. };
  348. static void __init dove_dt_init(void)
  349. {
  350. pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
  351. (dove_tclk + 499999) / 1000000);
  352. #ifdef CONFIG_CACHE_TAUROS2
  353. tauros2_init();
  354. #endif
  355. dove_setup_cpu_mbus();
  356. /* Setup root of clk tree */
  357. dove_clk_init();
  358. /* Internal devices not ported to DT yet */
  359. dove_rtc_init();
  360. dove_xor0_init();
  361. dove_xor1_init();
  362. dove_ge00_init(&dove_dt_ge00_data);
  363. dove_ehci0_init();
  364. dove_ehci1_init();
  365. dove_pcie_init(1, 1);
  366. dove_crypto_init();
  367. of_platform_populate(NULL, of_default_bus_match_table,
  368. dove_auxdata_lookup, NULL);
  369. }
  370. static const char * const dove_dt_board_compat[] = {
  371. "marvell,dove",
  372. NULL
  373. };
  374. DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
  375. .map_io = dove_map_io,
  376. .init_early = dove_init_early,
  377. .init_irq = orion_dt_init_irq,
  378. .timer = &dove_timer,
  379. .init_machine = dove_dt_init,
  380. .restart = dove_restart,
  381. .dt_compat = dove_dt_board_compat,
  382. MACHINE_END
  383. #endif