perf_event_cpu.c 7.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295
  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License version 2 as
  4. * published by the Free Software Foundation.
  5. *
  6. * This program is distributed in the hope that it will be useful,
  7. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. *
  11. * You should have received a copy of the GNU General Public License
  12. * along with this program; if not, write to the Free Software
  13. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  14. *
  15. * Copyright (C) 2012 ARM Limited
  16. *
  17. * Author: Will Deacon <will.deacon@arm.com>
  18. */
  19. #define pr_fmt(fmt) "CPU PMU: " fmt
  20. #include <linux/bitmap.h>
  21. #include <linux/export.h>
  22. #include <linux/kernel.h>
  23. #include <linux/of.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/spinlock.h>
  26. #include <asm/cputype.h>
  27. #include <asm/irq_regs.h>
  28. #include <asm/pmu.h>
  29. /* Set at runtime when we know what CPU type we are. */
  30. static struct arm_pmu *cpu_pmu;
  31. static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
  32. static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
  33. static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
  34. /*
  35. * Despite the names, these two functions are CPU-specific and are used
  36. * by the OProfile/perf code.
  37. */
  38. const char *perf_pmu_name(void)
  39. {
  40. if (!cpu_pmu)
  41. return NULL;
  42. return cpu_pmu->pmu.name;
  43. }
  44. EXPORT_SYMBOL_GPL(perf_pmu_name);
  45. int perf_num_counters(void)
  46. {
  47. int max_events = 0;
  48. if (cpu_pmu != NULL)
  49. max_events = cpu_pmu->num_events;
  50. return max_events;
  51. }
  52. EXPORT_SYMBOL_GPL(perf_num_counters);
  53. /* Include the PMU-specific implementations. */
  54. #include "perf_event_xscale.c"
  55. #include "perf_event_v6.c"
  56. #include "perf_event_v7.c"
  57. static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
  58. {
  59. return &__get_cpu_var(cpu_hw_events);
  60. }
  61. static void cpu_pmu_free_irq(void)
  62. {
  63. int i, irq, irqs;
  64. struct platform_device *pmu_device = cpu_pmu->plat_device;
  65. irqs = min(pmu_device->num_resources, num_possible_cpus());
  66. for (i = 0; i < irqs; ++i) {
  67. if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
  68. continue;
  69. irq = platform_get_irq(pmu_device, i);
  70. if (irq >= 0)
  71. free_irq(irq, cpu_pmu);
  72. }
  73. }
  74. static int cpu_pmu_request_irq(irq_handler_t handler)
  75. {
  76. int i, err, irq, irqs;
  77. struct platform_device *pmu_device = cpu_pmu->plat_device;
  78. if (!pmu_device)
  79. return -ENODEV;
  80. irqs = min(pmu_device->num_resources, num_possible_cpus());
  81. if (irqs < 1) {
  82. pr_err("no irqs for PMUs defined\n");
  83. return -ENODEV;
  84. }
  85. for (i = 0; i < irqs; ++i) {
  86. err = 0;
  87. irq = platform_get_irq(pmu_device, i);
  88. if (irq < 0)
  89. continue;
  90. /*
  91. * If we have a single PMU interrupt that we can't shift,
  92. * assume that we're running on a uniprocessor machine and
  93. * continue. Otherwise, continue without this interrupt.
  94. */
  95. if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
  96. pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
  97. irq, i);
  98. continue;
  99. }
  100. err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu",
  101. cpu_pmu);
  102. if (err) {
  103. pr_err("unable to request IRQ%d for ARM PMU counters\n",
  104. irq);
  105. return err;
  106. }
  107. cpumask_set_cpu(i, &cpu_pmu->active_irqs);
  108. }
  109. return 0;
  110. }
  111. static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
  112. {
  113. int cpu;
  114. for_each_possible_cpu(cpu) {
  115. struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
  116. events->events = per_cpu(hw_events, cpu);
  117. events->used_mask = per_cpu(used_mask, cpu);
  118. raw_spin_lock_init(&events->pmu_lock);
  119. }
  120. cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
  121. cpu_pmu->request_irq = cpu_pmu_request_irq;
  122. cpu_pmu->free_irq = cpu_pmu_free_irq;
  123. /* Ensure the PMU has sane values out of reset. */
  124. if (cpu_pmu && cpu_pmu->reset)
  125. on_each_cpu(cpu_pmu->reset, NULL, 1);
  126. }
  127. /*
  128. * PMU hardware loses all context when a CPU goes offline.
  129. * When a CPU is hotplugged back in, since some hardware registers are
  130. * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
  131. * junk values out of them.
  132. */
  133. static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
  134. unsigned long action, void *hcpu)
  135. {
  136. if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
  137. return NOTIFY_DONE;
  138. if (cpu_pmu && cpu_pmu->reset)
  139. cpu_pmu->reset(NULL);
  140. return NOTIFY_OK;
  141. }
  142. static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
  143. .notifier_call = cpu_pmu_notify,
  144. };
  145. /*
  146. * PMU platform driver and devicetree bindings.
  147. */
  148. static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
  149. {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
  150. {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
  151. {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
  152. {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
  153. {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
  154. {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
  155. {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init},
  156. {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init},
  157. {},
  158. };
  159. static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
  160. {.name = "arm-pmu"},
  161. {},
  162. };
  163. /*
  164. * CPU PMU identification and probing.
  165. */
  166. static struct arm_pmu *__devinit probe_current_pmu(void)
  167. {
  168. struct arm_pmu *pmu = NULL;
  169. int cpu = get_cpu();
  170. unsigned long cpuid = read_cpuid_id();
  171. unsigned long implementor = (cpuid & 0xFF000000) >> 24;
  172. unsigned long part_number = (cpuid & 0xFFF0);
  173. pr_info("probing PMU on CPU %d\n", cpu);
  174. /* ARM Ltd CPUs. */
  175. if (0x41 == implementor) {
  176. switch (part_number) {
  177. case 0xB360: /* ARM1136 */
  178. case 0xB560: /* ARM1156 */
  179. case 0xB760: /* ARM1176 */
  180. pmu = armv6pmu_init();
  181. break;
  182. case 0xB020: /* ARM11mpcore */
  183. pmu = armv6mpcore_pmu_init();
  184. break;
  185. case 0xC080: /* Cortex-A8 */
  186. pmu = armv7_a8_pmu_init();
  187. break;
  188. case 0xC090: /* Cortex-A9 */
  189. pmu = armv7_a9_pmu_init();
  190. break;
  191. case 0xC050: /* Cortex-A5 */
  192. pmu = armv7_a5_pmu_init();
  193. break;
  194. case 0xC0F0: /* Cortex-A15 */
  195. pmu = armv7_a15_pmu_init();
  196. break;
  197. case 0xC070: /* Cortex-A7 */
  198. pmu = armv7_a7_pmu_init();
  199. break;
  200. }
  201. /* Intel CPUs [xscale]. */
  202. } else if (0x69 == implementor) {
  203. part_number = (cpuid >> 13) & 0x7;
  204. switch (part_number) {
  205. case 1:
  206. pmu = xscale1pmu_init();
  207. break;
  208. case 2:
  209. pmu = xscale2pmu_init();
  210. break;
  211. }
  212. }
  213. put_cpu();
  214. return pmu;
  215. }
  216. static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
  217. {
  218. const struct of_device_id *of_id;
  219. struct arm_pmu *(*init_fn)(void);
  220. struct device_node *node = pdev->dev.of_node;
  221. if (cpu_pmu) {
  222. pr_info("attempt to register multiple PMU devices!");
  223. return -ENOSPC;
  224. }
  225. if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
  226. init_fn = of_id->data;
  227. cpu_pmu = init_fn();
  228. } else {
  229. cpu_pmu = probe_current_pmu();
  230. }
  231. if (!cpu_pmu)
  232. return -ENODEV;
  233. cpu_pmu->plat_device = pdev;
  234. cpu_pmu_init(cpu_pmu);
  235. register_cpu_notifier(&cpu_pmu_hotplug_notifier);
  236. armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
  237. return 0;
  238. }
  239. static struct platform_driver cpu_pmu_driver = {
  240. .driver = {
  241. .name = "arm-pmu",
  242. .pm = &armpmu_dev_pm_ops,
  243. .of_match_table = cpu_pmu_of_device_ids,
  244. },
  245. .probe = cpu_pmu_device_probe,
  246. .id_table = cpu_pmu_plat_device_ids,
  247. };
  248. static int __init register_pmu_driver(void)
  249. {
  250. return platform_driver_register(&cpu_pmu_driver);
  251. }
  252. device_initcall(register_pmu_driver);