tegra20-whistler.dts 13 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra2 Whistler evaluation board";
  5. compatible = "nvidia,whistler", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x20000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
  15. "gmc", "gmd", "gpu";
  16. nvidia,function = "gmi";
  17. };
  18. atc {
  19. nvidia,pins = "atc", "atd";
  20. nvidia,function = "sdio4";
  21. };
  22. cdev1 {
  23. nvidia,pins = "cdev1";
  24. nvidia,function = "plla_out";
  25. };
  26. cdev2 {
  27. nvidia,pins = "cdev2";
  28. nvidia,function = "osc";
  29. };
  30. crtp {
  31. nvidia,pins = "crtp";
  32. nvidia,function = "crt";
  33. };
  34. csus {
  35. nvidia,pins = "csus";
  36. nvidia,function = "vi_sensor_clk";
  37. };
  38. dap1 {
  39. nvidia,pins = "dap1";
  40. nvidia,function = "dap1";
  41. };
  42. dap2 {
  43. nvidia,pins = "dap2";
  44. nvidia,function = "dap2";
  45. };
  46. dap3 {
  47. nvidia,pins = "dap3";
  48. nvidia,function = "dap3";
  49. };
  50. dap4 {
  51. nvidia,pins = "dap4";
  52. nvidia,function = "dap4";
  53. };
  54. ddc {
  55. nvidia,pins = "ddc";
  56. nvidia,function = "i2c2";
  57. };
  58. dta {
  59. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  60. nvidia,function = "vi";
  61. };
  62. dte {
  63. nvidia,pins = "dte";
  64. nvidia,function = "rsvd1";
  65. };
  66. dtf {
  67. nvidia,pins = "dtf";
  68. nvidia,function = "i2c3";
  69. };
  70. gme {
  71. nvidia,pins = "gme";
  72. nvidia,function = "dap5";
  73. };
  74. gpu7 {
  75. nvidia,pins = "gpu7";
  76. nvidia,function = "rtck";
  77. };
  78. gpv {
  79. nvidia,pins = "gpv";
  80. nvidia,function = "pcie";
  81. };
  82. hdint {
  83. nvidia,pins = "hdint", "pta";
  84. nvidia,function = "hdmi";
  85. };
  86. i2cp {
  87. nvidia,pins = "i2cp";
  88. nvidia,function = "i2cp";
  89. };
  90. irrx {
  91. nvidia,pins = "irrx", "irtx";
  92. nvidia,function = "uartb";
  93. };
  94. kbca {
  95. nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
  96. nvidia,function = "kbc";
  97. };
  98. kbcb {
  99. nvidia,pins = "kbcb", "kbcd";
  100. nvidia,function = "sdio2";
  101. };
  102. lcsn {
  103. nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
  104. "spia", "spib", "spic";
  105. nvidia,function = "spi3";
  106. };
  107. ld0 {
  108. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  109. "ld5", "ld6", "ld7", "ld8", "ld9",
  110. "ld10", "ld11", "ld12", "ld13", "ld14",
  111. "ld15", "ld16", "ld17", "ldc", "ldi",
  112. "lhp0", "lhp1", "lhp2", "lhs", "lm0",
  113. "lm1", "lpp", "lpw0", "lpw1", "lpw2",
  114. "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
  115. "lvs";
  116. nvidia,function = "displaya";
  117. };
  118. owc {
  119. nvidia,pins = "owc", "uac";
  120. nvidia,function = "owr";
  121. };
  122. pmc {
  123. nvidia,pins = "pmc";
  124. nvidia,function = "pwr_on";
  125. };
  126. rm {
  127. nvidia,pins = "rm";
  128. nvidia,function = "i2c1";
  129. };
  130. sdb {
  131. nvidia,pins = "sdb", "sdc", "sdd", "slxa",
  132. "slxc", "slxd", "slxk";
  133. nvidia,function = "sdio3";
  134. };
  135. sdio1 {
  136. nvidia,pins = "sdio1";
  137. nvidia,function = "sdio1";
  138. };
  139. spdi {
  140. nvidia,pins = "spdi", "spdo";
  141. nvidia,function = "rsvd2";
  142. };
  143. spid {
  144. nvidia,pins = "spid", "spie", "spig", "spih";
  145. nvidia,function = "spi2_alt";
  146. };
  147. spif {
  148. nvidia,pins = "spif";
  149. nvidia,function = "spi2";
  150. };
  151. uaa {
  152. nvidia,pins = "uaa", "uab";
  153. nvidia,function = "uarta";
  154. };
  155. uad {
  156. nvidia,pins = "uad";
  157. nvidia,function = "irda";
  158. };
  159. uca {
  160. nvidia,pins = "uca", "ucb";
  161. nvidia,function = "uartc";
  162. };
  163. uda {
  164. nvidia,pins = "uda";
  165. nvidia,function = "spi1";
  166. };
  167. conf_ata {
  168. nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
  169. "gmb", "gmc", "gmd", "irrx", "irtx",
  170. "kbca", "kbcb", "kbcc", "kbcd", "kbce",
  171. "kbcf", "sdc", "sdd", "spie", "spig",
  172. "spih", "uaa", "uab", "uad", "uca",
  173. "ucb";
  174. nvidia,pull = <2>;
  175. nvidia,tristate = <0>;
  176. };
  177. conf_atd {
  178. nvidia,pins = "atd", "ate", "cdev1", "csus",
  179. "dap1", "dap2", "dap3", "dap4", "dte",
  180. "dtf", "gpu", "gpu7", "gpv", "i2cp",
  181. "rm", "sdio1", "slxa", "slxc", "slxd",
  182. "slxk", "spdi", "spdo", "uac", "uda";
  183. nvidia,pull = <0>;
  184. nvidia,tristate = <0>;
  185. };
  186. conf_cdev2 {
  187. nvidia,pins = "cdev2", "spia", "spib";
  188. nvidia,pull = <1>;
  189. nvidia,tristate = <1>;
  190. };
  191. conf_ck32 {
  192. nvidia,pins = "ck32", "ddrc", "lc", "pmca",
  193. "pmcb", "pmcc", "pmcd", "xm2c",
  194. "xm2d";
  195. nvidia,pull = <0>;
  196. };
  197. conf_crtp {
  198. nvidia,pins = "crtp";
  199. nvidia,pull = <0>;
  200. nvidia,tristate = <1>;
  201. };
  202. conf_dta {
  203. nvidia,pins = "dta", "dtb", "dtc", "dtd",
  204. "spid", "spif";
  205. nvidia,pull = <1>;
  206. nvidia,tristate = <0>;
  207. };
  208. conf_gme {
  209. nvidia,pins = "gme", "owc", "pta", "spic";
  210. nvidia,pull = <2>;
  211. nvidia,tristate = <1>;
  212. };
  213. conf_ld17_0 {
  214. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  215. "ld23_22";
  216. nvidia,pull = <1>;
  217. };
  218. conf_ls {
  219. nvidia,pins = "ls", "pmce";
  220. nvidia,pull = <2>;
  221. };
  222. drive_dap1 {
  223. nvidia,pins = "drive_dap1";
  224. nvidia,high-speed-mode = <0>;
  225. nvidia,schmitt = <1>;
  226. nvidia,low-power-mode = <0>;
  227. nvidia,pull-down-strength = <0>;
  228. nvidia,pull-up-strength = <0>;
  229. nvidia,slew-rate-rising = <0>;
  230. nvidia,slew-rate-falling = <0>;
  231. };
  232. };
  233. };
  234. i2s@70002800 {
  235. status = "okay";
  236. };
  237. serial@70006000 {
  238. status = "okay";
  239. clock-frequency = <216000000>;
  240. };
  241. i2c@7000d000 {
  242. status = "okay";
  243. clock-frequency = <100000>;
  244. codec: codec@1a {
  245. compatible = "wlf,wm8753";
  246. reg = <0x1a>;
  247. };
  248. tca6416: gpio@20 {
  249. compatible = "ti,tca6416";
  250. reg = <0x20>;
  251. gpio-controller;
  252. #gpio-cells = <2>;
  253. };
  254. max8907@3c {
  255. compatible = "maxim,max8907";
  256. reg = <0x3c>;
  257. interrupts = <0 86 0x4>;
  258. maxim,system-power-controller;
  259. mbatt-supply = <&usb0_vbus_reg>;
  260. in-v1-supply = <&mbatt_reg>;
  261. in-v2-supply = <&mbatt_reg>;
  262. in-v3-supply = <&mbatt_reg>;
  263. in1-supply = <&mbatt_reg>;
  264. in2-supply = <&nvvdd_sv3_reg>;
  265. in3-supply = <&mbatt_reg>;
  266. in4-supply = <&mbatt_reg>;
  267. in5-supply = <&mbatt_reg>;
  268. in6-supply = <&mbatt_reg>;
  269. in7-supply = <&mbatt_reg>;
  270. in8-supply = <&mbatt_reg>;
  271. in9-supply = <&mbatt_reg>;
  272. in10-supply = <&mbatt_reg>;
  273. in11-supply = <&mbatt_reg>;
  274. in12-supply = <&mbatt_reg>;
  275. in13-supply = <&mbatt_reg>;
  276. in14-supply = <&mbatt_reg>;
  277. in15-supply = <&mbatt_reg>;
  278. in16-supply = <&mbatt_reg>;
  279. in17-supply = <&nvvdd_sv3_reg>;
  280. in18-supply = <&nvvdd_sv3_reg>;
  281. in19-supply = <&mbatt_reg>;
  282. in20-supply = <&mbatt_reg>;
  283. regulators {
  284. #address-cells = <1>;
  285. #size-cells = <0>;
  286. mbatt_reg: regulator@0 {
  287. reg = <0>;
  288. regulator-compatible = "mbatt";
  289. regulator-name = "vbat_pmu";
  290. regulator-always-on;
  291. };
  292. regulator@1 {
  293. reg = <1>;
  294. regulator-compatible = "sd1";
  295. regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
  296. regulator-min-microvolt = <1000000>;
  297. regulator-max-microvolt = <1000000>;
  298. regulator-always-on;
  299. };
  300. regulator@2 {
  301. reg = <2>;
  302. regulator-compatible = "sd2";
  303. regulator-name = "nvvdd_sv2,vdd_core";
  304. regulator-min-microvolt = <1200000>;
  305. regulator-max-microvolt = <1200000>;
  306. regulator-always-on;
  307. };
  308. nvvdd_sv3_reg: regulator@3 {
  309. reg = <3>;
  310. regulator-compatible = "sd3";
  311. regulator-name = "nvvdd_sv3";
  312. regulator-min-microvolt = <1800000>;
  313. regulator-max-microvolt = <1800000>;
  314. regulator-always-on;
  315. };
  316. regulator@4 {
  317. reg = <4>;
  318. regulator-compatible = "ldo1";
  319. regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
  320. regulator-min-microvolt = <3300000>;
  321. regulator-max-microvolt = <3300000>;
  322. regulator-always-on;
  323. };
  324. regulator@5 {
  325. reg = <5>;
  326. regulator-compatible = "ldo2";
  327. regulator-name = "nvvdd_ldo2,avdd_pll*";
  328. regulator-min-microvolt = <1100000>;
  329. regulator-max-microvolt = <1100000>;
  330. regulator-always-on;
  331. };
  332. regulator@6 {
  333. reg = <6>;
  334. regulator-compatible = "ldo3";
  335. regulator-name = "nvvdd_ldo3,vcom_1v8b";
  336. regulator-min-microvolt = <1800000>;
  337. regulator-max-microvolt = <1800000>;
  338. regulator-always-on;
  339. };
  340. regulator@7 {
  341. reg = <7>;
  342. regulator-compatible = "ldo4";
  343. regulator-name = "nvvdd_ldo4,avdd_usb*";
  344. regulator-min-microvolt = <3300000>;
  345. regulator-max-microvolt = <3300000>;
  346. regulator-always-on;
  347. };
  348. regulator@8 {
  349. reg = <8>;
  350. regulator-compatible = "ldo5";
  351. regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
  352. regulator-min-microvolt = <2800000>;
  353. regulator-max-microvolt = <2800000>;
  354. regulator-always-on;
  355. };
  356. regulator@9 {
  357. reg = <9>;
  358. regulator-compatible = "ldo6";
  359. regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
  360. regulator-min-microvolt = <1800000>;
  361. regulator-max-microvolt = <1800000>;
  362. };
  363. regulator@10 {
  364. reg = <10>;
  365. regulator-compatible = "ldo7";
  366. regulator-name = "nvvdd_ldo7,avddio_audio";
  367. regulator-min-microvolt = <2800000>;
  368. regulator-max-microvolt = <2800000>;
  369. regulator-always-on;
  370. };
  371. regulator@11 {
  372. reg = <11>;
  373. regulator-compatible = "ldo8";
  374. regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
  375. regulator-min-microvolt = <3000000>;
  376. regulator-max-microvolt = <3000000>;
  377. };
  378. regulator@12 {
  379. reg = <12>;
  380. regulator-compatible = "ldo9";
  381. regulator-name = "nvvdd_ldo9,avdd_cam*";
  382. regulator-min-microvolt = <2800000>;
  383. regulator-max-microvolt = <2800000>;
  384. };
  385. regulator@13 {
  386. reg = <13>;
  387. regulator-compatible = "ldo10";
  388. regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
  389. regulator-min-microvolt = <3000000>;
  390. regulator-max-microvolt = <3000000>;
  391. regulator-always-on;
  392. };
  393. regulator@14 {
  394. reg = <14>;
  395. regulator-compatible = "ldo11";
  396. regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
  397. regulator-min-microvolt = <3300000>;
  398. regulator-max-microvolt = <3300000>;
  399. };
  400. regulator@15 {
  401. reg = <15>;
  402. regulator-compatible = "ldo12";
  403. regulator-name = "nvvdd_ldo12,vddio_sdio";
  404. regulator-min-microvolt = <2800000>;
  405. regulator-max-microvolt = <2800000>;
  406. regulator-always-on;
  407. };
  408. regulator@16 {
  409. reg = <16>;
  410. regulator-compatible = "ldo13";
  411. regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
  412. regulator-min-microvolt = <2800000>;
  413. regulator-max-microvolt = <2800000>;
  414. };
  415. regulator@17 {
  416. reg = <17>;
  417. regulator-compatible = "ldo14";
  418. regulator-name = "nvvdd_ldo14,avdd_vdac";
  419. regulator-min-microvolt = <2800000>;
  420. regulator-max-microvolt = <2800000>;
  421. };
  422. regulator@18 {
  423. reg = <18>;
  424. regulator-compatible = "ldo15";
  425. regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
  426. regulator-min-microvolt = <3300000>;
  427. regulator-max-microvolt = <3300000>;
  428. };
  429. regulator@19 {
  430. reg = <19>;
  431. regulator-compatible = "ldo16";
  432. regulator-name = "nvvdd_ldo16,vdd_dbrtr";
  433. regulator-min-microvolt = <1300000>;
  434. regulator-max-microvolt = <1300000>;
  435. };
  436. regulator@20 {
  437. reg = <20>;
  438. regulator-compatible = "ldo17";
  439. regulator-name = "nvvdd_ldo17,vddio_mipi";
  440. regulator-min-microvolt = <1200000>;
  441. regulator-max-microvolt = <1200000>;
  442. };
  443. regulator@21 {
  444. reg = <21>;
  445. regulator-compatible = "ldo18";
  446. regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
  447. regulator-min-microvolt = <1800000>;
  448. regulator-max-microvolt = <1800000>;
  449. };
  450. regulator@22 {
  451. reg = <22>;
  452. regulator-compatible = "ldo19";
  453. regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
  454. regulator-min-microvolt = <2800000>;
  455. regulator-max-microvolt = <2800000>;
  456. };
  457. regulator@23 {
  458. reg = <23>;
  459. regulator-compatible = "ldo20";
  460. regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
  461. regulator-min-microvolt = <1200000>;
  462. regulator-max-microvolt = <1200000>;
  463. regulator-always-on;
  464. };
  465. regulator@24 {
  466. reg = <24>;
  467. regulator-compatible = "out5v";
  468. regulator-name = "usb0_vbus_reg";
  469. };
  470. regulator@25 {
  471. reg = <25>;
  472. regulator-compatible = "out33v";
  473. regulator-name = "pmu_out3v3";
  474. };
  475. regulator@26 {
  476. reg = <26>;
  477. regulator-compatible = "bbat";
  478. regulator-name = "pmu_bbat";
  479. regulator-min-microvolt = <2400000>;
  480. regulator-max-microvolt = <2400000>;
  481. regulator-always-on;
  482. };
  483. regulator@27 {
  484. reg = <27>;
  485. regulator-compatible = "sdby";
  486. regulator-name = "vdd_aon";
  487. regulator-always-on;
  488. };
  489. regulator@28 {
  490. reg = <28>;
  491. regulator-compatible = "vrtc";
  492. regulator-name = "vrtc,pmu_vccadc";
  493. regulator-always-on;
  494. };
  495. };
  496. };
  497. };
  498. pmc {
  499. nvidia,invert-interrupt;
  500. };
  501. usb@c5000000 {
  502. status = "okay";
  503. nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
  504. };
  505. usb@c5008000 {
  506. status = "okay";
  507. nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
  508. };
  509. sdhci@c8000400 {
  510. status = "okay";
  511. wp-gpios = <&gpio 173 0>; /* gpio PV5 */
  512. bus-width = <8>;
  513. };
  514. sdhci@c8000600 {
  515. status = "okay";
  516. bus-width = <8>;
  517. };
  518. regulators {
  519. compatible = "simple-bus";
  520. #address-cells = <1>;
  521. #size-cells = <0>;
  522. usb0_vbus_reg: regulator {
  523. compatible = "regulator-fixed";
  524. reg = <0>;
  525. regulator-name = "usb0_vbus";
  526. regulator-min-microvolt = <5000000>;
  527. regulator-max-microvolt = <5000000>;
  528. regulator-always-on;
  529. };
  530. };
  531. sound {
  532. compatible = "nvidia,tegra-audio-wm8753-whistler",
  533. "nvidia,tegra-audio-wm8753";
  534. nvidia,model = "NVIDIA Tegra Whistler";
  535. nvidia,audio-routing =
  536. "Headphone Jack", "LOUT1",
  537. "Headphone Jack", "ROUT1",
  538. "MIC2", "Mic Jack",
  539. "MIC2N", "Mic Jack";
  540. nvidia,i2s-controller = <&tegra_i2s1>;
  541. nvidia,audio-codec = <&codec>;
  542. };
  543. };