tegra20-ventana.dts 12 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra2 Ventana evaluation board";
  5. compatible = "nvidia,ventana", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata";
  15. nvidia,function = "ide";
  16. };
  17. atb {
  18. nvidia,pins = "atb", "gma", "gme";
  19. nvidia,function = "sdio4";
  20. };
  21. atc {
  22. nvidia,pins = "atc";
  23. nvidia,function = "nand";
  24. };
  25. atd {
  26. nvidia,pins = "atd", "ate", "gmb", "spia",
  27. "spib", "spic";
  28. nvidia,function = "gmi";
  29. };
  30. cdev1 {
  31. nvidia,pins = "cdev1";
  32. nvidia,function = "plla_out";
  33. };
  34. cdev2 {
  35. nvidia,pins = "cdev2";
  36. nvidia,function = "pllp_out4";
  37. };
  38. crtp {
  39. nvidia,pins = "crtp", "lm1";
  40. nvidia,function = "crt";
  41. };
  42. csus {
  43. nvidia,pins = "csus";
  44. nvidia,function = "vi_sensor_clk";
  45. };
  46. dap1 {
  47. nvidia,pins = "dap1";
  48. nvidia,function = "dap1";
  49. };
  50. dap2 {
  51. nvidia,pins = "dap2";
  52. nvidia,function = "dap2";
  53. };
  54. dap3 {
  55. nvidia,pins = "dap3";
  56. nvidia,function = "dap3";
  57. };
  58. dap4 {
  59. nvidia,pins = "dap4";
  60. nvidia,function = "dap4";
  61. };
  62. ddc {
  63. nvidia,pins = "ddc", "owc", "spdi", "spdo",
  64. "uac";
  65. nvidia,function = "rsvd2";
  66. };
  67. dta {
  68. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  69. nvidia,function = "vi";
  70. };
  71. dtf {
  72. nvidia,pins = "dtf";
  73. nvidia,function = "i2c3";
  74. };
  75. gmc {
  76. nvidia,pins = "gmc";
  77. nvidia,function = "uartd";
  78. };
  79. gmd {
  80. nvidia,pins = "gmd";
  81. nvidia,function = "sflash";
  82. };
  83. gpu {
  84. nvidia,pins = "gpu";
  85. nvidia,function = "pwm";
  86. };
  87. gpu7 {
  88. nvidia,pins = "gpu7";
  89. nvidia,function = "rtck";
  90. };
  91. gpv {
  92. nvidia,pins = "gpv", "slxa", "slxk";
  93. nvidia,function = "pcie";
  94. };
  95. hdint {
  96. nvidia,pins = "hdint", "pta";
  97. nvidia,function = "hdmi";
  98. };
  99. i2cp {
  100. nvidia,pins = "i2cp";
  101. nvidia,function = "i2cp";
  102. };
  103. irrx {
  104. nvidia,pins = "irrx", "irtx";
  105. nvidia,function = "uartb";
  106. };
  107. kbca {
  108. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  109. "kbce", "kbcf";
  110. nvidia,function = "kbc";
  111. };
  112. lcsn {
  113. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  114. "lsdi", "lvp0";
  115. nvidia,function = "rsvd4";
  116. };
  117. ld0 {
  118. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  119. "ld5", "ld6", "ld7", "ld8", "ld9",
  120. "ld10", "ld11", "ld12", "ld13", "ld14",
  121. "ld15", "ld16", "ld17", "ldi", "lhp0",
  122. "lhp1", "lhp2", "lhs", "lpp", "lpw0",
  123. "lpw2", "lsc0", "lsc1", "lsck", "lsda",
  124. "lspi", "lvp1", "lvs";
  125. nvidia,function = "displaya";
  126. };
  127. pmc {
  128. nvidia,pins = "pmc";
  129. nvidia,function = "pwr_on";
  130. };
  131. rm {
  132. nvidia,pins = "rm";
  133. nvidia,function = "i2c1";
  134. };
  135. sdb {
  136. nvidia,pins = "sdb", "sdc", "sdd", "slxc";
  137. nvidia,function = "sdio3";
  138. };
  139. sdio1 {
  140. nvidia,pins = "sdio1";
  141. nvidia,function = "sdio1";
  142. };
  143. slxd {
  144. nvidia,pins = "slxd";
  145. nvidia,function = "spdif";
  146. };
  147. spid {
  148. nvidia,pins = "spid", "spie", "spif";
  149. nvidia,function = "spi1";
  150. };
  151. spig {
  152. nvidia,pins = "spig", "spih";
  153. nvidia,function = "spi2_alt";
  154. };
  155. uaa {
  156. nvidia,pins = "uaa", "uab", "uda";
  157. nvidia,function = "ulpi";
  158. };
  159. uad {
  160. nvidia,pins = "uad";
  161. nvidia,function = "irda";
  162. };
  163. uca {
  164. nvidia,pins = "uca", "ucb";
  165. nvidia,function = "uartc";
  166. };
  167. conf_ata {
  168. nvidia,pins = "ata", "atb", "atc", "atd",
  169. "cdev1", "cdev2", "dap1", "dap2",
  170. "dap4", "ddc", "dtf", "gma", "gmc",
  171. "gme", "gpu", "gpu7", "i2cp", "irrx",
  172. "irtx", "pta", "rm", "sdc", "sdd",
  173. "slxc", "slxd", "slxk", "spdi", "spdo",
  174. "uac", "uad", "uca", "ucb", "uda";
  175. nvidia,pull = <0>;
  176. nvidia,tristate = <0>;
  177. };
  178. conf_ate {
  179. nvidia,pins = "ate", "csus", "dap3", "gmd",
  180. "gpv", "owc", "spia", "spib", "spic",
  181. "spid", "spie", "spig";
  182. nvidia,pull = <0>;
  183. nvidia,tristate = <1>;
  184. };
  185. conf_ck32 {
  186. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  187. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  188. nvidia,pull = <0>;
  189. };
  190. conf_crtp {
  191. nvidia,pins = "crtp", "gmb", "slxa", "spih";
  192. nvidia,pull = <2>;
  193. nvidia,tristate = <1>;
  194. };
  195. conf_dta {
  196. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  197. nvidia,pull = <1>;
  198. nvidia,tristate = <0>;
  199. };
  200. conf_dte {
  201. nvidia,pins = "dte", "spif";
  202. nvidia,pull = <1>;
  203. nvidia,tristate = <1>;
  204. };
  205. conf_hdint {
  206. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  207. "lpw1", "lsck", "lsda", "lsdi", "lvp0";
  208. nvidia,tristate = <1>;
  209. };
  210. conf_kbca {
  211. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  212. "kbce", "kbcf", "sdio1", "uaa", "uab";
  213. nvidia,pull = <2>;
  214. nvidia,tristate = <0>;
  215. };
  216. conf_lc {
  217. nvidia,pins = "lc", "ls";
  218. nvidia,pull = <2>;
  219. };
  220. conf_ld0 {
  221. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  222. "ld5", "ld6", "ld7", "ld8", "ld9",
  223. "ld10", "ld11", "ld12", "ld13", "ld14",
  224. "ld15", "ld16", "ld17", "ldi", "lhp0",
  225. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  226. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  227. "lvp1", "lvs", "pmc", "sdb";
  228. nvidia,tristate = <0>;
  229. };
  230. conf_ld17_0 {
  231. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  232. "ld23_22";
  233. nvidia,pull = <1>;
  234. };
  235. };
  236. };
  237. i2s@70002800 {
  238. status = "okay";
  239. };
  240. serial@70006300 {
  241. status = "okay";
  242. clock-frequency = <216000000>;
  243. };
  244. i2c@7000c000 {
  245. status = "okay";
  246. clock-frequency = <400000>;
  247. wm8903: wm8903@1a {
  248. compatible = "wlf,wm8903";
  249. reg = <0x1a>;
  250. interrupt-parent = <&gpio>;
  251. interrupts = <187 0x04>;
  252. gpio-controller;
  253. #gpio-cells = <2>;
  254. micdet-cfg = <0>;
  255. micdet-delay = <100>;
  256. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  257. };
  258. /* ALS and proximity sensor */
  259. isl29018@44 {
  260. compatible = "isil,isl29018";
  261. reg = <0x44>;
  262. interrupt-parent = <&gpio>;
  263. interrupts = <202 0x04>; /*gpio PZ2 */
  264. };
  265. };
  266. i2c@7000c400 {
  267. status = "okay";
  268. clock-frequency = <400000>;
  269. };
  270. i2c@7000c500 {
  271. status = "okay";
  272. clock-frequency = <400000>;
  273. };
  274. i2c@7000d000 {
  275. status = "okay";
  276. clock-frequency = <400000>;
  277. pmic: tps6586x@34 {
  278. compatible = "ti,tps6586x";
  279. reg = <0x34>;
  280. interrupts = <0 86 0x4>;
  281. ti,system-power-controller;
  282. #gpio-cells = <2>;
  283. gpio-controller;
  284. sys-supply = <&vdd_5v0_reg>;
  285. vin-sm0-supply = <&sys_reg>;
  286. vin-sm1-supply = <&sys_reg>;
  287. vin-sm2-supply = <&sys_reg>;
  288. vinldo01-supply = <&sm2_reg>;
  289. vinldo23-supply = <&sm2_reg>;
  290. vinldo4-supply = <&sm2_reg>;
  291. vinldo678-supply = <&sm2_reg>;
  292. vinldo9-supply = <&sm2_reg>;
  293. regulators {
  294. #address-cells = <1>;
  295. #size-cells = <0>;
  296. sys_reg: regulator@0 {
  297. reg = <0>;
  298. regulator-compatible = "sys";
  299. regulator-name = "vdd_sys";
  300. regulator-always-on;
  301. };
  302. regulator@1 {
  303. reg = <1>;
  304. regulator-compatible = "sm0";
  305. regulator-name = "vdd_sm0,vdd_core";
  306. regulator-min-microvolt = <1200000>;
  307. regulator-max-microvolt = <1200000>;
  308. regulator-always-on;
  309. };
  310. regulator@2 {
  311. reg = <2>;
  312. regulator-compatible = "sm1";
  313. regulator-name = "vdd_sm1,vdd_cpu";
  314. regulator-min-microvolt = <1000000>;
  315. regulator-max-microvolt = <1000000>;
  316. regulator-always-on;
  317. };
  318. sm2_reg: regulator@3 {
  319. reg = <3>;
  320. regulator-compatible = "sm2";
  321. regulator-name = "vdd_sm2,vin_ldo*";
  322. regulator-min-microvolt = <3700000>;
  323. regulator-max-microvolt = <3700000>;
  324. regulator-always-on;
  325. };
  326. /* LDO0 is not connected to anything */
  327. regulator@5 {
  328. reg = <5>;
  329. regulator-compatible = "ldo1";
  330. regulator-name = "vdd_ldo1,avdd_pll*";
  331. regulator-min-microvolt = <1100000>;
  332. regulator-max-microvolt = <1100000>;
  333. regulator-always-on;
  334. };
  335. regulator@6 {
  336. reg = <6>;
  337. regulator-compatible = "ldo2";
  338. regulator-name = "vdd_ldo2,vdd_rtc";
  339. regulator-min-microvolt = <1200000>;
  340. regulator-max-microvolt = <1200000>;
  341. };
  342. regulator@7 {
  343. reg = <7>;
  344. regulator-compatible = "ldo3";
  345. regulator-name = "vdd_ldo3,avdd_usb*";
  346. regulator-min-microvolt = <3300000>;
  347. regulator-max-microvolt = <3300000>;
  348. regulator-always-on;
  349. };
  350. regulator@8 {
  351. reg = <8>;
  352. regulator-compatible = "ldo4";
  353. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  354. regulator-min-microvolt = <1800000>;
  355. regulator-max-microvolt = <1800000>;
  356. regulator-always-on;
  357. };
  358. regulator@9 {
  359. reg = <9>;
  360. regulator-compatible = "ldo5";
  361. regulator-name = "vdd_ldo5,vcore_mmc";
  362. regulator-min-microvolt = <2850000>;
  363. regulator-max-microvolt = <2850000>;
  364. regulator-always-on;
  365. };
  366. regulator@10 {
  367. reg = <10>;
  368. regulator-compatible = "ldo6";
  369. regulator-name = "vdd_ldo6,avdd_vdac";
  370. regulator-min-microvolt = <1800000>;
  371. regulator-max-microvolt = <1800000>;
  372. };
  373. regulator@11 {
  374. reg = <11>;
  375. regulator-compatible = "ldo7";
  376. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  377. regulator-min-microvolt = <3300000>;
  378. regulator-max-microvolt = <3300000>;
  379. };
  380. regulator@12 {
  381. reg = <12>;
  382. regulator-compatible = "ldo8";
  383. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  384. regulator-min-microvolt = <1800000>;
  385. regulator-max-microvolt = <1800000>;
  386. };
  387. regulator@13 {
  388. reg = <13>;
  389. regulator-compatible = "ldo9";
  390. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  391. regulator-min-microvolt = <2850000>;
  392. regulator-max-microvolt = <2850000>;
  393. regulator-always-on;
  394. };
  395. regulator@14 {
  396. reg = <14>;
  397. regulator-compatible = "ldo_rtc";
  398. regulator-name = "vdd_rtc_out,vdd_cell";
  399. regulator-min-microvolt = <3300000>;
  400. regulator-max-microvolt = <3300000>;
  401. regulator-always-on;
  402. };
  403. };
  404. };
  405. };
  406. pmc {
  407. nvidia,invert-interrupt;
  408. };
  409. usb@c5000000 {
  410. status = "okay";
  411. };
  412. usb@c5004000 {
  413. status = "okay";
  414. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  415. };
  416. usb@c5008000 {
  417. status = "okay";
  418. };
  419. sdhci@c8000400 {
  420. status = "okay";
  421. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  422. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  423. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  424. bus-width = <4>;
  425. };
  426. sdhci@c8000600 {
  427. status = "okay";
  428. bus-width = <8>;
  429. };
  430. regulators {
  431. compatible = "simple-bus";
  432. #address-cells = <1>;
  433. #size-cells = <0>;
  434. vdd_5v0_reg: regulator@0 {
  435. compatible = "regulator-fixed";
  436. reg = <0>;
  437. regulator-name = "vdd_5v0";
  438. regulator-min-microvolt = <5000000>;
  439. regulator-max-microvolt = <5000000>;
  440. regulator-always-on;
  441. };
  442. regulator@1 {
  443. compatible = "regulator-fixed";
  444. reg = <1>;
  445. regulator-name = "vdd_1v5";
  446. regulator-min-microvolt = <1500000>;
  447. regulator-max-microvolt = <1500000>;
  448. gpio = <&pmic 0 0>;
  449. };
  450. regulator@2 {
  451. compatible = "regulator-fixed";
  452. reg = <2>;
  453. regulator-name = "vdd_1v2";
  454. regulator-min-microvolt = <1200000>;
  455. regulator-max-microvolt = <1200000>;
  456. gpio = <&pmic 1 0>;
  457. enable-active-high;
  458. };
  459. regulator@3 {
  460. compatible = "regulator-fixed";
  461. reg = <3>;
  462. regulator-name = "vdd_pnl";
  463. regulator-min-microvolt = <2800000>;
  464. regulator-max-microvolt = <2800000>;
  465. gpio = <&gpio 22 0>; /* gpio PC6 */
  466. enable-active-high;
  467. };
  468. regulator@4 {
  469. compatible = "regulator-fixed";
  470. reg = <4>;
  471. regulator-name = "vdd_bl";
  472. regulator-min-microvolt = <2800000>;
  473. regulator-max-microvolt = <2800000>;
  474. gpio = <&gpio 176 0>; /* gpio PW0 */
  475. enable-active-high;
  476. };
  477. };
  478. sound {
  479. compatible = "nvidia,tegra-audio-wm8903-ventana",
  480. "nvidia,tegra-audio-wm8903";
  481. nvidia,model = "NVIDIA Tegra Ventana";
  482. nvidia,audio-routing =
  483. "Headphone Jack", "HPOUTR",
  484. "Headphone Jack", "HPOUTL",
  485. "Int Spk", "ROP",
  486. "Int Spk", "RON",
  487. "Int Spk", "LOP",
  488. "Int Spk", "LON",
  489. "Mic Jack", "MICBIAS",
  490. "IN1L", "Mic Jack";
  491. nvidia,i2s-controller = <&tegra_i2s1>;
  492. nvidia,audio-codec = <&wm8903>;
  493. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  494. nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
  495. nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
  496. nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
  497. };
  498. };