tegra20-harmony.dts 12 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra2 Harmony evaluation board";
  5. compatible = "nvidia,harmony", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata";
  15. nvidia,function = "ide";
  16. };
  17. atb {
  18. nvidia,pins = "atb", "gma", "gme";
  19. nvidia,function = "sdio4";
  20. };
  21. atc {
  22. nvidia,pins = "atc";
  23. nvidia,function = "nand";
  24. };
  25. atd {
  26. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  27. "spia", "spib", "spic";
  28. nvidia,function = "gmi";
  29. };
  30. cdev1 {
  31. nvidia,pins = "cdev1";
  32. nvidia,function = "plla_out";
  33. };
  34. cdev2 {
  35. nvidia,pins = "cdev2";
  36. nvidia,function = "pllp_out4";
  37. };
  38. crtp {
  39. nvidia,pins = "crtp";
  40. nvidia,function = "crt";
  41. };
  42. csus {
  43. nvidia,pins = "csus";
  44. nvidia,function = "vi_sensor_clk";
  45. };
  46. dap1 {
  47. nvidia,pins = "dap1";
  48. nvidia,function = "dap1";
  49. };
  50. dap2 {
  51. nvidia,pins = "dap2";
  52. nvidia,function = "dap2";
  53. };
  54. dap3 {
  55. nvidia,pins = "dap3";
  56. nvidia,function = "dap3";
  57. };
  58. dap4 {
  59. nvidia,pins = "dap4";
  60. nvidia,function = "dap4";
  61. };
  62. ddc {
  63. nvidia,pins = "ddc";
  64. nvidia,function = "i2c2";
  65. };
  66. dta {
  67. nvidia,pins = "dta", "dtd";
  68. nvidia,function = "sdio2";
  69. };
  70. dtb {
  71. nvidia,pins = "dtb", "dtc", "dte";
  72. nvidia,function = "rsvd1";
  73. };
  74. dtf {
  75. nvidia,pins = "dtf";
  76. nvidia,function = "i2c3";
  77. };
  78. gmc {
  79. nvidia,pins = "gmc";
  80. nvidia,function = "uartd";
  81. };
  82. gpu7 {
  83. nvidia,pins = "gpu7";
  84. nvidia,function = "rtck";
  85. };
  86. gpv {
  87. nvidia,pins = "gpv", "slxa", "slxk";
  88. nvidia,function = "pcie";
  89. };
  90. hdint {
  91. nvidia,pins = "hdint", "pta";
  92. nvidia,function = "hdmi";
  93. };
  94. i2cp {
  95. nvidia,pins = "i2cp";
  96. nvidia,function = "i2cp";
  97. };
  98. irrx {
  99. nvidia,pins = "irrx", "irtx";
  100. nvidia,function = "uarta";
  101. };
  102. kbca {
  103. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  104. "kbce", "kbcf";
  105. nvidia,function = "kbc";
  106. };
  107. lcsn {
  108. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  109. "ld3", "ld4", "ld5", "ld6", "ld7",
  110. "ld8", "ld9", "ld10", "ld11", "ld12",
  111. "ld13", "ld14", "ld15", "ld16", "ld17",
  112. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  113. "lhs", "lm0", "lm1", "lpp", "lpw0",
  114. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  115. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  116. "lvs";
  117. nvidia,function = "displaya";
  118. };
  119. owc {
  120. nvidia,pins = "owc", "spdi", "spdo", "uac";
  121. nvidia,function = "rsvd2";
  122. };
  123. pmc {
  124. nvidia,pins = "pmc";
  125. nvidia,function = "pwr_on";
  126. };
  127. rm {
  128. nvidia,pins = "rm";
  129. nvidia,function = "i2c1";
  130. };
  131. sdb {
  132. nvidia,pins = "sdb", "sdc", "sdd";
  133. nvidia,function = "pwm";
  134. };
  135. sdio1 {
  136. nvidia,pins = "sdio1";
  137. nvidia,function = "sdio1";
  138. };
  139. slxc {
  140. nvidia,pins = "slxc", "slxd";
  141. nvidia,function = "spdif";
  142. };
  143. spid {
  144. nvidia,pins = "spid", "spie", "spif";
  145. nvidia,function = "spi1";
  146. };
  147. spig {
  148. nvidia,pins = "spig", "spih";
  149. nvidia,function = "spi2_alt";
  150. };
  151. uaa {
  152. nvidia,pins = "uaa", "uab", "uda";
  153. nvidia,function = "ulpi";
  154. };
  155. uad {
  156. nvidia,pins = "uad";
  157. nvidia,function = "irda";
  158. };
  159. uca {
  160. nvidia,pins = "uca", "ucb";
  161. nvidia,function = "uartc";
  162. };
  163. conf_ata {
  164. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  165. "cdev1", "cdev2", "dap1", "dtb", "gma",
  166. "gmb", "gmc", "gmd", "gme", "gpu7",
  167. "gpv", "i2cp", "pta", "rm", "slxa",
  168. "slxk", "spia", "spib", "uac";
  169. nvidia,pull = <0>;
  170. nvidia,tristate = <0>;
  171. };
  172. conf_ck32 {
  173. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  174. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  175. nvidia,pull = <0>;
  176. };
  177. conf_csus {
  178. nvidia,pins = "csus", "spid", "spif";
  179. nvidia,pull = <1>;
  180. nvidia,tristate = <1>;
  181. };
  182. conf_crtp {
  183. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  184. "dtc", "dte", "dtf", "gpu", "sdio1",
  185. "slxc", "slxd", "spdi", "spdo", "spig",
  186. "uda";
  187. nvidia,pull = <0>;
  188. nvidia,tristate = <1>;
  189. };
  190. conf_ddc {
  191. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  192. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  193. "sdc";
  194. nvidia,pull = <2>;
  195. nvidia,tristate = <0>;
  196. };
  197. conf_hdint {
  198. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  199. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  200. "lvp0", "owc", "sdb";
  201. nvidia,tristate = <1>;
  202. };
  203. conf_irrx {
  204. nvidia,pins = "irrx", "irtx", "sdd", "spic",
  205. "spie", "spih", "uaa", "uab", "uad",
  206. "uca", "ucb";
  207. nvidia,pull = <2>;
  208. nvidia,tristate = <1>;
  209. };
  210. conf_lc {
  211. nvidia,pins = "lc", "ls";
  212. nvidia,pull = <2>;
  213. };
  214. conf_ld0 {
  215. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  216. "ld5", "ld6", "ld7", "ld8", "ld9",
  217. "ld10", "ld11", "ld12", "ld13", "ld14",
  218. "ld15", "ld16", "ld17", "ldi", "lhp0",
  219. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  220. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  221. "lvs", "pmc";
  222. nvidia,tristate = <0>;
  223. };
  224. conf_ld17_0 {
  225. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  226. "ld23_22";
  227. nvidia,pull = <1>;
  228. };
  229. };
  230. };
  231. i2s@70002800 {
  232. status = "okay";
  233. };
  234. serial@70006300 {
  235. status = "okay";
  236. clock-frequency = <216000000>;
  237. };
  238. i2c@7000c000 {
  239. status = "okay";
  240. clock-frequency = <400000>;
  241. wm8903: wm8903@1a {
  242. compatible = "wlf,wm8903";
  243. reg = <0x1a>;
  244. interrupt-parent = <&gpio>;
  245. interrupts = <187 0x04>;
  246. gpio-controller;
  247. #gpio-cells = <2>;
  248. micdet-cfg = <0>;
  249. micdet-delay = <100>;
  250. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  251. };
  252. };
  253. i2c@7000c400 {
  254. status = "okay";
  255. clock-frequency = <400000>;
  256. };
  257. i2c@7000c500 {
  258. status = "okay";
  259. clock-frequency = <400000>;
  260. };
  261. i2c@7000d000 {
  262. status = "okay";
  263. clock-frequency = <400000>;
  264. pmic: tps6586x@34 {
  265. compatible = "ti,tps6586x";
  266. reg = <0x34>;
  267. interrupts = <0 86 0x4>;
  268. ti,system-power-controller;
  269. #gpio-cells = <2>;
  270. gpio-controller;
  271. sys-supply = <&vdd_5v0_reg>;
  272. vin-sm0-supply = <&sys_reg>;
  273. vin-sm1-supply = <&sys_reg>;
  274. vin-sm2-supply = <&sys_reg>;
  275. vinldo01-supply = <&sm2_reg>;
  276. vinldo23-supply = <&sm2_reg>;
  277. vinldo4-supply = <&sm2_reg>;
  278. vinldo678-supply = <&sm2_reg>;
  279. vinldo9-supply = <&sm2_reg>;
  280. regulators {
  281. #address-cells = <1>;
  282. #size-cells = <0>;
  283. sys_reg: regulator@0 {
  284. reg = <0>;
  285. regulator-compatible = "sys";
  286. regulator-name = "vdd_sys";
  287. regulator-always-on;
  288. };
  289. regulator@1 {
  290. reg = <1>;
  291. regulator-compatible = "sm0";
  292. regulator-name = "vdd_sm0,vdd_core";
  293. regulator-min-microvolt = <1200000>;
  294. regulator-max-microvolt = <1200000>;
  295. regulator-always-on;
  296. };
  297. regulator@2 {
  298. reg = <2>;
  299. regulator-compatible = "sm1";
  300. regulator-name = "vdd_sm1,vdd_cpu";
  301. regulator-min-microvolt = <1000000>;
  302. regulator-max-microvolt = <1000000>;
  303. regulator-always-on;
  304. };
  305. sm2_reg: regulator@3 {
  306. reg = <3>;
  307. regulator-compatible = "sm2";
  308. regulator-name = "vdd_sm2,vin_ldo*";
  309. regulator-min-microvolt = <3700000>;
  310. regulator-max-microvolt = <3700000>;
  311. regulator-always-on;
  312. };
  313. regulator@4 {
  314. reg = <4>;
  315. regulator-compatible = "ldo0";
  316. regulator-name = "vdd_ldo0,vddio_pex_clk";
  317. regulator-min-microvolt = <3300000>;
  318. regulator-max-microvolt = <3300000>;
  319. };
  320. regulator@5 {
  321. reg = <5>;
  322. regulator-compatible = "ldo1";
  323. regulator-name = "vdd_ldo1,avdd_pll*";
  324. regulator-min-microvolt = <1100000>;
  325. regulator-max-microvolt = <1100000>;
  326. regulator-always-on;
  327. };
  328. regulator@6 {
  329. reg = <6>;
  330. regulator-compatible = "ldo2";
  331. regulator-name = "vdd_ldo2,vdd_rtc";
  332. regulator-min-microvolt = <1200000>;
  333. regulator-max-microvolt = <1200000>;
  334. };
  335. regulator@7 {
  336. reg = <7>;
  337. regulator-compatible = "ldo3";
  338. regulator-name = "vdd_ldo3,avdd_usb*";
  339. regulator-min-microvolt = <3300000>;
  340. regulator-max-microvolt = <3300000>;
  341. regulator-always-on;
  342. };
  343. regulator@8 {
  344. reg = <8>;
  345. regulator-compatible = "ldo4";
  346. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  347. regulator-min-microvolt = <1800000>;
  348. regulator-max-microvolt = <1800000>;
  349. regulator-always-on;
  350. };
  351. regulator@9 {
  352. reg = <9>;
  353. regulator-compatible = "ldo5";
  354. regulator-name = "vdd_ldo5,vcore_mmc";
  355. regulator-min-microvolt = <2850000>;
  356. regulator-max-microvolt = <2850000>;
  357. regulator-always-on;
  358. };
  359. regulator@10 {
  360. reg = <10>;
  361. regulator-compatible = "ldo6";
  362. regulator-name = "vdd_ldo6,avdd_vdac";
  363. regulator-min-microvolt = <1800000>;
  364. regulator-max-microvolt = <1800000>;
  365. };
  366. regulator@11 {
  367. reg = <11>;
  368. regulator-compatible = "ldo7";
  369. regulator-name = "vdd_ldo7,avdd_hdmi";
  370. regulator-min-microvolt = <3300000>;
  371. regulator-max-microvolt = <3300000>;
  372. };
  373. regulator@12 {
  374. reg = <12>;
  375. regulator-compatible = "ldo8";
  376. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  377. regulator-min-microvolt = <1800000>;
  378. regulator-max-microvolt = <1800000>;
  379. };
  380. regulator@13 {
  381. reg = <13>;
  382. regulator-compatible = "ldo9";
  383. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  384. regulator-min-microvolt = <2850000>;
  385. regulator-max-microvolt = <2850000>;
  386. regulator-always-on;
  387. };
  388. regulator@14 {
  389. reg = <14>;
  390. regulator-compatible = "ldo_rtc";
  391. regulator-name = "vdd_rtc_out,vdd_cell";
  392. regulator-min-microvolt = <3300000>;
  393. regulator-max-microvolt = <3300000>;
  394. regulator-always-on;
  395. };
  396. };
  397. };
  398. };
  399. pmc {
  400. nvidia,invert-interrupt;
  401. };
  402. usb@c5000000 {
  403. status = "okay";
  404. };
  405. usb@c5004000 {
  406. status = "okay";
  407. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  408. };
  409. usb@c5008000 {
  410. status = "okay";
  411. };
  412. sdhci@c8000200 {
  413. status = "okay";
  414. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  415. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  416. power-gpios = <&gpio 155 0>; /* gpio PT3 */
  417. bus-width = <4>;
  418. };
  419. sdhci@c8000600 {
  420. status = "okay";
  421. cd-gpios = <&gpio 58 0>; /* gpio PH2 */
  422. wp-gpios = <&gpio 59 0>; /* gpio PH3 */
  423. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  424. bus-width = <8>;
  425. };
  426. regulators {
  427. compatible = "simple-bus";
  428. #address-cells = <1>;
  429. #size-cells = <0>;
  430. vdd_5v0_reg: regulator@0 {
  431. compatible = "regulator-fixed";
  432. reg = <0>;
  433. regulator-name = "vdd_5v0";
  434. regulator-min-microvolt = <5000000>;
  435. regulator-max-microvolt = <5000000>;
  436. regulator-always-on;
  437. };
  438. regulator@1 {
  439. compatible = "regulator-fixed";
  440. reg = <1>;
  441. regulator-name = "vdd_1v5";
  442. regulator-min-microvolt = <1500000>;
  443. regulator-max-microvolt = <1500000>;
  444. gpio = <&pmic 0 0>;
  445. };
  446. regulator@2 {
  447. compatible = "regulator-fixed";
  448. reg = <2>;
  449. regulator-name = "vdd_1v2";
  450. regulator-min-microvolt = <1200000>;
  451. regulator-max-microvolt = <1200000>;
  452. gpio = <&pmic 1 0>;
  453. enable-active-high;
  454. };
  455. regulator@3 {
  456. compatible = "regulator-fixed";
  457. reg = <3>;
  458. regulator-name = "vdd_1v05";
  459. regulator-min-microvolt = <1050000>;
  460. regulator-max-microvolt = <1050000>;
  461. gpio = <&pmic 2 0>;
  462. enable-active-high;
  463. /* Hack until board-harmony-pcie.c is removed */
  464. status = "disabled";
  465. };
  466. regulator@4 {
  467. compatible = "regulator-fixed";
  468. reg = <4>;
  469. regulator-name = "vdd_pnl";
  470. regulator-min-microvolt = <2800000>;
  471. regulator-max-microvolt = <2800000>;
  472. gpio = <&gpio 22 0>; /* gpio PC6 */
  473. enable-active-high;
  474. };
  475. regulator@5 {
  476. compatible = "regulator-fixed";
  477. reg = <5>;
  478. regulator-name = "vdd_bl";
  479. regulator-min-microvolt = <2800000>;
  480. regulator-max-microvolt = <2800000>;
  481. gpio = <&gpio 176 0>; /* gpio PW0 */
  482. enable-active-high;
  483. };
  484. };
  485. sound {
  486. compatible = "nvidia,tegra-audio-wm8903-harmony",
  487. "nvidia,tegra-audio-wm8903";
  488. nvidia,model = "NVIDIA Tegra Harmony";
  489. nvidia,audio-routing =
  490. "Headphone Jack", "HPOUTR",
  491. "Headphone Jack", "HPOUTL",
  492. "Int Spk", "ROP",
  493. "Int Spk", "RON",
  494. "Int Spk", "LOP",
  495. "Int Spk", "LON",
  496. "Mic Jack", "MICBIAS",
  497. "IN1L", "Mic Jack";
  498. nvidia,i2s-controller = <&tegra_i2s1>;
  499. nvidia,audio-codec = <&wm8903>;
  500. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  501. nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
  502. nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
  503. nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
  504. };
  505. };