at91sam9n12.dtsi 5.1 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. };
  29. cpus {
  30. cpu@0 {
  31. compatible = "arm,arm926ejs";
  32. };
  33. };
  34. memory {
  35. reg = <0x20000000 0x10000000>;
  36. };
  37. ahb {
  38. compatible = "simple-bus";
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. ranges;
  42. apb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. aic: interrupt-controller@fffff000 {
  48. #interrupt-cells = <3>;
  49. compatible = "atmel,at91rm9200-aic";
  50. interrupt-controller;
  51. reg = <0xfffff000 0x200>;
  52. };
  53. ramc0: ramc@ffffe800 {
  54. compatible = "atmel,at91sam9g45-ddramc";
  55. reg = <0xffffe800 0x200>;
  56. };
  57. pmc: pmc@fffffc00 {
  58. compatible = "atmel,at91rm9200-pmc";
  59. reg = <0xfffffc00 0x100>;
  60. };
  61. rstc@fffffe00 {
  62. compatible = "atmel,at91sam9g45-rstc";
  63. reg = <0xfffffe00 0x10>;
  64. };
  65. pit: timer@fffffe30 {
  66. compatible = "atmel,at91sam9260-pit";
  67. reg = <0xfffffe30 0xf>;
  68. interrupts = <1 4 7>;
  69. };
  70. shdwc@fffffe10 {
  71. compatible = "atmel,at91sam9x5-shdwc";
  72. reg = <0xfffffe10 0x10>;
  73. };
  74. tcb0: timer@f8008000 {
  75. compatible = "atmel,at91sam9x5-tcb";
  76. reg = <0xf8008000 0x100>;
  77. interrupts = <17 4 0>;
  78. };
  79. tcb1: timer@f800c000 {
  80. compatible = "atmel,at91sam9x5-tcb";
  81. reg = <0xf800c000 0x100>;
  82. interrupts = <17 4 0>;
  83. };
  84. dma: dma-controller@ffffec00 {
  85. compatible = "atmel,at91sam9g45-dma";
  86. reg = <0xffffec00 0x200>;
  87. interrupts = <20 4 0>;
  88. };
  89. pioA: gpio@fffff400 {
  90. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  91. reg = <0xfffff400 0x100>;
  92. interrupts = <2 4 1>;
  93. #gpio-cells = <2>;
  94. gpio-controller;
  95. interrupt-controller;
  96. #interrupt-cells = <2>;
  97. };
  98. pioB: gpio@fffff600 {
  99. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  100. reg = <0xfffff600 0x100>;
  101. interrupts = <2 4 1>;
  102. #gpio-cells = <2>;
  103. gpio-controller;
  104. interrupt-controller;
  105. #interrupt-cells = <2>;
  106. };
  107. pioC: gpio@fffff800 {
  108. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  109. reg = <0xfffff800 0x100>;
  110. interrupts = <3 4 1>;
  111. #gpio-cells = <2>;
  112. gpio-controller;
  113. interrupt-controller;
  114. #interrupt-cells = <2>;
  115. };
  116. pioD: gpio@fffffa00 {
  117. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  118. reg = <0xfffffa00 0x100>;
  119. interrupts = <3 4 1>;
  120. #gpio-cells = <2>;
  121. gpio-controller;
  122. interrupt-controller;
  123. #interrupt-cells = <2>;
  124. };
  125. dbgu: serial@fffff200 {
  126. compatible = "atmel,at91sam9260-usart";
  127. reg = <0xfffff200 0x200>;
  128. interrupts = <1 4 7>;
  129. status = "disabled";
  130. };
  131. usart0: serial@f801c000 {
  132. compatible = "atmel,at91sam9260-usart";
  133. reg = <0xf801c000 0x4000>;
  134. interrupts = <5 4 5>;
  135. atmel,use-dma-rx;
  136. atmel,use-dma-tx;
  137. status = "disabled";
  138. };
  139. usart1: serial@f8020000 {
  140. compatible = "atmel,at91sam9260-usart";
  141. reg = <0xf8020000 0x4000>;
  142. interrupts = <6 4 5>;
  143. atmel,use-dma-rx;
  144. atmel,use-dma-tx;
  145. status = "disabled";
  146. };
  147. usart2: serial@f8024000 {
  148. compatible = "atmel,at91sam9260-usart";
  149. reg = <0xf8024000 0x4000>;
  150. interrupts = <7 4 5>;
  151. atmel,use-dma-rx;
  152. atmel,use-dma-tx;
  153. status = "disabled";
  154. };
  155. usart3: serial@f8028000 {
  156. compatible = "atmel,at91sam9260-usart";
  157. reg = <0xf8028000 0x4000>;
  158. interrupts = <8 4 5>;
  159. atmel,use-dma-rx;
  160. atmel,use-dma-tx;
  161. status = "disabled";
  162. };
  163. i2c0: i2c@f8010000 {
  164. compatible = "atmel,at91sam9x5-i2c";
  165. reg = <0xf8010000 0x100>;
  166. interrupts = <9 4 6>;
  167. #address-cells = <1>;
  168. #size-cells = <0>;
  169. status = "disabled";
  170. };
  171. i2c1: i2c@f8014000 {
  172. compatible = "atmel,at91sam9x5-i2c";
  173. reg = <0xf8014000 0x100>;
  174. interrupts = <10 4 6>;
  175. #address-cells = <1>;
  176. #size-cells = <0>;
  177. status = "disabled";
  178. };
  179. };
  180. nand0: nand@40000000 {
  181. compatible = "atmel,at91rm9200-nand";
  182. #address-cells = <1>;
  183. #size-cells = <1>;
  184. reg = < 0x40000000 0x10000000
  185. 0xffffe000 0x00000600
  186. 0xffffe600 0x00000200
  187. 0x00100000 0x00100000
  188. >;
  189. atmel,nand-addr-offset = <21>;
  190. atmel,nand-cmd-offset = <22>;
  191. gpios = <&pioD 5 0
  192. &pioD 4 0
  193. 0
  194. >;
  195. status = "disabled";
  196. };
  197. usb0: ohci@00500000 {
  198. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  199. reg = <0x00500000 0x00100000>;
  200. interrupts = <22 4 2>;
  201. status = "disabled";
  202. };
  203. };
  204. i2c@0 {
  205. compatible = "i2c-gpio";
  206. gpios = <&pioA 30 0 /* sda */
  207. &pioA 31 0 /* scl */
  208. >;
  209. i2c-gpio,sda-open-drain;
  210. i2c-gpio,scl-open-drain;
  211. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. status = "disabled";
  215. };
  216. };