synclink_cs.c 111 KB

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  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/module.h>
  36. #include <linux/errno.h>
  37. #include <linux/signal.h>
  38. #include <linux/sched.h>
  39. #include <linux/timer.h>
  40. #include <linux/time.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/tty.h>
  43. #include <linux/tty_flip.h>
  44. #include <linux/serial.h>
  45. #include <linux/major.h>
  46. #include <linux/string.h>
  47. #include <linux/fcntl.h>
  48. #include <linux/ptrace.h>
  49. #include <linux/ioport.h>
  50. #include <linux/mm.h>
  51. #include <linux/seq_file.h>
  52. #include <linux/slab.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/vmalloc.h>
  55. #include <linux/init.h>
  56. #include <linux/delay.h>
  57. #include <linux/ioctl.h>
  58. #include <linux/synclink.h>
  59. #include <asm/system.h>
  60. #include <asm/io.h>
  61. #include <asm/irq.h>
  62. #include <asm/dma.h>
  63. #include <linux/bitops.h>
  64. #include <asm/types.h>
  65. #include <linux/termios.h>
  66. #include <linux/workqueue.h>
  67. #include <linux/hdlc.h>
  68. #include <pcmcia/cs_types.h>
  69. #include <pcmcia/cs.h>
  70. #include <pcmcia/cistpl.h>
  71. #include <pcmcia/cisreg.h>
  72. #include <pcmcia/ds.h>
  73. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
  74. #define SYNCLINK_GENERIC_HDLC 1
  75. #else
  76. #define SYNCLINK_GENERIC_HDLC 0
  77. #endif
  78. #define GET_USER(error,value,addr) error = get_user(value,addr)
  79. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  80. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  81. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  82. #include <asm/uaccess.h>
  83. static MGSL_PARAMS default_params = {
  84. MGSL_MODE_HDLC, /* unsigned long mode */
  85. 0, /* unsigned char loopback; */
  86. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  87. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  88. 0, /* unsigned long clock_speed; */
  89. 0xff, /* unsigned char addr_filter; */
  90. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  91. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  92. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  93. 9600, /* unsigned long data_rate; */
  94. 8, /* unsigned char data_bits; */
  95. 1, /* unsigned char stop_bits; */
  96. ASYNC_PARITY_NONE /* unsigned char parity; */
  97. };
  98. typedef struct
  99. {
  100. int count;
  101. unsigned char status;
  102. char data[1];
  103. } RXBUF;
  104. /* The queue of BH actions to be performed */
  105. #define BH_RECEIVE 1
  106. #define BH_TRANSMIT 2
  107. #define BH_STATUS 4
  108. #define IO_PIN_SHUTDOWN_LIMIT 100
  109. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  110. struct _input_signal_events {
  111. int ri_up;
  112. int ri_down;
  113. int dsr_up;
  114. int dsr_down;
  115. int dcd_up;
  116. int dcd_down;
  117. int cts_up;
  118. int cts_down;
  119. };
  120. /*
  121. * Device instance data structure
  122. */
  123. typedef struct _mgslpc_info {
  124. struct tty_port port;
  125. void *if_ptr; /* General purpose pointer (used by SPPP) */
  126. int magic;
  127. int line;
  128. struct mgsl_icount icount;
  129. int timeout;
  130. int x_char; /* xon/xoff character */
  131. unsigned char read_status_mask;
  132. unsigned char ignore_status_mask;
  133. unsigned char *tx_buf;
  134. int tx_put;
  135. int tx_get;
  136. int tx_count;
  137. /* circular list of fixed length rx buffers */
  138. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  139. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  140. int rx_put; /* index of next empty rx buffer */
  141. int rx_get; /* index of next full rx buffer */
  142. int rx_buf_size; /* size in bytes of single rx buffer */
  143. int rx_buf_count; /* total number of rx buffers */
  144. int rx_frame_count; /* number of full rx buffers */
  145. wait_queue_head_t status_event_wait_q;
  146. wait_queue_head_t event_wait_q;
  147. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  148. struct _mgslpc_info *next_device; /* device list link */
  149. unsigned short imra_value;
  150. unsigned short imrb_value;
  151. unsigned char pim_value;
  152. spinlock_t lock;
  153. struct work_struct task; /* task structure for scheduling bh */
  154. u32 max_frame_size;
  155. u32 pending_bh;
  156. bool bh_running;
  157. bool bh_requested;
  158. int dcd_chkcount; /* check counts to prevent */
  159. int cts_chkcount; /* too many IRQs if a signal */
  160. int dsr_chkcount; /* is floating */
  161. int ri_chkcount;
  162. bool rx_enabled;
  163. bool rx_overflow;
  164. bool tx_enabled;
  165. bool tx_active;
  166. bool tx_aborting;
  167. u32 idle_mode;
  168. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  169. char device_name[25]; /* device instance name */
  170. unsigned int io_base; /* base I/O address of adapter */
  171. unsigned int irq_level;
  172. MGSL_PARAMS params; /* communications parameters */
  173. unsigned char serial_signals; /* current serial signal states */
  174. bool irq_occurred; /* for diagnostics use */
  175. char testing_irq;
  176. unsigned int init_error; /* startup error (DIAGS) */
  177. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  178. bool drop_rts_on_tx_done;
  179. struct _input_signal_events input_signal_events;
  180. /* PCMCIA support */
  181. struct pcmcia_device *p_dev;
  182. dev_node_t node;
  183. int stop;
  184. /* SPPP/Cisco HDLC device parts */
  185. int netcount;
  186. spinlock_t netlock;
  187. #if SYNCLINK_GENERIC_HDLC
  188. struct net_device *netdev;
  189. #endif
  190. } MGSLPC_INFO;
  191. #define MGSLPC_MAGIC 0x5402
  192. /*
  193. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  194. */
  195. #define TXBUFSIZE 4096
  196. #define CHA 0x00 /* channel A offset */
  197. #define CHB 0x40 /* channel B offset */
  198. /*
  199. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  200. */
  201. #undef PVR
  202. #define RXFIFO 0
  203. #define TXFIFO 0
  204. #define STAR 0x20
  205. #define CMDR 0x20
  206. #define RSTA 0x21
  207. #define PRE 0x21
  208. #define MODE 0x22
  209. #define TIMR 0x23
  210. #define XAD1 0x24
  211. #define XAD2 0x25
  212. #define RAH1 0x26
  213. #define RAH2 0x27
  214. #define DAFO 0x27
  215. #define RAL1 0x28
  216. #define RFC 0x28
  217. #define RHCR 0x29
  218. #define RAL2 0x29
  219. #define RBCL 0x2a
  220. #define XBCL 0x2a
  221. #define RBCH 0x2b
  222. #define XBCH 0x2b
  223. #define CCR0 0x2c
  224. #define CCR1 0x2d
  225. #define CCR2 0x2e
  226. #define CCR3 0x2f
  227. #define VSTR 0x34
  228. #define BGR 0x34
  229. #define RLCR 0x35
  230. #define AML 0x36
  231. #define AMH 0x37
  232. #define GIS 0x38
  233. #define IVA 0x38
  234. #define IPC 0x39
  235. #define ISR 0x3a
  236. #define IMR 0x3a
  237. #define PVR 0x3c
  238. #define PIS 0x3d
  239. #define PIM 0x3d
  240. #define PCR 0x3e
  241. #define CCR4 0x3f
  242. // IMR/ISR
  243. #define IRQ_BREAK_ON BIT15 // rx break detected
  244. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  245. #define IRQ_ALLSENT BIT13 // all sent
  246. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  247. #define IRQ_TIMER BIT11 // timer interrupt
  248. #define IRQ_CTS BIT10 // CTS status change
  249. #define IRQ_TXREPEAT BIT9 // tx message repeat
  250. #define IRQ_TXFIFO BIT8 // transmit pool ready
  251. #define IRQ_RXEOM BIT7 // receive message end
  252. #define IRQ_EXITHUNT BIT6 // receive frame start
  253. #define IRQ_RXTIME BIT6 // rx char timeout
  254. #define IRQ_DCD BIT2 // carrier detect status change
  255. #define IRQ_OVERRUN BIT1 // receive frame overflow
  256. #define IRQ_RXFIFO BIT0 // receive pool full
  257. // STAR
  258. #define XFW BIT6 // transmit FIFO write enable
  259. #define CEC BIT2 // command executing
  260. #define CTS BIT1 // CTS state
  261. #define PVR_DTR BIT0
  262. #define PVR_DSR BIT1
  263. #define PVR_RI BIT2
  264. #define PVR_AUTOCTS BIT3
  265. #define PVR_RS232 0x20 /* 0010b */
  266. #define PVR_V35 0xe0 /* 1110b */
  267. #define PVR_RS422 0x40 /* 0100b */
  268. /* Register access functions */
  269. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  270. #define read_reg(info, reg) inb((info)->io_base + (reg))
  271. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  272. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  273. #define set_reg_bits(info, reg, mask) \
  274. write_reg(info, (reg), \
  275. (unsigned char) (read_reg(info, (reg)) | (mask)))
  276. #define clear_reg_bits(info, reg, mask) \
  277. write_reg(info, (reg), \
  278. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  279. /*
  280. * interrupt enable/disable routines
  281. */
  282. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  283. {
  284. if (channel == CHA) {
  285. info->imra_value |= mask;
  286. write_reg16(info, CHA + IMR, info->imra_value);
  287. } else {
  288. info->imrb_value |= mask;
  289. write_reg16(info, CHB + IMR, info->imrb_value);
  290. }
  291. }
  292. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  293. {
  294. if (channel == CHA) {
  295. info->imra_value &= ~mask;
  296. write_reg16(info, CHA + IMR, info->imra_value);
  297. } else {
  298. info->imrb_value &= ~mask;
  299. write_reg16(info, CHB + IMR, info->imrb_value);
  300. }
  301. }
  302. #define port_irq_disable(info, mask) \
  303. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  304. #define port_irq_enable(info, mask) \
  305. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  306. static void rx_start(MGSLPC_INFO *info);
  307. static void rx_stop(MGSLPC_INFO *info);
  308. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
  309. static void tx_stop(MGSLPC_INFO *info);
  310. static void tx_set_idle(MGSLPC_INFO *info);
  311. static void get_signals(MGSLPC_INFO *info);
  312. static void set_signals(MGSLPC_INFO *info);
  313. static void reset_device(MGSLPC_INFO *info);
  314. static void hdlc_mode(MGSLPC_INFO *info);
  315. static void async_mode(MGSLPC_INFO *info);
  316. static void tx_timeout(unsigned long context);
  317. static int carrier_raised(struct tty_port *port);
  318. static void dtr_rts(struct tty_port *port, int onoff);
  319. #if SYNCLINK_GENERIC_HDLC
  320. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  321. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  322. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  323. static int hdlcdev_init(MGSLPC_INFO *info);
  324. static void hdlcdev_exit(MGSLPC_INFO *info);
  325. #endif
  326. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  327. static bool register_test(MGSLPC_INFO *info);
  328. static bool irq_test(MGSLPC_INFO *info);
  329. static int adapter_test(MGSLPC_INFO *info);
  330. static int claim_resources(MGSLPC_INFO *info);
  331. static void release_resources(MGSLPC_INFO *info);
  332. static void mgslpc_add_device(MGSLPC_INFO *info);
  333. static void mgslpc_remove_device(MGSLPC_INFO *info);
  334. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
  335. static void rx_reset_buffers(MGSLPC_INFO *info);
  336. static int rx_alloc_buffers(MGSLPC_INFO *info);
  337. static void rx_free_buffers(MGSLPC_INFO *info);
  338. static irqreturn_t mgslpc_isr(int irq, void *dev_id);
  339. /*
  340. * Bottom half interrupt handlers
  341. */
  342. static void bh_handler(struct work_struct *work);
  343. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
  344. static void bh_status(MGSLPC_INFO *info);
  345. /*
  346. * ioctl handlers
  347. */
  348. static int tiocmget(struct tty_struct *tty, struct file *file);
  349. static int tiocmset(struct tty_struct *tty, struct file *file,
  350. unsigned int set, unsigned int clear);
  351. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  352. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  353. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
  354. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  355. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  356. static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
  357. static int tx_abort(MGSLPC_INFO *info);
  358. static int set_rxenable(MGSLPC_INFO *info, int enable);
  359. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  360. static MGSLPC_INFO *mgslpc_device_list = NULL;
  361. static int mgslpc_device_count = 0;
  362. /*
  363. * Set this param to non-zero to load eax with the
  364. * .text section address and breakpoint on module load.
  365. * This is useful for use with gdb and add-symbol-file command.
  366. */
  367. static int break_on_load=0;
  368. /*
  369. * Driver major number, defaults to zero to get auto
  370. * assigned major number. May be forced as module parameter.
  371. */
  372. static int ttymajor=0;
  373. static int debug_level = 0;
  374. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  375. module_param(break_on_load, bool, 0);
  376. module_param(ttymajor, int, 0);
  377. module_param(debug_level, int, 0);
  378. module_param_array(maxframe, int, NULL, 0);
  379. MODULE_LICENSE("GPL");
  380. static char *driver_name = "SyncLink PC Card driver";
  381. static char *driver_version = "$Revision: 4.34 $";
  382. static struct tty_driver *serial_driver;
  383. /* number of characters left in xmit buffer before we ask for more */
  384. #define WAKEUP_CHARS 256
  385. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
  386. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  387. /* PCMCIA prototypes */
  388. static int mgslpc_config(struct pcmcia_device *link);
  389. static void mgslpc_release(u_long arg);
  390. static void mgslpc_detach(struct pcmcia_device *p_dev);
  391. /*
  392. * 1st function defined in .text section. Calling this function in
  393. * init_module() followed by a breakpoint allows a remote debugger
  394. * (gdb) to get the .text address for the add-symbol-file command.
  395. * This allows remote debugging of dynamically loadable modules.
  396. */
  397. static void* mgslpc_get_text_ptr(void)
  398. {
  399. return mgslpc_get_text_ptr;
  400. }
  401. /**
  402. * line discipline callback wrappers
  403. *
  404. * The wrappers maintain line discipline references
  405. * while calling into the line discipline.
  406. *
  407. * ldisc_receive_buf - pass receive data to line discipline
  408. */
  409. static void ldisc_receive_buf(struct tty_struct *tty,
  410. const __u8 *data, char *flags, int count)
  411. {
  412. struct tty_ldisc *ld;
  413. if (!tty)
  414. return;
  415. ld = tty_ldisc_ref(tty);
  416. if (ld) {
  417. if (ld->ops->receive_buf)
  418. ld->ops->receive_buf(tty, data, flags, count);
  419. tty_ldisc_deref(ld);
  420. }
  421. }
  422. static const struct tty_port_operations mgslpc_port_ops = {
  423. .carrier_raised = carrier_raised,
  424. .dtr_rts = dtr_rts
  425. };
  426. static int mgslpc_probe(struct pcmcia_device *link)
  427. {
  428. MGSLPC_INFO *info;
  429. int ret;
  430. if (debug_level >= DEBUG_LEVEL_INFO)
  431. printk("mgslpc_attach\n");
  432. info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  433. if (!info) {
  434. printk("Error can't allocate device instance data\n");
  435. return -ENOMEM;
  436. }
  437. info->magic = MGSLPC_MAGIC;
  438. tty_port_init(&info->port);
  439. info->port.ops = &mgslpc_port_ops;
  440. INIT_WORK(&info->task, bh_handler);
  441. info->max_frame_size = 4096;
  442. info->port.close_delay = 5*HZ/10;
  443. info->port.closing_wait = 30*HZ;
  444. init_waitqueue_head(&info->status_event_wait_q);
  445. init_waitqueue_head(&info->event_wait_q);
  446. spin_lock_init(&info->lock);
  447. spin_lock_init(&info->netlock);
  448. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  449. info->idle_mode = HDLC_TXIDLE_FLAGS;
  450. info->imra_value = 0xffff;
  451. info->imrb_value = 0xffff;
  452. info->pim_value = 0xff;
  453. info->p_dev = link;
  454. link->priv = info;
  455. /* Initialize the struct pcmcia_device structure */
  456. link->conf.Attributes = 0;
  457. link->conf.IntType = INT_MEMORY_AND_IO;
  458. ret = mgslpc_config(link);
  459. if (ret)
  460. return ret;
  461. mgslpc_add_device(info);
  462. return 0;
  463. }
  464. /* Card has been inserted.
  465. */
  466. static int mgslpc_ioprobe(struct pcmcia_device *p_dev,
  467. cistpl_cftable_entry_t *cfg,
  468. cistpl_cftable_entry_t *dflt,
  469. unsigned int vcc,
  470. void *priv_data)
  471. {
  472. if (cfg->io.nwin > 0) {
  473. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
  474. if (!(cfg->io.flags & CISTPL_IO_8BIT))
  475. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_16;
  476. if (!(cfg->io.flags & CISTPL_IO_16BIT))
  477. p_dev->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
  478. p_dev->io.IOAddrLines = cfg->io.flags & CISTPL_IO_LINES_MASK;
  479. p_dev->io.BasePort1 = cfg->io.win[0].base;
  480. p_dev->io.NumPorts1 = cfg->io.win[0].len;
  481. return pcmcia_request_io(p_dev, &p_dev->io);
  482. }
  483. return -ENODEV;
  484. }
  485. static int mgslpc_config(struct pcmcia_device *link)
  486. {
  487. MGSLPC_INFO *info = link->priv;
  488. int ret;
  489. if (debug_level >= DEBUG_LEVEL_INFO)
  490. printk("mgslpc_config(0x%p)\n", link);
  491. ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
  492. if (ret != 0)
  493. goto failed;
  494. link->conf.Attributes = CONF_ENABLE_IRQ;
  495. link->conf.IntType = INT_MEMORY_AND_IO;
  496. link->conf.ConfigIndex = 8;
  497. link->conf.Present = PRESENT_OPTION;
  498. ret = pcmcia_request_irq(link, mgslpc_isr);
  499. if (ret)
  500. goto failed;
  501. ret = pcmcia_request_configuration(link, &link->conf);
  502. if (ret)
  503. goto failed;
  504. info->io_base = link->io.BasePort1;
  505. info->irq_level = link->irq;
  506. /* add to linked list of devices */
  507. sprintf(info->node.dev_name, "mgslpc0");
  508. info->node.major = info->node.minor = 0;
  509. link->dev_node = &info->node;
  510. printk(KERN_INFO "%s: index 0x%02x:",
  511. info->node.dev_name, link->conf.ConfigIndex);
  512. if (link->conf.Attributes & CONF_ENABLE_IRQ)
  513. printk(", irq %d", link->irq);
  514. if (link->io.NumPorts1)
  515. printk(", io 0x%04x-0x%04x", link->io.BasePort1,
  516. link->io.BasePort1+link->io.NumPorts1-1);
  517. printk("\n");
  518. return 0;
  519. failed:
  520. mgslpc_release((u_long)link);
  521. return -ENODEV;
  522. }
  523. /* Card has been removed.
  524. * Unregister device and release PCMCIA configuration.
  525. * If device is open, postpone until it is closed.
  526. */
  527. static void mgslpc_release(u_long arg)
  528. {
  529. struct pcmcia_device *link = (struct pcmcia_device *)arg;
  530. if (debug_level >= DEBUG_LEVEL_INFO)
  531. printk("mgslpc_release(0x%p)\n", link);
  532. pcmcia_disable_device(link);
  533. }
  534. static void mgslpc_detach(struct pcmcia_device *link)
  535. {
  536. if (debug_level >= DEBUG_LEVEL_INFO)
  537. printk("mgslpc_detach(0x%p)\n", link);
  538. ((MGSLPC_INFO *)link->priv)->stop = 1;
  539. mgslpc_release((u_long)link);
  540. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  541. }
  542. static int mgslpc_suspend(struct pcmcia_device *link)
  543. {
  544. MGSLPC_INFO *info = link->priv;
  545. info->stop = 1;
  546. return 0;
  547. }
  548. static int mgslpc_resume(struct pcmcia_device *link)
  549. {
  550. MGSLPC_INFO *info = link->priv;
  551. info->stop = 0;
  552. return 0;
  553. }
  554. static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
  555. char *name, const char *routine)
  556. {
  557. #ifdef MGSLPC_PARANOIA_CHECK
  558. static const char *badmagic =
  559. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  560. static const char *badinfo =
  561. "Warning: null mgslpc_info for (%s) in %s\n";
  562. if (!info) {
  563. printk(badinfo, name, routine);
  564. return true;
  565. }
  566. if (info->magic != MGSLPC_MAGIC) {
  567. printk(badmagic, name, routine);
  568. return true;
  569. }
  570. #else
  571. if (!info)
  572. return true;
  573. #endif
  574. return false;
  575. }
  576. #define CMD_RXFIFO BIT7 // release current rx FIFO
  577. #define CMD_RXRESET BIT6 // receiver reset
  578. #define CMD_RXFIFO_READ BIT5
  579. #define CMD_START_TIMER BIT4
  580. #define CMD_TXFIFO BIT3 // release current tx FIFO
  581. #define CMD_TXEOM BIT1 // transmit end message
  582. #define CMD_TXRESET BIT0 // transmit reset
  583. static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  584. {
  585. int i = 0;
  586. /* wait for command completion */
  587. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  588. udelay(1);
  589. if (i++ == 1000)
  590. return false;
  591. }
  592. return true;
  593. }
  594. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  595. {
  596. wait_command_complete(info, channel);
  597. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  598. }
  599. static void tx_pause(struct tty_struct *tty)
  600. {
  601. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  602. unsigned long flags;
  603. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  604. return;
  605. if (debug_level >= DEBUG_LEVEL_INFO)
  606. printk("tx_pause(%s)\n",info->device_name);
  607. spin_lock_irqsave(&info->lock,flags);
  608. if (info->tx_enabled)
  609. tx_stop(info);
  610. spin_unlock_irqrestore(&info->lock,flags);
  611. }
  612. static void tx_release(struct tty_struct *tty)
  613. {
  614. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  615. unsigned long flags;
  616. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  617. return;
  618. if (debug_level >= DEBUG_LEVEL_INFO)
  619. printk("tx_release(%s)\n",info->device_name);
  620. spin_lock_irqsave(&info->lock,flags);
  621. if (!info->tx_enabled)
  622. tx_start(info, tty);
  623. spin_unlock_irqrestore(&info->lock,flags);
  624. }
  625. /* Return next bottom half action to perform.
  626. * or 0 if nothing to do.
  627. */
  628. static int bh_action(MGSLPC_INFO *info)
  629. {
  630. unsigned long flags;
  631. int rc = 0;
  632. spin_lock_irqsave(&info->lock,flags);
  633. if (info->pending_bh & BH_RECEIVE) {
  634. info->pending_bh &= ~BH_RECEIVE;
  635. rc = BH_RECEIVE;
  636. } else if (info->pending_bh & BH_TRANSMIT) {
  637. info->pending_bh &= ~BH_TRANSMIT;
  638. rc = BH_TRANSMIT;
  639. } else if (info->pending_bh & BH_STATUS) {
  640. info->pending_bh &= ~BH_STATUS;
  641. rc = BH_STATUS;
  642. }
  643. if (!rc) {
  644. /* Mark BH routine as complete */
  645. info->bh_running = false;
  646. info->bh_requested = false;
  647. }
  648. spin_unlock_irqrestore(&info->lock,flags);
  649. return rc;
  650. }
  651. static void bh_handler(struct work_struct *work)
  652. {
  653. MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
  654. struct tty_struct *tty;
  655. int action;
  656. if (!info)
  657. return;
  658. if (debug_level >= DEBUG_LEVEL_BH)
  659. printk( "%s(%d):bh_handler(%s) entry\n",
  660. __FILE__,__LINE__,info->device_name);
  661. info->bh_running = true;
  662. tty = tty_port_tty_get(&info->port);
  663. while((action = bh_action(info)) != 0) {
  664. /* Process work item */
  665. if ( debug_level >= DEBUG_LEVEL_BH )
  666. printk( "%s(%d):bh_handler() work item action=%d\n",
  667. __FILE__,__LINE__,action);
  668. switch (action) {
  669. case BH_RECEIVE:
  670. while(rx_get_frame(info, tty));
  671. break;
  672. case BH_TRANSMIT:
  673. bh_transmit(info, tty);
  674. break;
  675. case BH_STATUS:
  676. bh_status(info);
  677. break;
  678. default:
  679. /* unknown work item ID */
  680. printk("Unknown work item ID=%08X!\n", action);
  681. break;
  682. }
  683. }
  684. tty_kref_put(tty);
  685. if (debug_level >= DEBUG_LEVEL_BH)
  686. printk( "%s(%d):bh_handler(%s) exit\n",
  687. __FILE__,__LINE__,info->device_name);
  688. }
  689. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
  690. {
  691. if (debug_level >= DEBUG_LEVEL_BH)
  692. printk("bh_transmit() entry on %s\n", info->device_name);
  693. if (tty)
  694. tty_wakeup(tty);
  695. }
  696. static void bh_status(MGSLPC_INFO *info)
  697. {
  698. info->ri_chkcount = 0;
  699. info->dsr_chkcount = 0;
  700. info->dcd_chkcount = 0;
  701. info->cts_chkcount = 0;
  702. }
  703. /* eom: non-zero = end of frame */
  704. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  705. {
  706. unsigned char data[2];
  707. unsigned char fifo_count, read_count, i;
  708. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  709. if (debug_level >= DEBUG_LEVEL_ISR)
  710. printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
  711. if (!info->rx_enabled)
  712. return;
  713. if (info->rx_frame_count >= info->rx_buf_count) {
  714. /* no more free buffers */
  715. issue_command(info, CHA, CMD_RXRESET);
  716. info->pending_bh |= BH_RECEIVE;
  717. info->rx_overflow = true;
  718. info->icount.buf_overrun++;
  719. return;
  720. }
  721. if (eom) {
  722. /* end of frame, get FIFO count from RBCL register */
  723. if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
  724. fifo_count = 32;
  725. } else
  726. fifo_count = 32;
  727. do {
  728. if (fifo_count == 1) {
  729. read_count = 1;
  730. data[0] = read_reg(info, CHA + RXFIFO);
  731. } else {
  732. read_count = 2;
  733. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  734. }
  735. fifo_count -= read_count;
  736. if (!fifo_count && eom)
  737. buf->status = data[--read_count];
  738. for (i = 0; i < read_count; i++) {
  739. if (buf->count >= info->max_frame_size) {
  740. /* frame too large, reset receiver and reset current buffer */
  741. issue_command(info, CHA, CMD_RXRESET);
  742. buf->count = 0;
  743. return;
  744. }
  745. *(buf->data + buf->count) = data[i];
  746. buf->count++;
  747. }
  748. } while (fifo_count);
  749. if (eom) {
  750. info->pending_bh |= BH_RECEIVE;
  751. info->rx_frame_count++;
  752. info->rx_put++;
  753. if (info->rx_put >= info->rx_buf_count)
  754. info->rx_put = 0;
  755. }
  756. issue_command(info, CHA, CMD_RXFIFO);
  757. }
  758. static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty)
  759. {
  760. unsigned char data, status, flag;
  761. int fifo_count;
  762. int work = 0;
  763. struct mgsl_icount *icount = &info->icount;
  764. if (tcd) {
  765. /* early termination, get FIFO count from RBCL register */
  766. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  767. /* Zero fifo count could mean 0 or 32 bytes available.
  768. * If BIT5 of STAR is set then at least 1 byte is available.
  769. */
  770. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  771. fifo_count = 32;
  772. } else
  773. fifo_count = 32;
  774. tty_buffer_request_room(tty, fifo_count);
  775. /* Flush received async data to receive data buffer. */
  776. while (fifo_count) {
  777. data = read_reg(info, CHA + RXFIFO);
  778. status = read_reg(info, CHA + RXFIFO);
  779. fifo_count -= 2;
  780. icount->rx++;
  781. flag = TTY_NORMAL;
  782. // if no frameing/crc error then save data
  783. // BIT7:parity error
  784. // BIT6:framing error
  785. if (status & (BIT7 + BIT6)) {
  786. if (status & BIT7)
  787. icount->parity++;
  788. else
  789. icount->frame++;
  790. /* discard char if tty control flags say so */
  791. if (status & info->ignore_status_mask)
  792. continue;
  793. status &= info->read_status_mask;
  794. if (status & BIT7)
  795. flag = TTY_PARITY;
  796. else if (status & BIT6)
  797. flag = TTY_FRAME;
  798. }
  799. work += tty_insert_flip_char(tty, data, flag);
  800. }
  801. issue_command(info, CHA, CMD_RXFIFO);
  802. if (debug_level >= DEBUG_LEVEL_ISR) {
  803. printk("%s(%d):rx_ready_async",
  804. __FILE__,__LINE__);
  805. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  806. __FILE__,__LINE__,icount->rx,icount->brk,
  807. icount->parity,icount->frame,icount->overrun);
  808. }
  809. if (work)
  810. tty_flip_buffer_push(tty);
  811. }
  812. static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
  813. {
  814. if (!info->tx_active)
  815. return;
  816. info->tx_active = false;
  817. info->tx_aborting = false;
  818. if (info->params.mode == MGSL_MODE_ASYNC)
  819. return;
  820. info->tx_count = info->tx_put = info->tx_get = 0;
  821. del_timer(&info->tx_timer);
  822. if (info->drop_rts_on_tx_done) {
  823. get_signals(info);
  824. if (info->serial_signals & SerialSignal_RTS) {
  825. info->serial_signals &= ~SerialSignal_RTS;
  826. set_signals(info);
  827. }
  828. info->drop_rts_on_tx_done = false;
  829. }
  830. #if SYNCLINK_GENERIC_HDLC
  831. if (info->netcount)
  832. hdlcdev_tx_done(info);
  833. else
  834. #endif
  835. {
  836. if (tty->stopped || tty->hw_stopped) {
  837. tx_stop(info);
  838. return;
  839. }
  840. info->pending_bh |= BH_TRANSMIT;
  841. }
  842. }
  843. static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
  844. {
  845. unsigned char fifo_count = 32;
  846. int c;
  847. if (debug_level >= DEBUG_LEVEL_ISR)
  848. printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
  849. if (info->params.mode == MGSL_MODE_HDLC) {
  850. if (!info->tx_active)
  851. return;
  852. } else {
  853. if (tty->stopped || tty->hw_stopped) {
  854. tx_stop(info);
  855. return;
  856. }
  857. if (!info->tx_count)
  858. info->tx_active = false;
  859. }
  860. if (!info->tx_count)
  861. return;
  862. while (info->tx_count && fifo_count) {
  863. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  864. if (c == 1) {
  865. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  866. } else {
  867. write_reg16(info, CHA + TXFIFO,
  868. *((unsigned short*)(info->tx_buf + info->tx_get)));
  869. }
  870. info->tx_count -= c;
  871. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  872. fifo_count -= c;
  873. }
  874. if (info->params.mode == MGSL_MODE_ASYNC) {
  875. if (info->tx_count < WAKEUP_CHARS)
  876. info->pending_bh |= BH_TRANSMIT;
  877. issue_command(info, CHA, CMD_TXFIFO);
  878. } else {
  879. if (info->tx_count)
  880. issue_command(info, CHA, CMD_TXFIFO);
  881. else
  882. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  883. }
  884. }
  885. static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
  886. {
  887. get_signals(info);
  888. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  889. irq_disable(info, CHB, IRQ_CTS);
  890. info->icount.cts++;
  891. if (info->serial_signals & SerialSignal_CTS)
  892. info->input_signal_events.cts_up++;
  893. else
  894. info->input_signal_events.cts_down++;
  895. wake_up_interruptible(&info->status_event_wait_q);
  896. wake_up_interruptible(&info->event_wait_q);
  897. if (info->port.flags & ASYNC_CTS_FLOW) {
  898. if (tty->hw_stopped) {
  899. if (info->serial_signals & SerialSignal_CTS) {
  900. if (debug_level >= DEBUG_LEVEL_ISR)
  901. printk("CTS tx start...");
  902. if (tty)
  903. tty->hw_stopped = 0;
  904. tx_start(info, tty);
  905. info->pending_bh |= BH_TRANSMIT;
  906. return;
  907. }
  908. } else {
  909. if (!(info->serial_signals & SerialSignal_CTS)) {
  910. if (debug_level >= DEBUG_LEVEL_ISR)
  911. printk("CTS tx stop...");
  912. if (tty)
  913. tty->hw_stopped = 1;
  914. tx_stop(info);
  915. }
  916. }
  917. }
  918. info->pending_bh |= BH_STATUS;
  919. }
  920. static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
  921. {
  922. get_signals(info);
  923. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  924. irq_disable(info, CHB, IRQ_DCD);
  925. info->icount.dcd++;
  926. if (info->serial_signals & SerialSignal_DCD) {
  927. info->input_signal_events.dcd_up++;
  928. }
  929. else
  930. info->input_signal_events.dcd_down++;
  931. #if SYNCLINK_GENERIC_HDLC
  932. if (info->netcount) {
  933. if (info->serial_signals & SerialSignal_DCD)
  934. netif_carrier_on(info->netdev);
  935. else
  936. netif_carrier_off(info->netdev);
  937. }
  938. #endif
  939. wake_up_interruptible(&info->status_event_wait_q);
  940. wake_up_interruptible(&info->event_wait_q);
  941. if (info->port.flags & ASYNC_CHECK_CD) {
  942. if (debug_level >= DEBUG_LEVEL_ISR)
  943. printk("%s CD now %s...", info->device_name,
  944. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  945. if (info->serial_signals & SerialSignal_DCD)
  946. wake_up_interruptible(&info->port.open_wait);
  947. else {
  948. if (debug_level >= DEBUG_LEVEL_ISR)
  949. printk("doing serial hangup...");
  950. if (tty)
  951. tty_hangup(tty);
  952. }
  953. }
  954. info->pending_bh |= BH_STATUS;
  955. }
  956. static void dsr_change(MGSLPC_INFO *info)
  957. {
  958. get_signals(info);
  959. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  960. port_irq_disable(info, PVR_DSR);
  961. info->icount.dsr++;
  962. if (info->serial_signals & SerialSignal_DSR)
  963. info->input_signal_events.dsr_up++;
  964. else
  965. info->input_signal_events.dsr_down++;
  966. wake_up_interruptible(&info->status_event_wait_q);
  967. wake_up_interruptible(&info->event_wait_q);
  968. info->pending_bh |= BH_STATUS;
  969. }
  970. static void ri_change(MGSLPC_INFO *info)
  971. {
  972. get_signals(info);
  973. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  974. port_irq_disable(info, PVR_RI);
  975. info->icount.rng++;
  976. if (info->serial_signals & SerialSignal_RI)
  977. info->input_signal_events.ri_up++;
  978. else
  979. info->input_signal_events.ri_down++;
  980. wake_up_interruptible(&info->status_event_wait_q);
  981. wake_up_interruptible(&info->event_wait_q);
  982. info->pending_bh |= BH_STATUS;
  983. }
  984. /* Interrupt service routine entry point.
  985. *
  986. * Arguments:
  987. *
  988. * irq interrupt number that caused interrupt
  989. * dev_id device ID supplied during interrupt registration
  990. */
  991. static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
  992. {
  993. MGSLPC_INFO *info = dev_id;
  994. struct tty_struct *tty;
  995. unsigned short isr;
  996. unsigned char gis, pis;
  997. int count=0;
  998. if (debug_level >= DEBUG_LEVEL_ISR)
  999. printk("mgslpc_isr(%d) entry.\n", info->irq_level);
  1000. if (!(info->p_dev->_locked))
  1001. return IRQ_HANDLED;
  1002. tty = tty_port_tty_get(&info->port);
  1003. spin_lock(&info->lock);
  1004. while ((gis = read_reg(info, CHA + GIS))) {
  1005. if (debug_level >= DEBUG_LEVEL_ISR)
  1006. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  1007. if ((gis & 0x70) || count > 1000) {
  1008. printk("synclink_cs:hardware failed or ejected\n");
  1009. break;
  1010. }
  1011. count++;
  1012. if (gis & (BIT1 + BIT0)) {
  1013. isr = read_reg16(info, CHB + ISR);
  1014. if (isr & IRQ_DCD)
  1015. dcd_change(info, tty);
  1016. if (isr & IRQ_CTS)
  1017. cts_change(info, tty);
  1018. }
  1019. if (gis & (BIT3 + BIT2))
  1020. {
  1021. isr = read_reg16(info, CHA + ISR);
  1022. if (isr & IRQ_TIMER) {
  1023. info->irq_occurred = true;
  1024. irq_disable(info, CHA, IRQ_TIMER);
  1025. }
  1026. /* receive IRQs */
  1027. if (isr & IRQ_EXITHUNT) {
  1028. info->icount.exithunt++;
  1029. wake_up_interruptible(&info->event_wait_q);
  1030. }
  1031. if (isr & IRQ_BREAK_ON) {
  1032. info->icount.brk++;
  1033. if (info->port.flags & ASYNC_SAK)
  1034. do_SAK(tty);
  1035. }
  1036. if (isr & IRQ_RXTIME) {
  1037. issue_command(info, CHA, CMD_RXFIFO_READ);
  1038. }
  1039. if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
  1040. if (info->params.mode == MGSL_MODE_HDLC)
  1041. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1042. else
  1043. rx_ready_async(info, isr & IRQ_RXEOM, tty);
  1044. }
  1045. /* transmit IRQs */
  1046. if (isr & IRQ_UNDERRUN) {
  1047. if (info->tx_aborting)
  1048. info->icount.txabort++;
  1049. else
  1050. info->icount.txunder++;
  1051. tx_done(info, tty);
  1052. }
  1053. else if (isr & IRQ_ALLSENT) {
  1054. info->icount.txok++;
  1055. tx_done(info, tty);
  1056. }
  1057. else if (isr & IRQ_TXFIFO)
  1058. tx_ready(info, tty);
  1059. }
  1060. if (gis & BIT7) {
  1061. pis = read_reg(info, CHA + PIS);
  1062. if (pis & BIT1)
  1063. dsr_change(info);
  1064. if (pis & BIT2)
  1065. ri_change(info);
  1066. }
  1067. }
  1068. /* Request bottom half processing if there's something
  1069. * for it to do and the bh is not already running
  1070. */
  1071. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1072. if ( debug_level >= DEBUG_LEVEL_ISR )
  1073. printk("%s(%d):%s queueing bh task.\n",
  1074. __FILE__,__LINE__,info->device_name);
  1075. schedule_work(&info->task);
  1076. info->bh_requested = true;
  1077. }
  1078. spin_unlock(&info->lock);
  1079. tty_kref_put(tty);
  1080. if (debug_level >= DEBUG_LEVEL_ISR)
  1081. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1082. __FILE__, __LINE__, info->irq_level);
  1083. return IRQ_HANDLED;
  1084. }
  1085. /* Initialize and start device.
  1086. */
  1087. static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
  1088. {
  1089. int retval = 0;
  1090. if (debug_level >= DEBUG_LEVEL_INFO)
  1091. printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1092. if (info->port.flags & ASYNC_INITIALIZED)
  1093. return 0;
  1094. if (!info->tx_buf) {
  1095. /* allocate a page of memory for a transmit buffer */
  1096. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1097. if (!info->tx_buf) {
  1098. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1099. __FILE__,__LINE__,info->device_name);
  1100. return -ENOMEM;
  1101. }
  1102. }
  1103. info->pending_bh = 0;
  1104. memset(&info->icount, 0, sizeof(info->icount));
  1105. setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
  1106. /* Allocate and claim adapter resources */
  1107. retval = claim_resources(info);
  1108. /* perform existance check and diagnostics */
  1109. if ( !retval )
  1110. retval = adapter_test(info);
  1111. if ( retval ) {
  1112. if (capable(CAP_SYS_ADMIN) && tty)
  1113. set_bit(TTY_IO_ERROR, &tty->flags);
  1114. release_resources(info);
  1115. return retval;
  1116. }
  1117. /* program hardware for current parameters */
  1118. mgslpc_change_params(info, tty);
  1119. if (tty)
  1120. clear_bit(TTY_IO_ERROR, &tty->flags);
  1121. info->port.flags |= ASYNC_INITIALIZED;
  1122. return 0;
  1123. }
  1124. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1125. */
  1126. static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
  1127. {
  1128. unsigned long flags;
  1129. if (!(info->port.flags & ASYNC_INITIALIZED))
  1130. return;
  1131. if (debug_level >= DEBUG_LEVEL_INFO)
  1132. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1133. __FILE__,__LINE__, info->device_name );
  1134. /* clear status wait queue because status changes */
  1135. /* can't happen after shutting down the hardware */
  1136. wake_up_interruptible(&info->status_event_wait_q);
  1137. wake_up_interruptible(&info->event_wait_q);
  1138. del_timer_sync(&info->tx_timer);
  1139. if (info->tx_buf) {
  1140. free_page((unsigned long) info->tx_buf);
  1141. info->tx_buf = NULL;
  1142. }
  1143. spin_lock_irqsave(&info->lock,flags);
  1144. rx_stop(info);
  1145. tx_stop(info);
  1146. /* TODO:disable interrupts instead of reset to preserve signal states */
  1147. reset_device(info);
  1148. if (!tty || tty->termios->c_cflag & HUPCL) {
  1149. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1150. set_signals(info);
  1151. }
  1152. spin_unlock_irqrestore(&info->lock,flags);
  1153. release_resources(info);
  1154. if (tty)
  1155. set_bit(TTY_IO_ERROR, &tty->flags);
  1156. info->port.flags &= ~ASYNC_INITIALIZED;
  1157. }
  1158. static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
  1159. {
  1160. unsigned long flags;
  1161. spin_lock_irqsave(&info->lock,flags);
  1162. rx_stop(info);
  1163. tx_stop(info);
  1164. info->tx_count = info->tx_put = info->tx_get = 0;
  1165. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1166. hdlc_mode(info);
  1167. else
  1168. async_mode(info);
  1169. set_signals(info);
  1170. info->dcd_chkcount = 0;
  1171. info->cts_chkcount = 0;
  1172. info->ri_chkcount = 0;
  1173. info->dsr_chkcount = 0;
  1174. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1175. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1176. get_signals(info);
  1177. if (info->netcount || (tty && (tty->termios->c_cflag & CREAD)))
  1178. rx_start(info);
  1179. spin_unlock_irqrestore(&info->lock,flags);
  1180. }
  1181. /* Reconfigure adapter based on new parameters
  1182. */
  1183. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
  1184. {
  1185. unsigned cflag;
  1186. int bits_per_char;
  1187. if (!tty || !tty->termios)
  1188. return;
  1189. if (debug_level >= DEBUG_LEVEL_INFO)
  1190. printk("%s(%d):mgslpc_change_params(%s)\n",
  1191. __FILE__,__LINE__, info->device_name );
  1192. cflag = tty->termios->c_cflag;
  1193. /* if B0 rate (hangup) specified then negate DTR and RTS */
  1194. /* otherwise assert DTR and RTS */
  1195. if (cflag & CBAUD)
  1196. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1197. else
  1198. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1199. /* byte size and parity */
  1200. switch (cflag & CSIZE) {
  1201. case CS5: info->params.data_bits = 5; break;
  1202. case CS6: info->params.data_bits = 6; break;
  1203. case CS7: info->params.data_bits = 7; break;
  1204. case CS8: info->params.data_bits = 8; break;
  1205. default: info->params.data_bits = 7; break;
  1206. }
  1207. if (cflag & CSTOPB)
  1208. info->params.stop_bits = 2;
  1209. else
  1210. info->params.stop_bits = 1;
  1211. info->params.parity = ASYNC_PARITY_NONE;
  1212. if (cflag & PARENB) {
  1213. if (cflag & PARODD)
  1214. info->params.parity = ASYNC_PARITY_ODD;
  1215. else
  1216. info->params.parity = ASYNC_PARITY_EVEN;
  1217. #ifdef CMSPAR
  1218. if (cflag & CMSPAR)
  1219. info->params.parity = ASYNC_PARITY_SPACE;
  1220. #endif
  1221. }
  1222. /* calculate number of jiffies to transmit a full
  1223. * FIFO (32 bytes) at specified data rate
  1224. */
  1225. bits_per_char = info->params.data_bits +
  1226. info->params.stop_bits + 1;
  1227. /* if port data rate is set to 460800 or less then
  1228. * allow tty settings to override, otherwise keep the
  1229. * current data rate.
  1230. */
  1231. if (info->params.data_rate <= 460800) {
  1232. info->params.data_rate = tty_get_baud_rate(tty);
  1233. }
  1234. if ( info->params.data_rate ) {
  1235. info->timeout = (32*HZ*bits_per_char) /
  1236. info->params.data_rate;
  1237. }
  1238. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1239. if (cflag & CRTSCTS)
  1240. info->port.flags |= ASYNC_CTS_FLOW;
  1241. else
  1242. info->port.flags &= ~ASYNC_CTS_FLOW;
  1243. if (cflag & CLOCAL)
  1244. info->port.flags &= ~ASYNC_CHECK_CD;
  1245. else
  1246. info->port.flags |= ASYNC_CHECK_CD;
  1247. /* process tty input control flags */
  1248. info->read_status_mask = 0;
  1249. if (I_INPCK(tty))
  1250. info->read_status_mask |= BIT7 | BIT6;
  1251. if (I_IGNPAR(tty))
  1252. info->ignore_status_mask |= BIT7 | BIT6;
  1253. mgslpc_program_hw(info, tty);
  1254. }
  1255. /* Add a character to the transmit buffer
  1256. */
  1257. static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1258. {
  1259. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1260. unsigned long flags;
  1261. if (debug_level >= DEBUG_LEVEL_INFO) {
  1262. printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
  1263. __FILE__,__LINE__,ch,info->device_name);
  1264. }
  1265. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1266. return 0;
  1267. if (!info->tx_buf)
  1268. return 0;
  1269. spin_lock_irqsave(&info->lock,flags);
  1270. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1271. if (info->tx_count < TXBUFSIZE - 1) {
  1272. info->tx_buf[info->tx_put++] = ch;
  1273. info->tx_put &= TXBUFSIZE-1;
  1274. info->tx_count++;
  1275. }
  1276. }
  1277. spin_unlock_irqrestore(&info->lock,flags);
  1278. return 1;
  1279. }
  1280. /* Enable transmitter so remaining characters in the
  1281. * transmit buffer are sent.
  1282. */
  1283. static void mgslpc_flush_chars(struct tty_struct *tty)
  1284. {
  1285. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1286. unsigned long flags;
  1287. if (debug_level >= DEBUG_LEVEL_INFO)
  1288. printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1289. __FILE__,__LINE__,info->device_name,info->tx_count);
  1290. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1291. return;
  1292. if (info->tx_count <= 0 || tty->stopped ||
  1293. tty->hw_stopped || !info->tx_buf)
  1294. return;
  1295. if (debug_level >= DEBUG_LEVEL_INFO)
  1296. printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1297. __FILE__,__LINE__,info->device_name);
  1298. spin_lock_irqsave(&info->lock,flags);
  1299. if (!info->tx_active)
  1300. tx_start(info, tty);
  1301. spin_unlock_irqrestore(&info->lock,flags);
  1302. }
  1303. /* Send a block of data
  1304. *
  1305. * Arguments:
  1306. *
  1307. * tty pointer to tty information structure
  1308. * buf pointer to buffer containing send data
  1309. * count size of send data in bytes
  1310. *
  1311. * Returns: number of characters written
  1312. */
  1313. static int mgslpc_write(struct tty_struct * tty,
  1314. const unsigned char *buf, int count)
  1315. {
  1316. int c, ret = 0;
  1317. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1318. unsigned long flags;
  1319. if (debug_level >= DEBUG_LEVEL_INFO)
  1320. printk( "%s(%d):mgslpc_write(%s) count=%d\n",
  1321. __FILE__,__LINE__,info->device_name,count);
  1322. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1323. !info->tx_buf)
  1324. goto cleanup;
  1325. if (info->params.mode == MGSL_MODE_HDLC) {
  1326. if (count > TXBUFSIZE) {
  1327. ret = -EIO;
  1328. goto cleanup;
  1329. }
  1330. if (info->tx_active)
  1331. goto cleanup;
  1332. else if (info->tx_count)
  1333. goto start;
  1334. }
  1335. for (;;) {
  1336. c = min(count,
  1337. min(TXBUFSIZE - info->tx_count - 1,
  1338. TXBUFSIZE - info->tx_put));
  1339. if (c <= 0)
  1340. break;
  1341. memcpy(info->tx_buf + info->tx_put, buf, c);
  1342. spin_lock_irqsave(&info->lock,flags);
  1343. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1344. info->tx_count += c;
  1345. spin_unlock_irqrestore(&info->lock,flags);
  1346. buf += c;
  1347. count -= c;
  1348. ret += c;
  1349. }
  1350. start:
  1351. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1352. spin_lock_irqsave(&info->lock,flags);
  1353. if (!info->tx_active)
  1354. tx_start(info, tty);
  1355. spin_unlock_irqrestore(&info->lock,flags);
  1356. }
  1357. cleanup:
  1358. if (debug_level >= DEBUG_LEVEL_INFO)
  1359. printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
  1360. __FILE__,__LINE__,info->device_name,ret);
  1361. return ret;
  1362. }
  1363. /* Return the count of free bytes in transmit buffer
  1364. */
  1365. static int mgslpc_write_room(struct tty_struct *tty)
  1366. {
  1367. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1368. int ret;
  1369. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1370. return 0;
  1371. if (info->params.mode == MGSL_MODE_HDLC) {
  1372. /* HDLC (frame oriented) mode */
  1373. if (info->tx_active)
  1374. return 0;
  1375. else
  1376. return HDLC_MAX_FRAME_SIZE;
  1377. } else {
  1378. ret = TXBUFSIZE - info->tx_count - 1;
  1379. if (ret < 0)
  1380. ret = 0;
  1381. }
  1382. if (debug_level >= DEBUG_LEVEL_INFO)
  1383. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1384. __FILE__,__LINE__, info->device_name, ret);
  1385. return ret;
  1386. }
  1387. /* Return the count of bytes in transmit buffer
  1388. */
  1389. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1390. {
  1391. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1392. int rc;
  1393. if (debug_level >= DEBUG_LEVEL_INFO)
  1394. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1395. __FILE__,__LINE__, info->device_name );
  1396. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1397. return 0;
  1398. if (info->params.mode == MGSL_MODE_HDLC)
  1399. rc = info->tx_active ? info->max_frame_size : 0;
  1400. else
  1401. rc = info->tx_count;
  1402. if (debug_level >= DEBUG_LEVEL_INFO)
  1403. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1404. __FILE__,__LINE__, info->device_name, rc);
  1405. return rc;
  1406. }
  1407. /* Discard all data in the send buffer
  1408. */
  1409. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1410. {
  1411. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1412. unsigned long flags;
  1413. if (debug_level >= DEBUG_LEVEL_INFO)
  1414. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1415. __FILE__,__LINE__, info->device_name );
  1416. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1417. return;
  1418. spin_lock_irqsave(&info->lock,flags);
  1419. info->tx_count = info->tx_put = info->tx_get = 0;
  1420. del_timer(&info->tx_timer);
  1421. spin_unlock_irqrestore(&info->lock,flags);
  1422. wake_up_interruptible(&tty->write_wait);
  1423. tty_wakeup(tty);
  1424. }
  1425. /* Send a high-priority XON/XOFF character
  1426. */
  1427. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1428. {
  1429. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1430. unsigned long flags;
  1431. if (debug_level >= DEBUG_LEVEL_INFO)
  1432. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1433. __FILE__,__LINE__, info->device_name, ch );
  1434. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1435. return;
  1436. info->x_char = ch;
  1437. if (ch) {
  1438. spin_lock_irqsave(&info->lock,flags);
  1439. if (!info->tx_enabled)
  1440. tx_start(info, tty);
  1441. spin_unlock_irqrestore(&info->lock,flags);
  1442. }
  1443. }
  1444. /* Signal remote device to throttle send data (our receive data)
  1445. */
  1446. static void mgslpc_throttle(struct tty_struct * tty)
  1447. {
  1448. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1449. unsigned long flags;
  1450. if (debug_level >= DEBUG_LEVEL_INFO)
  1451. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1452. __FILE__,__LINE__, info->device_name );
  1453. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1454. return;
  1455. if (I_IXOFF(tty))
  1456. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1457. if (tty->termios->c_cflag & CRTSCTS) {
  1458. spin_lock_irqsave(&info->lock,flags);
  1459. info->serial_signals &= ~SerialSignal_RTS;
  1460. set_signals(info);
  1461. spin_unlock_irqrestore(&info->lock,flags);
  1462. }
  1463. }
  1464. /* Signal remote device to stop throttling send data (our receive data)
  1465. */
  1466. static void mgslpc_unthrottle(struct tty_struct * tty)
  1467. {
  1468. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1469. unsigned long flags;
  1470. if (debug_level >= DEBUG_LEVEL_INFO)
  1471. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1472. __FILE__,__LINE__, info->device_name );
  1473. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1474. return;
  1475. if (I_IXOFF(tty)) {
  1476. if (info->x_char)
  1477. info->x_char = 0;
  1478. else
  1479. mgslpc_send_xchar(tty, START_CHAR(tty));
  1480. }
  1481. if (tty->termios->c_cflag & CRTSCTS) {
  1482. spin_lock_irqsave(&info->lock,flags);
  1483. info->serial_signals |= SerialSignal_RTS;
  1484. set_signals(info);
  1485. spin_unlock_irqrestore(&info->lock,flags);
  1486. }
  1487. }
  1488. /* get the current serial statistics
  1489. */
  1490. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1491. {
  1492. int err;
  1493. if (debug_level >= DEBUG_LEVEL_INFO)
  1494. printk("get_params(%s)\n", info->device_name);
  1495. if (!user_icount) {
  1496. memset(&info->icount, 0, sizeof(info->icount));
  1497. } else {
  1498. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1499. if (err)
  1500. return -EFAULT;
  1501. }
  1502. return 0;
  1503. }
  1504. /* get the current serial parameters
  1505. */
  1506. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1507. {
  1508. int err;
  1509. if (debug_level >= DEBUG_LEVEL_INFO)
  1510. printk("get_params(%s)\n", info->device_name);
  1511. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1512. if (err)
  1513. return -EFAULT;
  1514. return 0;
  1515. }
  1516. /* set the serial parameters
  1517. *
  1518. * Arguments:
  1519. *
  1520. * info pointer to device instance data
  1521. * new_params user buffer containing new serial params
  1522. *
  1523. * Returns: 0 if success, otherwise error code
  1524. */
  1525. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
  1526. {
  1527. unsigned long flags;
  1528. MGSL_PARAMS tmp_params;
  1529. int err;
  1530. if (debug_level >= DEBUG_LEVEL_INFO)
  1531. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1532. info->device_name );
  1533. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1534. if (err) {
  1535. if ( debug_level >= DEBUG_LEVEL_INFO )
  1536. printk( "%s(%d):set_params(%s) user buffer copy failed\n",
  1537. __FILE__,__LINE__,info->device_name);
  1538. return -EFAULT;
  1539. }
  1540. spin_lock_irqsave(&info->lock,flags);
  1541. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1542. spin_unlock_irqrestore(&info->lock,flags);
  1543. mgslpc_change_params(info, tty);
  1544. return 0;
  1545. }
  1546. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1547. {
  1548. int err;
  1549. if (debug_level >= DEBUG_LEVEL_INFO)
  1550. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1551. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1552. if (err)
  1553. return -EFAULT;
  1554. return 0;
  1555. }
  1556. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1557. {
  1558. unsigned long flags;
  1559. if (debug_level >= DEBUG_LEVEL_INFO)
  1560. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1561. spin_lock_irqsave(&info->lock,flags);
  1562. info->idle_mode = idle_mode;
  1563. tx_set_idle(info);
  1564. spin_unlock_irqrestore(&info->lock,flags);
  1565. return 0;
  1566. }
  1567. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1568. {
  1569. int err;
  1570. if (debug_level >= DEBUG_LEVEL_INFO)
  1571. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1572. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1573. if (err)
  1574. return -EFAULT;
  1575. return 0;
  1576. }
  1577. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1578. {
  1579. unsigned long flags;
  1580. unsigned char val;
  1581. if (debug_level >= DEBUG_LEVEL_INFO)
  1582. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1583. spin_lock_irqsave(&info->lock,flags);
  1584. info->if_mode = if_mode;
  1585. val = read_reg(info, PVR) & 0x0f;
  1586. switch (info->if_mode)
  1587. {
  1588. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1589. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1590. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1591. }
  1592. write_reg(info, PVR, val);
  1593. spin_unlock_irqrestore(&info->lock,flags);
  1594. return 0;
  1595. }
  1596. static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
  1597. {
  1598. unsigned long flags;
  1599. if (debug_level >= DEBUG_LEVEL_INFO)
  1600. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1601. spin_lock_irqsave(&info->lock,flags);
  1602. if (enable) {
  1603. if (!info->tx_enabled)
  1604. tx_start(info, tty);
  1605. } else {
  1606. if (info->tx_enabled)
  1607. tx_stop(info);
  1608. }
  1609. spin_unlock_irqrestore(&info->lock,flags);
  1610. return 0;
  1611. }
  1612. static int tx_abort(MGSLPC_INFO * info)
  1613. {
  1614. unsigned long flags;
  1615. if (debug_level >= DEBUG_LEVEL_INFO)
  1616. printk("tx_abort(%s)\n", info->device_name);
  1617. spin_lock_irqsave(&info->lock,flags);
  1618. if (info->tx_active && info->tx_count &&
  1619. info->params.mode == MGSL_MODE_HDLC) {
  1620. /* clear data count so FIFO is not filled on next IRQ.
  1621. * This results in underrun and abort transmission.
  1622. */
  1623. info->tx_count = info->tx_put = info->tx_get = 0;
  1624. info->tx_aborting = true;
  1625. }
  1626. spin_unlock_irqrestore(&info->lock,flags);
  1627. return 0;
  1628. }
  1629. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1630. {
  1631. unsigned long flags;
  1632. if (debug_level >= DEBUG_LEVEL_INFO)
  1633. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1634. spin_lock_irqsave(&info->lock,flags);
  1635. if (enable) {
  1636. if (!info->rx_enabled)
  1637. rx_start(info);
  1638. } else {
  1639. if (info->rx_enabled)
  1640. rx_stop(info);
  1641. }
  1642. spin_unlock_irqrestore(&info->lock,flags);
  1643. return 0;
  1644. }
  1645. /* wait for specified event to occur
  1646. *
  1647. * Arguments: info pointer to device instance data
  1648. * mask pointer to bitmask of events to wait for
  1649. * Return Value: 0 if successful and bit mask updated with
  1650. * of events triggerred,
  1651. * otherwise error code
  1652. */
  1653. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1654. {
  1655. unsigned long flags;
  1656. int s;
  1657. int rc=0;
  1658. struct mgsl_icount cprev, cnow;
  1659. int events;
  1660. int mask;
  1661. struct _input_signal_events oldsigs, newsigs;
  1662. DECLARE_WAITQUEUE(wait, current);
  1663. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1664. if (rc)
  1665. return -EFAULT;
  1666. if (debug_level >= DEBUG_LEVEL_INFO)
  1667. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1668. spin_lock_irqsave(&info->lock,flags);
  1669. /* return immediately if state matches requested events */
  1670. get_signals(info);
  1671. s = info->serial_signals;
  1672. events = mask &
  1673. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1674. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1675. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1676. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1677. if (events) {
  1678. spin_unlock_irqrestore(&info->lock,flags);
  1679. goto exit;
  1680. }
  1681. /* save current irq counts */
  1682. cprev = info->icount;
  1683. oldsigs = info->input_signal_events;
  1684. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1685. (mask & MgslEvent_ExitHuntMode))
  1686. irq_enable(info, CHA, IRQ_EXITHUNT);
  1687. set_current_state(TASK_INTERRUPTIBLE);
  1688. add_wait_queue(&info->event_wait_q, &wait);
  1689. spin_unlock_irqrestore(&info->lock,flags);
  1690. for(;;) {
  1691. schedule();
  1692. if (signal_pending(current)) {
  1693. rc = -ERESTARTSYS;
  1694. break;
  1695. }
  1696. /* get current irq counts */
  1697. spin_lock_irqsave(&info->lock,flags);
  1698. cnow = info->icount;
  1699. newsigs = info->input_signal_events;
  1700. set_current_state(TASK_INTERRUPTIBLE);
  1701. spin_unlock_irqrestore(&info->lock,flags);
  1702. /* if no change, wait aborted for some reason */
  1703. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1704. newsigs.dsr_down == oldsigs.dsr_down &&
  1705. newsigs.dcd_up == oldsigs.dcd_up &&
  1706. newsigs.dcd_down == oldsigs.dcd_down &&
  1707. newsigs.cts_up == oldsigs.cts_up &&
  1708. newsigs.cts_down == oldsigs.cts_down &&
  1709. newsigs.ri_up == oldsigs.ri_up &&
  1710. newsigs.ri_down == oldsigs.ri_down &&
  1711. cnow.exithunt == cprev.exithunt &&
  1712. cnow.rxidle == cprev.rxidle) {
  1713. rc = -EIO;
  1714. break;
  1715. }
  1716. events = mask &
  1717. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1718. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1719. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1720. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1721. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1722. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1723. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1724. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1725. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1726. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1727. if (events)
  1728. break;
  1729. cprev = cnow;
  1730. oldsigs = newsigs;
  1731. }
  1732. remove_wait_queue(&info->event_wait_q, &wait);
  1733. set_current_state(TASK_RUNNING);
  1734. if (mask & MgslEvent_ExitHuntMode) {
  1735. spin_lock_irqsave(&info->lock,flags);
  1736. if (!waitqueue_active(&info->event_wait_q))
  1737. irq_disable(info, CHA, IRQ_EXITHUNT);
  1738. spin_unlock_irqrestore(&info->lock,flags);
  1739. }
  1740. exit:
  1741. if (rc == 0)
  1742. PUT_USER(rc, events, mask_ptr);
  1743. return rc;
  1744. }
  1745. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1746. {
  1747. unsigned long flags;
  1748. int rc;
  1749. struct mgsl_icount cprev, cnow;
  1750. DECLARE_WAITQUEUE(wait, current);
  1751. /* save current irq counts */
  1752. spin_lock_irqsave(&info->lock,flags);
  1753. cprev = info->icount;
  1754. add_wait_queue(&info->status_event_wait_q, &wait);
  1755. set_current_state(TASK_INTERRUPTIBLE);
  1756. spin_unlock_irqrestore(&info->lock,flags);
  1757. for(;;) {
  1758. schedule();
  1759. if (signal_pending(current)) {
  1760. rc = -ERESTARTSYS;
  1761. break;
  1762. }
  1763. /* get new irq counts */
  1764. spin_lock_irqsave(&info->lock,flags);
  1765. cnow = info->icount;
  1766. set_current_state(TASK_INTERRUPTIBLE);
  1767. spin_unlock_irqrestore(&info->lock,flags);
  1768. /* if no change, wait aborted for some reason */
  1769. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1770. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1771. rc = -EIO;
  1772. break;
  1773. }
  1774. /* check for change in caller specified modem input */
  1775. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1776. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1777. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1778. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1779. rc = 0;
  1780. break;
  1781. }
  1782. cprev = cnow;
  1783. }
  1784. remove_wait_queue(&info->status_event_wait_q, &wait);
  1785. set_current_state(TASK_RUNNING);
  1786. return rc;
  1787. }
  1788. /* return the state of the serial control and status signals
  1789. */
  1790. static int tiocmget(struct tty_struct *tty, struct file *file)
  1791. {
  1792. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1793. unsigned int result;
  1794. unsigned long flags;
  1795. spin_lock_irqsave(&info->lock,flags);
  1796. get_signals(info);
  1797. spin_unlock_irqrestore(&info->lock,flags);
  1798. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1799. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1800. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1801. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1802. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1803. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1804. if (debug_level >= DEBUG_LEVEL_INFO)
  1805. printk("%s(%d):%s tiocmget() value=%08X\n",
  1806. __FILE__,__LINE__, info->device_name, result );
  1807. return result;
  1808. }
  1809. /* set modem control signals (DTR/RTS)
  1810. */
  1811. static int tiocmset(struct tty_struct *tty, struct file *file,
  1812. unsigned int set, unsigned int clear)
  1813. {
  1814. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1815. unsigned long flags;
  1816. if (debug_level >= DEBUG_LEVEL_INFO)
  1817. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1818. __FILE__,__LINE__,info->device_name, set, clear);
  1819. if (set & TIOCM_RTS)
  1820. info->serial_signals |= SerialSignal_RTS;
  1821. if (set & TIOCM_DTR)
  1822. info->serial_signals |= SerialSignal_DTR;
  1823. if (clear & TIOCM_RTS)
  1824. info->serial_signals &= ~SerialSignal_RTS;
  1825. if (clear & TIOCM_DTR)
  1826. info->serial_signals &= ~SerialSignal_DTR;
  1827. spin_lock_irqsave(&info->lock,flags);
  1828. set_signals(info);
  1829. spin_unlock_irqrestore(&info->lock,flags);
  1830. return 0;
  1831. }
  1832. /* Set or clear transmit break condition
  1833. *
  1834. * Arguments: tty pointer to tty instance data
  1835. * break_state -1=set break condition, 0=clear
  1836. */
  1837. static int mgslpc_break(struct tty_struct *tty, int break_state)
  1838. {
  1839. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1840. unsigned long flags;
  1841. if (debug_level >= DEBUG_LEVEL_INFO)
  1842. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1843. __FILE__,__LINE__, info->device_name, break_state);
  1844. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1845. return -EINVAL;
  1846. spin_lock_irqsave(&info->lock,flags);
  1847. if (break_state == -1)
  1848. set_reg_bits(info, CHA+DAFO, BIT6);
  1849. else
  1850. clear_reg_bits(info, CHA+DAFO, BIT6);
  1851. spin_unlock_irqrestore(&info->lock,flags);
  1852. return 0;
  1853. }
  1854. /* Service an IOCTL request
  1855. *
  1856. * Arguments:
  1857. *
  1858. * tty pointer to tty instance data
  1859. * file pointer to associated file object for device
  1860. * cmd IOCTL command code
  1861. * arg command argument/context
  1862. *
  1863. * Return Value: 0 if success, otherwise error code
  1864. */
  1865. static int mgslpc_ioctl(struct tty_struct *tty, struct file * file,
  1866. unsigned int cmd, unsigned long arg)
  1867. {
  1868. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1869. int error;
  1870. struct mgsl_icount cnow; /* kernel counter temps */
  1871. struct serial_icounter_struct __user *p_cuser; /* user space */
  1872. void __user *argp = (void __user *)arg;
  1873. unsigned long flags;
  1874. if (debug_level >= DEBUG_LEVEL_INFO)
  1875. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  1876. info->device_name, cmd );
  1877. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1878. return -ENODEV;
  1879. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1880. (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
  1881. if (tty->flags & (1 << TTY_IO_ERROR))
  1882. return -EIO;
  1883. }
  1884. switch (cmd) {
  1885. case MGSL_IOCGPARAMS:
  1886. return get_params(info, argp);
  1887. case MGSL_IOCSPARAMS:
  1888. return set_params(info, argp, tty);
  1889. case MGSL_IOCGTXIDLE:
  1890. return get_txidle(info, argp);
  1891. case MGSL_IOCSTXIDLE:
  1892. return set_txidle(info, (int)arg);
  1893. case MGSL_IOCGIF:
  1894. return get_interface(info, argp);
  1895. case MGSL_IOCSIF:
  1896. return set_interface(info,(int)arg);
  1897. case MGSL_IOCTXENABLE:
  1898. return set_txenable(info,(int)arg, tty);
  1899. case MGSL_IOCRXENABLE:
  1900. return set_rxenable(info,(int)arg);
  1901. case MGSL_IOCTXABORT:
  1902. return tx_abort(info);
  1903. case MGSL_IOCGSTATS:
  1904. return get_stats(info, argp);
  1905. case MGSL_IOCWAITEVENT:
  1906. return wait_events(info, argp);
  1907. case TIOCMIWAIT:
  1908. return modem_input_wait(info,(int)arg);
  1909. case TIOCGICOUNT:
  1910. spin_lock_irqsave(&info->lock,flags);
  1911. cnow = info->icount;
  1912. spin_unlock_irqrestore(&info->lock,flags);
  1913. p_cuser = argp;
  1914. PUT_USER(error,cnow.cts, &p_cuser->cts);
  1915. if (error) return error;
  1916. PUT_USER(error,cnow.dsr, &p_cuser->dsr);
  1917. if (error) return error;
  1918. PUT_USER(error,cnow.rng, &p_cuser->rng);
  1919. if (error) return error;
  1920. PUT_USER(error,cnow.dcd, &p_cuser->dcd);
  1921. if (error) return error;
  1922. PUT_USER(error,cnow.rx, &p_cuser->rx);
  1923. if (error) return error;
  1924. PUT_USER(error,cnow.tx, &p_cuser->tx);
  1925. if (error) return error;
  1926. PUT_USER(error,cnow.frame, &p_cuser->frame);
  1927. if (error) return error;
  1928. PUT_USER(error,cnow.overrun, &p_cuser->overrun);
  1929. if (error) return error;
  1930. PUT_USER(error,cnow.parity, &p_cuser->parity);
  1931. if (error) return error;
  1932. PUT_USER(error,cnow.brk, &p_cuser->brk);
  1933. if (error) return error;
  1934. PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
  1935. if (error) return error;
  1936. return 0;
  1937. default:
  1938. return -ENOIOCTLCMD;
  1939. }
  1940. return 0;
  1941. }
  1942. /* Set new termios settings
  1943. *
  1944. * Arguments:
  1945. *
  1946. * tty pointer to tty structure
  1947. * termios pointer to buffer to hold returned old termios
  1948. */
  1949. static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  1950. {
  1951. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1952. unsigned long flags;
  1953. if (debug_level >= DEBUG_LEVEL_INFO)
  1954. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
  1955. tty->driver->name );
  1956. /* just return if nothing has changed */
  1957. if ((tty->termios->c_cflag == old_termios->c_cflag)
  1958. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  1959. == RELEVANT_IFLAG(old_termios->c_iflag)))
  1960. return;
  1961. mgslpc_change_params(info, tty);
  1962. /* Handle transition to B0 status */
  1963. if (old_termios->c_cflag & CBAUD &&
  1964. !(tty->termios->c_cflag & CBAUD)) {
  1965. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1966. spin_lock_irqsave(&info->lock,flags);
  1967. set_signals(info);
  1968. spin_unlock_irqrestore(&info->lock,flags);
  1969. }
  1970. /* Handle transition away from B0 status */
  1971. if (!(old_termios->c_cflag & CBAUD) &&
  1972. tty->termios->c_cflag & CBAUD) {
  1973. info->serial_signals |= SerialSignal_DTR;
  1974. if (!(tty->termios->c_cflag & CRTSCTS) ||
  1975. !test_bit(TTY_THROTTLED, &tty->flags)) {
  1976. info->serial_signals |= SerialSignal_RTS;
  1977. }
  1978. spin_lock_irqsave(&info->lock,flags);
  1979. set_signals(info);
  1980. spin_unlock_irqrestore(&info->lock,flags);
  1981. }
  1982. /* Handle turning off CRTSCTS */
  1983. if (old_termios->c_cflag & CRTSCTS &&
  1984. !(tty->termios->c_cflag & CRTSCTS)) {
  1985. tty->hw_stopped = 0;
  1986. tx_release(tty);
  1987. }
  1988. }
  1989. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  1990. {
  1991. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1992. struct tty_port *port = &info->port;
  1993. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  1994. return;
  1995. if (debug_level >= DEBUG_LEVEL_INFO)
  1996. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  1997. __FILE__,__LINE__, info->device_name, port->count);
  1998. WARN_ON(!port->count);
  1999. if (tty_port_close_start(port, tty, filp) == 0)
  2000. goto cleanup;
  2001. if (port->flags & ASYNC_INITIALIZED)
  2002. mgslpc_wait_until_sent(tty, info->timeout);
  2003. mgslpc_flush_buffer(tty);
  2004. tty_ldisc_flush(tty);
  2005. shutdown(info, tty);
  2006. tty_port_close_end(port, tty);
  2007. tty_port_tty_set(port, NULL);
  2008. cleanup:
  2009. if (debug_level >= DEBUG_LEVEL_INFO)
  2010. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  2011. tty->driver->name, port->count);
  2012. }
  2013. /* Wait until the transmitter is empty.
  2014. */
  2015. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  2016. {
  2017. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2018. unsigned long orig_jiffies, char_time;
  2019. if (!info )
  2020. return;
  2021. if (debug_level >= DEBUG_LEVEL_INFO)
  2022. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  2023. __FILE__,__LINE__, info->device_name );
  2024. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  2025. return;
  2026. if (!(info->port.flags & ASYNC_INITIALIZED))
  2027. goto exit;
  2028. orig_jiffies = jiffies;
  2029. /* Set check interval to 1/5 of estimated time to
  2030. * send a character, and make it at least 1. The check
  2031. * interval should also be less than the timeout.
  2032. * Note: use tight timings here to satisfy the NIST-PCTS.
  2033. */
  2034. if ( info->params.data_rate ) {
  2035. char_time = info->timeout/(32 * 5);
  2036. if (!char_time)
  2037. char_time++;
  2038. } else
  2039. char_time = 1;
  2040. if (timeout)
  2041. char_time = min_t(unsigned long, char_time, timeout);
  2042. if (info->params.mode == MGSL_MODE_HDLC) {
  2043. while (info->tx_active) {
  2044. msleep_interruptible(jiffies_to_msecs(char_time));
  2045. if (signal_pending(current))
  2046. break;
  2047. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2048. break;
  2049. }
  2050. } else {
  2051. while ((info->tx_count || info->tx_active) &&
  2052. info->tx_enabled) {
  2053. msleep_interruptible(jiffies_to_msecs(char_time));
  2054. if (signal_pending(current))
  2055. break;
  2056. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2057. break;
  2058. }
  2059. }
  2060. exit:
  2061. if (debug_level >= DEBUG_LEVEL_INFO)
  2062. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2063. __FILE__,__LINE__, info->device_name );
  2064. }
  2065. /* Called by tty_hangup() when a hangup is signaled.
  2066. * This is the same as closing all open files for the port.
  2067. */
  2068. static void mgslpc_hangup(struct tty_struct *tty)
  2069. {
  2070. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2071. if (debug_level >= DEBUG_LEVEL_INFO)
  2072. printk("%s(%d):mgslpc_hangup(%s)\n",
  2073. __FILE__,__LINE__, info->device_name );
  2074. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2075. return;
  2076. mgslpc_flush_buffer(tty);
  2077. shutdown(info, tty);
  2078. tty_port_hangup(&info->port);
  2079. }
  2080. static int carrier_raised(struct tty_port *port)
  2081. {
  2082. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2083. unsigned long flags;
  2084. spin_lock_irqsave(&info->lock,flags);
  2085. get_signals(info);
  2086. spin_unlock_irqrestore(&info->lock,flags);
  2087. if (info->serial_signals & SerialSignal_DCD)
  2088. return 1;
  2089. return 0;
  2090. }
  2091. static void dtr_rts(struct tty_port *port, int onoff)
  2092. {
  2093. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2094. unsigned long flags;
  2095. spin_lock_irqsave(&info->lock,flags);
  2096. if (onoff)
  2097. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2098. else
  2099. info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
  2100. set_signals(info);
  2101. spin_unlock_irqrestore(&info->lock,flags);
  2102. }
  2103. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2104. {
  2105. MGSLPC_INFO *info;
  2106. struct tty_port *port;
  2107. int retval, line;
  2108. unsigned long flags;
  2109. /* verify range of specified line number */
  2110. line = tty->index;
  2111. if ((line < 0) || (line >= mgslpc_device_count)) {
  2112. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2113. __FILE__,__LINE__,line);
  2114. return -ENODEV;
  2115. }
  2116. /* find the info structure for the specified line */
  2117. info = mgslpc_device_list;
  2118. while(info && info->line != line)
  2119. info = info->next_device;
  2120. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2121. return -ENODEV;
  2122. port = &info->port;
  2123. tty->driver_data = info;
  2124. tty_port_tty_set(port, tty);
  2125. if (debug_level >= DEBUG_LEVEL_INFO)
  2126. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2127. __FILE__,__LINE__,tty->driver->name, port->count);
  2128. /* If port is closing, signal caller to try again */
  2129. if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
  2130. if (port->flags & ASYNC_CLOSING)
  2131. interruptible_sleep_on(&port->close_wait);
  2132. retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
  2133. -EAGAIN : -ERESTARTSYS);
  2134. goto cleanup;
  2135. }
  2136. tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2137. spin_lock_irqsave(&info->netlock, flags);
  2138. if (info->netcount) {
  2139. retval = -EBUSY;
  2140. spin_unlock_irqrestore(&info->netlock, flags);
  2141. goto cleanup;
  2142. }
  2143. spin_lock(&port->lock);
  2144. port->count++;
  2145. spin_unlock(&port->lock);
  2146. spin_unlock_irqrestore(&info->netlock, flags);
  2147. if (port->count == 1) {
  2148. /* 1st open on this device, init hardware */
  2149. retval = startup(info, tty);
  2150. if (retval < 0)
  2151. goto cleanup;
  2152. }
  2153. retval = tty_port_block_til_ready(&info->port, tty, filp);
  2154. if (retval) {
  2155. if (debug_level >= DEBUG_LEVEL_INFO)
  2156. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2157. __FILE__,__LINE__, info->device_name, retval);
  2158. goto cleanup;
  2159. }
  2160. if (debug_level >= DEBUG_LEVEL_INFO)
  2161. printk("%s(%d):mgslpc_open(%s) success\n",
  2162. __FILE__,__LINE__, info->device_name);
  2163. retval = 0;
  2164. cleanup:
  2165. return retval;
  2166. }
  2167. /*
  2168. * /proc fs routines....
  2169. */
  2170. static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
  2171. {
  2172. char stat_buf[30];
  2173. unsigned long flags;
  2174. seq_printf(m, "%s:io:%04X irq:%d",
  2175. info->device_name, info->io_base, info->irq_level);
  2176. /* output current serial signal states */
  2177. spin_lock_irqsave(&info->lock,flags);
  2178. get_signals(info);
  2179. spin_unlock_irqrestore(&info->lock,flags);
  2180. stat_buf[0] = 0;
  2181. stat_buf[1] = 0;
  2182. if (info->serial_signals & SerialSignal_RTS)
  2183. strcat(stat_buf, "|RTS");
  2184. if (info->serial_signals & SerialSignal_CTS)
  2185. strcat(stat_buf, "|CTS");
  2186. if (info->serial_signals & SerialSignal_DTR)
  2187. strcat(stat_buf, "|DTR");
  2188. if (info->serial_signals & SerialSignal_DSR)
  2189. strcat(stat_buf, "|DSR");
  2190. if (info->serial_signals & SerialSignal_DCD)
  2191. strcat(stat_buf, "|CD");
  2192. if (info->serial_signals & SerialSignal_RI)
  2193. strcat(stat_buf, "|RI");
  2194. if (info->params.mode == MGSL_MODE_HDLC) {
  2195. seq_printf(m, " HDLC txok:%d rxok:%d",
  2196. info->icount.txok, info->icount.rxok);
  2197. if (info->icount.txunder)
  2198. seq_printf(m, " txunder:%d", info->icount.txunder);
  2199. if (info->icount.txabort)
  2200. seq_printf(m, " txabort:%d", info->icount.txabort);
  2201. if (info->icount.rxshort)
  2202. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  2203. if (info->icount.rxlong)
  2204. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  2205. if (info->icount.rxover)
  2206. seq_printf(m, " rxover:%d", info->icount.rxover);
  2207. if (info->icount.rxcrc)
  2208. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  2209. } else {
  2210. seq_printf(m, " ASYNC tx:%d rx:%d",
  2211. info->icount.tx, info->icount.rx);
  2212. if (info->icount.frame)
  2213. seq_printf(m, " fe:%d", info->icount.frame);
  2214. if (info->icount.parity)
  2215. seq_printf(m, " pe:%d", info->icount.parity);
  2216. if (info->icount.brk)
  2217. seq_printf(m, " brk:%d", info->icount.brk);
  2218. if (info->icount.overrun)
  2219. seq_printf(m, " oe:%d", info->icount.overrun);
  2220. }
  2221. /* Append serial signal status to end */
  2222. seq_printf(m, " %s\n", stat_buf+1);
  2223. seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2224. info->tx_active,info->bh_requested,info->bh_running,
  2225. info->pending_bh);
  2226. }
  2227. /* Called to print information about devices
  2228. */
  2229. static int mgslpc_proc_show(struct seq_file *m, void *v)
  2230. {
  2231. MGSLPC_INFO *info;
  2232. seq_printf(m, "synclink driver:%s\n", driver_version);
  2233. info = mgslpc_device_list;
  2234. while( info ) {
  2235. line_info(m, info);
  2236. info = info->next_device;
  2237. }
  2238. return 0;
  2239. }
  2240. static int mgslpc_proc_open(struct inode *inode, struct file *file)
  2241. {
  2242. return single_open(file, mgslpc_proc_show, NULL);
  2243. }
  2244. static const struct file_operations mgslpc_proc_fops = {
  2245. .owner = THIS_MODULE,
  2246. .open = mgslpc_proc_open,
  2247. .read = seq_read,
  2248. .llseek = seq_lseek,
  2249. .release = single_release,
  2250. };
  2251. static int rx_alloc_buffers(MGSLPC_INFO *info)
  2252. {
  2253. /* each buffer has header and data */
  2254. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2255. /* calculate total allocation size for 8 buffers */
  2256. info->rx_buf_total_size = info->rx_buf_size * 8;
  2257. /* limit total allocated memory */
  2258. if (info->rx_buf_total_size > 0x10000)
  2259. info->rx_buf_total_size = 0x10000;
  2260. /* calculate number of buffers */
  2261. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2262. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2263. if (info->rx_buf == NULL)
  2264. return -ENOMEM;
  2265. rx_reset_buffers(info);
  2266. return 0;
  2267. }
  2268. static void rx_free_buffers(MGSLPC_INFO *info)
  2269. {
  2270. kfree(info->rx_buf);
  2271. info->rx_buf = NULL;
  2272. }
  2273. static int claim_resources(MGSLPC_INFO *info)
  2274. {
  2275. if (rx_alloc_buffers(info) < 0 ) {
  2276. printk( "Cant allocate rx buffer %s\n", info->device_name);
  2277. release_resources(info);
  2278. return -ENODEV;
  2279. }
  2280. return 0;
  2281. }
  2282. static void release_resources(MGSLPC_INFO *info)
  2283. {
  2284. if (debug_level >= DEBUG_LEVEL_INFO)
  2285. printk("release_resources(%s)\n", info->device_name);
  2286. rx_free_buffers(info);
  2287. }
  2288. /* Add the specified device instance data structure to the
  2289. * global linked list of devices and increment the device count.
  2290. *
  2291. * Arguments: info pointer to device instance data
  2292. */
  2293. static void mgslpc_add_device(MGSLPC_INFO *info)
  2294. {
  2295. info->next_device = NULL;
  2296. info->line = mgslpc_device_count;
  2297. sprintf(info->device_name,"ttySLP%d",info->line);
  2298. if (info->line < MAX_DEVICE_COUNT) {
  2299. if (maxframe[info->line])
  2300. info->max_frame_size = maxframe[info->line];
  2301. }
  2302. mgslpc_device_count++;
  2303. if (!mgslpc_device_list)
  2304. mgslpc_device_list = info;
  2305. else {
  2306. MGSLPC_INFO *current_dev = mgslpc_device_list;
  2307. while( current_dev->next_device )
  2308. current_dev = current_dev->next_device;
  2309. current_dev->next_device = info;
  2310. }
  2311. if (info->max_frame_size < 4096)
  2312. info->max_frame_size = 4096;
  2313. else if (info->max_frame_size > 65535)
  2314. info->max_frame_size = 65535;
  2315. printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2316. info->device_name, info->io_base, info->irq_level);
  2317. #if SYNCLINK_GENERIC_HDLC
  2318. hdlcdev_init(info);
  2319. #endif
  2320. }
  2321. static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2322. {
  2323. MGSLPC_INFO *info = mgslpc_device_list;
  2324. MGSLPC_INFO *last = NULL;
  2325. while(info) {
  2326. if (info == remove_info) {
  2327. if (last)
  2328. last->next_device = info->next_device;
  2329. else
  2330. mgslpc_device_list = info->next_device;
  2331. #if SYNCLINK_GENERIC_HDLC
  2332. hdlcdev_exit(info);
  2333. #endif
  2334. release_resources(info);
  2335. kfree(info);
  2336. mgslpc_device_count--;
  2337. return;
  2338. }
  2339. last = info;
  2340. info = info->next_device;
  2341. }
  2342. }
  2343. static struct pcmcia_device_id mgslpc_ids[] = {
  2344. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2345. PCMCIA_DEVICE_NULL
  2346. };
  2347. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2348. static struct pcmcia_driver mgslpc_driver = {
  2349. .owner = THIS_MODULE,
  2350. .drv = {
  2351. .name = "synclink_cs",
  2352. },
  2353. .probe = mgslpc_probe,
  2354. .remove = mgslpc_detach,
  2355. .id_table = mgslpc_ids,
  2356. .suspend = mgslpc_suspend,
  2357. .resume = mgslpc_resume,
  2358. };
  2359. static const struct tty_operations mgslpc_ops = {
  2360. .open = mgslpc_open,
  2361. .close = mgslpc_close,
  2362. .write = mgslpc_write,
  2363. .put_char = mgslpc_put_char,
  2364. .flush_chars = mgslpc_flush_chars,
  2365. .write_room = mgslpc_write_room,
  2366. .chars_in_buffer = mgslpc_chars_in_buffer,
  2367. .flush_buffer = mgslpc_flush_buffer,
  2368. .ioctl = mgslpc_ioctl,
  2369. .throttle = mgslpc_throttle,
  2370. .unthrottle = mgslpc_unthrottle,
  2371. .send_xchar = mgslpc_send_xchar,
  2372. .break_ctl = mgslpc_break,
  2373. .wait_until_sent = mgslpc_wait_until_sent,
  2374. .set_termios = mgslpc_set_termios,
  2375. .stop = tx_pause,
  2376. .start = tx_release,
  2377. .hangup = mgslpc_hangup,
  2378. .tiocmget = tiocmget,
  2379. .tiocmset = tiocmset,
  2380. .proc_fops = &mgslpc_proc_fops,
  2381. };
  2382. static void synclink_cs_cleanup(void)
  2383. {
  2384. int rc;
  2385. printk("Unloading %s: version %s\n", driver_name, driver_version);
  2386. while(mgslpc_device_list)
  2387. mgslpc_remove_device(mgslpc_device_list);
  2388. if (serial_driver) {
  2389. if ((rc = tty_unregister_driver(serial_driver)))
  2390. printk("%s(%d) failed to unregister tty driver err=%d\n",
  2391. __FILE__,__LINE__,rc);
  2392. put_tty_driver(serial_driver);
  2393. }
  2394. pcmcia_unregister_driver(&mgslpc_driver);
  2395. }
  2396. static int __init synclink_cs_init(void)
  2397. {
  2398. int rc;
  2399. if (break_on_load) {
  2400. mgslpc_get_text_ptr();
  2401. BREAKPOINT();
  2402. }
  2403. printk("%s %s\n", driver_name, driver_version);
  2404. if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
  2405. return rc;
  2406. serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
  2407. if (!serial_driver) {
  2408. rc = -ENOMEM;
  2409. goto error;
  2410. }
  2411. /* Initialize the tty_driver structure */
  2412. serial_driver->owner = THIS_MODULE;
  2413. serial_driver->driver_name = "synclink_cs";
  2414. serial_driver->name = "ttySLP";
  2415. serial_driver->major = ttymajor;
  2416. serial_driver->minor_start = 64;
  2417. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2418. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2419. serial_driver->init_termios = tty_std_termios;
  2420. serial_driver->init_termios.c_cflag =
  2421. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2422. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  2423. tty_set_operations(serial_driver, &mgslpc_ops);
  2424. if ((rc = tty_register_driver(serial_driver)) < 0) {
  2425. printk("%s(%d):Couldn't register serial driver\n",
  2426. __FILE__,__LINE__);
  2427. put_tty_driver(serial_driver);
  2428. serial_driver = NULL;
  2429. goto error;
  2430. }
  2431. printk("%s %s, tty major#%d\n",
  2432. driver_name, driver_version,
  2433. serial_driver->major);
  2434. return 0;
  2435. error:
  2436. synclink_cs_cleanup();
  2437. return rc;
  2438. }
  2439. static void __exit synclink_cs_exit(void)
  2440. {
  2441. synclink_cs_cleanup();
  2442. }
  2443. module_init(synclink_cs_init);
  2444. module_exit(synclink_cs_exit);
  2445. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2446. {
  2447. unsigned int M, N;
  2448. unsigned char val;
  2449. /* note:standard BRG mode is broken in V3.2 chip
  2450. * so enhanced mode is always used
  2451. */
  2452. if (rate) {
  2453. N = 3686400 / rate;
  2454. if (!N)
  2455. N = 1;
  2456. N >>= 1;
  2457. for (M = 1; N > 64 && M < 16; M++)
  2458. N >>= 1;
  2459. N--;
  2460. /* BGR[5..0] = N
  2461. * BGR[9..6] = M
  2462. * BGR[7..0] contained in BGR register
  2463. * BGR[9..8] contained in CCR2[7..6]
  2464. * divisor = (N+1)*2^M
  2465. *
  2466. * Note: M *must* not be zero (causes asymetric duty cycle)
  2467. */
  2468. write_reg(info, (unsigned char) (channel + BGR),
  2469. (unsigned char) ((M << 6) + N));
  2470. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2471. val |= ((M << 4) & 0xc0);
  2472. write_reg(info, (unsigned char) (channel + CCR2), val);
  2473. }
  2474. }
  2475. /* Enabled the AUX clock output at the specified frequency.
  2476. */
  2477. static void enable_auxclk(MGSLPC_INFO *info)
  2478. {
  2479. unsigned char val;
  2480. /* MODE
  2481. *
  2482. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2483. * 05 ADM Address Mode, 0 = no addr recognition
  2484. * 04 TMD Timer Mode, 0 = external
  2485. * 03 RAC Receiver Active, 0 = inactive
  2486. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2487. * 01 TRS Timer Resolution, 1=512
  2488. * 00 TLP Test Loop, 0 = no loop
  2489. *
  2490. * 1000 0010
  2491. */
  2492. val = 0x82;
  2493. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2494. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2495. val |= BIT2;
  2496. write_reg(info, CHB + MODE, val);
  2497. /* CCR0
  2498. *
  2499. * 07 PU Power Up, 1=active, 0=power down
  2500. * 06 MCE Master Clock Enable, 1=enabled
  2501. * 05 Reserved, 0
  2502. * 04..02 SC[2..0] Encoding
  2503. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2504. *
  2505. * 11000000
  2506. */
  2507. write_reg(info, CHB + CCR0, 0xc0);
  2508. /* CCR1
  2509. *
  2510. * 07 SFLG Shared Flag, 0 = disable shared flags
  2511. * 06 GALP Go Active On Loop, 0 = not used
  2512. * 05 GLP Go On Loop, 0 = not used
  2513. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2514. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2515. * 02..00 CM[2..0] Clock Mode
  2516. *
  2517. * 0001 0111
  2518. */
  2519. write_reg(info, CHB + CCR1, 0x17);
  2520. /* CCR2 (Channel B)
  2521. *
  2522. * 07..06 BGR[9..8] Baud rate bits 9..8
  2523. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2524. * 04 SSEL Clock source select, 1=submode b
  2525. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2526. * 02 RWX Read/Write Exchange 0=disabled
  2527. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2528. * 00 DIV, data inversion 0=disabled, 1=enabled
  2529. *
  2530. * 0011 1000
  2531. */
  2532. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2533. write_reg(info, CHB + CCR2, 0x38);
  2534. else
  2535. write_reg(info, CHB + CCR2, 0x30);
  2536. /* CCR4
  2537. *
  2538. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2539. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2540. * 05 TST1 Test Pin, 0=normal operation
  2541. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2542. * 03..02 Reserved, must be 0
  2543. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2544. *
  2545. * 0101 0000
  2546. */
  2547. write_reg(info, CHB + CCR4, 0x50);
  2548. /* if auxclk not enabled, set internal BRG so
  2549. * CTS transitions can be detected (requires TxC)
  2550. */
  2551. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2552. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2553. else
  2554. mgslpc_set_rate(info, CHB, 921600);
  2555. }
  2556. static void loopback_enable(MGSLPC_INFO *info)
  2557. {
  2558. unsigned char val;
  2559. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2560. val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
  2561. write_reg(info, CHA + CCR1, val);
  2562. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2563. val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
  2564. write_reg(info, CHA + CCR2, val);
  2565. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2566. if (info->params.clock_speed)
  2567. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2568. else
  2569. mgslpc_set_rate(info, CHA, 1843200);
  2570. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2571. val = read_reg(info, CHA + MODE) | BIT0;
  2572. write_reg(info, CHA + MODE, val);
  2573. }
  2574. static void hdlc_mode(MGSLPC_INFO *info)
  2575. {
  2576. unsigned char val;
  2577. unsigned char clkmode, clksubmode;
  2578. /* disable all interrupts */
  2579. irq_disable(info, CHA, 0xffff);
  2580. irq_disable(info, CHB, 0xffff);
  2581. port_irq_disable(info, 0xff);
  2582. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2583. clkmode = clksubmode = 0;
  2584. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2585. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2586. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2587. clkmode = 7;
  2588. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2589. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2590. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2591. clkmode = 7;
  2592. clksubmode = 1;
  2593. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2594. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2595. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2596. clkmode = 6;
  2597. clksubmode = 1;
  2598. } else {
  2599. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2600. clkmode = 6;
  2601. }
  2602. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2603. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2604. clksubmode = 1;
  2605. }
  2606. /* MODE
  2607. *
  2608. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2609. * 05 ADM Address Mode, 0 = no addr recognition
  2610. * 04 TMD Timer Mode, 0 = external
  2611. * 03 RAC Receiver Active, 0 = inactive
  2612. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2613. * 01 TRS Timer Resolution, 1=512
  2614. * 00 TLP Test Loop, 0 = no loop
  2615. *
  2616. * 1000 0010
  2617. */
  2618. val = 0x82;
  2619. if (info->params.loopback)
  2620. val |= BIT0;
  2621. /* preserve RTS state */
  2622. if (info->serial_signals & SerialSignal_RTS)
  2623. val |= BIT2;
  2624. write_reg(info, CHA + MODE, val);
  2625. /* CCR0
  2626. *
  2627. * 07 PU Power Up, 1=active, 0=power down
  2628. * 06 MCE Master Clock Enable, 1=enabled
  2629. * 05 Reserved, 0
  2630. * 04..02 SC[2..0] Encoding
  2631. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2632. *
  2633. * 11000000
  2634. */
  2635. val = 0xc0;
  2636. switch (info->params.encoding)
  2637. {
  2638. case HDLC_ENCODING_NRZI:
  2639. val |= BIT3;
  2640. break;
  2641. case HDLC_ENCODING_BIPHASE_SPACE:
  2642. val |= BIT4;
  2643. break; // FM0
  2644. case HDLC_ENCODING_BIPHASE_MARK:
  2645. val |= BIT4 + BIT2;
  2646. break; // FM1
  2647. case HDLC_ENCODING_BIPHASE_LEVEL:
  2648. val |= BIT4 + BIT3;
  2649. break; // Manchester
  2650. }
  2651. write_reg(info, CHA + CCR0, val);
  2652. /* CCR1
  2653. *
  2654. * 07 SFLG Shared Flag, 0 = disable shared flags
  2655. * 06 GALP Go Active On Loop, 0 = not used
  2656. * 05 GLP Go On Loop, 0 = not used
  2657. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2658. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2659. * 02..00 CM[2..0] Clock Mode
  2660. *
  2661. * 0001 0000
  2662. */
  2663. val = 0x10 + clkmode;
  2664. write_reg(info, CHA + CCR1, val);
  2665. /* CCR2
  2666. *
  2667. * 07..06 BGR[9..8] Baud rate bits 9..8
  2668. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2669. * 04 SSEL Clock source select, 1=submode b
  2670. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2671. * 02 RWX Read/Write Exchange 0=disabled
  2672. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2673. * 00 DIV, data inversion 0=disabled, 1=enabled
  2674. *
  2675. * 0000 0000
  2676. */
  2677. val = 0x00;
  2678. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2679. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2680. val |= BIT5;
  2681. if (clksubmode)
  2682. val |= BIT4;
  2683. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2684. val |= BIT1;
  2685. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2686. val |= BIT0;
  2687. write_reg(info, CHA + CCR2, val);
  2688. /* CCR3
  2689. *
  2690. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2691. * 05 EPT Enable preamble transmission, 1=enabled
  2692. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2693. * 03 CRL CRC Reset Level, 0=FFFF
  2694. * 02 RCRC Rx CRC 0=On 1=Off
  2695. * 01 TCRC Tx CRC 0=On 1=Off
  2696. * 00 PSD DPLL Phase Shift Disable
  2697. *
  2698. * 0000 0000
  2699. */
  2700. val = 0x00;
  2701. if (info->params.crc_type == HDLC_CRC_NONE)
  2702. val |= BIT2 + BIT1;
  2703. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2704. val |= BIT5;
  2705. switch (info->params.preamble_length)
  2706. {
  2707. case HDLC_PREAMBLE_LENGTH_16BITS:
  2708. val |= BIT6;
  2709. break;
  2710. case HDLC_PREAMBLE_LENGTH_32BITS:
  2711. val |= BIT6;
  2712. break;
  2713. case HDLC_PREAMBLE_LENGTH_64BITS:
  2714. val |= BIT7 + BIT6;
  2715. break;
  2716. }
  2717. write_reg(info, CHA + CCR3, val);
  2718. /* PRE - Preamble pattern */
  2719. val = 0;
  2720. switch (info->params.preamble)
  2721. {
  2722. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2723. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2724. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2725. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2726. }
  2727. write_reg(info, CHA + PRE, val);
  2728. /* CCR4
  2729. *
  2730. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2731. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2732. * 05 TST1 Test Pin, 0=normal operation
  2733. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2734. * 03..02 Reserved, must be 0
  2735. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2736. *
  2737. * 0101 0000
  2738. */
  2739. val = 0x50;
  2740. write_reg(info, CHA + CCR4, val);
  2741. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2742. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2743. else
  2744. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2745. /* RLCR Receive length check register
  2746. *
  2747. * 7 1=enable receive length check
  2748. * 6..0 Max frame length = (RL + 1) * 32
  2749. */
  2750. write_reg(info, CHA + RLCR, 0);
  2751. /* XBCH Transmit Byte Count High
  2752. *
  2753. * 07 DMA mode, 0 = interrupt driven
  2754. * 06 NRM, 0=ABM (ignored)
  2755. * 05 CAS Carrier Auto Start
  2756. * 04 XC Transmit Continuously (ignored)
  2757. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2758. *
  2759. * 0000 0000
  2760. */
  2761. val = 0x00;
  2762. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2763. val |= BIT5;
  2764. write_reg(info, CHA + XBCH, val);
  2765. enable_auxclk(info);
  2766. if (info->params.loopback || info->testing_irq)
  2767. loopback_enable(info);
  2768. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2769. {
  2770. irq_enable(info, CHB, IRQ_CTS);
  2771. /* PVR[3] 1=AUTO CTS active */
  2772. set_reg_bits(info, CHA + PVR, BIT3);
  2773. } else
  2774. clear_reg_bits(info, CHA + PVR, BIT3);
  2775. irq_enable(info, CHA,
  2776. IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
  2777. IRQ_UNDERRUN + IRQ_TXFIFO);
  2778. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2779. wait_command_complete(info, CHA);
  2780. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2781. /* Master clock mode enabled above to allow reset commands
  2782. * to complete even if no data clocks are present.
  2783. *
  2784. * Disable master clock mode for normal communications because
  2785. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2786. * IRQ when in master clock mode.
  2787. *
  2788. * Leave master clock mode enabled for IRQ test because the
  2789. * timer IRQ used by the test can only happen in master clock mode.
  2790. */
  2791. if (!info->testing_irq)
  2792. clear_reg_bits(info, CHA + CCR0, BIT6);
  2793. tx_set_idle(info);
  2794. tx_stop(info);
  2795. rx_stop(info);
  2796. }
  2797. static void rx_stop(MGSLPC_INFO *info)
  2798. {
  2799. if (debug_level >= DEBUG_LEVEL_ISR)
  2800. printk("%s(%d):rx_stop(%s)\n",
  2801. __FILE__,__LINE__, info->device_name );
  2802. /* MODE:03 RAC Receiver Active, 0=inactive */
  2803. clear_reg_bits(info, CHA + MODE, BIT3);
  2804. info->rx_enabled = false;
  2805. info->rx_overflow = false;
  2806. }
  2807. static void rx_start(MGSLPC_INFO *info)
  2808. {
  2809. if (debug_level >= DEBUG_LEVEL_ISR)
  2810. printk("%s(%d):rx_start(%s)\n",
  2811. __FILE__,__LINE__, info->device_name );
  2812. rx_reset_buffers(info);
  2813. info->rx_enabled = false;
  2814. info->rx_overflow = false;
  2815. /* MODE:03 RAC Receiver Active, 1=active */
  2816. set_reg_bits(info, CHA + MODE, BIT3);
  2817. info->rx_enabled = true;
  2818. }
  2819. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
  2820. {
  2821. if (debug_level >= DEBUG_LEVEL_ISR)
  2822. printk("%s(%d):tx_start(%s)\n",
  2823. __FILE__,__LINE__, info->device_name );
  2824. if (info->tx_count) {
  2825. /* If auto RTS enabled and RTS is inactive, then assert */
  2826. /* RTS and set a flag indicating that the driver should */
  2827. /* negate RTS when the transmission completes. */
  2828. info->drop_rts_on_tx_done = false;
  2829. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  2830. get_signals(info);
  2831. if (!(info->serial_signals & SerialSignal_RTS)) {
  2832. info->serial_signals |= SerialSignal_RTS;
  2833. set_signals(info);
  2834. info->drop_rts_on_tx_done = true;
  2835. }
  2836. }
  2837. if (info->params.mode == MGSL_MODE_ASYNC) {
  2838. if (!info->tx_active) {
  2839. info->tx_active = true;
  2840. tx_ready(info, tty);
  2841. }
  2842. } else {
  2843. info->tx_active = true;
  2844. tx_ready(info, tty);
  2845. mod_timer(&info->tx_timer, jiffies +
  2846. msecs_to_jiffies(5000));
  2847. }
  2848. }
  2849. if (!info->tx_enabled)
  2850. info->tx_enabled = true;
  2851. }
  2852. static void tx_stop(MGSLPC_INFO *info)
  2853. {
  2854. if (debug_level >= DEBUG_LEVEL_ISR)
  2855. printk("%s(%d):tx_stop(%s)\n",
  2856. __FILE__,__LINE__, info->device_name );
  2857. del_timer(&info->tx_timer);
  2858. info->tx_enabled = false;
  2859. info->tx_active = false;
  2860. }
  2861. /* Reset the adapter to a known state and prepare it for further use.
  2862. */
  2863. static void reset_device(MGSLPC_INFO *info)
  2864. {
  2865. /* power up both channels (set BIT7) */
  2866. write_reg(info, CHA + CCR0, 0x80);
  2867. write_reg(info, CHB + CCR0, 0x80);
  2868. write_reg(info, CHA + MODE, 0);
  2869. write_reg(info, CHB + MODE, 0);
  2870. /* disable all interrupts */
  2871. irq_disable(info, CHA, 0xffff);
  2872. irq_disable(info, CHB, 0xffff);
  2873. port_irq_disable(info, 0xff);
  2874. /* PCR Port Configuration Register
  2875. *
  2876. * 07..04 DEC[3..0] Serial I/F select outputs
  2877. * 03 output, 1=AUTO CTS control enabled
  2878. * 02 RI Ring Indicator input 0=active
  2879. * 01 DSR input 0=active
  2880. * 00 DTR output 0=active
  2881. *
  2882. * 0000 0110
  2883. */
  2884. write_reg(info, PCR, 0x06);
  2885. /* PVR Port Value Register
  2886. *
  2887. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  2888. * 03 AUTO CTS output 1=enabled
  2889. * 02 RI Ring Indicator input
  2890. * 01 DSR input
  2891. * 00 DTR output (1=inactive)
  2892. *
  2893. * 0000 0001
  2894. */
  2895. // write_reg(info, PVR, PVR_DTR);
  2896. /* IPC Interrupt Port Configuration
  2897. *
  2898. * 07 VIS 1=Masked interrupts visible
  2899. * 06..05 Reserved, 0
  2900. * 04..03 SLA Slave address, 00 ignored
  2901. * 02 CASM Cascading Mode, 1=daisy chain
  2902. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  2903. *
  2904. * 0000 0101
  2905. */
  2906. write_reg(info, IPC, 0x05);
  2907. }
  2908. static void async_mode(MGSLPC_INFO *info)
  2909. {
  2910. unsigned char val;
  2911. /* disable all interrupts */
  2912. irq_disable(info, CHA, 0xffff);
  2913. irq_disable(info, CHB, 0xffff);
  2914. port_irq_disable(info, 0xff);
  2915. /* MODE
  2916. *
  2917. * 07 Reserved, 0
  2918. * 06 FRTS RTS State, 0=active
  2919. * 05 FCTS Flow Control on CTS
  2920. * 04 FLON Flow Control Enable
  2921. * 03 RAC Receiver Active, 0 = inactive
  2922. * 02 RTS 0=Auto RTS, 1=manual RTS
  2923. * 01 TRS Timer Resolution, 1=512
  2924. * 00 TLP Test Loop, 0 = no loop
  2925. *
  2926. * 0000 0110
  2927. */
  2928. val = 0x06;
  2929. if (info->params.loopback)
  2930. val |= BIT0;
  2931. /* preserve RTS state */
  2932. if (!(info->serial_signals & SerialSignal_RTS))
  2933. val |= BIT6;
  2934. write_reg(info, CHA + MODE, val);
  2935. /* CCR0
  2936. *
  2937. * 07 PU Power Up, 1=active, 0=power down
  2938. * 06 MCE Master Clock Enable, 1=enabled
  2939. * 05 Reserved, 0
  2940. * 04..02 SC[2..0] Encoding, 000=NRZ
  2941. * 01..00 SM[1..0] Serial Mode, 11=Async
  2942. *
  2943. * 1000 0011
  2944. */
  2945. write_reg(info, CHA + CCR0, 0x83);
  2946. /* CCR1
  2947. *
  2948. * 07..05 Reserved, 0
  2949. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2950. * 03 BCR Bit Clock Rate, 1=16x
  2951. * 02..00 CM[2..0] Clock Mode, 111=BRG
  2952. *
  2953. * 0001 1111
  2954. */
  2955. write_reg(info, CHA + CCR1, 0x1f);
  2956. /* CCR2 (channel A)
  2957. *
  2958. * 07..06 BGR[9..8] Baud rate bits 9..8
  2959. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2960. * 04 SSEL Clock source select, 1=submode b
  2961. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2962. * 02 RWX Read/Write Exchange 0=disabled
  2963. * 01 Reserved, 0
  2964. * 00 DIV, data inversion 0=disabled, 1=enabled
  2965. *
  2966. * 0001 0000
  2967. */
  2968. write_reg(info, CHA + CCR2, 0x10);
  2969. /* CCR3
  2970. *
  2971. * 07..01 Reserved, 0
  2972. * 00 PSD DPLL Phase Shift Disable
  2973. *
  2974. * 0000 0000
  2975. */
  2976. write_reg(info, CHA + CCR3, 0);
  2977. /* CCR4
  2978. *
  2979. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2980. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2981. * 05 TST1 Test Pin, 0=normal operation
  2982. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2983. * 03..00 Reserved, must be 0
  2984. *
  2985. * 0101 0000
  2986. */
  2987. write_reg(info, CHA + CCR4, 0x50);
  2988. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  2989. /* DAFO Data Format
  2990. *
  2991. * 07 Reserved, 0
  2992. * 06 XBRK transmit break, 0=normal operation
  2993. * 05 Stop bits (0=1, 1=2)
  2994. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  2995. * 02 PAREN Parity Enable
  2996. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  2997. *
  2998. */
  2999. val = 0x00;
  3000. if (info->params.data_bits != 8)
  3001. val |= BIT0; /* 7 bits */
  3002. if (info->params.stop_bits != 1)
  3003. val |= BIT5;
  3004. if (info->params.parity != ASYNC_PARITY_NONE)
  3005. {
  3006. val |= BIT2; /* Parity enable */
  3007. if (info->params.parity == ASYNC_PARITY_ODD)
  3008. val |= BIT3;
  3009. else
  3010. val |= BIT4;
  3011. }
  3012. write_reg(info, CHA + DAFO, val);
  3013. /* RFC Rx FIFO Control
  3014. *
  3015. * 07 Reserved, 0
  3016. * 06 DPS, 1=parity bit not stored in data byte
  3017. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  3018. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  3019. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  3020. * 01 Reserved, 0
  3021. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  3022. *
  3023. * 0101 1100
  3024. */
  3025. write_reg(info, CHA + RFC, 0x5c);
  3026. /* RLCR Receive length check register
  3027. *
  3028. * Max frame length = (RL + 1) * 32
  3029. */
  3030. write_reg(info, CHA + RLCR, 0);
  3031. /* XBCH Transmit Byte Count High
  3032. *
  3033. * 07 DMA mode, 0 = interrupt driven
  3034. * 06 NRM, 0=ABM (ignored)
  3035. * 05 CAS Carrier Auto Start
  3036. * 04 XC Transmit Continuously (ignored)
  3037. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  3038. *
  3039. * 0000 0000
  3040. */
  3041. val = 0x00;
  3042. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3043. val |= BIT5;
  3044. write_reg(info, CHA + XBCH, val);
  3045. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3046. irq_enable(info, CHA, IRQ_CTS);
  3047. /* MODE:03 RAC Receiver Active, 1=active */
  3048. set_reg_bits(info, CHA + MODE, BIT3);
  3049. enable_auxclk(info);
  3050. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3051. irq_enable(info, CHB, IRQ_CTS);
  3052. /* PVR[3] 1=AUTO CTS active */
  3053. set_reg_bits(info, CHA + PVR, BIT3);
  3054. } else
  3055. clear_reg_bits(info, CHA + PVR, BIT3);
  3056. irq_enable(info, CHA,
  3057. IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
  3058. IRQ_ALLSENT + IRQ_TXFIFO);
  3059. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3060. wait_command_complete(info, CHA);
  3061. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3062. }
  3063. /* Set the HDLC idle mode for the transmitter.
  3064. */
  3065. static void tx_set_idle(MGSLPC_INFO *info)
  3066. {
  3067. /* Note: ESCC2 only supports flags and one idle modes */
  3068. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3069. set_reg_bits(info, CHA + CCR1, BIT3);
  3070. else
  3071. clear_reg_bits(info, CHA + CCR1, BIT3);
  3072. }
  3073. /* get state of the V24 status (input) signals.
  3074. */
  3075. static void get_signals(MGSLPC_INFO *info)
  3076. {
  3077. unsigned char status = 0;
  3078. /* preserve DTR and RTS */
  3079. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  3080. if (read_reg(info, CHB + VSTR) & BIT7)
  3081. info->serial_signals |= SerialSignal_DCD;
  3082. if (read_reg(info, CHB + STAR) & BIT1)
  3083. info->serial_signals |= SerialSignal_CTS;
  3084. status = read_reg(info, CHA + PVR);
  3085. if (!(status & PVR_RI))
  3086. info->serial_signals |= SerialSignal_RI;
  3087. if (!(status & PVR_DSR))
  3088. info->serial_signals |= SerialSignal_DSR;
  3089. }
  3090. /* Set the state of DTR and RTS based on contents of
  3091. * serial_signals member of device extension.
  3092. */
  3093. static void set_signals(MGSLPC_INFO *info)
  3094. {
  3095. unsigned char val;
  3096. val = read_reg(info, CHA + MODE);
  3097. if (info->params.mode == MGSL_MODE_ASYNC) {
  3098. if (info->serial_signals & SerialSignal_RTS)
  3099. val &= ~BIT6;
  3100. else
  3101. val |= BIT6;
  3102. } else {
  3103. if (info->serial_signals & SerialSignal_RTS)
  3104. val |= BIT2;
  3105. else
  3106. val &= ~BIT2;
  3107. }
  3108. write_reg(info, CHA + MODE, val);
  3109. if (info->serial_signals & SerialSignal_DTR)
  3110. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3111. else
  3112. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3113. }
  3114. static void rx_reset_buffers(MGSLPC_INFO *info)
  3115. {
  3116. RXBUF *buf;
  3117. int i;
  3118. info->rx_put = 0;
  3119. info->rx_get = 0;
  3120. info->rx_frame_count = 0;
  3121. for (i=0 ; i < info->rx_buf_count ; i++) {
  3122. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3123. buf->status = buf->count = 0;
  3124. }
  3125. }
  3126. /* Attempt to return a received HDLC frame
  3127. * Only frames received without errors are returned.
  3128. *
  3129. * Returns true if frame returned, otherwise false
  3130. */
  3131. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
  3132. {
  3133. unsigned short status;
  3134. RXBUF *buf;
  3135. unsigned int framesize = 0;
  3136. unsigned long flags;
  3137. bool return_frame = false;
  3138. if (info->rx_frame_count == 0)
  3139. return false;
  3140. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3141. status = buf->status;
  3142. /* 07 VFR 1=valid frame
  3143. * 06 RDO 1=data overrun
  3144. * 05 CRC 1=OK, 0=error
  3145. * 04 RAB 1=frame aborted
  3146. */
  3147. if ((status & 0xf0) != 0xA0) {
  3148. if (!(status & BIT7) || (status & BIT4))
  3149. info->icount.rxabort++;
  3150. else if (status & BIT6)
  3151. info->icount.rxover++;
  3152. else if (!(status & BIT5)) {
  3153. info->icount.rxcrc++;
  3154. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3155. return_frame = true;
  3156. }
  3157. framesize = 0;
  3158. #if SYNCLINK_GENERIC_HDLC
  3159. {
  3160. info->netdev->stats.rx_errors++;
  3161. info->netdev->stats.rx_frame_errors++;
  3162. }
  3163. #endif
  3164. } else
  3165. return_frame = true;
  3166. if (return_frame)
  3167. framesize = buf->count;
  3168. if (debug_level >= DEBUG_LEVEL_BH)
  3169. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3170. __FILE__,__LINE__,info->device_name,status,framesize);
  3171. if (debug_level >= DEBUG_LEVEL_DATA)
  3172. trace_block(info, buf->data, framesize, 0);
  3173. if (framesize) {
  3174. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3175. framesize+1 > info->max_frame_size) ||
  3176. framesize > info->max_frame_size)
  3177. info->icount.rxlong++;
  3178. else {
  3179. if (status & BIT5)
  3180. info->icount.rxok++;
  3181. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3182. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3183. ++framesize;
  3184. }
  3185. #if SYNCLINK_GENERIC_HDLC
  3186. if (info->netcount)
  3187. hdlcdev_rx(info, buf->data, framesize);
  3188. else
  3189. #endif
  3190. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3191. }
  3192. }
  3193. spin_lock_irqsave(&info->lock,flags);
  3194. buf->status = buf->count = 0;
  3195. info->rx_frame_count--;
  3196. info->rx_get++;
  3197. if (info->rx_get >= info->rx_buf_count)
  3198. info->rx_get = 0;
  3199. spin_unlock_irqrestore(&info->lock,flags);
  3200. return true;
  3201. }
  3202. static bool register_test(MGSLPC_INFO *info)
  3203. {
  3204. static unsigned char patterns[] =
  3205. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3206. static unsigned int count = ARRAY_SIZE(patterns);
  3207. unsigned int i;
  3208. bool rc = true;
  3209. unsigned long flags;
  3210. spin_lock_irqsave(&info->lock,flags);
  3211. reset_device(info);
  3212. for (i = 0; i < count; i++) {
  3213. write_reg(info, XAD1, patterns[i]);
  3214. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3215. if ((read_reg(info, XAD1) != patterns[i]) ||
  3216. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3217. rc = false;
  3218. break;
  3219. }
  3220. }
  3221. spin_unlock_irqrestore(&info->lock,flags);
  3222. return rc;
  3223. }
  3224. static bool irq_test(MGSLPC_INFO *info)
  3225. {
  3226. unsigned long end_time;
  3227. unsigned long flags;
  3228. spin_lock_irqsave(&info->lock,flags);
  3229. reset_device(info);
  3230. info->testing_irq = true;
  3231. hdlc_mode(info);
  3232. info->irq_occurred = false;
  3233. /* init hdlc mode */
  3234. irq_enable(info, CHA, IRQ_TIMER);
  3235. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3236. issue_command(info, CHA, CMD_START_TIMER);
  3237. spin_unlock_irqrestore(&info->lock,flags);
  3238. end_time=100;
  3239. while(end_time-- && !info->irq_occurred) {
  3240. msleep_interruptible(10);
  3241. }
  3242. info->testing_irq = false;
  3243. spin_lock_irqsave(&info->lock,flags);
  3244. reset_device(info);
  3245. spin_unlock_irqrestore(&info->lock,flags);
  3246. return info->irq_occurred;
  3247. }
  3248. static int adapter_test(MGSLPC_INFO *info)
  3249. {
  3250. if (!register_test(info)) {
  3251. info->init_error = DiagStatus_AddressFailure;
  3252. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  3253. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  3254. return -ENODEV;
  3255. }
  3256. if (!irq_test(info)) {
  3257. info->init_error = DiagStatus_IrqFailure;
  3258. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3259. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  3260. return -ENODEV;
  3261. }
  3262. if (debug_level >= DEBUG_LEVEL_INFO)
  3263. printk("%s(%d):device %s passed diagnostics\n",
  3264. __FILE__,__LINE__,info->device_name);
  3265. return 0;
  3266. }
  3267. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3268. {
  3269. int i;
  3270. int linecount;
  3271. if (xmit)
  3272. printk("%s tx data:\n",info->device_name);
  3273. else
  3274. printk("%s rx data:\n",info->device_name);
  3275. while(count) {
  3276. if (count > 16)
  3277. linecount = 16;
  3278. else
  3279. linecount = count;
  3280. for(i=0;i<linecount;i++)
  3281. printk("%02X ",(unsigned char)data[i]);
  3282. for(;i<17;i++)
  3283. printk(" ");
  3284. for(i=0;i<linecount;i++) {
  3285. if (data[i]>=040 && data[i]<=0176)
  3286. printk("%c",data[i]);
  3287. else
  3288. printk(".");
  3289. }
  3290. printk("\n");
  3291. data += linecount;
  3292. count -= linecount;
  3293. }
  3294. }
  3295. /* HDLC frame time out
  3296. * update stats and do tx completion processing
  3297. */
  3298. static void tx_timeout(unsigned long context)
  3299. {
  3300. MGSLPC_INFO *info = (MGSLPC_INFO*)context;
  3301. unsigned long flags;
  3302. if ( debug_level >= DEBUG_LEVEL_INFO )
  3303. printk( "%s(%d):tx_timeout(%s)\n",
  3304. __FILE__,__LINE__,info->device_name);
  3305. if(info->tx_active &&
  3306. info->params.mode == MGSL_MODE_HDLC) {
  3307. info->icount.txtimeout++;
  3308. }
  3309. spin_lock_irqsave(&info->lock,flags);
  3310. info->tx_active = false;
  3311. info->tx_count = info->tx_put = info->tx_get = 0;
  3312. spin_unlock_irqrestore(&info->lock,flags);
  3313. #if SYNCLINK_GENERIC_HDLC
  3314. if (info->netcount)
  3315. hdlcdev_tx_done(info);
  3316. else
  3317. #endif
  3318. {
  3319. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3320. bh_transmit(info, tty);
  3321. tty_kref_put(tty);
  3322. }
  3323. }
  3324. #if SYNCLINK_GENERIC_HDLC
  3325. /**
  3326. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3327. * set encoding and frame check sequence (FCS) options
  3328. *
  3329. * dev pointer to network device structure
  3330. * encoding serial encoding setting
  3331. * parity FCS setting
  3332. *
  3333. * returns 0 if success, otherwise error code
  3334. */
  3335. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3336. unsigned short parity)
  3337. {
  3338. MGSLPC_INFO *info = dev_to_port(dev);
  3339. struct tty_struct *tty;
  3340. unsigned char new_encoding;
  3341. unsigned short new_crctype;
  3342. /* return error if TTY interface open */
  3343. if (info->port.count)
  3344. return -EBUSY;
  3345. switch (encoding)
  3346. {
  3347. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3348. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3349. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3350. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3351. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3352. default: return -EINVAL;
  3353. }
  3354. switch (parity)
  3355. {
  3356. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3357. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3358. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3359. default: return -EINVAL;
  3360. }
  3361. info->params.encoding = new_encoding;
  3362. info->params.crc_type = new_crctype;
  3363. /* if network interface up, reprogram hardware */
  3364. if (info->netcount) {
  3365. tty = tty_port_tty_get(&info->port);
  3366. mgslpc_program_hw(info, tty);
  3367. tty_kref_put(tty);
  3368. }
  3369. return 0;
  3370. }
  3371. /**
  3372. * called by generic HDLC layer to send frame
  3373. *
  3374. * skb socket buffer containing HDLC frame
  3375. * dev pointer to network device structure
  3376. */
  3377. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  3378. struct net_device *dev)
  3379. {
  3380. MGSLPC_INFO *info = dev_to_port(dev);
  3381. unsigned long flags;
  3382. if (debug_level >= DEBUG_LEVEL_INFO)
  3383. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  3384. /* stop sending until this frame completes */
  3385. netif_stop_queue(dev);
  3386. /* copy data to device buffers */
  3387. skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
  3388. info->tx_get = 0;
  3389. info->tx_put = info->tx_count = skb->len;
  3390. /* update network statistics */
  3391. dev->stats.tx_packets++;
  3392. dev->stats.tx_bytes += skb->len;
  3393. /* done with socket buffer, so free it */
  3394. dev_kfree_skb(skb);
  3395. /* save start time for transmit timeout detection */
  3396. dev->trans_start = jiffies;
  3397. /* start hardware transmitter if necessary */
  3398. spin_lock_irqsave(&info->lock,flags);
  3399. if (!info->tx_active) {
  3400. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3401. tx_start(info, tty);
  3402. tty_kref_put(tty);
  3403. }
  3404. spin_unlock_irqrestore(&info->lock,flags);
  3405. return NETDEV_TX_OK;
  3406. }
  3407. /**
  3408. * called by network layer when interface enabled
  3409. * claim resources and initialize hardware
  3410. *
  3411. * dev pointer to network device structure
  3412. *
  3413. * returns 0 if success, otherwise error code
  3414. */
  3415. static int hdlcdev_open(struct net_device *dev)
  3416. {
  3417. MGSLPC_INFO *info = dev_to_port(dev);
  3418. struct tty_struct *tty;
  3419. int rc;
  3420. unsigned long flags;
  3421. if (debug_level >= DEBUG_LEVEL_INFO)
  3422. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  3423. /* generic HDLC layer open processing */
  3424. if ((rc = hdlc_open(dev)))
  3425. return rc;
  3426. /* arbitrate between network and tty opens */
  3427. spin_lock_irqsave(&info->netlock, flags);
  3428. if (info->port.count != 0 || info->netcount != 0) {
  3429. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3430. spin_unlock_irqrestore(&info->netlock, flags);
  3431. return -EBUSY;
  3432. }
  3433. info->netcount=1;
  3434. spin_unlock_irqrestore(&info->netlock, flags);
  3435. tty = tty_port_tty_get(&info->port);
  3436. /* claim resources and init adapter */
  3437. if ((rc = startup(info, tty)) != 0) {
  3438. tty_kref_put(tty);
  3439. spin_lock_irqsave(&info->netlock, flags);
  3440. info->netcount=0;
  3441. spin_unlock_irqrestore(&info->netlock, flags);
  3442. return rc;
  3443. }
  3444. /* assert DTR and RTS, apply hardware settings */
  3445. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  3446. mgslpc_program_hw(info, tty);
  3447. tty_kref_put(tty);
  3448. /* enable network layer transmit */
  3449. dev->trans_start = jiffies;
  3450. netif_start_queue(dev);
  3451. /* inform generic HDLC layer of current DCD status */
  3452. spin_lock_irqsave(&info->lock, flags);
  3453. get_signals(info);
  3454. spin_unlock_irqrestore(&info->lock, flags);
  3455. if (info->serial_signals & SerialSignal_DCD)
  3456. netif_carrier_on(dev);
  3457. else
  3458. netif_carrier_off(dev);
  3459. return 0;
  3460. }
  3461. /**
  3462. * called by network layer when interface is disabled
  3463. * shutdown hardware and release resources
  3464. *
  3465. * dev pointer to network device structure
  3466. *
  3467. * returns 0 if success, otherwise error code
  3468. */
  3469. static int hdlcdev_close(struct net_device *dev)
  3470. {
  3471. MGSLPC_INFO *info = dev_to_port(dev);
  3472. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3473. unsigned long flags;
  3474. if (debug_level >= DEBUG_LEVEL_INFO)
  3475. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  3476. netif_stop_queue(dev);
  3477. /* shutdown adapter and release resources */
  3478. shutdown(info, tty);
  3479. tty_kref_put(tty);
  3480. hdlc_close(dev);
  3481. spin_lock_irqsave(&info->netlock, flags);
  3482. info->netcount=0;
  3483. spin_unlock_irqrestore(&info->netlock, flags);
  3484. return 0;
  3485. }
  3486. /**
  3487. * called by network layer to process IOCTL call to network device
  3488. *
  3489. * dev pointer to network device structure
  3490. * ifr pointer to network interface request structure
  3491. * cmd IOCTL command code
  3492. *
  3493. * returns 0 if success, otherwise error code
  3494. */
  3495. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3496. {
  3497. const size_t size = sizeof(sync_serial_settings);
  3498. sync_serial_settings new_line;
  3499. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3500. MGSLPC_INFO *info = dev_to_port(dev);
  3501. unsigned int flags;
  3502. if (debug_level >= DEBUG_LEVEL_INFO)
  3503. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  3504. /* return error if TTY interface open */
  3505. if (info->port.count)
  3506. return -EBUSY;
  3507. if (cmd != SIOCWANDEV)
  3508. return hdlc_ioctl(dev, ifr, cmd);
  3509. switch(ifr->ifr_settings.type) {
  3510. case IF_GET_IFACE: /* return current sync_serial_settings */
  3511. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3512. if (ifr->ifr_settings.size < size) {
  3513. ifr->ifr_settings.size = size; /* data size wanted */
  3514. return -ENOBUFS;
  3515. }
  3516. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3517. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3518. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3519. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3520. switch (flags){
  3521. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3522. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3523. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3524. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3525. default: new_line.clock_type = CLOCK_DEFAULT;
  3526. }
  3527. new_line.clock_rate = info->params.clock_speed;
  3528. new_line.loopback = info->params.loopback ? 1:0;
  3529. if (copy_to_user(line, &new_line, size))
  3530. return -EFAULT;
  3531. return 0;
  3532. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3533. if(!capable(CAP_NET_ADMIN))
  3534. return -EPERM;
  3535. if (copy_from_user(&new_line, line, size))
  3536. return -EFAULT;
  3537. switch (new_line.clock_type)
  3538. {
  3539. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3540. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3541. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3542. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3543. case CLOCK_DEFAULT: flags = info->params.flags &
  3544. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3545. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3546. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3547. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3548. default: return -EINVAL;
  3549. }
  3550. if (new_line.loopback != 0 && new_line.loopback != 1)
  3551. return -EINVAL;
  3552. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3553. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3554. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3555. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3556. info->params.flags |= flags;
  3557. info->params.loopback = new_line.loopback;
  3558. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3559. info->params.clock_speed = new_line.clock_rate;
  3560. else
  3561. info->params.clock_speed = 0;
  3562. /* if network interface up, reprogram hardware */
  3563. if (info->netcount) {
  3564. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3565. mgslpc_program_hw(info, tty);
  3566. tty_kref_put(tty);
  3567. }
  3568. return 0;
  3569. default:
  3570. return hdlc_ioctl(dev, ifr, cmd);
  3571. }
  3572. }
  3573. /**
  3574. * called by network layer when transmit timeout is detected
  3575. *
  3576. * dev pointer to network device structure
  3577. */
  3578. static void hdlcdev_tx_timeout(struct net_device *dev)
  3579. {
  3580. MGSLPC_INFO *info = dev_to_port(dev);
  3581. unsigned long flags;
  3582. if (debug_level >= DEBUG_LEVEL_INFO)
  3583. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  3584. dev->stats.tx_errors++;
  3585. dev->stats.tx_aborted_errors++;
  3586. spin_lock_irqsave(&info->lock,flags);
  3587. tx_stop(info);
  3588. spin_unlock_irqrestore(&info->lock,flags);
  3589. netif_wake_queue(dev);
  3590. }
  3591. /**
  3592. * called by device driver when transmit completes
  3593. * reenable network layer transmit if stopped
  3594. *
  3595. * info pointer to device instance information
  3596. */
  3597. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3598. {
  3599. if (netif_queue_stopped(info->netdev))
  3600. netif_wake_queue(info->netdev);
  3601. }
  3602. /**
  3603. * called by device driver when frame received
  3604. * pass frame to network layer
  3605. *
  3606. * info pointer to device instance information
  3607. * buf pointer to buffer contianing frame data
  3608. * size count of data bytes in buf
  3609. */
  3610. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3611. {
  3612. struct sk_buff *skb = dev_alloc_skb(size);
  3613. struct net_device *dev = info->netdev;
  3614. if (debug_level >= DEBUG_LEVEL_INFO)
  3615. printk("hdlcdev_rx(%s)\n",dev->name);
  3616. if (skb == NULL) {
  3617. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3618. dev->stats.rx_dropped++;
  3619. return;
  3620. }
  3621. memcpy(skb_put(skb, size), buf, size);
  3622. skb->protocol = hdlc_type_trans(skb, dev);
  3623. dev->stats.rx_packets++;
  3624. dev->stats.rx_bytes += size;
  3625. netif_rx(skb);
  3626. }
  3627. static const struct net_device_ops hdlcdev_ops = {
  3628. .ndo_open = hdlcdev_open,
  3629. .ndo_stop = hdlcdev_close,
  3630. .ndo_change_mtu = hdlc_change_mtu,
  3631. .ndo_start_xmit = hdlc_start_xmit,
  3632. .ndo_do_ioctl = hdlcdev_ioctl,
  3633. .ndo_tx_timeout = hdlcdev_tx_timeout,
  3634. };
  3635. /**
  3636. * called by device driver when adding device instance
  3637. * do generic HDLC initialization
  3638. *
  3639. * info pointer to device instance information
  3640. *
  3641. * returns 0 if success, otherwise error code
  3642. */
  3643. static int hdlcdev_init(MGSLPC_INFO *info)
  3644. {
  3645. int rc;
  3646. struct net_device *dev;
  3647. hdlc_device *hdlc;
  3648. /* allocate and initialize network and HDLC layer objects */
  3649. if (!(dev = alloc_hdlcdev(info))) {
  3650. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  3651. return -ENOMEM;
  3652. }
  3653. /* for network layer reporting purposes only */
  3654. dev->base_addr = info->io_base;
  3655. dev->irq = info->irq_level;
  3656. /* network layer callbacks and settings */
  3657. dev->netdev_ops = &hdlcdev_ops;
  3658. dev->watchdog_timeo = 10 * HZ;
  3659. dev->tx_queue_len = 50;
  3660. /* generic HDLC layer callbacks and settings */
  3661. hdlc = dev_to_hdlc(dev);
  3662. hdlc->attach = hdlcdev_attach;
  3663. hdlc->xmit = hdlcdev_xmit;
  3664. /* register objects with HDLC layer */
  3665. if ((rc = register_hdlc_device(dev))) {
  3666. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  3667. free_netdev(dev);
  3668. return rc;
  3669. }
  3670. info->netdev = dev;
  3671. return 0;
  3672. }
  3673. /**
  3674. * called by device driver when removing device instance
  3675. * do generic HDLC cleanup
  3676. *
  3677. * info pointer to device instance information
  3678. */
  3679. static void hdlcdev_exit(MGSLPC_INFO *info)
  3680. {
  3681. unregister_hdlc_device(info->netdev);
  3682. free_netdev(info->netdev);
  3683. info->netdev = NULL;
  3684. }
  3685. #endif /* CONFIG_HDLC */