radeon_cs.c 15 KB

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  1. /*
  2. * Copyright 2008 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Jerome Glisse <glisse@freedesktop.org>
  26. */
  27. #include "drmP.h"
  28. #include "radeon_drm.h"
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. void r100_cs_dump_packet(struct radeon_cs_parser *p,
  32. struct radeon_cs_packet *pkt);
  33. int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
  34. {
  35. struct drm_device *ddev = p->rdev->ddev;
  36. struct radeon_cs_chunk *chunk;
  37. unsigned i, j;
  38. bool duplicate;
  39. if (p->chunk_relocs_idx == -1) {
  40. return 0;
  41. }
  42. chunk = &p->chunks[p->chunk_relocs_idx];
  43. /* FIXME: we assume that each relocs use 4 dwords */
  44. p->nrelocs = chunk->length_dw / 4;
  45. p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
  46. if (p->relocs_ptr == NULL) {
  47. return -ENOMEM;
  48. }
  49. p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  50. if (p->relocs == NULL) {
  51. return -ENOMEM;
  52. }
  53. for (i = 0; i < p->nrelocs; i++) {
  54. struct drm_radeon_cs_reloc *r;
  55. duplicate = false;
  56. r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
  57. for (j = 0; j < i; j++) {
  58. if (r->handle == p->relocs[j].handle) {
  59. p->relocs_ptr[i] = &p->relocs[j];
  60. duplicate = true;
  61. break;
  62. }
  63. }
  64. if (!duplicate) {
  65. p->relocs[i].gobj = drm_gem_object_lookup(ddev,
  66. p->filp,
  67. r->handle);
  68. if (p->relocs[i].gobj == NULL) {
  69. DRM_ERROR("gem object lookup failed 0x%x\n",
  70. r->handle);
  71. return -ENOENT;
  72. }
  73. p->relocs_ptr[i] = &p->relocs[i];
  74. p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
  75. p->relocs[i].lobj.bo = p->relocs[i].robj;
  76. p->relocs[i].lobj.wdomain = r->write_domain;
  77. p->relocs[i].lobj.rdomain = r->read_domains;
  78. p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
  79. p->relocs[i].handle = r->handle;
  80. p->relocs[i].flags = r->flags;
  81. radeon_bo_list_add_object(&p->relocs[i].lobj,
  82. &p->validated);
  83. } else
  84. p->relocs[i].handle = 0;
  85. }
  86. return radeon_bo_list_validate(&p->validated);
  87. }
  88. static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
  89. {
  90. p->priority = priority;
  91. switch (ring) {
  92. default:
  93. DRM_ERROR("unknown ring id: %d\n", ring);
  94. return -EINVAL;
  95. case RADEON_CS_RING_GFX:
  96. p->ring = RADEON_RING_TYPE_GFX_INDEX;
  97. break;
  98. case RADEON_CS_RING_COMPUTE:
  99. /* for now */
  100. p->ring = RADEON_RING_TYPE_GFX_INDEX;
  101. break;
  102. }
  103. return 0;
  104. }
  105. static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
  106. {
  107. bool sync_to_ring[RADEON_NUM_RINGS] = { };
  108. int i, r;
  109. for (i = 0; i < p->nrelocs; i++) {
  110. if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
  111. continue;
  112. if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
  113. struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
  114. if (!radeon_fence_signaled(fence)) {
  115. sync_to_ring[fence->ring] = true;
  116. }
  117. }
  118. }
  119. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  120. /* no need to sync to our own or unused rings */
  121. if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready)
  122. continue;
  123. if (!p->ib->fence->semaphore) {
  124. r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
  125. if (r)
  126. return r;
  127. }
  128. r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
  129. if (r)
  130. return r;
  131. radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
  132. radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);
  133. r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
  134. if (r)
  135. return r;
  136. radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
  137. radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
  138. }
  139. return 0;
  140. }
  141. int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
  142. {
  143. struct drm_radeon_cs *cs = data;
  144. uint64_t *chunk_array_ptr;
  145. unsigned size, i;
  146. u32 ring = RADEON_CS_RING_GFX;
  147. s32 priority = 0;
  148. if (!cs->num_chunks) {
  149. return 0;
  150. }
  151. /* get chunks */
  152. INIT_LIST_HEAD(&p->validated);
  153. p->idx = 0;
  154. p->chunk_ib_idx = -1;
  155. p->chunk_relocs_idx = -1;
  156. p->chunk_flags_idx = -1;
  157. p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
  158. if (p->chunks_array == NULL) {
  159. return -ENOMEM;
  160. }
  161. chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
  162. if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
  163. sizeof(uint64_t)*cs->num_chunks)) {
  164. return -EFAULT;
  165. }
  166. p->cs_flags = 0;
  167. p->nchunks = cs->num_chunks;
  168. p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
  169. if (p->chunks == NULL) {
  170. return -ENOMEM;
  171. }
  172. for (i = 0; i < p->nchunks; i++) {
  173. struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
  174. struct drm_radeon_cs_chunk user_chunk;
  175. uint32_t __user *cdata;
  176. chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
  177. if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
  178. sizeof(struct drm_radeon_cs_chunk))) {
  179. return -EFAULT;
  180. }
  181. p->chunks[i].length_dw = user_chunk.length_dw;
  182. p->chunks[i].kdata = NULL;
  183. p->chunks[i].chunk_id = user_chunk.chunk_id;
  184. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
  185. p->chunk_relocs_idx = i;
  186. }
  187. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
  188. p->chunk_ib_idx = i;
  189. /* zero length IB isn't useful */
  190. if (p->chunks[i].length_dw == 0)
  191. return -EINVAL;
  192. }
  193. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
  194. p->chunk_flags_idx = i;
  195. /* zero length flags aren't useful */
  196. if (p->chunks[i].length_dw == 0)
  197. return -EINVAL;
  198. }
  199. p->chunks[i].length_dw = user_chunk.length_dw;
  200. p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
  201. cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
  202. if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
  203. (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
  204. size = p->chunks[i].length_dw * sizeof(uint32_t);
  205. p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
  206. if (p->chunks[i].kdata == NULL) {
  207. return -ENOMEM;
  208. }
  209. if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
  210. p->chunks[i].user_ptr, size)) {
  211. return -EFAULT;
  212. }
  213. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
  214. p->cs_flags = p->chunks[i].kdata[0];
  215. if (p->chunks[i].length_dw > 1)
  216. ring = p->chunks[i].kdata[1];
  217. if (p->chunks[i].length_dw > 2)
  218. priority = (s32)p->chunks[i].kdata[2];
  219. }
  220. }
  221. }
  222. if ((p->cs_flags & RADEON_CS_USE_VM) &&
  223. !p->rdev->vm_manager.enabled) {
  224. DRM_ERROR("VM not active on asic!\n");
  225. if (p->chunk_relocs_idx != -1)
  226. kfree(p->chunks[p->chunk_relocs_idx].kdata);
  227. if (p->chunk_flags_idx != -1)
  228. kfree(p->chunks[p->chunk_flags_idx].kdata);
  229. return -EINVAL;
  230. }
  231. if (radeon_cs_get_ring(p, ring, priority)) {
  232. if (p->chunk_relocs_idx != -1)
  233. kfree(p->chunks[p->chunk_relocs_idx].kdata);
  234. if (p->chunk_flags_idx != -1)
  235. kfree(p->chunks[p->chunk_flags_idx].kdata);
  236. return -EINVAL;
  237. }
  238. /* deal with non-vm */
  239. if ((p->chunk_ib_idx != -1) &&
  240. ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
  241. (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
  242. if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
  243. DRM_ERROR("cs IB too big: %d\n",
  244. p->chunks[p->chunk_ib_idx].length_dw);
  245. return -EINVAL;
  246. }
  247. p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
  248. p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
  249. if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
  250. p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
  251. kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
  252. kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
  253. return -ENOMEM;
  254. }
  255. p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
  256. p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
  257. p->chunks[p->chunk_ib_idx].last_copied_page = -1;
  258. p->chunks[p->chunk_ib_idx].last_page_index =
  259. ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
  260. }
  261. return 0;
  262. }
  263. /**
  264. * cs_parser_fini() - clean parser states
  265. * @parser: parser structure holding parsing context.
  266. * @error: error number
  267. *
  268. * If error is set than unvalidate buffer, otherwise just free memory
  269. * used by parsing context.
  270. **/
  271. static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
  272. {
  273. unsigned i;
  274. if (!error && parser->ib)
  275. ttm_eu_fence_buffer_objects(&parser->validated,
  276. parser->ib->fence);
  277. else
  278. ttm_eu_backoff_reservation(&parser->validated);
  279. if (parser->relocs != NULL) {
  280. for (i = 0; i < parser->nrelocs; i++) {
  281. if (parser->relocs[i].gobj)
  282. drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
  283. }
  284. }
  285. kfree(parser->track);
  286. kfree(parser->relocs);
  287. kfree(parser->relocs_ptr);
  288. for (i = 0; i < parser->nchunks; i++) {
  289. kfree(parser->chunks[i].kdata);
  290. kfree(parser->chunks[i].kpage[0]);
  291. kfree(parser->chunks[i].kpage[1]);
  292. }
  293. kfree(parser->chunks);
  294. kfree(parser->chunks_array);
  295. radeon_ib_free(parser->rdev, &parser->ib);
  296. }
  297. static int radeon_cs_ib_chunk(struct radeon_device *rdev,
  298. struct radeon_cs_parser *parser)
  299. {
  300. struct radeon_cs_chunk *ib_chunk;
  301. int r;
  302. if (parser->chunk_ib_idx == -1)
  303. return 0;
  304. if (parser->cs_flags & RADEON_CS_USE_VM)
  305. return 0;
  306. ib_chunk = &parser->chunks[parser->chunk_ib_idx];
  307. /* Copy the packet into the IB, the parser will read from the
  308. * input memory (cached) and write to the IB (which can be
  309. * uncached).
  310. */
  311. r = radeon_ib_get(rdev, parser->ring, &parser->ib,
  312. ib_chunk->length_dw * 4);
  313. if (r) {
  314. DRM_ERROR("Failed to get ib !\n");
  315. return r;
  316. }
  317. parser->ib->length_dw = ib_chunk->length_dw;
  318. r = radeon_cs_parse(rdev, parser->ring, parser);
  319. if (r || parser->parser_error) {
  320. DRM_ERROR("Invalid command stream !\n");
  321. return r;
  322. }
  323. r = radeon_cs_finish_pages(parser);
  324. if (r) {
  325. DRM_ERROR("Invalid command stream !\n");
  326. return r;
  327. }
  328. r = radeon_cs_sync_rings(parser);
  329. if (r) {
  330. DRM_ERROR("Failed to synchronize rings !\n");
  331. }
  332. parser->ib->vm_id = 0;
  333. r = radeon_ib_schedule(rdev, parser->ib);
  334. if (r) {
  335. DRM_ERROR("Failed to schedule IB !\n");
  336. }
  337. return 0;
  338. }
  339. static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
  340. struct radeon_vm *vm)
  341. {
  342. struct radeon_bo_list *lobj;
  343. struct radeon_bo *bo;
  344. int r;
  345. list_for_each_entry(lobj, &parser->validated, tv.head) {
  346. bo = lobj->bo;
  347. r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
  348. if (r) {
  349. return r;
  350. }
  351. }
  352. return 0;
  353. }
  354. static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
  355. struct radeon_cs_parser *parser)
  356. {
  357. struct radeon_cs_chunk *ib_chunk;
  358. struct radeon_fpriv *fpriv = parser->filp->driver_priv;
  359. struct radeon_vm *vm = &fpriv->vm;
  360. int r;
  361. if (parser->chunk_ib_idx == -1)
  362. return 0;
  363. if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
  364. return 0;
  365. ib_chunk = &parser->chunks[parser->chunk_ib_idx];
  366. if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
  367. DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
  368. return -EINVAL;
  369. }
  370. r = radeon_ib_get(rdev, parser->ring, &parser->ib,
  371. ib_chunk->length_dw * 4);
  372. if (r) {
  373. DRM_ERROR("Failed to get ib !\n");
  374. return r;
  375. }
  376. parser->ib->length_dw = ib_chunk->length_dw;
  377. /* Copy the packet into the IB */
  378. if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
  379. ib_chunk->length_dw * 4)) {
  380. return -EFAULT;
  381. }
  382. r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
  383. if (r) {
  384. return r;
  385. }
  386. mutex_lock(&vm->mutex);
  387. r = radeon_vm_bind(rdev, vm);
  388. if (r) {
  389. goto out;
  390. }
  391. r = radeon_bo_vm_update_pte(parser, vm);
  392. if (r) {
  393. goto out;
  394. }
  395. r = radeon_cs_sync_rings(parser);
  396. if (r) {
  397. DRM_ERROR("Failed to synchronize rings !\n");
  398. }
  399. parser->ib->vm_id = vm->id;
  400. /* ib pool is bind at 0 in virtual address space to gpu_addr is the
  401. * offset inside the pool bo
  402. */
  403. parser->ib->gpu_addr = parser->ib->sa_bo.offset;
  404. r = radeon_ib_schedule(rdev, parser->ib);
  405. out:
  406. if (!r) {
  407. if (vm->fence) {
  408. radeon_fence_unref(&vm->fence);
  409. }
  410. vm->fence = radeon_fence_ref(parser->ib->fence);
  411. }
  412. mutex_unlock(&fpriv->vm.mutex);
  413. return r;
  414. }
  415. int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  416. {
  417. struct radeon_device *rdev = dev->dev_private;
  418. struct radeon_cs_parser parser;
  419. int r;
  420. radeon_mutex_lock(&rdev->cs_mutex);
  421. /* initialize parser */
  422. memset(&parser, 0, sizeof(struct radeon_cs_parser));
  423. parser.filp = filp;
  424. parser.rdev = rdev;
  425. parser.dev = rdev->dev;
  426. parser.family = rdev->family;
  427. r = radeon_cs_parser_init(&parser, data);
  428. if (r) {
  429. DRM_ERROR("Failed to initialize parser !\n");
  430. radeon_cs_parser_fini(&parser, r);
  431. radeon_mutex_unlock(&rdev->cs_mutex);
  432. return r;
  433. }
  434. r = radeon_cs_parser_relocs(&parser);
  435. if (r) {
  436. if (r != -ERESTARTSYS)
  437. DRM_ERROR("Failed to parse relocation %d!\n", r);
  438. radeon_cs_parser_fini(&parser, r);
  439. radeon_mutex_unlock(&rdev->cs_mutex);
  440. return r;
  441. }
  442. r = radeon_cs_ib_chunk(rdev, &parser);
  443. if (r) {
  444. goto out;
  445. }
  446. r = radeon_cs_ib_vm_chunk(rdev, &parser);
  447. if (r) {
  448. goto out;
  449. }
  450. out:
  451. radeon_cs_parser_fini(&parser, r);
  452. radeon_mutex_unlock(&rdev->cs_mutex);
  453. return r;
  454. }
  455. int radeon_cs_finish_pages(struct radeon_cs_parser *p)
  456. {
  457. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  458. int i;
  459. int size = PAGE_SIZE;
  460. for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
  461. if (i == ibc->last_page_index) {
  462. size = (ibc->length_dw * 4) % PAGE_SIZE;
  463. if (size == 0)
  464. size = PAGE_SIZE;
  465. }
  466. if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
  467. ibc->user_ptr + (i * PAGE_SIZE),
  468. size))
  469. return -EFAULT;
  470. }
  471. return 0;
  472. }
  473. int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
  474. {
  475. int new_page;
  476. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  477. int i;
  478. int size = PAGE_SIZE;
  479. for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
  480. if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
  481. ibc->user_ptr + (i * PAGE_SIZE),
  482. PAGE_SIZE)) {
  483. p->parser_error = -EFAULT;
  484. return 0;
  485. }
  486. }
  487. new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
  488. if (pg_idx == ibc->last_page_index) {
  489. size = (ibc->length_dw * 4) % PAGE_SIZE;
  490. if (size == 0)
  491. size = PAGE_SIZE;
  492. }
  493. if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
  494. ibc->user_ptr + (pg_idx * PAGE_SIZE),
  495. size)) {
  496. p->parser_error = -EFAULT;
  497. return 0;
  498. }
  499. /* copy to IB here */
  500. memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
  501. ibc->last_copied_page = pg_idx;
  502. ibc->kpage_idx[new_page] = pg_idx;
  503. return new_page;
  504. }