eeh-ioda.c 3.1 KB

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  1. /*
  2. * The file intends to implement the functions needed by EEH, which is
  3. * built on IODA compliant chip. Actually, lots of functions related
  4. * to EEH would be built based on the OPAL APIs.
  5. *
  6. * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/bootmem.h>
  14. #include <linux/delay.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <linux/irq.h>
  18. #include <linux/kernel.h>
  19. #include <linux/msi.h>
  20. #include <linux/pci.h>
  21. #include <linux/string.h>
  22. #include <asm/eeh.h>
  23. #include <asm/eeh_event.h>
  24. #include <asm/io.h>
  25. #include <asm/iommu.h>
  26. #include <asm/msi_bitmap.h>
  27. #include <asm/opal.h>
  28. #include <asm/pci-bridge.h>
  29. #include <asm/ppc-pci.h>
  30. #include <asm/tce.h>
  31. #include "powernv.h"
  32. #include "pci.h"
  33. /**
  34. * ioda_eeh_post_init - Chip dependent post initialization
  35. * @hose: PCI controller
  36. *
  37. * The function will be called after eeh PEs and devices
  38. * have been built. That means the EEH is ready to supply
  39. * service with I/O cache.
  40. */
  41. static int ioda_eeh_post_init(struct pci_controller *hose)
  42. {
  43. struct pnv_phb *phb = hose->private_data;
  44. /* FIXME: Enable it for PHB3 later */
  45. if (phb->type == PNV_PHB_IODA1)
  46. phb->eeh_enabled = 1;
  47. return 0;
  48. }
  49. /**
  50. * ioda_eeh_set_option - Set EEH operation or I/O setting
  51. * @pe: EEH PE
  52. * @option: options
  53. *
  54. * Enable or disable EEH option for the indicated PE. The
  55. * function also can be used to enable I/O or DMA for the
  56. * PE.
  57. */
  58. static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
  59. {
  60. s64 ret;
  61. u32 pe_no;
  62. struct pci_controller *hose = pe->phb;
  63. struct pnv_phb *phb = hose->private_data;
  64. /* Check on PE number */
  65. if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
  66. pr_err("%s: PE address %x out of range [0, %x] "
  67. "on PHB#%x\n",
  68. __func__, pe->addr, phb->ioda.total_pe,
  69. hose->global_number);
  70. return -EINVAL;
  71. }
  72. pe_no = pe->addr;
  73. switch (option) {
  74. case EEH_OPT_DISABLE:
  75. ret = -EEXIST;
  76. break;
  77. case EEH_OPT_ENABLE:
  78. ret = 0;
  79. break;
  80. case EEH_OPT_THAW_MMIO:
  81. ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
  82. OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
  83. if (ret) {
  84. pr_warning("%s: Failed to enable MMIO for "
  85. "PHB#%x-PE#%x, err=%lld\n",
  86. __func__, hose->global_number, pe_no, ret);
  87. return -EIO;
  88. }
  89. break;
  90. case EEH_OPT_THAW_DMA:
  91. ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
  92. OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
  93. if (ret) {
  94. pr_warning("%s: Failed to enable DMA for "
  95. "PHB#%x-PE#%x, err=%lld\n",
  96. __func__, hose->global_number, pe_no, ret);
  97. return -EIO;
  98. }
  99. break;
  100. default:
  101. pr_warning("%s: Invalid option %d\n", __func__, option);
  102. return -EINVAL;
  103. }
  104. return ret;
  105. }
  106. struct pnv_eeh_ops ioda_eeh_ops = {
  107. .post_init = ioda_eeh_post_init,
  108. .set_option = ioda_eeh_set_option,
  109. .get_state = NULL,
  110. .reset = NULL,
  111. .get_log = NULL,
  112. .configure_bridge = NULL,
  113. .next_error = NULL
  114. };